189 lines
6.1 KiB
ArmAsm
189 lines
6.1 KiB
ArmAsm
/********************************** (C) COPYRIGHT *******************************
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* File Name : portASM.S
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* Author : WCH
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* Version : V1.0
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* Date : 2024/08/13
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* Description : WCH Qingke V3C FreeRTOSÒÆÖ²»ã±à½Ó¿Ú
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* Copyright (c) 2024 Nanjing Qinheng Microelectronics Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#define portCONTEXT_SIZE ( 32 * 4 )
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.global xPortStartFirstTask
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.global pxPortInitialiseStack
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.global SW_Handler
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.extern pxCurrentTCB
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.extern vTaskSwitchContext
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.extern xISRStackTop
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.section .highcode.SW_Handler,"ax",@progbits
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.align 2
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.func
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SW_Handler:
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addi sp, sp, -portCONTEXT_SIZE
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sw x1, 1 * 4( sp )
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sw x5, 2 * 4( sp )
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sw x6, 3 * 4( sp )
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sw x7, 4 * 4( sp )
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sw x8, 5 * 4( sp )
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sw x9, 6 * 4( sp )
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sw x10, 7 * 4( sp )
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sw x11, 8 * 4( sp )
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sw x12, 9 * 4( sp )
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sw x13, 10 * 4( sp )
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sw x14, 11 * 4( sp )
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sw x15, 12 * 4( sp )
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sw x16, 13 * 4( sp )
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sw x17, 14 * 4( sp )
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sw x18, 15 * 4( sp )
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sw x19, 16 * 4( sp )
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sw x20, 17 * 4( sp )
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sw x21, 18 * 4( sp )
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sw x22, 19 * 4( sp )
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sw x23, 20 * 4( sp )
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sw x24, 21 * 4( sp )
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sw x25, 22 * 4( sp )
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sw x26, 23 * 4( sp )
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sw x27, 24 * 4( sp )
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sw x28, 25 * 4( sp )
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sw x29, 26 * 4( sp )
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sw x30, 27 * 4( sp )
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sw x31, 28 * 4( sp )
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sw x4, 29 * 4( sp ) /* tp - not sure it is useful */
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addi a1, x0, 0x20 /* Disable HPE */
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csrs 0x804, a1
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp to first TCB member. */
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csrr a1, mepc
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sw a1, 0( sp ) /* Save updated exception return address. */
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jal vTaskSwitchContext
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lw t1, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( t1 ) /* Read sp from first TCB member. */
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lw t0, 0(sp) /* Load mret with the address of the next instruction in the task to run next. */
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csrw mepc, t0
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lw x1, 1 * 4( sp )
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lw x5, 2 * 4( sp ) /* t0 */
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lw x6, 3 * 4( sp ) /* t1 */
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lw x7, 4 * 4( sp ) /* t2 */
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lw x8, 5 * 4( sp ) /* s0/fp */
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lw x9, 6 * 4( sp ) /* s1 */
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lw x10, 7 * 4( sp ) /* a0 */
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lw x11, 8 * 4( sp ) /* a1 */
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lw x12, 9 * 4( sp ) /* a2 */
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lw x13, 10 * 4( sp ) /* a3 */
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lw x14, 11 * 4( sp ) /* a4 */
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lw x15, 12 * 4( sp ) /* a5 */
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lw x16, 13 * 4( sp ) /* a6 */
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lw x17, 14 * 4( sp ) /* a7 */
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lw x18, 15 * 4( sp ) /* s2 */
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lw x19, 16 * 4( sp ) /* s3 */
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lw x20, 17 * 4( sp ) /* s4 */
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lw x21, 18 * 4( sp ) /* s5 */
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lw x22, 19 * 4( sp ) /* s6 */
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lw x23, 20 * 4( sp ) /* s7 */
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lw x24, 21 * 4( sp ) /* s8 */
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lw x25, 22 * 4( sp ) /* s9 */
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lw x26, 23 * 4( sp ) /* s10 */
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lw x27, 24 * 4( sp ) /* s11 */
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lw x28, 25 * 4( sp ) /* t3 */
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lw x29, 26 * 4( sp ) /* t4 */
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lw x30, 27 * 4( sp ) /* t5 */
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lw x31, 28 * 4( sp ) /* t6 */
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lw x4, 29 * 4( sp ) /* tp - not sure it is useful */
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addi sp, sp, portCONTEXT_SIZE
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mret
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.endfunc
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/*-----------------------------------------------------------*/
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.section .text,"ax",@progbits
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.align 2
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.func
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xPortStartFirstTask:
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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lw x6, 3 * 4( sp ) /* t1 */
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lw x7, 4 * 4( sp ) /* t2 */
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lw x8, 5 * 4( sp ) /* s0/fp */
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lw x9, 6 * 4( sp ) /* s1 */
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lw x10, 7 * 4( sp ) /* a0 */
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lw x11, 8 * 4( sp ) /* a1 */
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lw x12, 9 * 4( sp ) /* a2 */
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lw x13, 10 * 4( sp ) /* a3 */
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lw x14, 11 * 4( sp ) /* a4 */
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lw x15, 12 * 4( sp ) /* a5 */
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lw x16, 13 * 4( sp ) /* a6 */
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lw x17, 14 * 4( sp ) /* a7 */
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lw x18, 15 * 4( sp ) /* s2 */
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lw x19, 16 * 4( sp ) /* s3 */
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lw x20, 17 * 4( sp ) /* s4 */
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lw x21, 18 * 4( sp ) /* s5 */
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lw x22, 19 * 4( sp ) /* s6 */
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lw x23, 20 * 4( sp ) /* s7 */
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lw x24, 21 * 4( sp ) /* s8 */
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lw x25, 22 * 4( sp ) /* s9 */
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lw x26, 23 * 4( sp ) /* s10 */
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lw x27, 24 * 4( sp ) /* s11 */
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lw x28, 25 * 4( sp ) /* t3 */
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lw x29, 26 * 4( sp ) /* t4 */
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lw x30, 27 * 4( sp ) /* t5 */
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lw x31, 28 * 4( sp ) /* t6 */
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lw x5, 29 * 4( sp ) /* Initial mstatus into x5 (t0) */
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addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
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csrrw x0, mstatus, x5 /* Interrupts enabled from here! */
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lw x5, 2 * 4( sp ) /* Initial x5 (t0) value. */
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addi sp, sp, portCONTEXT_SIZE
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ret
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.endfunc
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/*-----------------------------------------------------------*/
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.section .text,"ax",@progbits
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.align 2
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.func
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pxPortInitialiseStack:
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csrr t0, mstatus /* Obtain current mstatus value. */
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andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
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addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
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slli t1, t1, 4
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or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
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addi a0, a0, -4
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sw t0, 0(a0) /* mstatus onto the stack. */
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addi a0, a0, -(22 * 4) /* Space for registers x11-x31. */
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sw a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
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addi a0, a0, -(6 * 4) /* Space for registers x5-x9. */
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sw x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
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addi t0, x0, 0 /* The number of chip specific additional registers. */
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chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
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beq t0, x0, 1f /* No more chip specific registers to save. */
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addi a0, a0, -4 /* Make space for chip specific register. */
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sw x0, 0(a0) /* Give the chip specific register an initial value of zero. */
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addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
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j chip_specific_stack_frame /* Until no more chip specific registers. */
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1:
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addi a0, a0, -4
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sw a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
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ret
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.endfunc
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/*-----------------------------------------------------------*/
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