From b36ac27555be3eff4ee694d4e5f790536bbc83e3 Mon Sep 17 00:00:00 2001 From: zhuchengnuo Date: Thu, 18 Jan 2024 10:15:45 +0800 Subject: [PATCH] init --- .../Keil_Mould/Drivers/SCDriver_List.h | 6 + .../FWLib/SC92F_Lib/inc/SC92F7003_C.H | 206 ++ .../FWLib/SC92F_Lib/inc/SC92F725X_C.H | 209 ++ .../FWLib/SC92F_Lib/inc/SC92F730x_C.H | 199 ++ .../FWLib/SC92F_Lib/inc/SC92F732x_C.H | 232 ++ .../FWLib/SC92F_Lib/inc/SC92F735x_C.H | 209 ++ .../FWLib/SC92F_Lib/inc/SC92F736xB_C.H | 252 ++ .../FWLib/SC92F_Lib/inc/SC92F740x_C.H | 222 ++ .../FWLib/SC92F_Lib/inc/SC92F742x_C.H | 237 ++ .../FWLib/SC92F_Lib/inc/SC92F744xB_C.H | 294 ++ .../FWLib/SC92F_Lib/inc/SC92F746xB_C.H | 251 ++ .../FWLib/SC92F_Lib/inc/SC92F748x_C.H | 254 ++ .../FWLib/SC92F_Lib/inc/SC92F7490_C.H | 176 ++ .../FWLib/SC92F_Lib/inc/SC92F74Ax_2_ASM.H | 294 ++ .../FWLib/SC92F_Lib/inc/SC92F74Ax_2_C.H | 296 ++ .../FWLib/SC92F_Lib/inc/SC92F754x_C.H | 313 ++ .../FWLib/SC92F_Lib/inc/SC92F759x_C.H | 297 ++ .../FWLib/SC92F_Lib/inc/SC92F8003_C.H | 207 ++ .../FWLib/SC92F_Lib/inc/SC92F827X_C.H | 195 ++ .../FWLib/SC92F_Lib/inc/SC92F836xB_C.H | 251 ++ .../FWLib/SC92F_Lib/inc/SC92F837X_C.H | 199 ++ .../FWLib/SC92F_Lib/inc/SC92F844xB_C.H | 294 ++ .../FWLib/SC92F_Lib/inc/SC92F846xB_C.H | 251 ++ .../FWLib/SC92F_Lib/inc/SC92F848x_C.H | 254 ++ .../FWLib/SC92F_Lib/inc/SC92F84Ax_2_ASM.H | 294 ++ .../FWLib/SC92F_Lib/inc/SC92F84Ax_2_C.H | 296 ++ .../FWLib/SC92F_Lib/inc/SC92F854x_C.H | 320 ++ .../FWLib/SC92F_Lib/inc/SC92F859x_C.H | 297 ++ .../FWLib/SC92F_Lib/inc/SC92FWxx_C.H | 286 ++ .../FWLib/SC92F_Lib/inc/SC92L753x_C.H | 277 ++ .../FWLib/SC92F_Lib/inc/SC92L853x_C.H | 277 ++ .../FWLib/SC92F_Lib/inc/SC92f73Ax_C.H | 252 ++ .../FWLib/SC92F_Lib/inc/SC92f74Ax_C.H | 253 ++ .../FWLib/SC92F_Lib/inc/SC92f83Ax_C.H | 253 ++ .../FWLib/SC92F_Lib/inc/SC92f84Ax_C.H | 253 ++ .../FWLib/SC92F_Lib/inc/SC93F743x_C.H | 242 ++ .../FWLib/SC92F_Lib/inc/SC93F833x_C.H | 247 ++ .../FWLib/SC92F_Lib/inc/SC93F843X_C.H | 247 ++ .../Keil_Mould/FWLib/SC92F_Lib/inc/sc92f.h | 201 ++ .../FWLib/SC92F_Lib/inc/sc92f_acmp.h | 78 + .../FWLib/SC92F_Lib/inc/sc92f_adc.h | 326 ++ .../FWLib/SC92F_Lib/inc/sc92f_btm.h | 89 + .../FWLib/SC92F_Lib/inc/sc92f_chksum.h | 28 + .../FWLib/SC92F_Lib/inc/sc92f_conf.h | 40 + .../FWLib/SC92F_Lib/inc/sc92f_crc.h | 24 + .../FWLib/SC92F_Lib/inc/sc92f_ddic.h | 195 ++ .../FWLib/SC92F_Lib/inc/sc92f_gpio.h | 94 + .../FWLib/SC92F_Lib/inc/sc92f_iap.h | 82 + .../FWLib/SC92F_Lib/inc/sc92f_int.h | 220 ++ .../FWLib/SC92F_Lib/inc/sc92f_lpd.h | 59 + .../FWLib/SC92F_Lib/inc/sc92f_mdu.h | 48 + .../FWLib/SC92F_Lib/inc/sc92f_option.h | 141 + .../FWLib/SC92F_Lib/inc/sc92f_pwm.h | 406 +++ .../FWLib/SC92F_Lib/inc/sc92f_pwr.h | 24 + .../FWLib/SC92F_Lib/inc/sc92f_ssi.h | 282 ++ .../FWLib/SC92F_Lib/inc/sc92f_timer0.h | 139 + .../FWLib/SC92F_Lib/inc/sc92f_timer1.h | 116 + .../FWLib/SC92F_Lib/inc/sc92f_timer2.h | 98 + .../FWLib/SC92F_Lib/inc/sc92f_timer3.h | 63 + .../FWLib/SC92F_Lib/inc/sc92f_timer4.h | 62 + .../FWLib/SC92F_Lib/inc/sc92f_uart0.h | 127 + .../FWLib/SC92F_Lib/inc/sc92f_usci0.h | 171 + .../FWLib/SC92F_Lib/inc/sc92f_usci1.h | 168 + .../FWLib/SC92F_Lib/inc/sc92f_usci2.h | 168 + .../FWLib/SC92F_Lib/inc/sc92f_wdt.h | 43 + .../FWLib/SC92F_Lib/src/sc92f_acmp.c | 129 + .../FWLib/SC92F_Lib/src/sc92f_adc.c | 462 +++ .../FWLib/SC92F_Lib/src/sc92f_btm.c | 78 + .../FWLib/SC92F_Lib/src/sc92f_chksum.c | 59 + .../FWLib/SC92F_Lib/src/sc92f_crc.c | 97 + .../FWLib/SC92F_Lib/src/sc92f_ddic.c | 228 ++ .../FWLib/SC92F_Lib/src/sc92f_gpio.c | 539 ++++ .../FWLib/SC92F_Lib/src/sc92f_iap.c | 172 ++ .../FWLib/SC92F_Lib/src/sc92f_int.c | 284 ++ .../FWLib/SC92F_Lib/src/sc92f_lpd.c | 94 + .../FWLib/SC92F_Lib/src/sc92f_mdu.c | 132 + .../FWLib/SC92F_Lib/src/sc92f_option.c | 178 ++ .../FWLib/SC92F_Lib/src/sc92f_pwm.c | 2086 +++++++++++++ .../FWLib/SC92F_Lib/src/sc92f_pwr.c | 62 + .../FWLib/SC92F_Lib/src/sc92f_ssi.c | 420 +++ .../FWLib/SC92F_Lib/src/sc92f_ssi0.c | 392 +++ .../FWLib/SC92F_Lib/src/sc92f_ssi1.c | 392 +++ .../FWLib/SC92F_Lib/src/sc92f_timer0.c | 165 + .../FWLib/SC92F_Lib/src/sc92f_timer1.c | 140 + .../FWLib/SC92F_Lib/src/sc92f_timer2.c | 541 ++++ .../FWLib/SC92F_Lib/src/sc92f_timer3.c | 280 ++ .../FWLib/SC92F_Lib/src/sc92f_timer4.c | 278 ++ .../FWLib/SC92F_Lib/src/sc92f_uart0.c | 388 +++ .../FWLib/SC92F_Lib/src/sc92f_usci0.c | 529 ++++ .../FWLib/SC92F_Lib/src/sc92f_usci1.c | 528 ++++ .../FWLib/SC92F_Lib/src/sc92f_usci2.c | 535 ++++ .../FWLib/SC92F_Lib/src/sc92f_wdt.c | 58 + CFG/SC92F8363B/Keil_Mould/List/SC_Init.lst | 284 ++ CFG/SC92F8363B/Keil_Mould/List/SC_it.lst | 124 + CFG/SC92F8363B/Keil_Mould/List/STARTUP.lst | 254 ++ CFG/SC92F8363B/Keil_Mould/List/main.lst | 52 + .../Keil_Mould/List/sc92f_chksum.lst | 86 + CFG/SC92F8363B/Keil_Mould/List/sc92f_gpio.lst | 433 +++ .../Keil_Mould/List/sc92f_option.lst | 187 ++ CFG/SC92F8363B/Keil_Mould/List/sc92f_pwm.lst | 945 ++++++ CFG/SC92F8363B/Keil_Mould/List/sc92f_pwr.lst | 92 + CFG/SC92F8363B/Keil_Mould/Output/project name | Bin 0 -> 169072 bytes .../Keil_Mould/Output/project name.SBR | Bin 0 -> 138245 bytes .../Output/project name.build_log.htm | 12 + .../Keil_Mould/Output/project name.lnp | 11 + .../Keil_Mould/Output/sc92f_chksum.__i | 1 + CFG/SC92F8363B/Keil_Mould/Project/STARTUP.A51 | 198 ++ CFG/SC92F8363B/Keil_Mould/Project/SinOne.soc | Bin 0 -> 254 bytes .../Project/project name.uvgui.Andy | 2737 +++++++++++++++++ .../Project/project name.uvgui_Andy.bak | 2737 +++++++++++++++++ .../Keil_Mould/Project/project name.uvopt | 1683 ++++++++++ .../Keil_Mould/Project/project name.uvproj | 417 +++ .../Keil_Mould/Project/project name_uvopt.bak | 1683 ++++++++++ .../Project/project name_uvproj.bak | 442 +++ .../Keil_Mould/User/CallBackFunction.c | 14 + .../Keil_Mould/User/CompCtrlDefine.c | 14 + .../User/HeadFiles/CompCtrlDefine.h | 14 + .../Keil_Mould/User/HeadFiles/CustomType.h | 14 + .../Keil_Mould/User/HeadFiles/FunctionType.h | 14 + .../Keil_Mould/User/HeadFiles/SC_itExtern.h | 15 + .../User/HeadFiles/SysFunVarDefine.h | 19 + .../Keil_Mould/User/HeadFiles/UserExport.h | 15 + CFG/SC92F8363B/Keil_Mould/User/SC_Init.c | 419 +++ CFG/SC92F8363B/Keil_Mould/User/SC_Init.h | 58 + CFG/SC92F8363B/Keil_Mould/User/SC_it.c | 237 ++ CFG/SC92F8363B/Keil_Mould/User/SC_it.h | 20 + .../Keil_Mould/User/SysFunVarDefine.c | 15 + CFG/SC92F8363B/Keil_Mould/User/main.c | 31 + CFG/SC92F8363B/PEP/SC92F8363B.db | Bin 0 -> 131072 bytes CFG/SC92F8363B/SC92F8363B.txt | Bin 0 -> 4336 bytes CFG/SC92F8363B/Temp/Function_Temp/ADC.txt | 2 + CFG/SC92F8363B/Temp/Function_Temp/OPTION.txt | 2 + CFG/SC92F8363B/Temp/Function_Temp/TIM0.txt | 2 + CFG/SC92F8363B/Temp/Function_Temp/UART1.txt | 2 + CFG/SC92F8363B/Temp/PEPCFG_Temp/ADC.txt | 19 + CFG/SC92F8363B/Temp/PEPCFG_Temp/GPIO.txt | 2 + CFG/SC92F8363B/Temp/PEPCFG_Temp/OPTION.txt | 9 + CFG/SC92F8363B/Temp/PEPCFG_Temp/TIM0.txt | 13 + CFG/SC92F8363B/Temp/PEPCFG_Temp/UART1.txt | 8 + .../Temp/PEPCFG_Temp/backup/ADC.txt | 19 + .../Temp/PEPCFG_Temp/backup/GPIO.txt | 2 + .../Temp/PEPCFG_Temp/backup/OPTION.txt | 9 + .../Temp/PEPCFG_Temp/backup/TIM0.txt | 13 + .../Temp/PEPCFG_Temp/backup/UART1.txt | 8 + CFG/SC92F8363B/结构图.png | Bin 0 -> 63605 bytes Keil_C/Apps/Uart1.c | 780 +++++ Keil_C/Apps/Uart1.h | 66 + Keil_C/Apps/adc.c | 83 + Keil_C/Apps/adc.h | 10 + Keil_C/Apps/motor.c | 1004 ++++++ Keil_C/Apps/motor.h | 62 + Keil_C/Apps/test.c | 80 + Keil_C/Apps/test.h | 21 + Keil_C/Drivers/SCDriver_List.h | 13 + Keil_C/FWLib/SC92F_Lib/inc/SC92F7003_C.H | 206 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F725X_C.H | 209 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F730x_C.H | 199 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F732x_C.H | 232 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F735x_C.H | 209 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F736xB_C.H | 252 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F740x_C.H | 222 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F742x_C.H | 237 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F744xB_C.H | 294 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F746xB_C.H | 251 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F748x_C.H | 254 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F7490_C.H | 176 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F74Ax_2_ASM.H | 294 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F74Ax_2_C.H | 296 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F754x_C.H | 313 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F759x_C.H | 297 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F8003_C.H | 207 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F827X_C.H | 195 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F836xB_C.H | 251 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F837X_C.H | 199 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F844xB_C.H | 294 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F846xB_C.H | 251 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F848x_C.H | 254 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F84Ax_2_ASM.H | 294 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F84Ax_2_C.H | 296 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F854x_C.H | 320 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92F859x_C.H | 297 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92FWxx_C.H | 286 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92L753x_C.H | 277 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92L853x_C.H | 277 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92f73Ax_C.H | 252 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92f74Ax_C.H | 253 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92f83Ax_C.H | 253 ++ Keil_C/FWLib/SC92F_Lib/inc/SC92f84Ax_C.H | 253 ++ Keil_C/FWLib/SC92F_Lib/inc/SC93F743x_C.H | 242 ++ Keil_C/FWLib/SC92F_Lib/inc/SC93F833x_C.H | 247 ++ Keil_C/FWLib/SC92F_Lib/inc/SC93F843X_C.H | 247 ++ Keil_C/FWLib/SC92F_Lib/inc/sc92f.h | 201 ++ Keil_C/FWLib/SC92F_Lib/inc/sc92f_acmp.h | 78 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_adc.h | 326 ++ Keil_C/FWLib/SC92F_Lib/inc/sc92f_btm.h | 89 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_chksum.h | 28 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_conf.h | 40 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_crc.h | 24 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_ddic.h | 195 ++ Keil_C/FWLib/SC92F_Lib/inc/sc92f_gpio.h | 94 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_iap.h | 82 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_int.h | 220 ++ Keil_C/FWLib/SC92F_Lib/inc/sc92f_lpd.h | 59 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_mdu.h | 48 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_option.h | 141 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_pwm.h | 406 +++ Keil_C/FWLib/SC92F_Lib/inc/sc92f_pwr.h | 24 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_ssi.h | 282 ++ Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer0.h | 139 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer1.h | 116 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer2.h | 98 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer3.h | 63 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer4.h | 62 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_uart0.h | 127 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci0.h | 171 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci1.h | 168 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci2.h | 168 + Keil_C/FWLib/SC92F_Lib/inc/sc92f_wdt.h | 43 + Keil_C/FWLib/SC92F_Lib/src/sc92f_acmp.c | 129 + Keil_C/FWLib/SC92F_Lib/src/sc92f_adc.c | 462 +++ Keil_C/FWLib/SC92F_Lib/src/sc92f_btm.c | 78 + Keil_C/FWLib/SC92F_Lib/src/sc92f_chksum.c | 59 + Keil_C/FWLib/SC92F_Lib/src/sc92f_crc.c | 97 + Keil_C/FWLib/SC92F_Lib/src/sc92f_ddic.c | 228 ++ Keil_C/FWLib/SC92F_Lib/src/sc92f_gpio.c | 539 ++++ Keil_C/FWLib/SC92F_Lib/src/sc92f_iap.c | 172 ++ Keil_C/FWLib/SC92F_Lib/src/sc92f_int.c | 284 ++ Keil_C/FWLib/SC92F_Lib/src/sc92f_lpd.c | 94 + Keil_C/FWLib/SC92F_Lib/src/sc92f_mdu.c | 132 + Keil_C/FWLib/SC92F_Lib/src/sc92f_option.c | 178 ++ Keil_C/FWLib/SC92F_Lib/src/sc92f_pwm.c | 2086 +++++++++++++ Keil_C/FWLib/SC92F_Lib/src/sc92f_pwr.c | 62 + Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi.c | 425 +++ Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi0.c | 392 +++ Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi1.c | 392 +++ Keil_C/FWLib/SC92F_Lib/src/sc92f_timer0.c | 165 + Keil_C/FWLib/SC92F_Lib/src/sc92f_timer1.c | 140 + Keil_C/FWLib/SC92F_Lib/src/sc92f_timer2.c | 541 ++++ Keil_C/FWLib/SC92F_Lib/src/sc92f_timer3.c | 280 ++ Keil_C/FWLib/SC92F_Lib/src/sc92f_timer4.c | 278 ++ Keil_C/FWLib/SC92F_Lib/src/sc92f_uart0.c | 388 +++ Keil_C/FWLib/SC92F_Lib/src/sc92f_usci0.c | 529 ++++ Keil_C/FWLib/SC92F_Lib/src/sc92f_usci1.c | 528 ++++ Keil_C/FWLib/SC92F_Lib/src/sc92f_usci2.c | 535 ++++ Keil_C/FWLib/SC92F_Lib/src/sc92f_wdt.c | 58 + Keil_C/List/CallBackFunction.lst | 43 + Keil_C/List/CompCtrlDefine.lst | 43 + Keil_C/List/SC_Init.lst | 212 ++ Keil_C/List/SC_it.lst | 256 ++ Keil_C/List/STARTUP.lst | 254 ++ Keil_C/List/SysFunVarDefine.lst | 43 + Keil_C/List/Uart1.lst | 838 +++++ Keil_C/List/adc.lst | 116 + Keil_C/List/main.lst | 89 + Keil_C/List/motor.lst | 1065 +++++++ Keil_C/List/sc92f_adc.lst | 535 ++++ Keil_C/List/sc92f_chksum.lst | 61 + Keil_C/List/sc92f_gpio.lst | 603 ++++ Keil_C/List/sc92f_option.lst | 217 ++ Keil_C/List/sc92f_pwm.lst | 613 ++++ Keil_C/List/sc92f_pwr.lst | 67 + Keil_C/List/sc92f_ssi.lst | 475 +++ Keil_C/List/sc92f_timer0.lst | 202 ++ Keil_C/List/sc92f_timer1.lst | 174 ++ Keil_C/List/test.lst | 111 + Keil_C/Project/STARTUP.A51 | 198 ++ Keil_C/Project/SinOne.soc | Bin 0 -> 254 bytes Keil_C/Project/Templst.soclst | Bin 0 -> 17279 bytes Keil_C/Project/magent_test.uvgui.admin | 1860 +++++++++++ Keil_C/Project/magent_test.uvopt | 478 +++ Keil_C/Project/magent_test.uvproj | 499 +++ Keil_C/Project/project name.uvgui.Andy | 2737 +++++++++++++++++ Keil_C/Project/project name.uvgui_Andy.bak | 2737 +++++++++++++++++ Keil_C/Project/project name.uvopt | 1683 ++++++++++ Keil_C/Project/project name_uvopt.bak | 1683 ++++++++++ Keil_C/Project/project name_uvproj.bak | 442 +++ Keil_C/User/CallBackFunction.c | 14 + Keil_C/User/CompCtrlDefine.c | 14 + Keil_C/User/HeadFiles/CompCtrlDefine.h | 13 + Keil_C/User/HeadFiles/CustomType.h | 19 + Keil_C/User/HeadFiles/FunctionType.h | 19 + Keil_C/User/HeadFiles/SC_itExtern.h | 14 + Keil_C/User/HeadFiles/SysFunVarDefine.h | 17 + Keil_C/User/HeadFiles/UserExport.h | 21 + Keil_C/User/SC_Init.c | 177 ++ Keil_C/User/SC_Init.h | 64 + Keil_C/User/SC_it.c | 218 ++ Keil_C/User/SC_it.h | 26 + Keil_C/User/SysFunVarDefine.c | 14 + Keil_C/User/Tmp/SC_it.bak | 272 ++ Keil_C/User/Tmp/SC_it.tmp | 272 ++ Keil_C/User/Tmp/main.bak | 39 + Keil_C/User/Tmp/main.tmp | 39 + Keil_C/User/main.c | 58 + Keil_C/User/readme.txt | 58 + magent_test.cgen | 89 + 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100644 Keil_C/List/CompCtrlDefine.lst create mode 100644 Keil_C/List/SC_Init.lst create mode 100644 Keil_C/List/SC_it.lst create mode 100644 Keil_C/List/STARTUP.lst create mode 100644 Keil_C/List/SysFunVarDefine.lst create mode 100644 Keil_C/List/Uart1.lst create mode 100644 Keil_C/List/adc.lst create mode 100644 Keil_C/List/main.lst create mode 100644 Keil_C/List/motor.lst create mode 100644 Keil_C/List/sc92f_adc.lst create mode 100644 Keil_C/List/sc92f_chksum.lst create mode 100644 Keil_C/List/sc92f_gpio.lst create mode 100644 Keil_C/List/sc92f_option.lst create mode 100644 Keil_C/List/sc92f_pwm.lst create mode 100644 Keil_C/List/sc92f_pwr.lst create mode 100644 Keil_C/List/sc92f_ssi.lst create mode 100644 Keil_C/List/sc92f_timer0.lst create mode 100644 Keil_C/List/sc92f_timer1.lst create mode 100644 Keil_C/List/test.lst create mode 100644 Keil_C/Project/STARTUP.A51 create mode 100644 Keil_C/Project/SinOne.soc create mode 100644 Keil_C/Project/Templst.soclst create mode 100644 Keil_C/Project/magent_test.uvgui.admin create mode 100644 Keil_C/Project/magent_test.uvopt create mode 100644 Keil_C/Project/magent_test.uvproj create mode 100644 Keil_C/Project/project name.uvgui.Andy create mode 100644 Keil_C/Project/project name.uvgui_Andy.bak create mode 100644 Keil_C/Project/project name.uvopt create mode 100644 Keil_C/Project/project name_uvopt.bak create mode 100644 Keil_C/Project/project name_uvproj.bak create mode 100644 Keil_C/User/CallBackFunction.c create mode 100644 Keil_C/User/CompCtrlDefine.c create mode 100644 Keil_C/User/HeadFiles/CompCtrlDefine.h create mode 100644 Keil_C/User/HeadFiles/CustomType.h create mode 100644 Keil_C/User/HeadFiles/FunctionType.h create mode 100644 Keil_C/User/HeadFiles/SC_itExtern.h create mode 100644 Keil_C/User/HeadFiles/SysFunVarDefine.h create mode 100644 Keil_C/User/HeadFiles/UserExport.h create mode 100644 Keil_C/User/SC_Init.c create mode 100644 Keil_C/User/SC_Init.h create mode 100644 Keil_C/User/SC_it.c create mode 100644 Keil_C/User/SC_it.h create mode 100644 Keil_C/User/SysFunVarDefine.c create mode 100644 Keil_C/User/Tmp/SC_it.bak create mode 100644 Keil_C/User/Tmp/SC_it.tmp create mode 100644 Keil_C/User/Tmp/main.bak create mode 100644 Keil_C/User/Tmp/main.tmp create mode 100644 Keil_C/User/main.c create mode 100644 Keil_C/User/readme.txt create mode 100644 magent_test.cgen create mode 100644 magent_test.fig create mode 100644 magent_test_01.fig create mode 100644 readme.txt diff --git a/CFG/SC92F8363B/Keil_Mould/Drivers/SCDriver_List.h b/CFG/SC92F8363B/Keil_Mould/Drivers/SCDriver_List.h new file mode 100644 index 0000000..1764b86 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/Drivers/SCDriver_List.h @@ -0,0 +1,6 @@ +#ifndef _SCDriver_List_H_ +#define _SCDriver_List_H_ + +/*write H Files here*/ + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F7003_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F7003_C.H new file mode 100644 index 0000000..7e09ca4 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F7003_C.H @@ -0,0 +1,206 @@ + /*-------------------------------------------------------------------------- +SC92F7003_C.H + +C Header file for SC92F7003 microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.24 +--------------------------------------------------------------------------*/ +#ifndef _SC92F7003_H_ +#define _SC92F7003_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG1 = 0xAA; //ADCüĴ0 +sfr ADCCFG0 = 0xAB; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON0 = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMCON1 = 0xDA; //PWMƼĴ +sfr PWMDTYB = 0xDB; //PWMռձüĴB +sfr PWMDTY3 = 0xDC; //PWM3üĴ +sfr PWMDTY4 = 0xDD; //PWM4üĴ +sfr PWMDTY5 = 0xDE; //PWM5üĴ +sfr PWMDTY6 = 0xDF; //PWM6üĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +sfr OTCON = 0X8F; //ƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //uartƼĴ +sfr SBUF = 0X99; //uart0ݼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSCON2 = 0X95; //SSIƼĴ2 +sfr SSDAT = 0X9F; //SSIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨 UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨 INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨 INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/* P0 */ +sbit P01 = P0^1; +sbit P00 = P0^0; + +/* P1 */ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/* P2 */ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F725X_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F725X_C.H new file mode 100644 index 0000000..8703946 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F725X_C.H @@ -0,0 +1,209 @@ + /*-------------------------------------------------------------------------- +SC92F725x_C.H + +C Header file for SC92F725x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.04.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F725x_H_ +#define _SC92F725x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON= 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD1; //PWMüĴ + +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMCFG1 = 0xD4; //PWMüĴ +sfr PWMDTY0 = 0xD5; //PWMռձüĴ +sfr PWMDTY1 = 0XD6; //PWMռձüĴ +sfr PWMDTY2 = 0XD7; //PWMռձüĴ +sfr PWMDTY3 = 0xDD; //PWMռձüĴ +sfr PWMDTY4 = 0XDE; //PWMռձüĴ +sfr PWMDTY5 = 0XDF; //PWMռձüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*option*/ +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT0жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT1жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT1ж 1:INT1ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7252װδĹܽţ +*SC92F7251װδĹܽţP04/P05 +*SC92F7250װδĹܽţP0 +******************************************/ +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7252װδĹܽţ +*SC92F7251װδĹܽţ +*SC92F7250װδĹܽţP10/P11/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7252װδĹܽţ +*SC92F7251װδĹܽţP26/P27 +*SC92F7250װδĹܽţP24/P25 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7252õú궨塣 +*****************************************************************************/ +#define SC92F7251_NIO_Init() {P0CON|=0xF0;P1CON|=0x30;P2CON|=0xCC;} //SC92F7251δIO +#define SC92F7250_NIO_Init() {P0CON|=0xFF;P1CON|=0xF3;P2CON|=0x3C;} //SC92F7250δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F730x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F730x_C.H new file mode 100644 index 0000000..5e3255f --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F730x_C.H @@ -0,0 +1,199 @@ + /*-------------------------------------------------------------------------- +SC92F730x_C.H + +C Header file for SC92F730x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.11.23 +--------------------------------------------------------------------------*/ +#ifndef _SC92F730x_H_ +#define _SC92F730x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON= 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD1; //PWMüĴ + +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMCFG1 = 0xD4; //PWMüĴ +sfr PWMDTY0 = 0xD5; //PWMռձüĴ +sfr PWMDTY1 = 0XD6; //PWMռձüĴ +sfr PWMDTY2 = 0XD7; //PWMռձüĴ +sfr PWMDTY3 = 0xDD; //PWMռձüĴ +sfr PWMDTY4 = 0XDE; //PWMռձüĴ +sfr PWMDTY5 = 0XDF; //PWMռձüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*option*/ +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT0жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT1жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7309װδĹܽţ +*SC92F7308װδĹܽţP00/P01 +******************************************/ +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7309װδĹܽţ +*SC92F7308װδĹܽţP10/P11 +******************************************/ +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7309װδĹܽţ +*SC92F7308װδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*****************************************************************************/ +#define SC92F7309_NIO_Init() {P0CON|=0xF0;P1CON|=0xF0;P2CON|=0x3C;} //SC92F7309δIO +#define SC92F7308_NIO_Init() {P0CON|=0xF3;P1CON|=0xF3;P2CON|=0x3C;} //SC92F7308δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F732x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F732x_C.H new file mode 100644 index 0000000..18f9a07 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F732x_C.H @@ -0,0 +1,232 @@ + /*-------------------------------------------------------------------------- +SC92F732x_C.H + +C Header file for SC92F732x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.04.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F732x_H_ +#define _SC92F732x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON= 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L= 0XCA; //ʱ2/׽8λ +sfr RCAP2H= 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMߵƽüĴ +sfr PWMDTY0 = 0xD5; //PWMߵƽüĴ +sfr PWMDTY1 = 0XD6; //PWMߵƽüĴ +sfr PWMDTY2 = 0XD7; //PWMߵƽüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*option*/ +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7323װδĹܽţ +*SC92F7322װδĹܽţP06/P07 +*SC92F7321װδĹܽţP04/P05/P06/P07 +*SC92F7320װδĹܽţP0 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/************************ P1 ********************* +*SC92F7323װδĹܽţ +*SC92F7322װδĹܽţP14/P15 +*SC92F7321װδĹܽţP14/P15 +*SC92F7320װδĹܽţP10/P11/P14/P15/P16/P17 +**************************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************** P2 *******%********** +*SC92F7323װδĹܽţ +*SC92F7322װδĹܽţP22/P23 +*SC92F7321װδĹܽţP24/P25/P26/P27 +*SC92F7320װδĹܽţP22/P23/P24/P25 +*********************************%*********/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************** P5 ************** +*SC92F7323װδĹܽţ +*SC92F7322װδĹܽţP50/P51 +*SC92F7321װδĹܽţP50/P51 +*SC92F7320װδĹܽţP50/P51 +***********************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7323õú궨塣 +*****************************************************************************/ +#define SC92F7322_NIO_Init() {P0CON|=0xC0;P1CON|=0x30;P2CON|=0x0C;P5CON|=0x03;} //SC92F7322δIO +#define SC92F7321_NIO_Init() {P0CON|=0xF0;P1CON|=0x30;P2CON|=0xF0;P5CON|=0x03;} //SC92F7321δIO +#define SC92F7320_NIO_Init() {P0CON|=0xFF;P1CON|=0xF3;P2CON|=0x3C;P5CON|=0x03;} //SC92F7320δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F735x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F735x_C.H new file mode 100644 index 0000000..1b062fb --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F735x_C.H @@ -0,0 +1,209 @@ + /*-------------------------------------------------------------------------- +SC92F735x_C.H + +C Header file for SC92F735x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.04.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F735x_H_ +#define _SC92F735x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON= 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD1; //PWMüĴ + +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMCFG1 = 0xD4; //PWMüĴ +sfr PWMDTY0 = 0xD5; //PWMռձüĴ +sfr PWMDTY1 = 0XD6; //PWMռձüĴ +sfr PWMDTY2 = 0XD7; //PWMռձüĴ +sfr PWMDTY3 = 0xDD; //PWMռձüĴ +sfr PWMDTY4 = 0XDE; //PWMռձüĴ +sfr PWMDTY5 = 0XDF; //PWMռձüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*option*/ +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT0жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT1жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7352װδĹܽţ +*SC92F7351װδĹܽţP04/P05 +*SC92F7350װδĹܽţP0 +******************************************/ +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7352װδĹܽţ +*SC92F7351װδĹܽţ +*SC92F7350װδĹܽţP10/P11/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7352װδĹܽţ +*SC92F7351װδĹܽţP26/P27 +*SC92F7350װδĹܽţP24/P25 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7352õú궨塣 +*****************************************************************************/ +#define SC92F7351_NIO_Init() {P0CON|=0xF0;P1CON|=0x30;P2CON|=0xCC;} //SC92F7351δIO +#define SC92F7350_NIO_Init() {P0CON|=0xFF;P1CON|=0xF3;P2CON|=0x3C;} //SC92F7350δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F736xB_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F736xB_C.H new file mode 100644 index 0000000..7ece2bf --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F736xB_C.H @@ -0,0 +1,252 @@ + /*-------------------------------------------------------------------------- +SC92F746xB_C.H + +C Header file for SC92F736xB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.06.15 +--------------------------------------------------------------------------*/ +#ifndef _SC92F736xB_H_ +#define _SC92F736xB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr16 RCAP2 = 0xCA; +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT0жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7363BװδĹܽţ +*SC92F736BװδĹܽţP06/P07 +*SC92F7361BװδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7363BװδĹܽţ +*SC92F7362BװδĹܽţP16/P17 +*SC92F7361BװδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7363BװδĹܽţ +*SC92F7362BװδĹܽţP22/P23 +*SC92F7361BװδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F7363BװδĹܽţ +*SC92F7362BװδĹܽţP50/P51 +*SC92F7361BװδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7363Bõú궨塣 +*****************************************************************************/ +#define SC92F7362B_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F7362BδIO +#define SC92F7361B_NIO_Init() {P0CON|=0xEC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F7361BδIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F740x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F740x_C.H new file mode 100644 index 0000000..76a2903 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F740x_C.H @@ -0,0 +1,222 @@ + /*-------------------------------------------------------------------------- +SC92F740x_C.H + +C Header file for SC92F740x microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.10.31 +--------------------------------------------------------------------------*/ +#ifndef _SC92F740x_H_ +#define _SC92F740x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG1 = 0xAA; //ADCüĴ0 +sfr ADCCFG0 = 0xAB; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON0 = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMCON1 = 0xDA; //PWMƼĴ +sfr PWMDTYB = 0xDB; //PWMռձüĴB +sfr PWMDTY3 = 0xDC; //PWM3üĴ +sfr PWMDTY4 = 0xDD; //PWM4üĴ +sfr PWMDTY5 = 0xDE; //PWM5üĴ +sfr PWMDTY6 = 0xDF; //PWM6üĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +sfr OTCON = 0X8F; //ƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //uartƼĴ +sfr SBUF = 0X99; //uart0ݼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSCON2 = 0X95; //SSIƼĴ2 +sfr SSDAT = 0X9F; //SSIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨 UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨 INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨 INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7402װδĹܽţ +*SC92F7401װδĹܽţ +******************************************/ +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7402װδĹܽţ +*SC92F7401װδĹܽţP12/P13 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7402װδĹܽţ +*SC92F7401װδĹܽţP24/P25 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7402õú궨塣 +*****************************************************************************/ +#define SC92F7401_NIO_Init() {P1CON|=0x0C,P2CON|=0x30;} //SC92F7401δIO +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F742x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F742x_C.H new file mode 100644 index 0000000..99ae7c6 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F742x_C.H @@ -0,0 +1,237 @@ + /*-------------------------------------------------------------------------- +SC92F742x_C.H + +C Header file for SC92F742x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.05.15 +--------------------------------------------------------------------------*/ +#ifndef _SC92F742x_H_ +#define _SC92F742x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD1; //PWMüĴ0 +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMCFG1 = 0xD4; //PWMüĴ1 +sfr PWMDTY0 = 0xD5; //PWM0ռձüĴ +sfr PWMDTY1 = 0XD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0XD7; //PWM2ռձüĴ +sfr PWMDTY3 = 0xDD; //PWM3ռձüĴ +sfr PWMDTY4 = 0XDE; //PWM4ռձüĴ +sfr PWMDTY5 = 0XDF; //PWM5ռձüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*SSI*/ +sfr SS0CON0 = 0XA5; //SSI0ƼĴ2 +sfr SS0CON1 = 0XA6; //SSI0ƼĴ1 +sfr SS0CON2 = 0XA4; //SSI0ƼĴ0 +sfr SS0DAT = 0XA7; //SSI0ݼĴ + +sfr SS1CON2 = 0X95; //SSI1ƼĴ2 +sfr SS1CON0 = 0X9D; //SSI1ƼĴ0 +sfr SS1CON1 = 0X9E; //SSI1ƼĴ1 +sfr SS1DAT = 0X9F; //SSI1ݼĴ + +/*CHKSUM*/ +sfr OPERCON = 0xEF; //ƼĴ +sfr CHKSUML = 0xFC; //CHKSUMĴλ +sfr CHKSUMH = 0XFD; //CHKSUMĴλ + +/*option*/ +sfr OPINX = 0XFE; //Optionָ +sfr OPREG = 0XFF; //OptionĴ + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPSSI0 = IP^4; //SSI0жȿλ 0:趨SSI0жȨ ͡ 1:趨SSI0жȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit ESSI0 = IE^4; //SSI0жʹܿ 0:رSSI0ж 1:SSI0ж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/******************* P0 ****************** +*SC92F7423װδĹܽţ +*SC92F7422װδĹܽţP06/P07 +*SC92F7421װδĹܽţP04/P05/P06/P07 +*SC92F7420װδĹܽţP0 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/************************ P1 ********************* +*SC92F7423װδĹܽţ +*SC92F7422װδĹܽţP14/P15 +*SC92F7421װδĹܽţP14/P15 +*SC92F7420װδĹܽţP10/P11/P14/P15/P16/P17 +**************************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************** P2 *******%********** +*SC92F7423װδĹܽţ +*SC92F7422װδĹܽţP22/P23 +*SC92F7421װδĹܽţP24/P25/P26/P27 +*SC92F7420װδĹܽţP22/P23/P24/P25 +*********************************%*********/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************** P5 ************** +*SC92F7423װδĹܽţ +*SC92F7422װδĹܽţP50/P51 +*SC92F7421װδĹܽţP50/P51 +*SC92F7420װδĹܽţP50/P51 +***********************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7423õú궨塣 +*****************************************************************************/ +#define SC92F7422_NIO_Init() {P0CON|=0xC0;P1CON|=0x30;P2CON|=0x0C;P5CON|=0x03;} //SC92F7422δIO +#define SC92F7421_NIO_Init() {P0CON|=0xF0;P1CON|=0x30;P2CON|=0xF0;P5CON|=0x03;} //SC92F7421δIO +#define SC92F7420_NIO_Init() {P0CON|=0xFF;P1CON|=0xF3;P2CON|=0x3C;P5CON|=0x03;} //SC92F7420δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F744xB_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F744xB_C.H new file mode 100644 index 0000000..e48dd76 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F744xB_C.H @@ -0,0 +1,294 @@ +/*-------------------------------------------------------------------------- +SC92F744xB_C.H + +C Header file for SC92F744xB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.10.30 +--------------------------------------------------------------------------*/ +#ifndef _SC92F744xB_H_ +#define _SC92F744xB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMƼĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţ +*SC92F7445BװδĹܽţP00 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţ +*SC92F7445BװδĹܽţ +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţ +*SC92F7445BװδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţ +*SC92F7445BװδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţP46/P47 +*SC92F7445BװδĹܽţP40 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţP54/P55 +*SC92F7445BװδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7447Bõú궨塣 +*****************************************************************************/ +#define SC92F7446B_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F7546BδIO +#define SC92F7445B_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F7545BδIO +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F746xB_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F746xB_C.H new file mode 100644 index 0000000..4cd2c72 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F746xB_C.H @@ -0,0 +1,251 @@ + /*-------------------------------------------------------------------------- +SC92F746XB_C.H + +C Header file for SC92F746XB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2018.08.24 +--------------------------------------------------------------------------*/ +#ifndef _SC92F746XB_H_ +#define _SC92F746XB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7463BװδĹܽţ +*SC92F7462BװδĹܽţP06/P07 +*SC92F7461BװδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7463BװδĹܽţ +*SC92F7462BװδĹܽţP16/P17 +*SC92F7461BװδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7463BװδĹܽţ +*SC92F7462BװδĹܽţP22/P23 +*SC92F7461BװδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F7463BװδĹܽţ +*SC92F7462BװδĹܽţP50/P51 +*SC92F7461BװδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7463Bõú궨塣 +*****************************************************************************/ +#define SC92F7462B_IO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F7462BδIO +#define SC92F7461B_IO_Init() {P0CON|=0xEC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F7461BδIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F748x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F748x_C.H new file mode 100644 index 0000000..6ac39b7 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F748x_C.H @@ -0,0 +1,254 @@ +/*-------------------------------------------------------------------------- +SC92F748x_C.H + +C Header file for SC92F748x microcontroller. +Copyright (c) 2021 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.2 +: 2021.07.14 +--------------------------------------------------------------------------*/ +#ifndef _SC92F748x_H_ +#define _SC92F748x_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr ACC = 0XE0; //ۼ +sfr B = 0XF0; //BĴ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr DPH = 0X83; //DPTRָλ +sfr DPL = 0X82; //DPTRָλ +sfr SP = 0X81; //ջָ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0XB8; //жȨƼĴ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr IOHCON = 0X97; //IOHüĴ +sfr P5PH = 0XDA; //P5ƼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P0VO = 0X9C; //P0LCDѹĴ +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0 = 0X80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr TH1 = 0X8D; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TL0 = 0X8A; //ʱ08λ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TCON = 0X88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ + +/*PWM*/ +sfr PWMCFG = 0XD1; //PWMüĴ +sfr PWMCON = 0XD2; //PWMƼĴ +sfr PWMPRD = 0XD3; //PWMüĴ +sfr PWMDTYA = 0XD4; //PWMռձüĴA +sfr PWMDTY0 = 0XD5; //PWM0üĴ +sfr PWMDTY1 = 0XD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0XD7; //PWM2ռձüĴ +sfr PWMDTYB = 0XDC; //PWMռձüĴB +sfr PWMDTY3 = 0XDD; //PWM3ռձüĴ/PWMʱüĴ +sfr PWMDTY4 = 0XDE; //PWM4ռձüĴ +sfr PWMDTY5 = 0XDF; //PWM5ռձüĴ + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0XF6; //IAPƼĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPADE = 0XF4; //IAPչַĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPKEY = 0XF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ +sfr OTCON = 0X8F; //ƼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //USCIƼĴ0 +sfr SSCON1 = 0X9E; //USCIƼĴ1 +sfr SSCON2 = 0X95; //USCIƼĴ2 +sfr SSDAT = 0X9F; //USCIݼĴ3 + +/*OPTION*/ +sfr OPINX = 0XFE; //Customer Optionָ +sfr OPREG = 0XFF; //Customer OptionĴ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ +sfr OPERCON = 0XEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; //ʱ2־λ +sbit EXF2 = T2CON^6; //T2EXⲿ¼(½)⵽ı־λ +sbit RCLK = T2CON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLK = T2CON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXEN2 = T2CON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TR2 = T2CON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit T2 = T2CON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = T2CON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + +/******************* P0 ****************** +*SC92F7483װδĹܽţ +*SC92F7482װδĹܽţP06/P07 +*SC92F7481װδĹܽţP02/P03/P04/P05/P06/P07 +*SC92F7480װδĹܽţP0 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7483װδĹܽţ +*SC92F7482װδĹܽţP16/P17 +*SC92F7481װδĹܽţP16/P17 +*SC92F7480װδĹܽţP14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7483װδĹܽţ +*SC92F7482װδĹܽţP22/P23 +*SC92F7481װδĹܽţP22/P23/P27 +*SC92F7480װδĹܽţP22/P23/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F7483װδĹܽţ +*SC92F7482װδĹܽţP50/P51 +*SC92F7481װδĹܽţP50/P51 +*SC92F7480װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7483õú궨塣 +*****************************************************************************/ +#define SC92F7482_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;}//SC92F7482δIO +#define SC92F7481_NIO_Init() {P0CON|=0xFC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;}//SC92F7481δIO +#define SC92F7480_NIO_Init() {P0CON|=0xFF,P1CON|=0xF0,P2CON|=0xEC,P5CON|=0x03;}//SC92F7480δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F7490_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F7490_C.H new file mode 100644 index 0000000..6a22ab7 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F7490_C.H @@ -0,0 +1,176 @@ + /*-------------------------------------------------------------------------- +SC92F7490_C.H + +C Header file for SC92F7490 microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.07.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F7490_H_ +#define _SC92F7490_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ + +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*SSI*/ +sfr SS0CON0 = 0XA5; //SSI0ƼĴ2 +sfr SS0CON1 = 0XA6; //SSI0ƼĴ1 +sfr SS0CON2 = 0XA4; //SSI0ƼĴ0 +sfr SS0DAT = 0XA7; //SSI0ݼĴ + +sfr SS1CON2 = 0X95; //SSI1ƼĴ2 +sfr SS1CON0 = 0X9D; //SSI1ƼĴ0 +sfr SS1CON1 = 0X9E; //SSI1ƼĴ1 +sfr SS1DAT = 0X9F; //SSI1ݼĴ + +/*CHKSUM*/ +sfr OPERCON = 0xEF; //ƼĴ +sfr CHKSUML = 0xFC; //CHKSUMĴλ +sfr CHKSUMH = 0XFD; //CHKSUMĴλ + +/*option*/ +sfr OPINX = 0XFE; //Optionָ +sfr OPREG = 0XFF; //OptionĴ + +sfr P5PH = 0xDA; +sfr P5CON = 0xD9; +sfr P5 = 0xD8; +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPSSI0 = IP^4; //SSI0жȿλ 0:趨SSI0жȨ ͡ 1:趨SSI0жȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit ESSI0 = IE^4; //SSI0жʹܿ 0:رSSI0ж 1:SSI0ж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/******************* P0 ******************/ +sbit P05 = P0^5; + +/******************* P1 ******************/ +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; + +/******************* P2 ******************/ +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺ʼIOںºꡣ +*****************************************************************************/ +#define SC92F7490_NIO_Init() {P0CON|=0xDF;P1CON|=0xF1;P2CON|=0xFC;P5CON|=0x03;} + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F74Ax_2_ASM.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F74Ax_2_ASM.H new file mode 100644 index 0000000..ffec448 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F74Ax_2_ASM.H @@ -0,0 +1,294 @@ +/*-------------------------------------------------------------------------- +SC92F74Ax_ASM.H + +ASM Header file for SC92F74Ax microcontroller. +Copyright (c) 2020 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2020.07.01 + + +--------------------------------------------------------------------------*/ +#ifndef _SC92F74Ax_ASM_H_ +#define _SC92F74Ax_ASM_H_ + +/* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +ACC EQU 0xE0; //ۼ +B EQU 0xF0; //ͨüĴB +PSW EQU 0xD0; //״̬ +DPH EQU 0x83; //ָ8λ +DPL EQU 0x82; //ָ8λ +SP EQU 0x81; //ջָ + +/*system*/ +PCON EQU 0x87; //ԴƼĴ + +/*interrupt*/ +IP EQU 0xB8; //жȨƼĴ +IE EQU 0xA8; //жϿƼĴ +IP1 EQU 0XB9; //жȼƼĴ1 +IE1 EQU 0XA9; //жϿƼĴ1 + +/*PORT*/ +P5PH EQU 0xDA; //P5ģʽƼĴ +P5CON EQU 0xD9; //P5ģʽƼĴ +P5 EQU 0xD8; //P5ݼĴ +P4PH EQU 0xC2; //P4ģʽƼĴ +P4CON EQU 0xC1; //P4ģʽƼĴ +P4 EQU 0xC0; //P4ݼĴ +P3PH EQU 0xB2; //P3ģʽƼĴ +P3CON EQU 0xB1; //P3ģʽƼĴ +P3 EQU 0xB0; //P3ݼĴ +P2PH EQU 0xA2; //P2ģʽƼĴ +P2CON EQU 0xA1; //P2ģʽƼĴ +P2 EQU 0xA0; //P2ݼĴ +P1PH EQU 0x92; //P1ģʽƼĴ +P1CON EQU 0x91; //P1ģʽƼĴ +P1 EQU 0x90; //P1ݼĴ +P0PH EQU 0x9B; //P0ģʽƼĴ +P0CON EQU 0x9A; //P0ģʽƼĴ +P0 EQU 0x80; //P0ݼĴ +IOHCON0 EQU 0x96; //IOH0üĴ +IOHCON1 EQU 0x97; //IOH1üĴ + +/*TIMER*/ +TMCON EQU 0x8E; //ʱƵʿƼĴ +TH1 EQU 0x8D; //ʱ18λ +TH0 EQU 0x8C; //ʱ08λ +TL1 EQU 0x8B; //ʱ18λ +TL0 EQU 0x8A; //ʱ08λ +TMOD EQU 0x89; //ʱģʽĴ +TCON EQU 0x88; //ʱƼĴ +T2CON EQU 0XC8; //ʱ2ƼĴ +T2MOD EQU 0XC9; //ʱ2ģʽĴ +RCAP2L EQU 0XCA; //ʱ2/׽8λ +RCAP2H EQU 0XCB; //ʱ2/׽8λ +TL2 EQU 0XCC; //ʱ28λ +TH2 EQU 0XCD; //ʱ28λ + +/*ADC*/ +ADCCFG0 EQU 0xAB; //ADCüĴ0 +ADCCFG1 EQU 0xAC; //ADCüĴ1 +ADCCFG2 EQU 0xAA; //ADCüĴ2 +ADCCON EQU 0XAD; //ADCƼĴ +ADCVL EQU 0xAE; //ADC Ĵ +ADCVH EQU 0xAF; //ADC Ĵ + +/*PWM*/ +PWMCFG EQU 0xD4; //PWMüĴ +PWMCON EQU 0xD3; //PWMƼĴ + +/*WatchDog*/ +BTMCON EQU 0XCE; //ƵʱƼĴ +WDTCON EQU 0xCF; //WDTƼĴ + +/*LCD*/ +OTCON EQU 0X8F; //LCDѹƼĴ +P0VO EQU 0X9C; //P0 LCD Bais Ĵ +P1VO EQU 0X94; //P1 LCD Bais Ĵ +P2VO EQU 0XA3; //P2 LCD Bais Ĵ +P3VO EQU 0XB3; //P3 LCD Bais Ĵ + +DDRCON EQU 0X93; //ʾüĴ + +/*INT*/ +INT0F EQU 0XBA; //INT0 ½жϿƼĴ +INT0R EQU 0XBB; //INT0 ϽжϿƼĴ +INT1F EQU 0XBC; //INT1 ½жϿƼĴ +INT1R EQU 0XBD; //INT1 ϽжϿƼĴ +INT2F EQU 0XC6; //INT2 ½жϿƼĴ +INT2R EQU 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +IAPCTL EQU 0xF6; //IAPƼĴ +IAPDAT EQU 0xF5; //IAPݼĴ +IAPADE EQU 0xF4; //IAPչַĴ +IAPADH EQU 0xF3; //IAPдַλĴ +IAPADL EQU 0xF2; //IAPдַ8λĴ +IAPKEY EQU 0xF1; //IAPĴ + +/*uart*/ +SCON EQU 0x98; //ڿƼĴ +SBUF EQU 0x99; //ݻĴ + +/*һ*/ +SSCON0 EQU 0X9D; //SSIƼĴ0 +SSCON1 EQU 0X9E; //SSIƼĴ1 +SSCON2 EQU 0X95; //SSIƼĴ2 +SSDAT EQU 0X9F; //SPIݼĴ + +OPINX EQU 0XFE; +OPREG EQU 0XFF; +EXADH EQU 0XF7; + +/*Check Sum*/ +CHKSUML EQU 0XFC; //Check SumĴλ +CHKSUMH EQU 0XFD; //Check SumĴλ + +/*˳*/ +EXA0 EQU 0xE9; //չۼ0 +EXA1 EQU 0xEA; //չۼ1 +EXA2 EQU 0xEB; //չۼ2 +EXA3 EQU 0xEC; //չۼ3 +EXBL EQU 0xED; //չBĴ0 +EXBH EQU 0xEE; //չBĴ1 +OPERCON EQU 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +CY EQU PSW .7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +AC EQU PSW .6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +F0 EQU PSW .5; //û־λ +RS1 EQU PSW .4; //Ĵѡλ +RS0 EQU PSW .3; //Ĵѡλ +OV EQU PSW .2; //־λ +F1 EQU PSW .1; //F1־ +P EQU PSW .0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +TF2 EQU T2CON .7; +EXF2 EQU T2CON .6; +RCLK EQU T2CON .5; +TCLK EQU T2CON .4; +EXEN2 EQU T2CON .3; +TR2 EQU T2CON .2; +T2 EQU T2CON .1; +CP EQU T2CON .0; + +/*IP*/ +IPADC EQU IP .6; //ADCжȿλ 0:趨ADCжȨ ͡ 1:趨ADCжȨ ߡ +IPT2 EQU IP .5; //PWMжȿλ 0:趨PWMжȨ ͡ 1:趨PWM жȨ ߡ +IPUART EQU IP .4; //Uartжȿλ 0:趨UartжȨ ͡ 1:趨UartжȨ ߡ +IPT1 EQU IP .3; //Timer1жȿλ 0:趨Timer1жȨ ͡ 1:趨Timer1жȨ ߡ +IPINT1 EQU IP .2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +IPT0 EQU IP .1; //Timer0жȿλ 0:趨Timer0жȨ ͡ 1:趨Timer0жȨ ߡ +IPINT0 EQU IP .0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +EA EQU IE .7; //жʹܵܿ 0:رеж 1:еж +EADC EQU IE .6; //ADCжʹܿ 0:رADCж 1:ADCж +ET2 EQU IE .5; //PWMжʹܿ 0:رPWMж 1:PWMж +EUART EQU IE .4; //UARTжʹܿ 0:رUARTж 1:UARTж +ET1 EQU IE .3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +EINT1 EQU IE .2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +ET0 EQU IE .1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +EINT0 EQU IE .0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +TF1 EQU TCON .7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +TR1 EQU TCON .6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +TF0 EQU TCON .5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +TR0 EQU TCON .4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +BITIE1 EQU TCON .3; //INT1ж־ +BITIE0 EQU TCON .1; //INT0ж־ + +/*SCON*/ +SM0 EQU SCON .7; +SM1 EQU SCON .6; +SM2 EQU SCON .5; +REN EQU SCON .4; +TB8 EQU SCON .3; +RB8 EQU SCON .2; +TI EQU SCON .1; +RI EQU SCON .0; + +/******************* P0 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţP00 +******************************************/ +P07 EQU P0 .7; +P06 EQU P0 .6; +P05 EQU P0 .5; +P04 EQU P0 .4; +P03 EQU P0 .3; +P02 EQU P0 .2; +P01 EQU P0 .1; +P00 EQU P0 .0; + +/******************* P1 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţ +******************************************/ +P17 EQU P1 .7; +P16 EQU P1 .6; +P15 EQU P1 .5; +P14 EQU P1 .4; +P13 EQU P1 .3; +P12 EQU P1 .2; +P11 EQU P1 .1; +P10 EQU P1 .0; + +/******************* P2 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţ +******************************************/ +P27 EQU P2 .7; +P26 EQU P2 .6; +P25 EQU P2 .5; +P24 EQU P2 .4; +P23 EQU P2 .3; +P22 EQU P2 .2; +P21 EQU P2 .1; +P20 EQU P2 .0; + +/******************* P3 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţP3 +******************************************/ +P37 EQU P3 .7; +P36 EQU P3 .6; +P35 EQU P3 .5; +P34 EQU P3 .4; +P33 EQU P3 .3; +P32 EQU P3 .2; +P31 EQU P3 .1; +P30 EQU P3 .0; + +/******************* P4 ****************** +*SC92F74A7װδĹܽţ +*SC92F84A6װδĹܽţP46/P47 +*SC92F84A5װδĹܽţP40 +******************************************/ +P47 EQU P4 .7; +P46 EQU P4 .6; +P45 EQU P4 .5; +P44 EQU P4 .4; +P43 EQU P4 .3; +P42 EQU P4 .2; +P41 EQU P4 .1; +P40 EQU P4 .0; + +/******************* P5 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP54/P55 +*SC92F84A5װδĹܽţP5 +******************************************/ +P55 EQU P5 .5; +P54 EQU P5 .4; +P53 EQU P5 .3; +P52 EQU P5 .2; +P51 EQU P5 .1; +P50 EQU P5 .0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F74A7õú궨塣 +*****************************************************************************/ +SC92F74A6_NIO_Init MACRO IO //SC92F74A6δܽŵIO + ORL P4CON,#0XC0 + ORL P5CON,#0X30 + ENDM +SC92F74A5_NIO_Init MACRO IO //SC92F74A5δܽŵIO + ORL P0CON,#0X01 + ORL P3CON,#0XFF + ORL P4CON,#0X01 + ORL P5CON,#0X3F + ENDM +#endif diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F74Ax_2_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F74Ax_2_C.H new file mode 100644 index 0000000..6356b52 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F74Ax_2_C.H @@ -0,0 +1,296 @@ +/*-------------------------------------------------------------------------- +SC92F74Ax_C.H + +C Header file for SC92F74Ax microcontroller. +Copyright (c) 2020 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2020.07.01 +--------------------------------------------------------------------------*/ +#ifndef _SC92F74Ax_H_ +#define _SC92F74Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMƼĴ + + +// +//*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ +sbit BITIE0 = TCON^1; //INT0ж־ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţP00 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţ +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţP46/P47 +*SC92F74A5װδĹܽţP40 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţP54/P55 +*SC92F74A5װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F74A7õú궨塣 +*****************************************************************************/ +#define SC92F74A6_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F74A6δIO +#define SC92F74A5_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0x3F;} //SC92F74A5δIO +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F754x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F754x_C.H new file mode 100644 index 0000000..fe6f5d3 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F754x_C.H @@ -0,0 +1,313 @@ + /*-------------------------------------------------------------------------- +SC92F754X_C.H + +C Header file for SC92F754X microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2019.03.18 +--------------------------------------------------------------------------*/ +#ifndef _SC92F754X_H_ +#define _SC92F754X_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMüĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*TKCON*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţ +*SC92F7545װδĹܽţP00 +*SC92F7543װδĹܽţP00/P01 +*SC92F7541װδĹܽţP00/P01/P04/P05/P06 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţ +*SC92F7545װδĹܽţ +*SC92F7543װδĹܽţP10/P14/P15/P16/P17 +*SC92F7541װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţ +*SC92F7545װδĹܽţ +*SC92F7543װδĹܽţP26/P27 +*SC92F7541װδĹܽţP24/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţ +*SC92F7545װδĹܽţP3 +*SC92F7543װδĹܽţ +*SC92F7541װδĹܽţP30/P31/P32/P33/P34/P35 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţP46/P47 +*SC92F7545װδĹܽţP40 +*SC92F7543װδĹܽţP40/P44/P45/P46/P47 +*SC92F7541װδĹܽţP4 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţP54/P55 +*SC92F7545װδĹܽţP5 +*SC92F7543װδĹܽţP5 +*SC92F7541װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7547õú궨塣 +*****************************************************************************/ +#define SC92F7546_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F7546δIO +#define SC92F7545_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F7545δIO +#define SC92F7543_NIO_Init() {P0CON|=0x03,P1CON|=0xF1,P2CON|=0xC0,P4CON|=0xF1,P5CON|=0xFF;} //SC92F7543δIO +#define SC92F7541_NIO_Init() {P0CON|=0x73,P1CON|=0xC1,P2CON|=0xF0,P3CON|=0x3F,P4CON|=0xFF,P5CON|=0xFF;} //SC92F7541δIO +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F759x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F759x_C.H new file mode 100644 index 0000000..5ab2301 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F759x_C.H @@ -0,0 +1,297 @@ +/*-------------------------------------------------------------------------- +SC92F859x_C.H + +C Header file for SC92F859x microcontroller. +Copyright (c) 2021 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.1 +: 2021.10.22 +--------------------------------------------------------------------------*/ +#ifndef _SC92F859x_H_ +#define _SC92F859x_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr SP = 0X81; //ջָ +sfr DPL = 0X82; //DPTRָλ +sfr DPH = 0X83; //DPTRָλ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr ACC = 0XE0; //ۼ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 +sfr B = 0XF0; //BĴ + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 +sfr IP = 0XB8; //жȨƼĴ +sfr IP1 = 0XB9; //жȼƼĴ1 + +/*PORT*/ +sfr P0 = 0X80; //P0ݼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr DDRCON = 0X93; //ʾƼĴ +sfr P1VO = 0X94; //P1ʾĴ +sfr IOHCON0 = 0X96; //IOHüĴ0 +sfr IOHCON1 = 0X97; //IOHüĴ1 +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P0VO = 0X9C; //P0LCDѹĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2VO = 0XA3; //P2ʾĴ +sfr P3 = 0XB0; //P3ݼĴ +sfr P3CON = 0XB1; //P3/ƼĴ +sfr P3PH = 0XB2; //P3ƼĴ +sfr P3VO = 0XB3; //P3ʾĴ +sfr P4 = 0XC0; //P4ݼĴ +sfr P4CON = 0XC1; //P4/ƼĴ +sfr P4PH = 0XC2; //P4ƼĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5PH = 0XDA; //P5ƼĴ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*TIMER*/ +sfr TCON = 0X88; //ʱƼĴ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TL0 = 0X8A; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TH1 = 0X8D; //ʱ18λ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ + +/*PWM*/ +sfr PWMCON = 0XD3; //PWM0ƼĴ0 +sfr PWMCFG = 0XD4; //PWMüĴ + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPKEY = 0XF1; //IAPĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADE = 0XF4; //IAPչַĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPCTL = 0XF6; //IAPƼĴ + +/*uart0*/ +sfr OTCON = 0X8F; //ƼĴ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*һ*/ +sfr SSCON2 = 0X95;//SSIƼĴ2 +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSDAT = 0X9F; //SSIݼĴ + +/*OPTION*/ +sfr OPINX = 0XFE; //Customer Optionָ +sfr OPREG = 0XFF; //Customer OptionĴ + +/*CRC*/ +sfr OPERCON = 0XEF; //ƼĴ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; //ʱ2־λ +sbit EXF2 = T2CON^6; //T2EXⲿ¼(½)⵽ı־λ +sbit RCLK = T2CON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLK = T2CON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXEN2 = T2CON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TR2 = T2CON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit T2 = T2CON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = T2CON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + + +/******************* P0 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţP00 +*SC92F8593װδĹܽţP00/P01 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţ +*SC92F8593װδĹܽţP10/P14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţ +*SC92F8593װδĹܽţP26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţP3 +*SC92F8593װδĹܽţ +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţP46/P47 +*SC92F8595װδĹܽţP40 +*SC92F8593װδĹܽţP40/P44/P45/P46/P47 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţP54/P55 +*SC92F8595װδĹܽţP5 +*SC92F8593װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8597õú궨塣 +*****************************************************************************/ +#define SC92F8596_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F8596δIO +#define SC92F8595_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F8595δIO +#define SC92F8593_NIO_Init() {P0CON|=0x03,P1CON|=0xF1,P2CON|=0xC0,P4CON|=0xF1,P5CON|=0xFF;}//SC92F8593δIO + + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F8003_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F8003_C.H new file mode 100644 index 0000000..d8e44f1 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F8003_C.H @@ -0,0 +1,207 @@ + /*-------------------------------------------------------------------------- +SC92F8003_C.H + +C Header file for SC92F8003 microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.05.02 +--------------------------------------------------------------------------*/ +#ifndef _SC92F8003_H_ +#define _SC92F8003_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG1 = 0xAA; //ADCüĴ0 +sfr ADCCFG0 = 0xAB; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON0 = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMCON1 = 0xDA; //PWMƼĴ +sfr PWMDTYB = 0xDB; //PWMռձüĴB +sfr PWMDTY3 = 0xDC; //PWM3üĴ +sfr PWMDTY4 = 0xDD; //PWM4üĴ +sfr PWMDTY5 = 0xDE; //PWM5üĴ +sfr PWMDTY6 = 0xDF; //PWM6üĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +sfr OTCON = 0X8F; //ƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //uartƼĴ +sfr SBUF = 0X99; //uart0ݼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSCON2 = 0X95; //SSIƼĴ2 +sfr SSDAT = 0X9F; //SSIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //PWMжȿλ 0:趨 PWMжȨ ͡ 1:趨 PWM жȨ ߡ +sbit IPUART = IP^4; //SIFжȿλ 0:趨 SIFжȨ ͡ 1:趨 SIFжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //32K Base Timerжȿλ 0:趨 32KжȨ ͡ 1:趨 32KжȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //PWMжʹܿ 0:رPWMж 1:PWMж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //32K Base Timerжʹܿ 0:ر32Kж 1:32Kж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //TouchKeyжʹܿ 0:رTouchKeyж 1:TouchKeyж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/* P0 */ +sbit P01 = P0^1; +sbit P00 = P0^0; + +/* P1 */ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/* P2 */ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F827X_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F827X_C.H new file mode 100644 index 0000000..8f6faa5 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F827X_C.H @@ -0,0 +1,195 @@ + /*-------------------------------------------------------------------------- +SC92F827x_C.H + +C Header file for SC92F827x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.04.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F827x_H_ +#define _SC92F827x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTY3 = 0xD4; //PWM3ռձüĴ +sfr PWMDTY0 = 0xD5; //PWM0ռձüĴ +sfr PWMDTY1 = 0xD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0xD7; //PWM2ռձüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*TKCON*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/******************* P0 ****************** +*SC92F8272װδĹܽţ +*SC92F8271װδĹܽţP02/P03/P04 +*SC92F8270װδĹܽţP00/P02/P03/P04/P05 +******************************************/ +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8272װδĹܽţ +*SC92F8271װδĹܽţ +*SC92F8270װδĹܽţP11/P14/P15 +******************************************/ +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8272װδĹܽţ +*SC92F8271װδĹܽţP27 +*SC92F8270װδĹܽţP24/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8272õú궨塣 +*****************************************************************************/ +#define SC92F8271_NIO_Init() {P0CON|=0x1C,P2CON|=0x80;} //SC92F8271δIO +#define SC92F8270_NIO_Init() {P0CON|=0x3D,P1CON|=0x32,P2CON|=0xF0;} //SC92F8270δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F836xB_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F836xB_C.H new file mode 100644 index 0000000..b0dcdef --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F836xB_C.H @@ -0,0 +1,251 @@ + /*-------------------------------------------------------------------------- +SC92F836XB_C.H + +C Header file for SC92F836XB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2018.08.24 +--------------------------------------------------------------------------*/ +#ifndef _SC92F836XB_H_ +#define _SC92F836XB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F8363BװδĹܽţ +*SC92F8362BװδĹܽţP06/P07 +*SC92F8361BװδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8363BװδĹܽţ +*SC92F8362BװδĹܽţP16/P17 +*SC92F8361BװδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8363BװδĹܽţ +*SC92F8362BװδĹܽţP22/P23 +*SC92F8361BװδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F8363BװδĹܽţ +*SC92F8362BװδĹܽţP50/P51 +*SC92F8361BװδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8363Bõú궨塣 +*****************************************************************************/ +#define SC92F8362B_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F8362BδIO +#define SC92F8361B_NIO_Init() {P0CON|=0xEC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F8361BδIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F837X_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F837X_C.H new file mode 100644 index 0000000..8da7e43 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F837X_C.H @@ -0,0 +1,199 @@ + /*-------------------------------------------------------------------------- +SC92F837x_C.H + +C Header file for SC92F837x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.03.06 +--------------------------------------------------------------------------*/ +#ifndef _SC92F837x_H_ +#define _SC92F837x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTY3 = 0xD4; //PWM3ռձüĴ +sfr PWMDTY0 = 0xD5; //PWM0ռձüĴ +sfr PWMDTY1 = 0xD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0xD7; //PWM2ռձüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*TKCON*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/******************* P0 ****************** +*SC92F8378װδĹܽţP02/P03/P04/P05 +*SC92F8372װδĹܽţ +*SC92F8371װδĹܽţP02/P03/P04 +*SC92F8370װδĹܽţP00/P02/P03/P04/P05 +******************************************/ +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8378װδĹܽţP11/P15 +*SC92F8372װδĹܽţ +*SC92F8371װδĹܽţ +*SC92F8370װδĹܽţP11/P14/P15 +******************************************/ +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8378װδĹܽţP24/P25/P26/P27 +*SC92F8372װδĹܽţ +*SC92F8371װδĹܽţP27 +*SC92F8370װδĹܽţP24/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8372õú궨塣 +*****************************************************************************/ +#define SC92F8378_NIO_Init() {P0CON|=0x3C,P1CON|=0x22,P2CON|=0xF0;} //SC92F8378δIO +#define SC92F8371_NIO_Init() {P0CON|=0x1C,P2CON|=0x80;} //SC92F8371δIO +#define SC92F8370_NIO_Init() {P0CON|=0x3D,P1CON|=0x32,P2CON|=0xF0;} //SC92F8370δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F844xB_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F844xB_C.H new file mode 100644 index 0000000..0358107 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F844xB_C.H @@ -0,0 +1,294 @@ +/*-------------------------------------------------------------------------- +SC92F844xB_C.H + +C Header file for SC92F844xB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.09.04 +--------------------------------------------------------------------------*/ +#ifndef _SC92F844xB_H_ +#define _SC92F844xB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMƼĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţ +*SC92F8445BװδĹܽţP00 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţ +*SC92F8445BװδĹܽţ +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţ +*SC92F8445BװδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţ +*SC92F8445BװδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţP46/P47 +*SC92F8445BװδĹܽţP40 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţP54/P55 +*SC92F8445BװδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8447Bõú궨塣 +*****************************************************************************/ +#define SC92F8446B_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F8546BδIO +#define SC92F8445B_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F8545BδIO +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F846xB_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F846xB_C.H new file mode 100644 index 0000000..6b09632 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F846xB_C.H @@ -0,0 +1,251 @@ + /*-------------------------------------------------------------------------- +SC92F846XB_C.H + +C Header file for SC92F846XB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2018.08.24 +--------------------------------------------------------------------------*/ +#ifndef _SC92F846XB_H_ +#define _SC92F846XB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F8463BװδĹܽţ +*SC92F8462BװδĹܽţP06/P07 +*SC92F8461BװδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8463BװδĹܽţ +*SC92F8462BװδĹܽţP16/P17 +*SC92F8461BװδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8463BװδĹܽţ +*SC92F8462BװδĹܽţP22/P23 +*SC92F8461BװδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F8463BװδĹܽţ +*SC92F8462BװδĹܽţP50/P51 +*SC92F8461BװδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8463Bõú궨塣 +*****************************************************************************/ +#define SC92F8462B_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F8462BδIO +#define SC92F8461B_NIO_Init() {P0CON|=0xEC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F8461BδIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F848x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F848x_C.H new file mode 100644 index 0000000..df073b7 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F848x_C.H @@ -0,0 +1,254 @@ +/*-------------------------------------------------------------------------- +SC92F848x_C.H + +C Header file for SC92F848x microcontroller. +Copyright (c) 2021 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.2 +: 2021.07.14 +--------------------------------------------------------------------------*/ +#ifndef _SC92F848x_H_ +#define _SC92F848x_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr ACC = 0XE0; //ۼ +sfr B = 0XF0; //BĴ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr DPH = 0X83; //DPTRָλ +sfr DPL = 0X82; //DPTRָλ +sfr SP = 0X81; //ջָ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0XB8; //жȨƼĴ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr IOHCON = 0X97; //IOHüĴ +sfr P5PH = 0XDA; //P5ƼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P0VO = 0X9C; //P0LCDѹĴ +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0 = 0X80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr TH1 = 0X8D; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TL0 = 0X8A; //ʱ08λ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TCON = 0X88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ + +/*PWM*/ +sfr PWMCFG = 0XD1; //PWMüĴ +sfr PWMCON = 0XD2; //PWMƼĴ +sfr PWMPRD = 0XD3; //PWMüĴ +sfr PWMDTYA = 0XD4; //PWMռձüĴA +sfr PWMDTY0 = 0XD5; //PWM0üĴ +sfr PWMDTY1 = 0XD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0XD7; //PWM2ռձüĴ +sfr PWMDTYB = 0XDC; //PWMռձüĴB +sfr PWMDTY3 = 0XDD; //PWM3ռձüĴ/PWMʱüĴ +sfr PWMDTY4 = 0XDE; //PWM4ռձüĴ +sfr PWMDTY5 = 0XDF; //PWM5ռձüĴ + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0XF6; //IAPƼĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPADE = 0XF4; //IAPչַĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPKEY = 0XF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ +sfr OTCON = 0X8F; //ƼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //USCIƼĴ0 +sfr SSCON1 = 0X9E; //USCIƼĴ1 +sfr SSCON2 = 0X95; //USCIƼĴ2 +sfr SSDAT = 0X9F; //USCIݼĴ3 + +/*OPTION*/ +sfr OPINX = 0XFE; //Customer Optionָ +sfr OPREG = 0XFF; //Customer OptionĴ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ +sfr OPERCON = 0XEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; //ʱ2־λ +sbit EXF2 = T2CON^6; //T2EXⲿ¼(½)⵽ı־λ +sbit RCLK = T2CON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLK = T2CON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXEN2 = T2CON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TR2 = T2CON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit T2 = T2CON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = T2CON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + +/******************* P0 ****************** +*SC92F8483װδĹܽţ +*SC92F8482װδĹܽţP06/P07 +*SC92F8481װδĹܽţP02/P03/P04/P05/P06/P07 +*SC92F8480װδĹܽţP0 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8483װδĹܽţ +*SC92F8482װδĹܽţP16/P17 +*SC92F8481װδĹܽţP16/P17 +*SC92F8480װδĹܽţP14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8483װδĹܽţ +*SC92F8482װδĹܽţP22/P23 +*SC92F8481װδĹܽţP22/P23/P27 +*SC92F8480װδĹܽţP22/P23/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F8483װδĹܽţ +*SC92F8482װδĹܽţP50/P51 +*SC92F8481װδĹܽţP50/P51 +*SC92F8480װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8483õú궨塣 +*****************************************************************************/ +#define SC92F8482_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;}//SC92F8482δIO +#define SC92F8481_NIO_Init() {P0CON|=0xFC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;}//SC92F8481δIO +#define SC92F8480_NIO_Init() {P0CON|=0xFF,P1CON|=0xF0,P2CON|=0xEC,P5CON|=0x03;}//SC92F8480δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F84Ax_2_ASM.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F84Ax_2_ASM.H new file mode 100644 index 0000000..6a83914 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F84Ax_2_ASM.H @@ -0,0 +1,294 @@ +/*-------------------------------------------------------------------------- +SC92F84Ax_ASM.H + +ASM Header file for SC92F84Ax microcontroller. +Copyright (c) 2020 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2020.07.01 + + +--------------------------------------------------------------------------*/ +#ifndef _SC92F84Ax_ASM_H_ +#define _SC92F84Ax_ASM_H_ + +/* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +ACC EQU 0xE0; //ۼ +B EQU 0xF0; //ͨüĴB +PSW EQU 0xD0; //״̬ +DPH EQU 0x83; //ָ8λ +DPL EQU 0x82; //ָ8λ +SP EQU 0x81; //ջָ + +/*system*/ +PCON EQU 0x87; //ԴƼĴ + +/*interrupt*/ +IP EQU 0xB8; //жȨƼĴ +IE EQU 0xA8; //жϿƼĴ +IP1 EQU 0XB9; //жȼƼĴ1 +IE1 EQU 0XA9; //жϿƼĴ1 + +/*PORT*/ +P5PH EQU 0xDA; //P5ģʽƼĴ +P5CON EQU 0xD9; //P5ģʽƼĴ +P5 EQU 0xD8; //P5ݼĴ +P4PH EQU 0xC2; //P4ģʽƼĴ +P4CON EQU 0xC1; //P4ģʽƼĴ +P4 EQU 0xC0; //P4ݼĴ +P3PH EQU 0xB2; //P3ģʽƼĴ +P3CON EQU 0xB1; //P3ģʽƼĴ +P3 EQU 0xB0; //P3ݼĴ +P2PH EQU 0xA2; //P2ģʽƼĴ +P2CON EQU 0xA1; //P2ģʽƼĴ +P2 EQU 0xA0; //P2ݼĴ +P1PH EQU 0x92; //P1ģʽƼĴ +P1CON EQU 0x91; //P1ģʽƼĴ +P1 EQU 0x90; //P1ݼĴ +P0PH EQU 0x9B; //P0ģʽƼĴ +P0CON EQU 0x9A; //P0ģʽƼĴ +P0 EQU 0x80; //P0ݼĴ +IOHCON0 EQU 0x96; //IOH0üĴ +IOHCON1 EQU 0x97; //IOH1üĴ + +/*TIMER*/ +TMCON EQU 0x8E; //ʱƵʿƼĴ +TH1 EQU 0x8D; //ʱ18λ +TH0 EQU 0x8C; //ʱ08λ +TL1 EQU 0x8B; //ʱ18λ +TL0 EQU 0x8A; //ʱ08λ +TMOD EQU 0x89; //ʱģʽĴ +TCON EQU 0x88; //ʱƼĴ +T2CON EQU 0XC8; //ʱ2ƼĴ +T2MOD EQU 0XC9; //ʱ2ģʽĴ +RCAP2L EQU 0XCA; //ʱ2/׽8λ +RCAP2H EQU 0XCB; //ʱ2/׽8λ +TL2 EQU 0XCC; //ʱ28λ +TH2 EQU 0XCD; //ʱ28λ + +/*ADC*/ +ADCCFG0 EQU 0xAB; //ADCüĴ0 +ADCCFG1 EQU 0xAC; //ADCüĴ1 +ADCCFG2 EQU 0xAA; //ADCüĴ2 +ADCCON EQU 0XAD; //ADCƼĴ +ADCVL EQU 0xAE; //ADC Ĵ +ADCVH EQU 0xAF; //ADC Ĵ + +/*PWM*/ +PWMCFG EQU 0xD4; //PWMüĴ +PWMCON EQU 0xD3; //PWMƼĴ + +/*WatchDog*/ +BTMCON EQU 0XCE; //ƵʱƼĴ +WDTCON EQU 0xCF; //WDTƼĴ + +/*LCD*/ +OTCON EQU 0X8F; //LCDѹƼĴ +P0VO EQU 0X9C; //P0 LCD Bais Ĵ +P1VO EQU 0X94; //P1 LCD Bais Ĵ +P2VO EQU 0XA3; //P2 LCD Bais Ĵ +P3VO EQU 0XB3; //P3 LCD Bais Ĵ + +DDRCON EQU 0X93; //ʾüĴ + +/*INT*/ +INT0F EQU 0XBA; //INT0 ½жϿƼĴ +INT0R EQU 0XBB; //INT0 ϽжϿƼĴ +INT1F EQU 0XBC; //INT1 ½жϿƼĴ +INT1R EQU 0XBD; //INT1 ϽжϿƼĴ +INT2F EQU 0XC6; //INT2 ½жϿƼĴ +INT2R EQU 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +IAPCTL EQU 0xF6; //IAPƼĴ +IAPDAT EQU 0xF5; //IAPݼĴ +IAPADE EQU 0xF4; //IAPչַĴ +IAPADH EQU 0xF3; //IAPдַλĴ +IAPADL EQU 0xF2; //IAPдַ8λĴ +IAPKEY EQU 0xF1; //IAPĴ + +/*uart*/ +SCON EQU 0x98; //ڿƼĴ +SBUF EQU 0x99; //ݻĴ + +/*һ*/ +SSCON0 EQU 0X9D; //SSIƼĴ0 +SSCON1 EQU 0X9E; //SSIƼĴ1 +SSCON2 EQU 0X95; //SSIƼĴ2 +SSDAT EQU 0X9F; //SPIݼĴ + +OPINX EQU 0XFE; +OPREG EQU 0XFF; +EXADH EQU 0XF7; + +/*Check Sum*/ +CHKSUML EQU 0XFC; //Check SumĴλ +CHKSUMH EQU 0XFD; //Check SumĴλ + +/*˳*/ +EXA0 EQU 0xE9; //չۼ0 +EXA1 EQU 0xEA; //չۼ1 +EXA2 EQU 0xEB; //չۼ2 +EXA3 EQU 0xEC; //չۼ3 +EXBL EQU 0xED; //չBĴ0 +EXBH EQU 0xEE; //չBĴ1 +OPERCON EQU 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +CY EQU PSW .7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +AC EQU PSW .6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +F0 EQU PSW .5; //û־λ +RS1 EQU PSW .4; //Ĵѡλ +RS0 EQU PSW .3; //Ĵѡλ +OV EQU PSW .2; //־λ +F1 EQU PSW .1; //F1־ +P EQU PSW .0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +TF2 EQU T2CON .7; +EXF2 EQU T2CON .6; +RCLK EQU T2CON .5; +TCLK EQU T2CON .4; +EXEN2 EQU T2CON .3; +TR2 EQU T2CON .2; +T2 EQU T2CON .1; +CP EQU T2CON .0; + +/*IP*/ +IPADC EQU IP .6; //ADCжȿλ 0:趨ADCжȨ ͡ 1:趨ADCжȨ ߡ +IPT2 EQU IP .5; //PWMжȿλ 0:趨PWMжȨ ͡ 1:趨PWM жȨ ߡ +IPUART EQU IP .4; //Uartжȿλ 0:趨UartжȨ ͡ 1:趨UartжȨ ߡ +IPT1 EQU IP .3; //Timer1жȿλ 0:趨Timer1жȨ ͡ 1:趨Timer1жȨ ߡ +IPINT1 EQU IP .2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +IPT0 EQU IP .1; //Timer0жȿλ 0:趨Timer0жȨ ͡ 1:趨Timer0жȨ ߡ +IPINT0 EQU IP .0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +EA EQU IE .7; //жʹܵܿ 0:رеж 1:еж +EADC EQU IE .6; //ADCжʹܿ 0:رADCж 1:ADCж +ET2 EQU IE .5; //PWMжʹܿ 0:رPWMж 1:PWMж +EUART EQU IE .4; //UARTжʹܿ 0:رUARTж 1:UARTж +ET1 EQU IE .3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +EINT1 EQU IE .2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +ET0 EQU IE .1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +EINT0 EQU IE .0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +TF1 EQU TCON .7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +TR1 EQU TCON .6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +TF0 EQU TCON .5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +TR0 EQU TCON .4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +BITIE1 EQU TCON .3; //INT1ж־ +BITIE0 EQU TCON .1; //INT0ж־ + +/*SCON*/ +SM0 EQU SCON .7; +SM1 EQU SCON .6; +SM2 EQU SCON .5; +REN EQU SCON .4; +TB8 EQU SCON .3; +RB8 EQU SCON .2; +TI EQU SCON .1; +RI EQU SCON .0; + +/******************* P0 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţP00 +******************************************/ +P07 EQU P0 .7; +P06 EQU P0 .6; +P05 EQU P0 .5; +P04 EQU P0 .4; +P03 EQU P0 .3; +P02 EQU P0 .2; +P01 EQU P0 .1; +P00 EQU P0 .0; + +/******************* P1 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţ +******************************************/ +P17 EQU P1 .7; +P16 EQU P1 .6; +P15 EQU P1 .5; +P14 EQU P1 .4; +P13 EQU P1 .3; +P12 EQU P1 .2; +P11 EQU P1 .1; +P10 EQU P1 .0; + +/******************* P2 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţ +******************************************/ +P27 EQU P2 .7; +P26 EQU P2 .6; +P25 EQU P2 .5; +P24 EQU P2 .4; +P23 EQU P2 .3; +P22 EQU P2 .2; +P21 EQU P2 .1; +P20 EQU P2 .0; + +/******************* P3 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţP3 +******************************************/ +P37 EQU P3 .7; +P36 EQU P3 .6; +P35 EQU P3 .5; +P34 EQU P3 .4; +P33 EQU P3 .3; +P32 EQU P3 .2; +P31 EQU P3 .1; +P30 EQU P3 .0; + +/******************* P4 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP46/P47 +*SC92F84A5װδĹܽţP40 +******************************************/ +P47 EQU P4 .7; +P46 EQU P4 .6; +P45 EQU P4 .5; +P44 EQU P4 .4; +P43 EQU P4 .3; +P42 EQU P4 .2; +P41 EQU P4 .1; +P40 EQU P4 .0; + +/******************* P5 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP54/P55 +*SC92F84A5װδĹܽţP5 +******************************************/ +P55 EQU P5 .5; +P54 EQU P5 .4; +P53 EQU P5 .3; +P52 EQU P5 .2; +P51 EQU P5 .1; +P50 EQU P5 .0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F84A7õú궨塣 +*****************************************************************************/ +SC92F84A6_NIO_Init MACRO IO //SC92F84A6δܽŵIO + ORL P4CON,#0XC0 + ORL P5CON,#0X30 + ENDM +SC92F84A5_NIO_Init MACRO IO //SC92F84A5δܽŵIO + ORL P0CON,#0X01 + ORL P3CON,#0XFF + ORL P4CON,#0X01 + ORL P5CON,#0X3F + ENDM +#endif diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F84Ax_2_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F84Ax_2_C.H new file mode 100644 index 0000000..ade8ddb --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F84Ax_2_C.H @@ -0,0 +1,296 @@ +/*-------------------------------------------------------------------------- +SC92F84Ax_C.H + +C Header file for SC92F84Ax microcontroller. +Copyright (c) 2020 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2020.07.01 +--------------------------------------------------------------------------*/ +#ifndef _SC92F84Ax_H_ +#define _SC92F84Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMƼĴ + + +// +//*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ +sbit BITIE0 = TCON^1; //INT0ж־ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţP00 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţ +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP46/P47 +*SC92F84A5װδĹܽţP40 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP54/P55 +*SC92F84A5װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F84A7õú궨塣 +*****************************************************************************/ +#define SC92F84A6_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F84A6δIO +#define SC92F84A5_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0x3F;} //SC92F84A5δIO +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F854x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F854x_C.H new file mode 100644 index 0000000..1ca0703 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F854x_C.H @@ -0,0 +1,320 @@ + /*-------------------------------------------------------------------------- +SC92F854X_C.H + +C Header file for SC92F854X microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.10.09 +--------------------------------------------------------------------------*/ +#ifndef _SC92F854X_H_ +#define _SC92F854X_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMüĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*TKCON*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţ +*SC92F8545װδĹܽţP00 +*SC92F8543װδĹܽţP00/P01 +*SC92F8542װδĹܽţP00/P01/P04/P05 +*SC92F8541װδĹܽţP00/P01/P04/P05/P06 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţ +*SC92F8545װδĹܽţ +*SC92F8543װδĹܽţP10/P14/P15/P16/P17 +*SC92F8542װδĹܽţP14/P15/P16/P17 +*SC92F8541װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţ +*SC92F8545װδĹܽţ +*SC92F8543װδĹܽţP26/P27 +*SC92F8542װδĹܽţP26/P27 +*SC92F8541װδĹܽţP24/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţ +*SC92F8545װδĹܽţP3 +*SC92F8543װδĹܽţ +*SC92F8542װδĹܽţP3 +*SC92F8541װδĹܽţP30/P31/P32/P33/P34/P35 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţP46/P47 +*SC92F8545װδĹܽţP40 +*SC92F8543װδĹܽţP40/P44/P45/P46/P47 +*SC92F8542װδĹܽţP44/P45/P46/P47 +*SC92F8541װδĹܽţP4 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţP54/P55 +*SC92F8545װδĹܽţP5 +*SC92F8543װδĹܽţP5 +*SC92F8542װδĹܽţP5 +*SC92F8541װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8547õú궨塣 +*****************************************************************************/ +#define SC92F8546_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F8546δIO +#define SC92F8545_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F8545δIO +#define SC92F8543_NIO_Init() {P0CON|=0x03,P1CON|=0xF1,P2CON|=0xC0,P4CON|=0xF1,P5CON|=0xFF;} //SC92F8543δIO +#define SC92F8542_NIO_Init() {P0CON|=0x33,P1CON|=0xF0,P2CON|=0xC0,P3CON|=0xFF,P4CON|=0xF0,P5CON|=0xFF;} //SC92F8542δIO +#define SC92F8541_NIO_Init() {P0CON|=0x73,P1CON|=0xC1,P2CON|=0xF0,P3CON|=0x3F,P4CON|=0xFF,P5CON|=0xFF;} //SC92F8541δIO +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F859x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F859x_C.H new file mode 100644 index 0000000..5ab2301 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92F859x_C.H @@ -0,0 +1,297 @@ +/*-------------------------------------------------------------------------- +SC92F859x_C.H + +C Header file for SC92F859x microcontroller. +Copyright (c) 2021 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.1 +: 2021.10.22 +--------------------------------------------------------------------------*/ +#ifndef _SC92F859x_H_ +#define _SC92F859x_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr SP = 0X81; //ջָ +sfr DPL = 0X82; //DPTRָλ +sfr DPH = 0X83; //DPTRָλ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr ACC = 0XE0; //ۼ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 +sfr B = 0XF0; //BĴ + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 +sfr IP = 0XB8; //жȨƼĴ +sfr IP1 = 0XB9; //жȼƼĴ1 + +/*PORT*/ +sfr P0 = 0X80; //P0ݼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr DDRCON = 0X93; //ʾƼĴ +sfr P1VO = 0X94; //P1ʾĴ +sfr IOHCON0 = 0X96; //IOHüĴ0 +sfr IOHCON1 = 0X97; //IOHüĴ1 +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P0VO = 0X9C; //P0LCDѹĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2VO = 0XA3; //P2ʾĴ +sfr P3 = 0XB0; //P3ݼĴ +sfr P3CON = 0XB1; //P3/ƼĴ +sfr P3PH = 0XB2; //P3ƼĴ +sfr P3VO = 0XB3; //P3ʾĴ +sfr P4 = 0XC0; //P4ݼĴ +sfr P4CON = 0XC1; //P4/ƼĴ +sfr P4PH = 0XC2; //P4ƼĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5PH = 0XDA; //P5ƼĴ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*TIMER*/ +sfr TCON = 0X88; //ʱƼĴ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TL0 = 0X8A; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TH1 = 0X8D; //ʱ18λ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ + +/*PWM*/ +sfr PWMCON = 0XD3; //PWM0ƼĴ0 +sfr PWMCFG = 0XD4; //PWMüĴ + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPKEY = 0XF1; //IAPĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADE = 0XF4; //IAPչַĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPCTL = 0XF6; //IAPƼĴ + +/*uart0*/ +sfr OTCON = 0X8F; //ƼĴ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*һ*/ +sfr SSCON2 = 0X95;//SSIƼĴ2 +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSDAT = 0X9F; //SSIݼĴ + +/*OPTION*/ +sfr OPINX = 0XFE; //Customer Optionָ +sfr OPREG = 0XFF; //Customer OptionĴ + +/*CRC*/ +sfr OPERCON = 0XEF; //ƼĴ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; //ʱ2־λ +sbit EXF2 = T2CON^6; //T2EXⲿ¼(½)⵽ı־λ +sbit RCLK = T2CON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLK = T2CON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXEN2 = T2CON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TR2 = T2CON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit T2 = T2CON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = T2CON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + + +/******************* P0 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţP00 +*SC92F8593װδĹܽţP00/P01 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţ +*SC92F8593װδĹܽţP10/P14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţ +*SC92F8593װδĹܽţP26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţP3 +*SC92F8593װδĹܽţ +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţP46/P47 +*SC92F8595װδĹܽţP40 +*SC92F8593װδĹܽţP40/P44/P45/P46/P47 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţP54/P55 +*SC92F8595װδĹܽţP5 +*SC92F8593װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8597õú궨塣 +*****************************************************************************/ +#define SC92F8596_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F8596δIO +#define SC92F8595_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F8595δIO +#define SC92F8593_NIO_Init() {P0CON|=0x03,P1CON|=0xF1,P2CON|=0xC0,P4CON|=0xF1,P5CON|=0xFF;}//SC92F8593δIO + + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92FWxx_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92FWxx_C.H new file mode 100644 index 0000000..815b979 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92FWxx_C.H @@ -0,0 +1,286 @@ + /*-------------------------------------------------------------------------- +SC92FWxx_C.H + +C Header file for SC92FWxx microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.10.09 +--------------------------------------------------------------------------*/ +#ifndef _SC92FWxx_H_ +#define _SC92FWxx_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD2; //PWM0üĴ +sfr PWMCON0 = 0xD1; //PWM0ƼĴ +sfr PWMCFG1 = 0xD4; //PWM1üĴ +sfr PWMCON1 = 0xD3; //PWM1üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +sfr OTCON = 0X8F; //ƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP04/P05/P06/P07 +*SC92FW16װδĹܽţP00/P01/P04/P05 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP10/P12/P14/P15/P16/P17 +*SC92FW16װδĹܽţP14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP26/P27 +*SC92FW16װδĹܽţP26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP34/P35/P36/P37 +*SC92FW16װδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP46/P47 +*SC92FW16װδĹܽţP44/P45/P46/P47 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP54/P55 +*SC92FW16װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92FW40õú궨塣 +*****************************************************************************/ +#define SC92FW24_NIO_Init() {P0CON|=0xF0,P1CON|=0xF5,P2CON|=0xC0,P3CON|=0xF0,P4CON|=0xC0,P5CON|=0xF0;} //SC92FW24δIO +#define SC92FW16_NIO_Init() {P0CON|=0x33,P1CON|=0xF0,P2CON|=0xC0,P3CON|=0xFF,P4CON|=0xF0,P5CON|=0xFF;} //SC92FW16δIO +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92L753x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92L753x_C.H new file mode 100644 index 0000000..15aba03 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92L753x_C.H @@ -0,0 +1,277 @@ +/*-------------------------------------------------------------------------- +SC92L753x_C.H + +C Header file for SC92L853x microcontroller. +Copyright (c) 2022 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V0.1 +: 2022.01.18 +--------------------------------------------------------------------------*/ +#ifndef _SC92L753x_C_H_ +#define _SC92L753x_C_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr SP = 0X81; //ջָ +sfr DPL = 0X82; //DPTRָλ +sfr DPH = 0X83; //DPTRָλ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr ACC = 0XE0; //ۼ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 +sfr B = 0XF0; //BĴ + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 +sfr IE2 = 0XAA; //жʹܼĴ2 +sfr IP = 0XB8; //жȨƼĴ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP2 = 0XBA; //жȼƼĴ2 + +/*PORT*/ +sfr P0 = 0X80; //P0ݼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr P1VO = 0X93; //P1ʾĴ +sfr P0VO = 0X94; //P0LCDѹĴ +sfr DDRCON = 0X95; //ʾƼĴ +sfr IOHCON0 = 0X96; //IOHüĴ0 +sfr IOHCON1 = 0X97; //IOHüĴ1 +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2VO = 0XA3; //P2ʾĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5PH = 0XDA; //P5ƼĴ +sfr P5VO = 0XDB; //P5ʾĴ + + +/*TIMER*/ +sfr TCON = 0X88; //ʱƼĴ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TL0 = 0X8A; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TH1 = 0X8D; //ʱ18λ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr TXCON = 0XC8; //ʱ2/3/4ƼĴ +sfr TXMOD = 0XC9; //ʱ2/3/4ģʽĴ +sfr RCAPXL = 0XCA; //ʱ2/3/4/׽8λ +sfr RCAPXH = 0XCB; //ʱ2/3/4/׽8λ +sfr TLX = 0XCC; //ʱ2/3/48λ +sfr THX = 0XCD; //ʱ2/3/48λ +sfr TXINX = 0XCE; //ʱƼĴָ + +/*ADC*/ +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ +sfr ADCCFG2 = 0XB5; //ADCüĴ2 + +/*PWM*/ +sfr PWMCFG = 0XD1; //PWMüĴ +sfr PWMCON0 = 0XD2; //PWMƼĴ0 +sfr PWMCON1 = 0XD3; //PWMƼĴ1 +sfr PWMPDL = 0XD4; //PWMڼĴ8λ +sfr PWMPDH = 0XD5; //PWMڼĴ8λ +sfr PWMDFR = 0XD6; //PWMüĴ +sfr PWMFLT = 0XD7; //PWMϼüĴ + +/*LPD*/ +sfr LPDCFG = 0XB7; //LPD + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XFB; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XB4; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XBE; //INT2 ½жϿƼĴ +sfr INT2R = 0XBF; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPKEY = 0XF1; //IAPĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADE = 0XF4; //IAPдչַĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPCTL = 0XF6; //IAPƼĴ + +/*uart0*/ +sfr OTCON = 0X8F; //ƼĴ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*һ*/ +sfr US0CON0 = 0X9C; //USCI0ƼĴ0 +sfr US0CON1 = 0X9D; //USCI0ƼĴ1 +sfr US0CON2 = 0X9E; //USCI0ƼĴ2 +sfr US0CON3 = 0X9F; //USCI0ƼĴ3 +sfr US1CON0 = 0XA4; //USCI1ƼĴ0 +sfr US1CON1 = 0XA5; //USCI1ƼĴ1 +sfr US1CON2 = 0XA6; //USCI1ƼĴ2 +sfr US1CON3 = 0XA7; //USCI1ƼĴ3 +sfr US2CON0 = 0XC4; //USCI2ƼĴ0 +sfr US2CON1 = 0XC5; //USCI2ƼĴ1 +sfr US2CON2 = 0XC6; //USCI2ƼĴ2 +sfr US2CON3 = 0XC7; //USCI2ƼĴ3 + +/*OPTION*/ +sfr OPINX = 0XFE; //Optionָ +sfr OPREG = 0XFF; //OptionĴ + +/*CRC*/ +sfr OPERCON = 0XEF; //ƼĴ +sfr CRCINX = 0XFC; //CRCָ +sfr CRCREG = 0XFD; //CRCĴ + + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*TXCON*/ +sbit TFX = TXCON^7; //ʱ2/3/4־λ +sbit EXFX = TXCON^6; //TnEXn=2/3/4ⲿ¼(½)⵽ı־λ +sbit RCLKX = TXCON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLKX = TXCON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXENX = TXCON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TRX = TXCON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit TX = TXCON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = TXCON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + + +/******************* P0 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţP06/P07 +*SC92L8531װδĹܽţP02/P03/P04/P06/P07 +***********************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţ +*SC92L8531װδĹܽţ +***********************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţ +*SC92L8531װδĹܽţP22/P23/P27 +***********************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + + +/******************* P5 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţP52/P53/P54/P55 +*SC92L8532װδĹܽţP5 +*SC92L8531װδĹܽţP5 +***********************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92L7535õú궨塣 +*****************************************************************************/ +#define SC92L7533_NIO_Init() {P5CON|=0x3C;} //SC92L8533δIO +#define SC92L7532_NIO_Init() {P0CON|=0xC0,P5CON|=0x3F;} //SC92L8532δIO +#define SC92L7531_NIO_Init() {P0CON|=0xDC,P2CON|=0X8C,P5CON|=0x3F;} //SC92L8531δIO +#endif diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92L853x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92L853x_C.H new file mode 100644 index 0000000..857cfa5 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92L853x_C.H @@ -0,0 +1,277 @@ +/*-------------------------------------------------------------------------- +SC92L853x_C.H + +C Header file for SC92L853x microcontroller. +Copyright (c) 2022 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V0.1 +: 2022.01.18 +--------------------------------------------------------------------------*/ +#ifndef _SC92L853x_C_H_ +#define _SC92L853x_C_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr SP = 0X81; //ջָ +sfr DPL = 0X82; //DPTRָλ +sfr DPH = 0X83; //DPTRָλ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr ACC = 0XE0; //ۼ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 +sfr B = 0XF0; //BĴ + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 +sfr IE2 = 0XAA; //жʹܼĴ2 +sfr IP = 0XB8; //жȨƼĴ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP2 = 0XBA; //жȼƼĴ2 + +/*PORT*/ +sfr P0 = 0X80; //P0ݼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr P1VO = 0X93; //P1ʾĴ +sfr P0VO = 0X94; //P0LCDѹĴ +sfr DDRCON = 0X95; //ʾƼĴ +sfr IOHCON0 = 0X96; //IOHüĴ0 +sfr IOHCON1 = 0X97; //IOHüĴ1 +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2VO = 0XA3; //P2ʾĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5PH = 0XDA; //P5ƼĴ +sfr P5VO = 0XDB; //P5ʾĴ + + +/*TIMER*/ +sfr TCON = 0X88; //ʱƼĴ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TL0 = 0X8A; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TH1 = 0X8D; //ʱ18λ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr TXCON = 0XC8; //ʱ2/3/4ƼĴ +sfr TXMOD = 0XC9; //ʱ2/3/4ģʽĴ +sfr RCAPXL = 0XCA; //ʱ2/3/4/׽8λ +sfr RCAPXH = 0XCB; //ʱ2/3/4/׽8λ +sfr TLX = 0XCC; //ʱ2/3/48λ +sfr THX = 0XCD; //ʱ2/3/48λ +sfr TXINX = 0XCE; //ʱƼĴָ + +/*ADC*/ +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ +sfr ADCCFG2 = 0XB5; //ADCüĴ2 + +/*PWM*/ +sfr PWMCFG = 0XD1; //PWMüĴ +sfr PWMCON0 = 0XD2; //PWMƼĴ0 +sfr PWMCON1 = 0XD3; //PWMƼĴ1 +sfr PWMPDL = 0XD4; //PWMڼĴ8λ +sfr PWMPDH = 0XD5; //PWMڼĴ8λ +sfr PWMDFR = 0XD6; //PWMüĴ +sfr PWMFLT = 0XD7; //PWMϼüĴ + +/*LPD*/ +sfr LPDCFG = 0XB7; //LPD + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XFB; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XB4; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XBE; //INT2 ½жϿƼĴ +sfr INT2R = 0XBF; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPKEY = 0XF1; //IAPĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADE = 0XF4; //IAPдչַĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPCTL = 0XF6; //IAPƼĴ + +/*uart0*/ +sfr OTCON = 0X8F; //ƼĴ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*һ*/ +sfr US0CON0 = 0X9C; //USCI0ƼĴ0 +sfr US0CON1 = 0X9D; //USCI0ƼĴ1 +sfr US0CON2 = 0X9E; //USCI0ƼĴ2 +sfr US0CON3 = 0X9F; //USCI0ƼĴ3 +sfr US1CON0 = 0XA4; //USCI1ƼĴ0 +sfr US1CON1 = 0XA5; //USCI1ƼĴ1 +sfr US1CON2 = 0XA6; //USCI1ƼĴ2 +sfr US1CON3 = 0XA7; //USCI1ƼĴ3 +sfr US2CON0 = 0XC4; //USCI2ƼĴ0 +sfr US2CON1 = 0XC5; //USCI2ƼĴ1 +sfr US2CON2 = 0XC6; //USCI2ƼĴ2 +sfr US2CON3 = 0XC7; //USCI2ƼĴ3 + +/*OPTION*/ +sfr OPINX = 0XFE; //Optionָ +sfr OPREG = 0XFF; //OptionĴ + +/*CRC*/ +sfr OPERCON = 0XEF; //ƼĴ +sfr CRCINX = 0XFC; //CRCָ +sfr CRCREG = 0XFD; //CRCĴ + + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*TXCON*/ +sbit TFX = TXCON^7; //ʱ2/3/4־λ +sbit EXFX = TXCON^6; //TnEXn=2/3/4ⲿ¼(½)⵽ı־λ +sbit RCLKX = TXCON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLKX = TXCON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXENX = TXCON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TRX = TXCON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit TX = TXCON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = TXCON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + + +/******************* P0 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţP06/P07 +*SC92L8531װδĹܽţP02/P03/P04/P06/P07 +***********************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţ +*SC92L8531װδĹܽţ +***********************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţ +*SC92L8531װδĹܽţP22/P23/P27 +***********************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + + +/******************* P5 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţP52/P53/P54/P55 +*SC92L8532װδĹܽţP5 +*SC92L8531װδĹܽţP5 +***********************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92L8535õú궨塣 +*****************************************************************************/ +#define SC92L8533_NIO_Init() {P5CON|=0x3C;} //SC92L8533δIO +#define SC92L8532_NIO_Init() {P0CON|=0xC0,P5CON|=0x3F;} //SC92L8532δIO +#define SC92L8531_NIO_Init() {P0CON|=0xDC,P2CON|=0X8C,P5CON|=0x3F;} //SC92L8531δIO +#endif diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f73Ax_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f73Ax_C.H new file mode 100644 index 0000000..724dc4a --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f73Ax_C.H @@ -0,0 +1,252 @@ + /*-------------------------------------------------------------------------- +SC92F73Ax_C.H + +C Header file for SC92F73Ax microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.17 +--------------------------------------------------------------------------*/ +#ifndef _SC92F73Ax_H_ +#define _SC92F73Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //ƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; //Option ָ +sfr OPREG = 0XFF; //OptionĴ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ 0:CPUӦӲ 1:жϲ +sbit BITIE0 = TCON^1; //INT0ж־ 0:CPUӦӲ 1:жϲ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F73A3װδĹܽţ +*SC92F73A2װδĹܽţP06/P07 +*SC92F73A1װδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F73A3װδĹܽţ +*SC92F73A2װδĹܽţP16/P17 +*SC92F73A1װδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F73A3װδĹܽţ +*SC92F73A2װδĹܽţP22/P23 +*SC92F73A1װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F73A3װδĹܽţ +*SC92F73A2װδĹܽţP50/P51 +*SC92F73A1װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F73A3õú궨塣 +*****************************************************************************/ +#define SC92F73A2_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F73A2δIO +#define SC92F73A1_NIO_Init() {P0CON|=0xDC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F73A1δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f74Ax_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f74Ax_C.H new file mode 100644 index 0000000..03a091e --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f74Ax_C.H @@ -0,0 +1,253 @@ + /*-------------------------------------------------------------------------- +SC92F74Ax_C.H + +C Header file for SC92F74Ax microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.17 +--------------------------------------------------------------------------*/ +#ifndef _SC92F74Ax_H_ +#define _SC92F74Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //ƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; //Option ָ +sfr OPREG = 0XFF; //OptionĴ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ 0:CPUӦӲ 1:жϲ +sbit BITIE0 = TCON^1; //INT0ж־ 0:CPUӦӲ 1:жϲ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F74A3װδĹܽţ +*SC92F74A2װδĹܽţP06/P07 +*SC92F74A1װδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F74A3װδĹܽţ +*SC92F74A2װδĹܽţP16/P17 +*SC92F74A1װδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F74A3װδĹܽţ +*SC92F74A2װδĹܽţP22/P23 +*SC92F74A1װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F74A3װδĹܽţ +*SC92F74A2װδĹܽţP50/P51 +*SC92F74A1װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F74A3õú궨塣 +*****************************************************************************/ +#define SC92F74A2_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F74A2δIO +#define SC92F74A1_NIO_Init() {P0CON|=0xDC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F74A1δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f83Ax_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f83Ax_C.H new file mode 100644 index 0000000..04c9bc5 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f83Ax_C.H @@ -0,0 +1,253 @@ + /*-------------------------------------------------------------------------- +SC92F83Ax_C.H + +C Header file for SC92F83Ax microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.17 +--------------------------------------------------------------------------*/ +#ifndef _SC92F83Ax_H_ +#define _SC92F83Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //ƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; //Option ָ +sfr OPREG = 0XFF; //OptionĴ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ 0:CPUӦӲ 1:жϲ +sbit BITIE0 = TCON^1; //INT0ж־ 0:CPUӦӲ 1:жϲ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F83A3װδĹܽţ +*SC92F83A2װδĹܽţP06/P07 +*SC92F83A1װδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F83A3װδĹܽţ +*SC92F83A2װδĹܽţP16/P17 +*SC92F83A1װδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F83A3װδĹܽţ +*SC92F83A2װδĹܽţP22/P23 +*SC92F83A1װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F83A3װδĹܽţ +*SC92F83A2װδĹܽţP50/P51 +*SC92F83A1װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F83A3õú궨塣 +*****************************************************************************/ +#define SC92F83A2_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F83A2δIO +#define SC92F83A1_NIO_Init() {P0CON|=0xDC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F83A1δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f84Ax_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f84Ax_C.H new file mode 100644 index 0000000..06d7a8e --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC92f84Ax_C.H @@ -0,0 +1,253 @@ + /*-------------------------------------------------------------------------- +SC92F84Ax_C.H + +C Header file for SC92F84Ax microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.17 +--------------------------------------------------------------------------*/ +#ifndef _SC92F84Ax_H_ +#define _SC92F84Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //ƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; //Option ָ +sfr OPREG = 0XFF; //OptionĴ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ 0:CPUӦӲ 1:жϲ +sbit BITIE0 = TCON^1; //INT0ж־ 0:CPUӦӲ 1:жϲ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F84A3װδĹܽţ +*SC92F84A2װδĹܽţP06/P07 +*SC92F84A1װδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F84A3װδĹܽţ +*SC92F84A2װδĹܽţP16/P17 +*SC92F84A1װδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F84A3װδĹܽţ +*SC92F84A2װδĹܽţP22/P23 +*SC92F84A1װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F84A3װδĹܽţ +*SC92F84A2װδĹܽţP50/P51 +*SC92F84A1װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F84A3õú궨塣 +*****************************************************************************/ +#define SC92F84A2_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F84A2δIO +#define SC92F84A1_NIO_Init() {P0CON|=0xDC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F84A1δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC93F743x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC93F743x_C.H new file mode 100644 index 0000000..5726c5b --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC93F743x_C.H @@ -0,0 +1,242 @@ + /*-------------------------------------------------------------------------- +SC93F743x_C.H + +C Header file for SC93F743x microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2019.06.24 +--------------------------------------------------------------------------*/ +#ifndef _SC93F743x_H_ +#define _SC93F743x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ +sfr DPL1 = 0x84; //DPTR1ָ1λ +sfr DPH1 = 0x85; //DPTR1ָ1λ +sfr DPS = 0x86; //DPTRѡĴ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMߵƽüĴ +sfr PWMDTY0 = 0xD5; //PWMߵƽüĴ +sfr PWMDTY1 = 0XD6; //PWMߵƽüĴ +sfr PWMDTY2 = 0XD7; //PWMߵƽüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ +sfr PGACFG = 0XBE; //PGAüĴ +sfr PGACON = 0XBF; //PGAƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ +sfr SSCON1 = 0X9E; //SPI״̬Ĵ +sfr SSCON2 = 0X95; //SPI״̬Ĵ +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr MXAX = 0XEA; +sfr TA = 0XEB; +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*temperature sensor*/ +sfr TSCFG = 0XAA; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC93F7433װδĹܽţ +*SC93F7432װδĹܽţP06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC93F7433װδĹܽţP10 +*SC93F7432װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; + +/******************* P2 ****************** +*SC93F7433װδĹܽţ +*SC93F7432װδĹܽţP22/P23 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC93F7433װδĹܽţ +*SC93F7432װδĹܽţP50/P51 +******************************************/ +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +* +*****************************************************************************/ +#define SC93F7433_NIO_Init() {P1CON|=0x01;} //SC93F7433δIO +#define SC93F7432_NIO_Init() {P0CON|=0xC0,P1CON|=0xC1,P2CON|=0x0C,P5CON|=0x03;} //SC93F7432δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC93F833x_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC93F833x_C.H new file mode 100644 index 0000000..02a0741 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC93F833x_C.H @@ -0,0 +1,247 @@ + /*-------------------------------------------------------------------------- +SC93F833x_C.H + +C Header file for SC93F833x microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2019.06.24 +--------------------------------------------------------------------------*/ +#ifndef _SC93F833x_H_ +#define _SC93F833x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ +sfr DPL1 = 0x84; //DPTR1ָ1λ +sfr DPH1 = 0x85; //DPTR1ָ1λ +sfr DPS = 0x86; //DPTRѡĴ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMߵƽüĴ +sfr PWMDTY0 = 0xD5; //PWMߵƽüĴ +sfr PWMDTY1 = 0XD6; //PWMߵƽüĴ +sfr PWMDTY2 = 0XD7; //PWMߵƽüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ +sfr PGACFG = 0XBE; //PGAüĴ +sfr PGACON = 0XBF; //PGAƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ +sfr SSCON1 = 0X9E; //SPI״̬Ĵ +sfr SSCON2 = 0X95; //SPI״̬Ĵ +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr MXAX = 0XEA; +sfr TA = 0XEB; +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*temperature sensor*/ +sfr TSCFG = 0XAA; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC93F8333װδĹܽţ +*SC93F8332װδĹܽţP06/P07 +*SC93F8331װδĹܽţP02/P03/P05/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC93F8333װδĹܽţP10 +*SC93F8332װδĹܽţP10/P16/P17 +*SC93F8331װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; + +/******************* P2 ****************** +*SC93F8333װδĹܽţ +*SC93F8332װδĹܽţP22/P23 +*SC93F8331װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC93F8333װδĹܽţ +*SC93F8332װδĹܽţP50/P51 +*SC93F8331װδĹܽţP50/P51 +******************************************/ +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +* +*****************************************************************************/ +#define SC93F8333_NIO_Init() {P1CON|=0x01;} //SC93F8333δIO +#define SC93F8332_NIO_Init() {P0CON|=0xC0,P1CON|=0xC1,P2CON|=0x0C,P5CON|=0x03;} //SC93F8332δIO +#define SC93F8331_NIO_Init() {P0CON|=0xEC,P1CON|=0xC1,P2CON|=0x8C,P5CON|=0x03;} //SC93F8331δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC93F843X_C.H b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC93F843X_C.H new file mode 100644 index 0000000..1ac6a17 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/SC93F843X_C.H @@ -0,0 +1,247 @@ + /*-------------------------------------------------------------------------- +SC93F843x_C.H + +C Header file for SC93F843x microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2019.06.24 +--------------------------------------------------------------------------*/ +#ifndef _SC93F843x_H_ +#define _SC93F843x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ +sfr DPL1 = 0x84; //DPTR1ָ1λ +sfr DPH1 = 0x85; //DPTR1ָ1λ +sfr DPS = 0x86; //DPTRѡĴ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMߵƽüĴ +sfr PWMDTY0 = 0xD5; //PWMߵƽüĴ +sfr PWMDTY1 = 0XD6; //PWMߵƽüĴ +sfr PWMDTY2 = 0XD7; //PWMߵƽüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ +sfr PGACFG = 0XBE; //PGAüĴ +sfr PGACON = 0XBF; //PGAƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ +sfr SSCON1 = 0X9E; //SPI״̬Ĵ +sfr SSCON2 = 0X95; //SPI״̬Ĵ +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr MXAX = 0XEA; +sfr TA = 0XEB; +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*temperature sensor*/ +sfr TSCFG = 0XAA; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC93F8433װδĹܽţ +*SC93F8432װδĹܽţP06/P07 +*SC93F8431װδĹܽţP02/P03/P05/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC93F8433װδĹܽţP10 +*SC93F8432װδĹܽţP10/P16/P17 +*SC93F8431װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; + +/******************* P2 ****************** +*SC93F8433װδĹܽţ +*SC93F8432װδĹܽţP22/P23 +*SC93F8431װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC93F8433װδĹܽţ +*SC93F8432װδĹܽţP50/P51 +*SC93F8431װδĹܽţP50/P51 +******************************************/ +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +* +*****************************************************************************/ +#define SC93F8433_NIO_Init() {P1CON|=0x01;} //SC93F8433δIO +#define SC93F8432_NIO_Init() {P0CON|=0xC0;P1CON|=0xC1;P2CON|=0x0C;P5CON|=0x03;} //SC93F8432δIO +#define SC93F8431_NIO_Init() {P0CON|=0xEC;P1CON|=0xC1;P2CON|=0x8C;P5CON|=0x03;} //SC93F8431δIO + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f.h new file mode 100644 index 0000000..7b393f5 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f.h @@ -0,0 +1,201 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f.h +// : +// ģ鹦 : ԪSC92ϵϵͳͷļ +// ֲб: +// : 202276 +// 汾 : V1.10030 +// ˵ ļԪ92FϵеƬ +//************************************************************* + +#ifndef _sc92f_H +#define _sc92f_H + +#ifdef SC92F854x + #include "SC92F854x_C.H" +#endif + +#ifdef SC92F754x + #include "SC92F754x_C.H" +#endif + +#ifdef SC92F844xB + #include "SC92F844xB_C.H" +#endif + +#ifdef SC92F744xB + #include "SC92F744xB_C.H" +#endif + +#ifdef SC92F846xB + #include "SC92F846xB_C.H" +#endif + +#ifdef SC92F746xB + #include "SC92F746xB_C.H" +#endif + +#ifdef SC92F836xB + #include "SC92F836xB_C.H" +#endif + +#ifdef SC92F736xB + #include "SC92F736xB_C.H" +#endif + +#ifdef SC92F742x + #include "SC92F742x_C.H" +#endif + +#ifdef SC92F7003 + #include "SC92F7003_C.H" +#endif + +#ifdef SC92F8003 + #include "SC92F8003_C.H" +#endif + +#ifdef SC92F740x + #include "SC92F740x_C.H" +#endif + +#ifdef SC92F74Ax + #include "SC92F74Ax_C.H" +#endif + +#ifdef SC92F84Ax + #include "SC92F84Ax_C.H" +#endif + +#ifdef SC92F73Ax + #include "SC92F73Ax_C.H" +#endif + +#ifdef SC92F83Ax + #include "SC92F83Ax_C.H" +#endif + +#ifdef SC92F74Ax_2 + #include "SC92F74Ax_2_C.H" +#endif + +#ifdef SC92F84Ax_2 + #include "SC92F84Ax_2_C.H" +#endif + +#ifdef SC92F730x + #include "SC92F730x_C.h" +#endif + +#ifdef SC92F827X + #include "SC92F827X_C.h" +#endif + +#ifdef SC92F837X + #include "SC92F837X_C.H" +#endif + +#ifdef SC92F7490 + #include "SC92F7490_C.H" +#endif + +#ifdef SC92F725X + #include "SC92F725X_C.h" +#endif + +#ifdef SC92F735X + #include "SC92F735X_C.h" +#endif + +#ifdef SC92F732X + #include "SC92F732X_C.H" +#endif + +#ifdef SC92FWxx + #include "SC92FWxx_C.H" +#endif + +#ifdef SC93F833x + #include "SC93F833x_C.H" +#endif + +#ifdef SC93F843x + #include "SC93F843x_C.H" +#endif + +#ifdef SC93F743x + #include "SC93F743x_C.H" +#endif + +#ifdef SC92F848x + #include "SC92F848x_C.H" +#endif + +#ifdef SC92F748x + #include "SC92F748x_C.H" +#endif + +#ifdef SC92F859x + #include "SC92F859x_C.H" +#endif + +#ifdef SC92F759x + #include "SC92F759x_C.H" +#endif + +#ifdef SC92L853x + #include "SC92L853x_C.H" +#endif + +#ifdef SC92L753x + #include "SC92L753x_C.H" +#endif + +#define enableInterrupts() EA=1 /** ж **/ +#define disableInterrupts() EA=0 /** رж **/ + +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*!< Signed integer types */ +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed long int32_t; + +/*!< Unsigned integer types */ +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned long uint32_t; + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, +ITStatus, BitStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +typedef enum {LOW = 0, HIGH = !LOW} PriorityStatus; + +#define SET_BIT(SFR,BIT) ((SFR) |= (BIT)) + +#define CLEAR_BIT(SFR,BIT) ((SFR) &= ~(BIT)) + +#define READ_BIT(SFR, BIT) ((SFR) & (BIT)) + +#define CLEAR_REG(SFR) ((SFR) = (0x0)) + +#define WRITE_REG(SFR, VAL) ((SFR) = (VAL)) + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_acmp.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_acmp.h new file mode 100644 index 0000000..6844837 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_acmp.h @@ -0,0 +1,78 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_acmp.h +// : +// ģ鹦 : ACMP̼⺯ͷļ +// : 2020/8/20 +// 汾 : V1.0001 +// ˵ : +//************************************************************* + +#ifndef _sc92f_ACMP_H_ +#define _sc92f_ACMP_H_ + +#include "sc92f.h" +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + ACMP_VREF_EXTERNAL = (uint8_t)0X00, //ѡCMPRΪACMPıȽϵѹ + ACMP_VREF_1D16VDD = (uint8_t)0X01, //ѡ1/16VDDΪACMPıȽϵѹ + ACMP_VREF_2D16VDD = (uint8_t)0X02, //ѡ2/16VDDΪACMPıȽϵѹ + ACMP_VREF_3D16VDD = (uint8_t)0X03, //ѡ3/16VDDΪACMPıȽϵѹ + ACMP_VREF_4D16VDD = (uint8_t)0X04, //ѡ4/16VDDΪACMPıȽϵѹ + ACMP_VREF_5D16VDD = (uint8_t)0X05, //ѡ5/16VDDΪACMPıȽϵѹ + ACMP_VREF_6D16VDD = (uint8_t)0X06, //ѡ6/16VDDΪACMPıȽϵѹ + ACMP_VREF_7D16VDD = (uint8_t)0X07, //ѡ7/16VDDΪACMPıȽϵѹ + ACMP_VREF_8D16VDD = (uint8_t)0X08, //ѡ8/16VDDΪACMPıȽϵѹ + ACMP_VREF_9D16VDD = (uint8_t)0X09, //ѡ9/16VDDΪACMPıȽϵѹ + ACMP_VREF_10D16VDD = (uint8_t)0X0A, //ѡ10/16VDDΪACMPıȽϵѹ + ACMP_VREF_11D16VDD = (uint8_t)0X0B, //ѡ11/16VDDΪACMPıȽϵѹ + ACMP_VREF_12D16VDD = (uint8_t)0X0C, //ѡ12/16VDDΪACMPıȽϵѹ + ACMP_VREF_13D16VDD = (uint8_t)0X0D, //ѡ13/16VDDΪACMPıȽϵѹ + ACMP_VREF_14D16VDD = (uint8_t)0X0E, //ѡ14/16VDDΪACMPıȽϵѹ + ACMP_VREF_15D16VDD = (uint8_t)0X0F //ѡ15/16VDDΪACMPıȽϵѹ +} ACMP_Vref_Typedef; + +typedef enum +{ + ACMP_CHANNEL_0 = (uint8_t)0x00, //ѡCMP0ACMP + ACMP_CHANNEL_1 = (uint8_t)0x01, //ѡCMP1ACMP + ACMP_CHANNEL_2 = (uint8_t)0x02, //ѡCMP2ACMP + ACMP_CHANNEL_3 = (uint8_t)0x03, //ѡCMP3ACMP + #if defined(SC92F859x) || defined (SC92F759x) + ACMP_CHANNEL_P = (uint8_t)0x10, //ѡCMPPACMPڣCMPPΪ׼ѹ1.5V + #endif +} ACMP_Channel_TypeDef; + +typedef enum +{ + ACMP_TRIGGER_NO = (uint8_t)0x00, //ж + ACMP_TRIGGER_RISE_ONLY = (uint8_t)0x04, //ģȽʽΪ + ACMP_TRIGGER_FALL_ONLY = (uint8_t)0x08, //ģȽʽΪ½ + ACMP_TRIGGER_RISE_FALL = (uint8_t)0x0C //ģȽʽΪ½ +} ACMP_TriggerMode_Typedef; + +typedef enum +{ + ACMP_FLAG_CMPIF = (uint8_t)0x40, //ACMPжϱ־λ + ACMP_FLAG_CMPSTA = (uint8_t)0x20 //ACMP״̬ +} ACMP_Flag_TypeDef; + +void ACMP_DeInit(void); +void ACMP_Init(ACMP_Vref_Typedef ACMP_Vref, + ACMP_Channel_TypeDef ACMP_Channel); +void ACMP_SetTriggerMode(ACMP_TriggerMode_Typedef + ACMP_TriggerMode); +void ACMP_Cmd(FunctionalState NewState); +void ACMP_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +FlagStatus ACMP_GetFlagStatus(ACMP_Flag_TypeDef + ACMP_Flag); +void ACMP_ClearFlag(void); + +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_adc.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_adc.h new file mode 100644 index 0000000..d0a2d7d --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_adc.h @@ -0,0 +1,326 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_adc.h +// : ԪӦŶ +// ģ鹦: ADC̼⺯ͷļ +// : 2022323 +// 汾: V1.100014 +// ˵: ļԪ92F/93F/92LϵеƬ +//************************************************************* +#ifndef _sc92f_ADC_H_ +#define _sc92f_ADC_H_ + +/* ͷļ */ +#include "sc92f.h" +/* ˵:ADCοԴöٶsc92f_option.hʹADCע⽫ļ */ +#include "sc92f_option.h" + +#if !defined(SC92F827X) && !defined(SC92F837X) +/* ADCʱӷƵת */ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2) || defined(SC92FWxx) +typedef enum +{ + ADC_PRESSEL_FOSC_D6 = (uint8_t)0x02, //ԤƵ fADC = fHRC/6 + ADC_PRESSEL_FOSC_D12 = (uint8_t)0x01 //ԤƵ fADC = fHRC/12 +} ADC_PresSel_TypeDef; +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + ADC_PRESSEL_FHRC_D32 = (uint8_t)0x00, //ԤƵ fADC = fHRC/32 + ADC_PRESSEL_FHRC_D24 = (uint8_t)0x01, //ԤƵ fADC = fHRC/24 + ADC_PRESSEL_FHRC_D16 = (uint8_t)0x02, //ԤƵ fADC = fHRC/16 + ADC_PRESSEL_FHRC_D12 = (uint8_t)0x03, //ԤƵ fADC = fHRC/12 + ADC_PRESSEL_FHRC_D8 = (uint8_t)0x04, //ԤƵ fADC = fHRC/8 + ADC_PRESSEL_FHRC_D6 = (uint8_t)0x05, //ԤƵ fADC = fHRC/6 + ADC_PRESSEL_FHRC_D4 = (uint8_t)0x06, //ԤƵ fADC = fHRC/4 + ADC_PRESSEL_FHRC_D3 = (uint8_t)0x07 //ԤƵ fADC = fHRC/3 +} ADC_PresSel_TypeDef; +#elif defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) || defined (SC92F7490)\ + || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + ADC_PRESSEL_2_MHz = (uint8_t)0x00, //ԤƵ fADC = 2MHz + ADC_PRESSEL_333_kHz = (uint8_t)0x20 //ԤƵ fADC = 333kHz +} ADC_PresSel_TypeDef; +#elif defined(SC92F848x) || defined(SC92F748x) +typedef enum +{ + ADC_PRESSEL_FSYS_D16 = (uint8_t)0x00, //ԤƵ fADC = fSYS/16 + ADC_PRESSEL_FSYS_D12 = (uint8_t)0x01, //ԤƵ fADC = fSYS/12 + ADC_PRESSEL_FSYS_D8 = (uint8_t)0x02, //ԤƵ fADC = fSYS/8 + ADC_PRESSEL_FSYS_D6 = (uint8_t)0x03, //ԤƵ fADC = fSYS/6 + ADC_PRESSEL_FSYS_D4 = (uint8_t)0x04, //ԤƵ fADC = fSYS/4 + ADC_PRESSEL_FSYS_D3 = (uint8_t)0x05, //ԤƵ fADC = fSYS/3 + ADC_PRESSEL_FSYS_D2 = (uint8_t)0x06, //ԤƵ fADC = fSYS/2 + ADC_PRESSEL_FSYS_D1 = (uint8_t)0x07 //ԤƵ fADC = fSYS/1 +} ADC_PresSel_TypeDef; +#elif defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + ADC_PRESSEL_FSYS_D16 = (uint8_t)0x00, //ԤƵ fADC = fSYS/16 + ADC_PRESSEL_FSYS_D12 = (uint8_t)0x01, //ԤƵ fADC = fSYS/12 + ADC_PRESSEL_FSYS_D6 = (uint8_t)0x02, //ԤƵ fADC = fSYS/6 + ADC_PRESSEL_FSYS_D4 = (uint8_t)0x03, //ԤƵ fADC = fSYS/4 +} ADC_PresSel_TypeDef; +#elif defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_PRESSEL_3CLOCK = (uint8_t)0x10, //ʱΪ3ϵͳʱ + ADC_PRESSEL_6CLOCK = (uint8_t)0x14, //ʱΪ6ϵͳʱ + ADC_PRESSEL_16CLOCK = (uint8_t)0x18, //ʱΪ16ϵͳʱ + ADC_PRESSEL_32CLOCK = (uint8_t)0x1c //ʱΪ32ϵͳʱ +} ADC_PresSel_TypeDef; +#endif + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ +|| defined(SC92FWxx) || defined(SC92F859x) || defined (SC92F759x) +typedef enum +{ + ADC_Cycle_6Cycle = (uint8_t)0x00, //ADCʱΪ6ADCʱ + ADC_Cycle_36Cycle = (uint8_t)0x04 //ADCʱΪ36ADCʱ +} ADC_Cycle_TypeDef; +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F7003) || defined(SC92F8003) || defined (SC92F740x) || defined (SC92F848x) || defined (SC92F748x) +typedef enum +{ + ADC_Cycle_6Cycle = (uint8_t)0x00, //ADCʱΪ6ADCʱ + ADC_Cycle_36Cycle = (uint8_t)0x08 //ADCʱΪ36ADCʱ +} ADC_Cycle_TypeDef; +#elif defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X)\ +|| defined (SC92F7490) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_Cycle_Null = (uint8_t)0x00, +} ADC_Cycle_TypeDef; +#endif + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_2 = (uint8_t)0x02, //ѡAIN2AD + ADC_CHANNEL_3 = (uint8_t)0x03, //ѡAIN3AD + ADC_CHANNEL_4 = (uint8_t)0x04, //ѡAIN4AD + ADC_CHANNEL_5 = (uint8_t)0x05, //ѡAIN5AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_7 = (uint8_t)0x07, //ѡAIN7AD + ADC_CHANNEL_8 = (uint8_t)0x08, //ѡAIN8AD + ADC_CHANNEL_9 = (uint8_t)0x09, //ѡAIN9AD + ADC_CHANNEL_10 = (uint8_t)0x0A, //ѡAIN10AD + ADC_CHANNEL_11 = (uint8_t)0x0B, //ѡAIN11AD + ADC_CHANNEL_12 = (uint8_t)0x0C, //ѡAIN12AD + ADC_CHANNEL_13 = (uint8_t)0x0D, //ѡAIN13AD + ADC_CHANNEL_14 = (uint8_t)0x0E, //ѡAIN14AD + ADC_CHANNEL_15 = (uint8_t)0x0F, //ѡAIN15AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_2 = (uint8_t)0x02, //ѡAIN2AD + ADC_CHANNEL_3 = (uint8_t)0x03, //ѡAIN3AD + ADC_CHANNEL_4 = (uint8_t)0x04, //ѡAIN4AD + ADC_CHANNEL_5 = (uint8_t)0x05, //ѡAIN5AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F83Ax)\ +|| defined(SC92F73Ax) || defined(SC92F84Ax) || defined(SC92F74Ax) || defined(SC92F742x) || defined(SC92F725X)\ +|| defined(SC92F735X) || defined(SC92F732X) || defined(SC92F848x) || defined(SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_2 = (uint8_t)0x02, //ѡAIN2AD + ADC_CHANNEL_3 = (uint8_t)0x03, //ѡAIN3AD + ADC_CHANNEL_4 = (uint8_t)0x04, //ѡAIN4AD + ADC_CHANNEL_5 = (uint8_t)0x05, //ѡAIN5AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_7 = (uint8_t)0x07, //ѡAIN7AD + ADC_CHANNEL_8 = (uint8_t)0x08, //ѡAIN8AD + ADC_CHANNEL_9 = (uint8_t)0x09, //ѡAIN9AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC92F730x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_7 = (uint8_t)0x07, //ѡAIN7AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC92F7490) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_2 = (uint8_t)0x02, //ѡAIN2AD + ADC_CHANNEL_3 = (uint8_t)0x03, //ѡAIN3AD + ADC_CHANNEL_4 = (uint8_t)0x04, //ѡAIN4AD + ADC_CHANNEL_5 = (uint8_t)0x05, //ѡAIN5AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_7 = (uint8_t)0x07, //ѡAIN7AD + ADC_CHANNEL_8 = (uint8_t)0x08, //ѡAIN8AD + ADC_CHANNEL_9 = (uint8_t)0x09, //ѡAIN9AD + ADC_CHANNEL_9_PGA = (uint8_t)0x19, //ѡAIN9PGA + ADC_CHANNEL_Temp = (uint8_t)0x0e, //ѡڲ¶ȴΪAD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x0f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#endif + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 + ADC_EAIN_2 = (uint16_t)0x0004, //ѡAIN2 + ADC_EAIN_3 = (uint16_t)0x0008, //ѡAIN3 + ADC_EAIN_4 = (uint16_t)0x0010, //ѡAIN4 + ADC_EAIN_5 = (uint16_t)0x0020, //ѡAIN5 + ADC_EAIN_6 = (uint16_t)0x0040, //ѡAIN6 + ADC_EAIN_7 = (uint16_t)0x0080, //ѡAIN7 + ADC_EAIN_8 = (uint16_t)0x0100, //ѡAIN8 + ADC_EAIN_9 = (uint16_t)0x0200, //ѡAIN9 + ADC_EAIN_10 = (uint16_t)0x0400, //ѡAIN10 + ADC_EAIN_11 = (uint16_t)0x0800, //ѡAIN11 + ADC_EAIN_12 = (uint16_t)0x1000, //ѡAIN12 + ADC_EAIN_13 = (uint16_t)0x2000, //ѡAIN13 + ADC_EAIN_14 = (uint16_t)0x4000, //ѡAIN14 + ADC_EAIN_15 = (uint16_t)0x8000 //ѡAIN15 +} ADC_EAIN_TypeDef; +#elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 + ADC_EAIN_2 = (uint16_t)0x0004, //ѡAIN2 + ADC_EAIN_3 = (uint16_t)0x0008, //ѡAIN3 + ADC_EAIN_4 = (uint16_t)0x0010, //ѡAIN4 + ADC_EAIN_5 = (uint16_t)0x0020, //ѡAIN5 + ADC_EAIN_6 = (uint16_t)0x0040 //ѡAIN6 +} ADC_EAIN_TypeDef; +#elif defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F83Ax)\ +|| defined(SC92F73Ax) || defined(SC92F84Ax) || defined(SC92F74Ax) || defined(SC92F742x) || defined(SC92F725X)\ +|| defined(SC92F735X) || defined(SC92F732X) || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x)\ +|| defined(SC92F848x) || defined(SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 + ADC_EAIN_2 = (uint16_t)0x0004, //ѡAIN2 + ADC_EAIN_3 = (uint16_t)0x0008, //ѡAIN3 + ADC_EAIN_4 = (uint16_t)0x0010, //ѡAIN4 + ADC_EAIN_5 = (uint16_t)0x0020, //ѡAIN5 + ADC_EAIN_6 = (uint16_t)0x0040, //ѡAIN6 + ADC_EAIN_7 = (uint16_t)0x0080, //ѡAIN7 + ADC_EAIN_8 = (uint16_t)0x0100, //ѡAIN8 + ADC_EAIN_9 = (uint16_t)0x0200, //ѡAIN9 +} ADC_EAIN_TypeDef; +#elif defined(SC92F730x) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 + ADC_EAIN_6 = (uint16_t)0x0040, //ѡAIN6 + ADC_EAIN_7 = (uint16_t)0x0080, //ѡAIN7 +} ADC_EAIN_TypeDef; +#elif defined(SC92F7490) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 +} ADC_EAIN_TypeDef; +#endif + +/* ڲ¶ȲɼͿɵŴPGAö*/ +#if defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +/* PGAģѹö */ +typedef enum +{ + ADC_PGACOM_0V = 0x00, //ģѹΪ0V + ADC_PGACOM_1_2V = 0x40, //ģѹΪ1.2V +} ADC_PGACOM_TypeDef; + +/* PGAͬö */ +typedef enum +{ + ADC_PGAGAN_NonInvert20 = 0x00, //ͬΪ20Ϊ19 + ADC_PGAGAN_NonInvert100 = 0x20, //ͬΪ100Ϊ99 +} ADC_PGAGAN_TypeDef; + +/* PGAλö */ +typedef enum +{ + ADC_PGAIPT_NonInvert = 0x00, //ͬ + ADC_PGAIPT_Invert = 0x10, // +} ADC_PGAIPT_TypeDef; +#endif + +/*******************************꺯*******************************/ +/***************************************************** +*:void ADC_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:ADCжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +#define ADC_ITConfig(NewState,Priority) \ + do{ \ + EADC = (bit)NewState; \ + IPADC = (bit)Priority; \ + }while(0) + +/***************************************************** +*:void ADC_StartConversion(void) +*:ʼһADת +*ڲ:void +*ڲ:void +*****************************************************/ +#define ADC_StartConversion() SET_BIT(ADCCON,0X40) + +/* ڲ¶ȲɼͿɵŴ */ +#if defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +/* ڲ¶Ȳɼغ */ +void ADC_TSCmd(FunctionalState NewState); +void ADC_CHOPConfig(PriorityStatus NewState); +uint16_t ADC_Get_TS_StandardData(void); +float ADC_GetTSValue(void); +/* PGAغ */ +void ADC_PGAConfig(ADC_PGACOM_TypeDef ADC_PGACOM, ADC_PGAGAN_TypeDef ADC_PGAGAN, ADC_PGAIPT_TypeDef ADC_PGAIPT); +void ADC_PGACmd(PriorityStatus NewState); +#endif + +/* ADCͨú */ +void ADC_DeInit(void); +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, ADC_Cycle_TypeDef ADC_Cycle); +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, + FunctionalState NewState); +void ADC_Cmd(FunctionalState NewState); +unsigned int ADC_GetConversionValue(void); +FlagStatus ADC_GetFlagStatus(void); +void ADC_ClearFlag(void); +void ADC_EAINConfig(uint16_t ADC_EAIN_Select, + FunctionalState NewState); +void ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref); + + +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_btm.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_btm.h new file mode 100644 index 0000000..5eb4f1b --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_btm.h @@ -0,0 +1,89 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_btm.h +// : ԪӦŶ +// ģ鹦: BTM̼⺯Hļ +// : 202242 +// 汾: V1.10002 +// ˵: +//************************************************************* +#ifndef _sc92f_BTM_H_ +#define _sc92f_BTM_H_ + +#include "sc92f.h" + +#if defined(SC92F748x) || defined(SC92F848x) || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + BTM_TIMEBASE_15_625MS = (uint8_t)0x00, //BTMÿ15.625MSһж + BTM_TIMEBASE_31_25MS = (uint8_t)0x01, //BTMÿ31.25MSһж + BTM_TIMEBASE_62_5MS = (uint8_t)0x02, //BTMÿ62.5MSһж + BTM_TIMEBASE_125MS = (uint8_t)0x03, //BTMÿ125MSһж + BTM_TIMEBASE_250MS = (uint8_t)0x04, //BTMÿ0.25Sһж + BTM_TIMEBASE_500MS = (uint8_t)0x05, //BTMÿ0.5Sһж + BTM_TIMEBASE_1S = (uint8_t)0x06, //BTMÿ1Sһж + BTM_TIMEBASE_2S = (uint8_t)0x07, //BTMÿ2Sһж + BTM_TIMEBASE_8S = (uint8_t)0x09, //BTMÿ8Sһж + BTM_TIMEBASE_16S = (uint8_t)0x0A, //BTMÿ16Sһж + BTM_TIMEBASE_32S = (uint8_t)0x0B, //BTMÿ32һж +} BTM_Timebase_TypeDef; +#elif defined (SC92F732X) +typedef enum +{ + BTM_TIMEBASE_15_625MS = (uint8_t)0x00, //BTMÿ15.625MSһж + BTM_TIMEBASE_31_25MS = (uint8_t)0x01, //BTMÿ31.25MSһж + BTM_TIMEBASE_62_5MS = (uint8_t)0x02, //BTMÿ62.5MSһж + BTM_TIMEBASE_125MS = (uint8_t)0x03, //BTMÿ125MSһж + BTM_TIMEBASE_250MS = (uint8_t)0x04, //BTMÿ0.25Sһж + BTM_TIMEBASE_500MS = (uint8_t)0x05, //BTMÿ0.5Sһж + BTM_TIMEBASE_1S = (uint8_t)0x06, //BTMÿ1Sһж + BTM_TIMEBASE_2S = (uint8_t)0x07, //BTMÿ2Sһж +} BTM_Timebase_TypeDef; +#else +typedef enum +{ + BTM_TIMEBASE_15_625MS = (uint8_t)0x00, //BTMÿ15.625MSһж + BTM_TIMEBASE_31_25MS = (uint8_t)0x01, //BTMÿ31.25MSһж + BTM_TIMEBASE_62_5MS = (uint8_t)0x02, //BTMÿ62.5MSһж + BTM_TIMEBASE_125MS = (uint8_t)0x03, //BTMÿ125MSһж + BTM_TIMEBASE_250MS = (uint8_t)0x04, //BTMÿ0.25Sһж + BTM_TIMEBASE_500MS = (uint8_t)0x05, //BTMÿ0.5Sһж + BTM_TIMEBASE_1S = (uint8_t)0x06, //BTMÿ1Sһж + BTM_TIMEBASE_2S = (uint8_t)0x07, //BTMÿ2Sһж + BTM_TIMEBASE_4S = (uint8_t)0x08, //BTMÿ4Sһж +} BTM_Timebase_TypeDef; +#endif + +/*******************************꺯*******************************/ +/************************************************** +*:void BTM_DeInit(void) +*:BTMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +#define BTM_DeInit() CLEAR_REG(BTMCON) + +/***************************************************** +*:void BTM_GetFlagStatus(void) +*:ȡBTMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:BTMжϱ־״̬ +*****************************************************/ +#define BTM_GetFlagStatus() ((READ_BIT(BTMCON,0x40)) ? (SET):(RESET)) + +/***************************************************** +*:void BTM_ClearFlag(void) +*:BTMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +#define BTM_ClearFlag() CLEAR_BIT(BTMCON,0x40) + +void BTM_Init(BTM_Timebase_TypeDef BTM_Timebase); +void BTM_Cmd(FunctionalState NewState); +void BTM_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_chksum.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_chksum.h new file mode 100644 index 0000000..b75a7b1 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_chksum.h @@ -0,0 +1,28 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_chksum.h +// : +// ģ鹦 : CHKSUM̼⺯ͷļ +// : 2021/8/20 +// 汾 : V1.10000 +// ˵ : +//************************************************************* + +#ifndef _sc92f_CHKSUM_H_ +#define _sc92f_CHKSUM_H_ + +#include "sc92f.h" + +#if defined(SC92F7003) || defined(SC92F8003) || defined(SC92F736xB) || defined(SC92F836xB) || defined(SC92F740x) || defined(SC92F742x)\ + || defined(SC92F73Ax) || defined(SC92F83Ax) || defined(SC92F744xB) || defined(SC92F844xB) || defined(SC92F746xB) || defined(SC92F846xB)\ + || defined(SC92F748x) || defined(SC92F848x) || defined(SC92F74Ax) || defined(SC92F84Ax) || defined(SC92F74Ax_2) || defined(SC92F84Ax_2)\ + || defined(SC92F754x) || defined (SC92F854x) || defined (SC92F759x) || defined(SC92F859x) || defined (SC92F7490) || defined(SC92FWxx)\ + || defined(SC92F827X) || defined(SC92F847X) + void CHKSUM_DeInit(void); + void CHKSUM_StartOperation(void); + uint16_t CHKSUM_GetCheckValue(void); +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_conf.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_conf.h new file mode 100644 index 0000000..ad2c889 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_conf.h @@ -0,0 +1,40 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_conf.h +// : +// ģ鹦 : sc92fͷļ +// : 2022/01/24 +// 汾 : V1.10002 +// ˵ ļԪ92FϵеƬ +//************************************************************* + +#ifndef _sc92f_CONF_H_ +#define _sc92f_CONF_H_ + +#include "sc92f_gpio.h" +#include "sc92f_timer0.h" +#include "sc92f_timer1.h" +#include "sc92f_timer2.h" +#include "sc92f_timer3.h" +#include "sc92f_timer4.h" +#include "sc92f_adc.h" +#include "sc92f_btm.h" +#include "sc92f_pwm.h" +#include "sc92f_int.h" +#include "sc92f_uart0.h" +#include "sc92f_ssi.h" +#include "sc92f_chksum.h" +#include "sc92f_iap.h" +#include "sc92f_option.h" +#include "sc92f_wdt.h" +#include "sc92f_pwr.h" +#include "sc92f_ddic.h" +#include "sc92f_acmp.h" +#include "sc92f_mdu.h" +#include "sc92f_CRC.h" +#include "sc92f_usci0.h" +#include "sc92f_usci1.h" +#include "sc92f_usci2.h" +#include "sc92f_lpd.h" + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_crc.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_crc.h new file mode 100644 index 0000000..bafba09 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_crc.h @@ -0,0 +1,24 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_CRC.h +// : +// ģ鹦 : CRC̼⺯ͷļ +// : 2020/8/14 +// 汾 : V1.0 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_CRC_H_ +#define _sc92f_CRC_H_ + +#include "sc92f.h" + +#if defined (SC92L853x) || defined (SC92L753x) +uint32_t CRC_All(void); //IAP RangeѡӲCRCCODEݣCRC +uint32_t CRC_Frame(uint8_t *buff, + uint8_t Length); //CRCbuffָCRC㣬CRC +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_ddic.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_ddic.h new file mode 100644 index 0000000..3933fe3 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_ddic.h @@ -0,0 +1,195 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ddic.c +// : +// ģ鹦 : DDIC̼⺯Cļ +// ֲб: +// : 2022/01/20 +// 汾 : V1.10002 +// ˵ : +//************************************************************* +#ifndef _sc92f_DDIC_H_ +#define _sc92f_DDIC_H_ + +#include "sc92f.h" + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + DDIC_PIN_X0 = ((uint8_t)0x01), //Px0ڴʾ + DDIC_PIN_X1 = ((uint8_t)0x02), //Px1ڴʾ + DDIC_PIN_X2 = ((uint8_t)0x04), //Px2ڴʾ + DDIC_PIN_X3 = ((uint8_t)0x08), //Px3ڴʾ + DDIC_PIN_X4 = ((uint8_t)0x10), //Px4ڴʾ + DDIC_PIN_X5 = ((uint8_t)0x20), //Px5ڴʾ + DDIC_PIN_X6 = ((uint8_t)0x40), //Px6ڴʾ + DDIC_PIN_X7 = ((uint8_t)0x80), //Px7ڴʾ +} DDIC_Pin_TypeDef; + +typedef enum +{ + DDIC_DUTYCYCLE_D8 = (uint8_t)0x00, //1/8 ռձ + DDIC_DUTYCYCLE_D6 = (uint8_t)0x10, //1/6 ռձ + DDIC_DUTYCYCLE_D5 = (uint8_t)0x20, //1/5 ռձ + DDIC_DUTYCYCLE_D4 = (uint8_t)0x30 //1/4 ռձ +} DDIC_DutyCycle_TypeDef; + +typedef enum +{ + DDIC_ResSel_100K = (uint8_t)0X00, //趨ڲѹΪ100k + DDIC_ResSel_200K = (uint8_t)0X04, //趨ڲѹΪ200k + DDIC_ResSel_400K = (uint8_t)0X08, //趨ڲѹΪ400k + DDIC_ResSel_800K = (uint8_t)0X0C //趨ڲѹΪ800k +} DDIC_ResSel_Typedef; + +typedef enum +{ + DDIC_BIAS_D3 = 0X01, //LCDƫõѹΪ1/3 + DDIC_BIAS_D4 = 0X00 //LCDƫõѹΪ1/4 +} DDIC_BiasVoltage_Typedef; + +#if defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + SEG0_27COM4_7 = (uint8_t)0x01, // 1/4ռձʱS0-S27ΪsegmentC4-C7Ϊcommon + SEG4_27COM0_3 = (uint8_t)0x00 // 1/4ռձʱS4-S27ΪsegmentC0-C3Ϊcommon +} DDIC_OutputPin_TypeDef; + +#else + +typedef enum +{ + SEG0_27COM4_7 = (uint8_t)0x00, // 1/4ռձʱS0-S27ΪsegmentC4-C7Ϊcommon + SEG4_27COM0_3 = (uint8_t)0x01 // 1/4ռձʱS4-S27ΪsegmentC0-C3Ϊcommon +} DDIC_OutputPin_TypeDef; + +#endif + +typedef enum +{ + DMOD_LCD = (uint8_t)0x00, // LCDģʽ + DMOD_LED = (uint8_t)0x01 // LEDģʽ +} DDIC_DMOD_TypeDef; + +typedef enum +{ + DDIC_SEG0 = (uint8_t)0, //SEG0 + DDIC_SEG1 = (uint8_t)1, //SEG1 + DDIC_SEG2 = (uint8_t)2, //SEG2 + DDIC_SEG3 = (uint8_t)3, //SEG3 + DDIC_SEG4 = (uint8_t)4, //SEG4 + DDIC_SEG5 = (uint8_t)5, //SEG5 + DDIC_SEG6 = (uint8_t)6, //SEG6 + DDIC_SEG7 = (uint8_t)7, //SEG7 + DDIC_SEG8 = (uint8_t)8, //SEG8 + DDIC_SEG9 = (uint8_t)9, //SEG9 + DDIC_SEG10 = (uint8_t)10, //SEG10 + DDIC_SEG11 = (uint8_t)11, //SEG11 + DDIC_SEG12 = (uint8_t)12, //SEG12 + DDIC_SEG13 = (uint8_t)13, //SEG13 + DDIC_SEG14 = (uint8_t)14, //SEG14 + DDIC_SEG15 = (uint8_t)15, //SEG15 + DDIC_SEG16 = (uint8_t)16, //SEG16 + DDIC_SEG17 = (uint8_t)17, //SEG17 + DDIC_SEG18 = (uint8_t)18, //SEG18 + DDIC_SEG19 = (uint8_t)19, //SEG19 + DDIC_SEG20 = (uint8_t)20, //SEG20 + DDIC_SEG21 = (uint8_t)21, //SEG21 + DDIC_SEG22 = (uint8_t)22, //SEG22 + DDIC_SEG23 = (uint8_t)23, //SEG23 + DDIC_SEG24 = (uint8_t)24, //SEG24 + DDIC_SEG25 = (uint8_t)25, //SEG25 + DDIC_SEG26 = (uint8_t)26, //SEG26 + DDIC_SEG27 = (uint8_t)27, //SEG27 +} DDIC_Control_SEG_TypeDef; + +typedef enum +{ + DDIC_COM0 = (uint8_t)0x01, //COM0 + DDIC_COM1 = (uint8_t)0x02, //COM1 + DDIC_COM2 = (uint8_t)0x04, //COM2 + DDIC_COM3 = (uint8_t)0x08, //COM3 + DDIC_COM4 = (uint8_t)0x10, //COM4 + DDIC_COM5 = (uint8_t)0x20, //COM5 + DDIC_COM6 = (uint8_t)0x40, //COM6 + DDIC_COM7 = (uint8_t)0x80 //COM7 +} DDIC_Control_COM_TypeDef; +typedef enum +{ + DDIC_Control_ON = (uint8_t)0x01, // + DDIC_Control_OFF = (uint8_t)0x00 //Ϩ +} DDIC_Control_Status; + + +extern uint8_t xdata LCDRAM[30]; + +void DDIC_DeInit(void); +void DDIC_Init(DDIC_DutyCycle_TypeDef + DDIC_DutyCylce, uint8_t P0OutputPin, + uint8_t P1OutputPin, uint8_t P2OutputPin, + uint8_t P3OutputPin); +void DDIC_LEDConfig(void); +void DDIC_LCDConfig(uint8_t LCDVoltage, + DDIC_ResSel_Typedef DDIC_ResSel, + DDIC_BiasVoltage_Typedef DDIC_BiasVoltage); +void DDIC_Cmd(FunctionalState NewState); +void DDIC_OutputPinOfDutycycleD4( + DDIC_OutputPin_TypeDef DDIC_OutputPin); +void DDIC_DMOD_Selcet(DDIC_DMOD_TypeDef + DDIC_DMOD); +void DDIC_Control(DDIC_Control_SEG_TypeDef DDIC_Seg, + uint8_t DDIC_Com, + DDIC_Control_Status DDIC_Contr); +#endif + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax)|| defined (SC92F74Ax)|| defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92F848x) || defined (SC92F748x) +#if defined (SC92F730x) +typedef enum +{ + DDIC_PIN_00 = ((uint8_t)0x01), //P0x0LCD + DDIC_PIN_01 = ((uint8_t)0x02), //P0x1LCD + DDIC_PIN_02 = ((uint8_t)0x04), //P0x2LCD + DDIC_PIN_03 = ((uint8_t)0x08), //P0x3LCD +} DDIC_Pin_TypeDef; +#else +typedef enum +{ + DDIC_PIN_00 = ((uint8_t)0x01), //P0x0LCD + DDIC_PIN_01 = ((uint8_t)0x02), //P0x1LCD + DDIC_PIN_02 = ((uint8_t)0x04), //P0x2LCD + DDIC_PIN_03 = ((uint8_t)0x08), //P0x3LCD + DDIC_PIN_04 = ((uint8_t)0x10), //P0x4LCD +} DDIC_Pin_TypeDef; +#endif + +#if defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + DDIC_ResSel_0K = (uint8_t)0X00, //رڲѹ + DDIC_ResSel_25K = (uint8_t)0X04, //趨ڲѹΪ12.5k + DDIC_ResSel_50K = (uint8_t)0X08, //趨ڲѹΪ37.5k + DDIC_ResSel_100K = (uint8_t)0X0c //趨ڲѹΪ87.5k +} DDIC_ResSel_Typedef; +#else +typedef enum +{ + DDIC_ResSel_0K = (uint8_t)0X00, //رڲѹ + DDIC_ResSel_12_5K = (uint8_t)0X04, //趨ڲѹΪ12.5k + DDIC_ResSel_37_5K = (uint8_t)0X08, //趨ڲѹΪ37.5k + DDIC_ResSel_87_5K = (uint8_t)0X0c //趨ڲѹΪ87.5k +} DDIC_ResSel_Typedef; + +#endif + +void DDIC_DeInit(); +void DDIC_Init(uint8_t P0OutputPin); +void DDIC_LCDConfig(DDIC_ResSel_Typedef + DDIC_ResSel); +void DDIC_Config_Init(uint8_t P0OutputPin, + DDIC_ResSel_Typedef DDIC_ResSel); +#endif + +#endif + +/******************* (C) COPYRIGHT 2022 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_gpio.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_gpio.h new file mode 100644 index 0000000..c5d7396 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_gpio.h @@ -0,0 +1,94 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_gpio.h +// : +// ģ鹦 : GPIO̼⺯ͷļ +// ֲб: +// : 2021/08/20 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#ifndef _sc92f_GPIO_H_ +#define _sc92f_GPIO_H_ + +#include "sc92f.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined(SC92FWxx)|| defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + + GPIO0 = (uint8_t)0x00, //P0 + GPIO1 = (uint8_t)0x01, //P1 + GPIO2 = (uint8_t)0x02, //P2 + GPIO3 = (uint8_t)0x03, //P3 + GPIO4 = (uint8_t)0x04, //P4 + GPIO5 = (uint8_t)0x05 //P5 +}GPIO_TypeDef; +#elif defined (SC92F730x ) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F8003) || defined (SC92F740x) || defined (SC92F827X) || defined (SC92F837X) || defined (SC92F7003) +typedef enum +{ + GPIO0 = (uint8_t)0x00, //P0 + GPIO1 = (uint8_t)0x01, //P1 + GPIO2 = (uint8_t)0x02, //P2 +}GPIO_TypeDef; +#else +typedef enum +{ + GPIO0 = (uint8_t)0x00, //P0 + GPIO1 = (uint8_t)0x01, //P1 + GPIO2 = (uint8_t)0x02, //P2 + GPIO5 = (uint8_t)0x05 //P5 +}GPIO_TypeDef; +#endif + + +typedef enum +{ + GPIO_MODE_IN_HI = (uint8_t)0x00, //ģʽ + GPIO_MODE_IN_PU = (uint8_t)0x01, //ģʽ + GPIO_MODE_OUT_PP = (uint8_t)0x02 //ǿģʽ +} GPIO_Mode_TypeDef; + +typedef enum +{ + GPIO_PIN_0 = ((uint8_t)0x01), //IOܽPx0 + GPIO_PIN_1 = ((uint8_t)0x02), //IOܽPx1 + GPIO_PIN_2 = ((uint8_t)0x04), //IOܽPx2 + GPIO_PIN_3 = ((uint8_t)0x08), //IOܽPx3 + GPIO_PIN_4 = ((uint8_t)0x10), //IOܽPx4 + GPIO_PIN_5 = ((uint8_t)0x20), //IOܽPx5 + GPIO_PIN_6 = ((uint8_t)0x40), //IOܽPx6 + GPIO_PIN_7 = ((uint8_t)0x80), //IOܽPx7 + GPIO_PIN_LNIB = ((uint8_t)0x0F), //IOܽPx0~3 + GPIO_PIN_HNIB = ((uint8_t)0xF0), //IOܽPx4~7 + GPIO_PIN_ALL = ((uint8_t)0xFF) //IOܽPx0~7 +} GPIO_Pin_TypeDef; + +typedef enum +{ + IOH_Grade_0 = ((uint8_t)0x00), //IOHȼ0 + IOH_Grade_1 = ((uint8_t)0x01), //IOHȼ1 + IOH_Grade_2 = ((uint8_t)0x02), //IOHȼ2 + IOH_Grade_3 = ((uint8_t)0x03), //IOHȼ3 +} GPIO_IOH_Grade_TypeDef; + +void GPIO_IOH_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef PortPins,GPIO_IOH_Grade_TypeDef GPIO_IOH_Grade); + +void GPIO_DeInit(void); +void GPIO_Init(GPIO_TypeDef GPIOx, + uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode); +void GPIO_Write(GPIO_TypeDef GPIOx, + uint8_t PortVal); +void GPIO_WriteHigh(GPIO_TypeDef GPIOx, + uint8_t PortPins); +void GPIO_WriteLow(GPIO_TypeDef GPIOx, + uint8_t PortPins); +uint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx); +BitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, + uint8_t PortPins); + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_iap.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_iap.h new file mode 100644 index 0000000..9f8ccf9 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_iap.h @@ -0,0 +1,82 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_iap.h +// : ԪӦŶ +// ģ鹦: IAP̼⺯ͷļ +// : 2022323 +// 汾: V1.100005 +// ˵: ļԪ92F/93F/92LϵеƬ +//************************************************************* + +#ifndef _sc92f_IAP_H_ +#define _sc92f_IAP_H_ + +#include "sc92f.h" +#include "intrins.h" + +typedef enum +{ + IAP_MEMTYPE_ROM = (uint8_t)0x00, //IAPΪROM + IAP_MEMTYPE_UID = (uint8_t)0x01, //IAPΪUIDֻ!!! + IAP_MEMTYPE_EEPROM = (uint8_t)0x02 //IAPΪEEPROM +} IAP_MemType_TypeDef; + + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ +|| defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) +typedef enum +{ + IAP_HOLDTIME_1500US = (uint8_t)0x08, //趨CPU Hold TimeΪ1.5MS + IAP_HOLDTIME_3000US = (uint8_t)0x04, //趨CPU Hold TimeΪ3MS + IAP_HOLDTIME_6000US = (uint8_t)0x00 //趨CPU Hold TimeΪ6MS +}IAP_HoldTime_TypeDef; +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax)|| defined (SC92F742x) || defined (SC92F730x) || defined (SC92F827X) || defined (SC92F837X) \ + || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) || defined (SC92F7490) || defined (SC93F833x) || defined (SC93F843x)\ + || defined (SC93F733x) || defined (SC93F743x) +typedef enum +{ + IAP_HOLDTIME_4MS = (uint8_t)0x00, //趨CPU Hold TimeΪ4MS + IAP_HOLDTIME_2MS = (uint8_t)0x04, //趨CPU Hold TimeΪ2MS + IAP_HOLDTIME_1MS = (uint8_t)0x08 //趨CPU Hold TimeΪ1MS +}IAP_HoldTime_TypeDef; +#elif defined (SC92FWxx) +typedef enum +{ + IAP_HOLDTIME_3000US = (uint8_t)0x00, //趨CPU Hold TimeΪ4MS + IAP_HOLDTIME_1500US = (uint8_t)0x04, //趨CPU Hold TimeΪ2MS + IAP_HOLDTIME_1000US = (uint8_t)0x08 //趨CPU Hold TimeΪ1MS +}IAP_HoldTime_TypeDef; +#elif defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + IAP_HOLDTIME_Null = (uint8_t)0x00 //FlashҪHold Time +}IAP_HoldTime_TypeDef; + +typedef enum +{ + IAP_BTLDType_APPROM = (uint8_t)0x00, //MCUλAPROMλ + IAP_BTLDType_LDROM = (uint8_t)0x01, //MCUλLDROMλ +} IAP_BTLDType_TypeDef; + + +#endif + + +void IAP_DeInit(void); +void IAP_SetHoldTime(IAP_HoldTime_TypeDef IAP_HoldTime); +void IAP_ProgramByte(uint16_t Address, + uint8_t Data, IAP_MemType_TypeDef IAP_MemType, + uint8_t WriteTimeLimit); +uint8_t IAP_ReadByte(uint16_t Address, + IAP_MemType_TypeDef IAP_MemType); + +#if defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +void IAP_SectorErase(IAP_MemType_TypeDef IAP_MemType, uint32_t IAP_SectorEraseAddress, + uint8_t WriteTimeLimit); +void IAP_BootLoaderControl(IAP_BTLDType_TypeDef IAP_BTLDType); +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_int.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_int.h new file mode 100644 index 0000000..ccc3d04 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_int.h @@ -0,0 +1,220 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_INT.h +// : +// ģ鹦 : INT̼⺯ͷļ +// ֲб: +// : 2022/01/05 +// 汾 : V1.10003 +// ˵ : +//************************************************************* + +#ifndef _sc92f_INT_H_ +#define _sc92f_INT_H_ + +#include "sc92f.h" + +typedef enum +{ + INT_TRIGGER_RISE_ONLY = (uint8_t)0x01, //ⲿжϴʽΪ + INT_TRIGGER_FALL_ONLY = (uint8_t)0x02, //ⲿжϴʽΪ½ + INT_TRIGGER_RISE_FALL = (uint8_t)0x03, //ⲿжϴʽΪ½ + INT_TRIGGER_DISABLE = (uint8_t)0x04 //رⲿжϴ +} INT_TriggerMode_Typedef; + +typedef enum +{ + INT0 = (uint8_t)0x00, //ⲿж0 + INT1 = (uint8_t)0x01, //ⲿж1 + INT2 = (uint8_t)0x02 //ⲿж2 +} INTx_Typedef; + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) +typedef enum +{ + INT01 = (uint8_t)0x02, //P11ΪINT0 + INT02 = (uint8_t)0x04, //P12ΪINT0 + INT03 = (uint8_t)0x08 //P13ΪINT0 + +} INT0x_Typedef; + +#elif defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ +|| defined (SC92FWxx) || defined (SC92F859x) || defined (SC92F759x) +typedef enum +{ + INT04 = (uint8_t)0x10, //P04ΪⲿжϽ + INT05 = (uint8_t)0x20, //P05ΪⲿжϽ + INT06 = (uint8_t)0x40, //P06ΪⲿжϽ + INT07 = (uint8_t)0x80 //P07ΪⲿжϽ +} INT0x_Typedef; + +#elif defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + INT00 = (uint8_t)0x01, //P00ΪINT0 + INT01 = (uint8_t)0x02 //P01ΪINT0 +} INT0x_Typedef; + +#elif defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) +typedef enum +{ + INT00 = (uint8_t)0x01, //P10ΪINT0 + INT01 = (uint8_t)0x02, //P11ΪINT0 + INT02 = (uint8_t)0x04, //P12ΪINT0 + INT03 = (uint8_t)0x08 //P13ΪINT0 +} INT0x_Typedef; + +#elif defined (SC92F827X) || defined (SC92F837X) || defined (SC92F7490) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + INT01 = (uint8_t)0x02, //P11ΪINT0 + INT02 = (uint8_t)0x04, //P12ΪINT0 + INT03 = (uint8_t)0x08 //P13ΪINT0 +} INT0x_Typedef; + +#endif + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ +|| defined (SC92FWxx) || defined (SC92F859x) || defined (SC92F759x) +typedef enum +{ + INT10 = (uint8_t)0x01, //P40ΪⲿжϽ + INT11 = (uint8_t)0x02, //P41ΪⲿжϽ + INT12 = (uint8_t)0x04, //P42ΪⲿжϽ + INT13 = (uint8_t)0x08, //P43ΪⲿжϽ + INT14 = (uint8_t)0x10, //P14ΪⲿжϽ + INT15 = (uint8_t)0x20, //P15ΪⲿжϽ + INT16 = (uint8_t)0x40, //P16ΪⲿжϽ + INT17 = (uint8_t)0x80 //P17ΪⲿжϽ +} INT1x_Typedef; + +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + INT10 = (uint8_t)0x01, //P14ΪINT1 + INT11 = (uint8_t)0x02, //P15ΪINT1 + INT12 = (uint8_t)0x04, //P16ΪINT1 + INT13 = (uint8_t)0x08 //P17ΪINT1 +} INT1x_Typedef; + +#elif defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + INT10 = (uint8_t)0x01, //P10ΪINT1 + INT11 = (uint8_t)0x02, //P11ΪINT1 + INT12 = (uint8_t)0x04, //P12ΪINT1 + INT13 = (uint8_t)0x08, //P13ΪINT1 + INT14 = (uint8_t)0x10, //P14ΪINT1 + INT15 = (uint8_t)0x20, //P15ΪINT1 + INT16 = (uint8_t)0x40 //P16ΪINT1 +} INT1x_Typedef; + +#elif defined (SC92F742x) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + INT10 = (uint8_t)0x01, //P14ΪINT1 + INT11 = (uint8_t)0x02, //P15ΪINT1 + INT12 = (uint8_t)0x04, //P16ΪINT1 + INT13 = (uint8_t)0x08 //P17ΪINT1 +} INT1x_Typedef; + +#elif defined (SC92F730x) || defined (SC92F827X) || defined (SC92F837X) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F7490) +typedef enum +{ + INT_Null = (uint8_t)0x00, //ûINT1 +} INT1x_Typedef; + +#endif + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ +|| defined (SC92FWxx) || defined (SC92F859x) || defined (SC92F759x) +typedef enum +{ + INT20 = (uint8_t)0x01, //P20ΪⲿжϽ + INT21 = (uint8_t)0x02, //P21ΪⲿжϽ + INT22 = (uint8_t)0x04, //P22ΪⲿжϽ + INT23 = (uint8_t)0x08 //P23ΪⲿжϽ +} INT2x_Typedef; + +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + INT20 = (uint8_t)0x01, //P04ΪINT2 + INT21 = (uint8_t)0x02, //P05ΪINT2 + INT22 = (uint8_t)0x04, //P06ΪINT2 + INT23 = (uint8_t)0x08, //P07ΪINT2 + INT24 = (uint8_t)0x10, //P20ΪINT2 + INT25 = (uint8_t)0x20 //P21ΪINT2 +} INT2x_Typedef; + +#elif defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + INT21 = (uint8_t)0x02, //P21ΪINT2 + INT22 = (uint8_t)0x04, //P22ΪINT2 + INT23 = (uint8_t)0x08, //P23ΪINT2 + INT24 = (uint8_t)0x10, //P24ΪINT2 + INT25 = (uint8_t)0x20, //P25ΪINT2 + INT26 = (uint8_t)0x40, //P26ΪINT2 + INT27 = (uint8_t)0x80 //P27ΪINT2 +} INT2x_Typedef; + +#elif defined (SC92F742x) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + INT20 = (uint8_t)0x01, //P04ΪINT2 + INT21 = (uint8_t)0x02, //P05ΪINT2 + INT22 = (uint8_t)0x04, //P06ΪINT2 + INT23 = (uint8_t)0x08, //P07ΪINT2 + INT24 = (uint8_t)0x10, //P20ΪINT2 + INT25 = (uint8_t)0x20 //P21ΪINT2 +} INT2x_Typedef; + +#elif defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) +typedef enum +{ + INT24 = (uint8_t)0x10, //P20ΪⲿжϽ + INT25 = (uint8_t)0x20 //P21ΪⲿжϽ +} INT2x_Typedef; + +#elif defined (SC92F837X) +typedef enum +{ + INT20 = (uint8_t)0x01, //P04ΪINT2 + INT21 = (uint8_t)0x02, //P05ΪINT2 + INT24 = (uint8_t)0x10, //P20ΪINT2 + INT25 = (uint8_t)0x20 //P21ΪINT2 +} INT2x_Typedef; + +#elif defined (SC92F7490) || defined (SC92F827X) +typedef enum +{ + INT21 = (uint8_t)0x02, //P05ΪINT2 + INT24 = (uint8_t)0x10, //P20ΪINT2 + INT25 = (uint8_t)0x20 //P21ΪINT2 +} INT2x_Typedef; + +#endif + + +void INT_DeInit(INTx_Typedef INTx); +void INT0_SetTriggerMode(uint8_t INT0x, + INT_TriggerMode_Typedef TriggerMode); +void INT0_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) || defined (SC92F735X) +void INT1_SetTriggerMode(uint8_t INT1x, + INT_TriggerMode_Typedef TriggerMode); +void INT1_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#endif +void INT2_SetTriggerMode(uint8_t INT2x, + INT_TriggerMode_Typedef TriggerMode); +void INT2_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_lpd.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_lpd.h new file mode 100644 index 0000000..fdc7da1 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_lpd.h @@ -0,0 +1,59 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92F_LPD.h +// : ԪӦŶ +// ģ鹦: LPD̼⺯ͷļ +// : 2022323 +// 汾: V1.100001 +// ˵: ļSC92LϵоƬ +//************************************************************* + +#ifndef _sc92f_LPD_H_ +#define _sc92f_LPD_H_ + +#include "sc92f.h" + +typedef enum +{ + LPD_VTRIP_1_85V = (uint8_t)0x00, //LPD޵ѹֵΪ1.85V + LPD_VTRIP_2_05V = (uint8_t)0x01, //LPD޵ѹֵΪ2.05V + LPD_VTRIP_2_25V = (uint8_t)0x02, //LPD޵ѹֵΪ2.25V + LPD_VTRIP_2_45V = (uint8_t)0x03, //LPD޵ѹֵΪ2.45V + LPD_VTRIP_2_85V = (uint8_t)0x04, //LPD޵ѹֵΪ2.85V + LPD_VTRIP_3_45V = (uint8_t)0x05, //LPD޵ѹֵΪ3.45V + LPD_VTRIP_3_85V = (uint8_t)0x06, //LPD޵ѹֵΪ3.85V + LPD_VTRIP_4_45V = (uint8_t)0x07, //LPD޵ѹֵΪ4.45V +} LPD_Vtrip_TypeDef; + +typedef enum +{ + LPD_FLAG_LPDIF = (uint8_t)0x40, //LPDж־ + LPD_FLAG_LPDOF = (uint8_t)0x80, //LPD״̬־λ +} LPD_Flag_TypeDef; + +/*******************************꺯*******************************/ +/***************************************************** +*:FlagStatus LPD_GetFlagStatus(LPD_Flag_Typedef LPD_Flag) +*:LPDжϱ־״̬ +*ڲ: +LPD_GetFlagStatus:LPD_Flag:жϱ־λѡ +*ڲ: +FlagStatus:LPDжϱ־λ״̬ +*****************************************************/ +#define LPD_GetFlagStatus(LPD_Flag) ((READ_BIT(SCON,LPD_Flag)) ? (SET):(RESET)) + +/***************************************************** +*:void LPD_ClearFlag(LPD_Flag_Typedef LPD_Flag) +*:LPDжϱ־״̬ +*ڲ: +LPD_Flag_Typedef;LPD_Flag:жϱ־λѡ +*ڲ:void +*****************************************************/ +#define LPD_ClearFlag() CLEAR_BIT(SCON,LPD_Flag) + +void LPD_DeInit(void); +void LPD_VtripConfig(LPD_Vtrip_TypeDef LPD_Vtrip); +void LPD_ITConfig(FunctionalState NewState, PriorityStatus Priority); +void LPD_Cmd(FunctionalState NewState); + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_mdu.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_mdu.h new file mode 100644 index 0000000..250de4d --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_mdu.h @@ -0,0 +1,48 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_mdu.h +// : +// ģ鹦 : MDU̼⺯ͷļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#ifndef _sc92f_MDU_H_ +#define _sc92f_MDU_H_ + +#include "sc92f.h" + +#if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F848x) || defined (SC92F748x)\ + || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +typedef struct +{ + uint8_t MDU_EXA3Reg; //EXA3Ĵ + uint8_t MDU_EXA2Reg; //EXA2Ĵ + uint8_t MDU_EXA1Reg; //EXA1Ĵ + uint8_t MDU_EXA0Reg; //EXA0Ĵ +} MDU_EXAxReg_Typedef; + +typedef union +{ + MDU_EXAxReg_Typedef MDU_EXAxReg; + uint32_t MDU_Temp; +} MDU_Temp_Union; + +void MDU_DeInit(void); +void MDU_MultiplicationConfig(uint16_t + Multiplicand, uint16_t Multiplier); +void MDU_DivisionConfig(uint32_t Dividend, + uint16_t Divisor); +void MDU_StartOperation(void); +uint32_t MDU_GetProduct(void); +uint32_t MDU_GetQuotient(void); +uint16_t MDU_GetRemainder(void); + +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_option.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_option.h new file mode 100644 index 0000000..d7bc40b --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_option.h @@ -0,0 +1,141 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_option.h +// : +// ģ鹦 : Customer OptionĴͷļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.0007 +// ˵ : +//************************************************************* + +#ifndef _sc92f_OPTION_H_ +#define _sc92f_OPTION_H_ + +#include "sc92f.h" + +#if defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + SYSCLK_PRESSEL_FOSC_D1 = (uint8_t)0x00, //ԤƵ Fsys = Fosc/1 + SYSCLK_PRESSEL_FOSC_D2 = (uint8_t)0x10, //ԤƵ Fsys = Fosc/2 + SYSCLK_PRESSEL_FOSC_D4 = (uint8_t)0x20, //ԤƵ Fsys = Fosc/4 + SYSCLK_PRESSEL_FOSC_D8 = (uint8_t)0x30 //ԤƵ Fsys = Fosc/8 +} SYSCLK_PresSel_TypeDef; +#else +typedef enum +{ + SYSCLK_PRESSEL_FOSC_D1 = (uint8_t)0x00, //ԤƵ Fsys = Fosc/1 + SYSCLK_PRESSEL_FOSC_D2 = (uint8_t)0x10, //ԤƵ Fsys = Fosc/2 + SYSCLK_PRESSEL_FOSC_D4 = (uint8_t)0x20, //ԤƵ Fsys = Fosc/4 + SYSCLK_PRESSEL_FOSC_D12 = (uint8_t)0x30 //ԤƵ Fsys = Fosc/12 +} SYSCLK_PresSel_TypeDef; +#endif + +#if defined (SC92F859x) || defined (SC92F759x)||defined (SC92F848x) || defined (SC92F748x) +typedef enum +{ + LVR_INVALID = (uint8_t)0x04, //LVRЧ + LVR_1_9V = (uint8_t)0x00, //LVR 1.9Vλ + LVR_2_9V = (uint8_t)0x01, //LVR 2.9Vλ + LVR_3_7V = (uint8_t)0x02, //LVR 3.7Vλ + LVR_4_3V = (uint8_t)0x03 //LVR 4.3Vλ +} LVR_Config_TypeDef; +#elif defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + LVR_INVALID = (uint8_t)0x04, //LVRЧ + LVR_1_7V = (uint8_t)0x00, //LVR 1.7Vλ + LVR_2_7V = (uint8_t)0x01, //LVR 2.7Vλ + LVR_3_7V = (uint8_t)0x02, //LVR 3.7Vλ + LVR_4_3V = (uint8_t)0x03 //LVR 4.3Vλ +} LVR_Config_TypeDef; +#else +typedef enum +{ + LVR_INVALID = (uint8_t)0x04, //LVRЧ + LVR_2_3V = (uint8_t)0x00, //LVR 2.3Vλ + LVR_2_9V = (uint8_t)0x01, //LVR 2.9Vλ + LVR_3_7V = (uint8_t)0x02, //LVR 3.7Vλ + LVR_4_3V = (uint8_t)0x03 //LVR 4.3Vλ +} LVR_Config_TypeDef; +#endif + +#if defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + IAP_OPERATERANGE_ONLY_EEPROM = (uint8_t)0x00, //ֻEEPROMIAP + IAP_OPERATERANGE__LAST_1K_CODEREGION = (uint8_t)0x04, //ROM1kEEPROMIAP + IAP_OPERATERANGE__LAST_2K_CODEREGION = (uint8_t)0x08, //ROM2kEEPROMIAP + IAP_OPERATERANGE__ALL_CODEREGION = (uint8_t)0x0c //ROMEEPROMIAP +} IAP_OperateRange_TypeDef; +#else +typedef enum +{ + IAP_OPERATERANGE_ONLY_EEPROM = (uint8_t)0x00, //ֻEEPROMIAP + IAP_OPERATERANGE__LAST_0_5K_CODEREGION = (uint8_t)0x04, //ROM0.5kEEPROMIAP + IAP_OPERATERANGE__LAST_1K_CODEREGION = (uint8_t)0x08, //ROM1kEEPROMIAP + IAP_OPERATERANGE__ALL_CODEREGION = (uint8_t)0x0c //ROMEEPROMIAP +} IAP_OperateRange_TypeDef; +#endif + + +#if defined (SC92F859x) || defined (SC92F759x) || defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_VREF_VDD = 0x00, //ѡVDDADCοѹ + ADC_VREF_1_024V = 0x40, //ѡڲ1.024VADCοѹ + ADC_VREF_2_4V = 0x80, //ѡڲ2.4VADCοѹ + ADC_VREF_2_048V = 0xC0, //ѡڲ2.048VADCοѹ +} ADC_Vref_TypeDef; +#else + +typedef enum +{ + ADC_VREF_VDD = 0x00, //ѡVDDADCοѹ + ADC_VREF_2_4V = 0x80, //ѡڲ2.4VADCοѹ +} ADC_Vref_TypeDef; +#endif + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax)\ + || defined (SC92F73Ax) || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F740x)\ + || defined (SC92F848x) || defined (SC92F748x) || defined (SC92F8003) || defined (SC92F7003) +typedef enum +{ + XTIPLL_HIGHER_THAN_12M = (uint8_t)0x40, //ӾƵʴڵ12M + XTIPLL_UNDER_12M = (uint8_t)0x00 //ӾƵС12M +} XTIPLL_Range_TypeDef; +#endif + +void OPTION_WDT_Cmd(FunctionalState NewState); + +void OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef + SYSCLK_PresSel); +#if !defined(SC92F848x) && !defined(SC92F748x) && !defined(SC92F859x) && !defined (SC92F759x) && !defined(SC92L853x) && !defined (SC92L753x) +void OPTION_RST_PIN_Cmd(FunctionalState NewState); +#endif +void OPTION_LVR_Init(LVR_Config_TypeDef + LVR_Config); +void OPTION_ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref); +void OPTION_IAP_SetOperateRange( + IAP_OperateRange_TypeDef IAP_OperateRange); + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax)\ + || defined (SC92F73Ax) || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F740x)\ + || defined (SC92F8003) || defined (SC92F7003) +void OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef + XTIPLL_Range); +#endif + +#if !defined(SC92F848x) && !defined(SC92F748x) +void OPTION_XTIPLL_Cmd(FunctionalState NewState); +#endif + +#if defined (SC92F742x)||defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) \ + ||defined (SC92F74Ax_2)||defined (SC92F84Ax_2)||defined (SC92F844xB)||defined (SC92F744xB) \ + ||defined (SC92F859x) || defined (SC92F759x) ||defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +void OPTION_JTG_Cmd(FunctionalState NewState); +#endif + + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_pwm.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_pwm.h new file mode 100644 index 0000000..2309a85 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_pwm.h @@ -0,0 +1,406 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_pwm.h +// : +// ģ鹦 : PWM̼⺯ͷļ +// ֲб: +// : 202276 +// 汾 : V1.10005 +// ˵ : +//************************************************************* + +#ifndef _sc92f_PWM_H_ +#define _sc92f_PWM_H_ + +#include "sc92f.h" +#if !defined (SC92F7490) +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + PWM_PRESSEL_FHRC_D1 = (uint8_t)0x00, //PWMԤƵΪFhrc/1 + PWM_PRESSEL_FHRC_D2 = (uint8_t)0x10, //PWMԤƵΪFhrc/2 + PWM_PRESSEL_FHRC_D4 = (uint8_t)0x20, //PWMԤƵΪFhrc/4 + PWM_PRESSEL_FHRC_D8 = (uint8_t)0x30 //PWMԤƵΪFhrc/8 +} PWM_PresSel_TypeDef; + +typedef enum +{ + PWM40 = (uint8_t)0x01, //PWMͨѡ:PWM40 + PWM41 = (uint8_t)0x02, //PWMͨѡ:PWM41 + PWM42 = (uint8_t)0x04, //PWMͨѡ:PWM42 + PWM43 = (uint8_t)0x08, //PWMͨѡ:PWM43 + PWM50 = (uint8_t)0x10, //PWMͨѡ:PWM50 + PWM51 = (uint8_t)0x20, //PWMͨѡ:PWM51 + PWM52 = (uint8_t)0x40, //PWMͨѡ:PWM52 + PWM53 = (uint8_t)0x80 //PWMͨѡ:PWM53 +} PWM_OutputPin_TypeDef; +#elif defined (SC92F742x) || defined (SC92F730x) || defined (SC92F827X) || defined (SC92F837X) || defined (SC92F725X) || defined(SC92F735X) +typedef enum +{ + PWM_PRESSEL_FSYS_D1 = (uint8_t)0x00, //PWMԤƵΪFsys/1 + PWM_PRESSEL_FSYS_D2 = (uint8_t)0x01, //PWMԤƵΪFsys/2 + PWM_PRESSEL_FSYS_D4 = (uint8_t)0x02, //PWMԤƵΪFsys/4 + PWM_PRESSEL_FSYS_D8 = (uint8_t)0x03, //PWMԤƵΪFsys/8 + PWM_PRESSEL_FSYS_D32 = (uint8_t)0x04, //PWMԤƵΪFsys/32 + PWM_PRESSEL_FSYS_D64 = (uint8_t)0x05, //PWMԤƵΪFsys/64 + PWM_PRESSEL_FSYS_D128 = (uint8_t)0x06, //PWMԤƵΪFsys/128 + PWM_PRESSEL_FSYS_D256 = (uint8_t)0x07 //PWMԤƵΪFsys/256 +} PWM_PresSel_TypeDef; + +#if defined (SC92F827X) +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 +} PWM_OutputPin_TypeDef; +#elif defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 +} PWM_OutputPin_TypeDef; +#elif defined (SC92F837X) +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM3 = (uint8_t)0x08, //PWMͨѡ:PWM3 +} PWM_OutputPin_TypeDef; +#elif defined (SC92F730x) +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM4 = (uint8_t)0x10, //PWMͨѡ:PWM4 + PWM5 = (uint8_t)0x20 //PWMͨѡ:PWM5 +} PWM_OutputPin_TypeDef; +#else +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM3 = (uint8_t)0x08, //PWMͨѡ:PWM3 + PWM4 = (uint8_t)0x10, //PWMͨѡ:PWM4 + PWM5 = (uint8_t)0x20 //PWMͨѡ:PWM5 +} PWM_OutputPin_TypeDef; +#endif + +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) +typedef enum +{ + PWM_PRESSEL_FOSC_D1 = (uint8_t)0x00, //PWMԤƵΪFosc/1 + PWM_PRESSEL_FOSC_D2 = (uint8_t)0x01, //PWMԤƵΪFosc/2 + PWM_PRESSEL_FOSC_D8 = (uint8_t)0x02, //PWMԤƵΪFosc/8 + PWM_PRESSEL_FOSC_D32 = (uint8_t)0x03 //PWMԤƵΪFosc/32 +} PWM_PresSel_TypeDef; +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM3 = (uint8_t)0x08, //PWMͨѡ:PWM3 + PWM4 = (uint8_t)0x10, //PWMͨѡ:PWM4 + PWM5 = (uint8_t)0x20, //PWMͨѡ:PWM5 +} PWM_OutputPin_TypeDef; + +typedef enum +{ + PWM0PWM3 = (uint8_t)0x00, //PWMģʽͨѡ:PWM0PWM3 + PWM1PWM4 = (uint8_t)0x01, //PWMģʽͨѡ:PWM1PWM4 + PWM2PWM5 = (uint8_t)0x02 //PWMģʽͨѡ:PWM2PWM5 +} PWM_ComplementaryOutputPin_TypeDef; +#elif defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + PWM_PRESSEL_FOSC_D1 = (uint8_t)0x00, //PWMԤƵΪFosc/1 + PWM_PRESSEL_FOSC_D2 = (uint8_t)0x01, //PWMԤƵΪFosc/2 + PWM_PRESSEL_FOSC_D8 = (uint8_t)0x02, //PWMԤƵΪFosc/8 + PWM_PRESSEL_FOSC_D32 = (uint8_t)0x03 //PWMԤƵΪFosc/32 +} PWM_PresSel_TypeDef; +typedef enum +{ + PWM2_OutputPin_P26 = ((uint8_t)0x00), //PWM2ѡP26 + PWM2_OutputPin_P14 = ((uint8_t)0x04) //PWM2ѡP14 +} PWM2_OutputPin_TypeDef; + +typedef enum +{ + PWM5_OutputPin_P12 = ((uint8_t)0x00), //PWM5ѡP12 + PWM5_OutputPin_P21 = ((uint8_t)0x08) //PWM5ѡP21 +} PWM5_OutputPin_TypeDef; + +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM3 = (uint8_t)0x08, //PWMͨѡ:PWM3 + PWM4 = (uint8_t)0x10, //PWMͨѡ:PWM4 + PWM5 = (uint8_t)0x20, //PWMͨѡ:PWM5 + PWM6 = (uint8_t)0x40, //PWMͨѡ:PWM6 +} PWM_OutputPin_TypeDef; + +typedef enum +{ + PWM0PWM3 = (uint8_t)0x00, //PWMģʽͨѡ:PWM0PWM3 + PWM1PWM4 = (uint8_t)0x01, //PWMģʽͨѡ:PWM1PWM4 + PWM2PWM5 = (uint8_t)0x02 //PWMģʽͨѡ:PWM2PWM5 +} PWM_ComplementaryOutputPin_TypeDef; +#elif defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + PWM_PRESSEL_FSYS_D1 = (uint8_t)0x00, //PWMԤƵΪFsys/1 + PWM_PRESSEL_FSYS_D2 = (uint8_t)0x01, //PWMԤƵΪFsys/2 + PWM_PRESSEL_FSYS_D4 = (uint8_t)0x02, //PWMԤƵΪFsys/4 + PWM_PRESSEL_FSYS_D8 = (uint8_t)0x03, //PWMԤƵΪFsys/8 + PWM_PRESSEL_FSYS_D32 = (uint8_t)0x04, //PWMԤƵΪFsys/32 + PWM_PRESSEL_FSYS_D64 = (uint8_t)0x05, //PWMԤƵΪFsys/64 + PWM_PRESSEL_FSYS_D128 = (uint8_t)0x06, //PWMԤƵΪFsys/128 + PWM_PRESSEL_FSYS_D256 = (uint8_t)0x07 //PWMԤƵΪFsys/256 +} PWM_PresSel_TypeDef; + +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 +} PWM_OutputPin_TypeDef; + +typedef enum +{ + PWM0_OutputPin_P00 = ((uint8_t)0x00), //PWM2ѡP26 + PWM0_OutputPin_P25 = ((uint8_t)0x01) //PWM2ѡP14 +} PWM0_OutputPin_TypeDef; + +typedef enum +{ + PWM1_OutputPin_P01 = ((uint8_t)0x00), //PWM5ѡP12 + PWM1_OutputPin_P26 = ((uint8_t)0x02) //PWM5ѡP21 +} PWM1_OutputPin_TypeDef; + +typedef enum +{ + PWM2_OutputPin_P02 = ((uint8_t)0x00), //PWM2ѡP26 + PWM2_OutputPin_P27 = ((uint8_t)0x04) //PWM2ѡP14 +} PWM2_OutputPin_TypeDef; + +//duty΢ƣĸPWM2Ϊһѭ: +typedef enum +{ + PWM_DutyMode0 = ((uint8_t)0x00), //00:ĸPWM2dutyΪPDT2趨ֵ(DDDD) + PWM_DutyMode1 = ((uint8_t)0x01), //01:һPWM2dutyΪPDT2趨ֵ1PWM2dutyΪPDT2趨ֵ(D+1DDD) + PWM_DutyMode2 = ((uint8_t)0x02), //10:һ͵ڶPWM2dutyΪPDT2趨ֵ1PWM2dutyΪPDT2趨ֵ(D+1D+1DD) + PWM_DutyMode3 = ((uint8_t)0x03), //11:һڶ͵PWM2dutyΪPDT2趨ֵ1ĸPWM2DutyΪPDT2趨ֵ (D+1D+1D+1D) +} PWM_DutyMode_TypeDef; +#elif defined (SC92FWxx) +typedef enum +{ + PWM0_PRESSEL_FHRC_D1 = (uint8_t)0x00, //PWM0ԤƵΪFhrc/1 + PWM0_PRESSEL_FHRC_D2 = (uint8_t)0x10, //PWM0ԤƵΪFhrc/2 + PWM0_PRESSEL_FHRC_D4 = (uint8_t)0x20, //PWM0ԤƵΪFhrc/4 + PWM0_PRESSEL_FHRC_D8 = (uint8_t)0x30, //PWM0ԤƵΪFhrc/8 + PWM1_PRESSEL_FHRC_D1 = (uint8_t)0x01, //PWM1ԤƵΪFhrc/1 + PWM1_PRESSEL_FHRC_D2 = (uint8_t)0x11, //PWM1ԤƵΪFhrc/2 + PWM1_PRESSEL_FHRC_D4 = (uint8_t)0x21, //PWM1ԤƵΪFhrc/4 + PWM1_PRESSEL_FHRC_D8 = (uint8_t)0x31, //PWM1ԤƵΪFhrc/8 +} PWM_PresSel_TypeDef; + +typedef enum +{ + PWM000 = (uint8_t)0x00, //PWMͨѡ: PWM000 + PWM001 = (uint8_t)0x02, //PWMͨѡ: PWM001 + PWM002 = (uint8_t)0x04, //PWMͨѡ: PWM002 + PWM003 = (uint8_t)0x06, //PWMͨѡ: PWM003 + PWM004 = (uint8_t)0x08, //PWMͨѡ: PWM004 + PWM005 = (uint8_t)0x0A, //PWMͨѡ: PWM005 + PWM006 = (uint8_t)0x0C, //PWMͨѡ: PWM006 + PWM007 = (uint8_t)0x0E, //PWMͨѡ: PWM007 + PWM010 = (uint8_t)0x10, //PWMͨѡ: PWM010 + PWM011 = (uint8_t)0x12, //PWMͨѡ: PWM011 + PWM012 = (uint8_t)0x14, //PWMͨѡ: PWM012 + PWM013 = (uint8_t)0x16, //PWMͨѡ: PWM013 + PWM014 = (uint8_t)0x18, //PWMͨѡ: PWM014 + PWM015 = (uint8_t)0x1A, //PWMͨѡ: PWM015 + PWM016 = (uint8_t)0x1C, //PWMͨѡ: PWM016 + PWM017 = (uint8_t)0x1E, //PWMͨѡ: PWM017 + PWM020 = (uint8_t)0x20, //PWMͨѡ: PWM020 + PWM021 = (uint8_t)0x22, //PWMͨѡ: PWM021 + PWM022 = (uint8_t)0x24, //PWMͨѡ: PWM022 + PWM023 = (uint8_t)0x26, //PWMͨѡ: PWM023 + PWM024 = (uint8_t)0x28, //PWMͨѡ: PWM024 + PWM025 = (uint8_t)0x2A, //PWMͨѡ: PWM025 + PWM026 = (uint8_t)0x2C, //PWMͨѡ: PWM026 + PWM027 = (uint8_t)0x2E, //PWMͨѡ: PWM027 + PWM030 = (uint8_t)0x30, //PWMͨѡ: PWM030 + PWM031 = (uint8_t)0x32, //PWMͨѡ: PWM031 + PWM032 = (uint8_t)0x34, //PWMͨѡ: PWM032 + PWM033 = (uint8_t)0x36, //PWMͨѡ: PWM033 + PWM034 = (uint8_t)0x38, //PWMͨѡ: PWM034 + PWM035 = (uint8_t)0x3A, //PWMͨѡ: PWM025 + PWM036 = (uint8_t)0x3C, //PWMͨѡ: PWM026 + PWM037 = (uint8_t)0x3E, //PWMͨѡ: PWM027 + PWM140 = (uint8_t)0x40, //PWMͨѡ: PWM140 + PWM141 = (uint8_t)0x42, //PWMͨѡ: PWM141 + PWM142 = (uint8_t)0x44, //PWMͨѡ: PWM142 + PWM143 = (uint8_t)0x46, //PWMͨѡ: PWM153 + PWM150 = (uint8_t)0x48, //PWMͨѡ: PWM150 + PWM151 = (uint8_t)0x4A, //PWMͨѡ: PWM151 + PWM152 = (uint8_t)0x4C, //PWMͨѡ: PWM152 + PWM153 = (uint8_t)0x4E, //PWMͨѡ: PWM153 +} PWM_OutputPin_TypeDef; + +typedef enum +{ + PWM0_Type = (uint8_t)0x00, //PWMԤƵΪFhrc/1 + PWM1_Type = (uint8_t)0x01, //PWMԤƵΪFhrc/2 +} PWM_Type_TypeDef; + +#elif defined (SC92L853x) || defined (SC92L753x) +//PWMԤƵѡ +typedef enum +{ + PWM_PRESSEL_FHRC_D1 = (uint8_t)0x00, //PWM0ԤƵΪFhrc/1 + PWM_PRESSEL_FHRC_D2 = (uint8_t)0x10, //PWM0ԤƵΪFhrc/2 + PWM_PRESSEL_FHRC_D4 = (uint8_t)0x20, //PWM0ԤƵΪFhrc/4 + PWM_PRESSEL_FHRC_D8 = (uint8_t)0x30, //PWM0ԤƵΪFhrc/8 +} PWM_PresSel_TypeDef; + +//PWMͨѡ +typedef enum +{ + PWM0 = (uint8_t)0x00, //PWMͨѡ: PWM00 + PWM1 = (uint8_t)0x02, //PWMͨѡ: PWM01 + PWM2 = (uint8_t)0x04, //PWMͨѡ: PWM02 + PWM3 = (uint8_t)0x06, //PWMͨѡ: PWM03 + PWM4 = (uint8_t)0x08, //PWMͨѡ: PWM04 + PWM5 = (uint8_t)0x0A, //PWMͨѡ: PWM05 + PWM6 = (uint8_t)0x0C, //PWMͨѡ: PWM06 + PWM7 = (uint8_t)0x0E, //PWMͨѡ: PWM07 +} PWM_OutputPin_TypeDef; + +//PWMģʽ +typedef enum +{ + PWM0_Edge_Aligned_Mode = (uint8_t)0x00, //PWMضģʽ + PWM0_Center_Alignment_Mode = (uint8_t)0x01, //PWMмģʽ +} PWM_Aligned_Mode_TypeDef; + +//PWMϼģʽ +typedef enum +{ + PWM0_Latch_Mode = ((uint8_t)0x00), //PWMϼģʽ:ģʽ + PWM0_Immediate_Mode = ((uint8_t)0x20) //PWMϼģʽ:ģʽ +} PWM_FaultDetectionMode_TypeDef; + +//PWMϼƽѡ +typedef enum +{ + PWM0_FaultDetectionVoltage_Low = ((uint8_t)0x00), //PWMϼ͵ƽѡ + PWM0_FaultDetectionVoltage_high = ((uint8_t)0x10) //PWMϼߵƽѡ +} PWM_FaultDetectionVoltageSelect_TypeDef; + +//PWMϼź˲ʱ +typedef enum +{ + PWM0_WaveFilteringTime_0us = ((uint8_t)0x00), //PWMϼź˲ʱ0us + PWM0_WaveFilteringTime_1us = ((uint8_t)0x01), //PWMϼź˲ʱ1us + PWM0_WaveFilteringTime_4us = ((uint8_t)0x02), //PWMϼź˲ʱ4us + PWM0_WaveFilteringTime_16us = ((uint8_t)0x03) //PWMϼź˲ʱ16us +} PWM_FaultDetectionWaveFilteringTime_TypeDef; + +//PWMģʽͨѡ +typedef enum +{ + PWM0PWM1 = (uint8_t)0x00, //PWMģʽͨѡ:PWM00PWM01 + PWM2PWM3 = (uint8_t)0x04, //PWMģʽͨѡ:PWM02PWM03 + PWM4PWM5 = (uint8_t)0x08, //PWMģʽͨѡ:PWM04PWM05 + PWM6PWM7 = (uint8_t)0x0C //PWMģʽͨѡ:PWM06PWM07 +} PWM_ComplementaryOutputPin_TypeDef; + +//PWMԴѡ +typedef enum +{ + PWM0_Type = (uint8_t)0x00, //PWM0 +} PWM_Type_TypeDef; +#endif + +typedef enum +{ + PWM_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), //PINΪGPIO + PWM_OUTPUTSTATE_ENABLE = ((uint8_t)0x01) //PINΪPWM +} PWM_OutputState_TypeDef; + +typedef enum +{ + PWM_POLARITY_NON_INVERT = ((uint8_t)0x00), //PWM` + PWM_POLARITY_INVERT = ((uint8_t)0x01) //PWM +} PWM_Polarity_TypeDef; + +void PWM_DeInit(void); +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period); +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState); +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity); +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle); +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority); + +#if defined (SC92FWxx) || defined (SC92L853x) || defined (SC92L753x) +#if !defined (SC92FWxx) +void PWM_Aligned_Mode_Select(PWM_Aligned_Mode_TypeDef PWM_Aligned_Mode); +void PWM_FaultDetectionModeConfigEX(PWM_Type_TypeDef PWM_Type, + PWM_FaultDetectionMode_TypeDef FaultDetectionMode, + PWM_FaultDetectionVoltageSelect_TypeDef FaultDetectionVoltageSelect, + PWM_FaultDetectionWaveFilteringTime_TypeDef FaultDetectionWaveFilteringTime); +#endif +void PWM_CmdEX(PWM_Type_TypeDef PWM_Type, + FunctionalState NewState); +FlagStatus PWM_GetFlagStatusEX(PWM_Type_TypeDef PWM_Type); +void PWM_ClearFlagEX(PWM_Type_TypeDef PWM_Type); +void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle, + PWM_OutputState_TypeDef PWM_OutputState); + +void PWM_ITConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState, PriorityStatus Priority); +FlagStatus PWM_GetFaultDetectionFlagStatusEX(PWM_Type_TypeDef PWM_Type); +void PWM_ClearFaultDetectionFlagEX(PWM_Type_TypeDef PWM_Type); +void PWM_FaultDetectionConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState); +#else +void PWM_Cmd(FunctionalState NewState); +FlagStatus PWM_GetFlagStatus(void); +void PWM_ClearFlag(void); +#endif + +/* ͨԼú */ +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax)|| defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) || defined (SC92F848x) || defined (SC92F748x) || defined (SC92F848x) || defined (SC92F748x) +void PWM_ComplementaryModeConfig( PWM_ComplementaryOutputPin_TypeDef + PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle); +void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime); +#endif +#if defined (SC92L853x) || defined (SC92L753x) +void PWM_DeadTimeConfigEX(PWM_Type_TypeDef PWM_Type, uint8_t PWM_RisingDeadTime, uint8_t PWM_FallingDeadTime); +#endif +/* PWMͨѡ */ +#if defined (SC92F8003) || defined (SC92F740x) || defined (SC92F7003) + void PWM_PWM2Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin); + void PWM_PWM5Selection(PWM5_OutputPin_TypeDef PWM5_OutputPin); +#endif +#if defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) + void PWM_PWM0Selection(PWM0_OutputPin_TypeDef PWM0_OutputPin); + void PWM_PWM1Selection(PWM1_OutputPin_TypeDef PWM1_OutputPin); + void PWM_PWM2Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin); + void PMM_DutyModeSelection(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_DutyMode_TypeDef PWM_DutyMode); +#endif + +#endif + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_pwr.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_pwr.h new file mode 100644 index 0000000..ddb4f72 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_pwr.h @@ -0,0 +1,24 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_pwr.h +// : +// ģ鹦 : PWR̼⺯ͷļ +// ֲб: +// : 2020/8/18 +// 汾 : V1.0 +// ˵ : +//************************************************************* + +#ifndef _sc92f_PWR_H_ +#define _sc92f_PWR_H_ + +#include "sc92f.h" +#include + +void PWR_DeInit(void); +void PWR_EnterSTOPMode(void); +void PWR_EnterIDLEMode(void); + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_ssi.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_ssi.h new file mode 100644 index 0000000..4d9d33e --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_ssi.h @@ -0,0 +1,282 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ssi.h +// : +// ģ鹦 : SSI̼⺯ͷļ +// ֲб: +// : 2020/08/20 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#ifndef _sc92f_SSI_H_ +#define _sc92f_SSI_H_ + +#include "sc92f.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)||defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined (SC92F83Ax) || defined (SC92F73Ax) || defined (SC92F7003) || defined(SC92F8003) || defined (SC92F740x) || defined (SC92F827X)\ + || defined (SC92F837X) || defined (SC92FWxx) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92F848x) || defined (SC92F748x)\ + || defined (SC92F859x) || defined (SC92F859x) +typedef enum +{ + SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} SPI_FirstBit_TypeDef; + +typedef enum +{ + SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x00, //SPIʱΪϵͳʱӳ4 + SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x01, //SPIʱΪϵͳʱӳ8 + SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x02, //SPIʱΪϵͳʱӳ16 + SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x03, //SPIʱΪϵͳʱӳ32 + SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x04, //SPIʱΪϵͳʱӳ64 + SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x05, //SPIʱΪϵͳʱӳ128 + SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x06, //SPIʱΪϵͳʱӳ256 + SPI_BAUDRATEPRESCALER_512 = (uint8_t)0x07 //SPIʱΪϵͳʱӳ512 +} SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} SPI_Mode_TypeDef; + +typedef enum +{ + SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} SPI_ClockPolarity_TypeDef; + +typedef enum +{ + SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} SPI_ClockPhase_TypeDef; + +typedef enum + { + //Ϊӻ + TWI_SlaveBusy = 0x00, + TWI_SlaveReceivedaAddress = 0x01, + TWI_SlaveReceivedaData = 0x02, + TWI_SlaveSendData = 0x03, + TWI_SlaveReceivedaUACK = 0x04, + TWI_SlaveDisableACK = 0x05, + TWI_SlaveAddressError = 0x06, + +}SSI_TWIState_TypeDef; + +typedef enum +{ + SPI_TXE_DISINT = (uint8_t)0x00, //TXEΪ1ʱж + SPI_TXE_ENINT = (uint8_t)0x01 //TXEΪ1ʱж +} SPI_TXE_INT_TypeDef; + +typedef enum +{ + UART1_Mode_10B = 0X00,//UART1Ϊ10λģʽ + UART1_Mode_11B = 0X80 //UART1Ϊ11λģʽ +} UART1_Mode_TypeDef; + +typedef enum +{ + UART1_RX_ENABLE = 0X10,//UART1 + UART1_RX_DISABLE = 0X00 //UART1ֹ +} UART1_RX_TypeDef; + +typedef enum +{ + SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + UART1_FLAG_TI = (uint8_t)0x02, //UART1жϱ־λTI + UART1_FLAG_RI = (uint8_t)0x01 //UART1жϱ־λRI +} SSI_Flag_TypeDef; + +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + SSI_PinSelection_P10P27P26 = (uint8_t)0x00, //SSIΪP10P27P26 + SSI_PinSelection_P21P22P23 = (uint8_t)0x20, //SSIΪP21P22P23 + SSI_PinSelection_URATP27 = (uint8_t)0x00, //SSIUARTΪP27,RX + SSI_PinSelection_URATP22 = (uint8_t)0x20 //SSIUARTΪP22,RX +} SSI_PinSelection_TypeDef; +void SSI_PinSelection(SSI_PinSelection_TypeDef + PinSeletion); +#endif + +void SSI_DeInit(void); +void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT); +void SSI_SPI_Cmd(FunctionalState NewState); +void SSI_SPI_SendData(uint8_t Data); +uint8_t SSI_SPI_ReceiveData(void); +void SSI_TWI_Init(uint8_t TWI_Address); +void SSI_TWI_AcknowledgeConfig(FunctionalState NewState); +void SSI_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus SSI_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState); +FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG); +void SSI_TWI_Cmd(FunctionalState NewState); +void SSI_TWI_SendData(uint8_t Data); +uint8_t SSI_TWI_ReceiveData(void); +void SSI_UART1_Init(uint32_t UART1Fsys, + uint32_t BaudRate, UART1_Mode_TypeDef Mode, + UART1_RX_TypeDef RxMode); +void SSI_UART1_SendData8(uint8_t Data); +uint8_t SSI_UART1_ReceiveData8(void); +void SSI_UART1_SendData9(uint16_t Data); +uint16_t SSI_UART1_ReceiveData9(void); +void SSI_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG); +#endif + +#if defined (SC92F742x) || defined (SC92F7490) +typedef enum +{ + SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} SPI_FirstBit_TypeDef; + +typedef enum +{ + SPI_BAUDRATEPRESCALER_1 = (uint8_t)0x00, //SPIʱΪFsys/1 + SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x01, //SPIʱΪFsys/2 + SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x02, //SPIʱΪFsys/4 + SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x03, //SPIʱΪFsys/8 + SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x04, //SPIʱΪFsys/16 + SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x05, //SPIʱΪFsys/32 + SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x06, //SPIʱΪFsys/64 + SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x07 //SPIʱΪFsys/128 +} SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} SPI_Mode_TypeDef; + +typedef enum +{ + SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} SPI_ClockPolarity_TypeDef; + +typedef enum +{ + SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} SPI_ClockPhase_TypeDef; + +typedef enum +{ + SPI_TXE_DISINT = (uint8_t)0x00, //TXEΪ0ʱж + SPI_TXE_ENINT = (uint8_t)0x01 //TXEΪ1ʱж +} SPI_TXE_INT_TypeDef; + +typedef enum +{ + UART_Mode_10B = 0X00, //UARTΪ10λģʽ + UART_Mode_11B = 0X80 //UARTΪ11λģʽ +} UART_Mode_TypeDef; + +typedef enum +{ + UART_RX_ENABLE = 0X10, //UART + UART_RX_DISABLE = 0X00 //UARTֹ +} UART_RX_TypeDef; + +typedef enum{ + //Ϊӻ + TWI_SlaveBusy = 0x00, + TWI_SlaveReceivedaAddress = 0x01, + TWI_SlaveReceivedaData = 0x02, + TWI_SlaveSendData = 0x03, + TWI_SlaveReceivedaUACK = 0x04, + TWI_SlaveDisableACK = 0x05, + TWI_SlaveAddressError = 0x06, + +}SSI_TWIState_TypeDef; + +typedef enum +{ + SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + UART_FLAG_TI = (uint8_t)0x02, //UARTжϱ־λTI + UART_FLAG_RI = (uint8_t)0x01 //UARTжϱ־λRI +} SSI_Flag_TypeDef; + +void SSI0_DeInit(void); +void SSI0_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT); +void SSI0_SPI_Cmd(FunctionalState NewState); +void SSI0_SPI_SendData(uint8_t Data); +uint8_t SSI0_SPI_ReceiveData(void); +void SSI0_TWI_Init(uint8_t TWI_Address); +void SSI0_TWI_AcknowledgeConfig(FunctionalState NewState); +void SSI0_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus SSI0_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState); +void SSI0_TWI_Cmd(FunctionalState NewState); +void SSI0_TWI_SendData(uint8_t Data); +uint8_t SSI0_TWI_ReceiveData(void); +void SSI0_UART_Init(uint32_t UARTFsys, + uint32_t BaudRate, UART_Mode_TypeDef Mode, + UART_RX_TypeDef RxMode); +void SSI0_UART_SendData8(uint8_t Data); +uint8_t SSI0_UART_ReceiveData8(void); +void SSI0_UART_SendData9(uint16_t Data); +uint16_t SSI0_UART_ReceiveData9(void); +void SSI0_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +FlagStatus SSI0_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG); +void SSI0_ClearFlag(SSI_Flag_TypeDef SSI_FLAG); + +void SSI1_DeInit(void); +void SSI1_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT); +void SSI1_SPI_Cmd(FunctionalState NewState); +void SSI1_SPI_SendData(uint8_t Data); +uint8_t SSI1_SPI_ReceiveData(void); +void SSI1_TWI_Init(uint8_t TWI_Address); +void SSI1_TWI_AcknowledgeConfig(FunctionalState NewState); +void SSI1_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus SSI1_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState); +void SSI1_TWI_Cmd(FunctionalState NewState); +void SSI1_TWI_SendData(uint8_t Data); +uint8_t SSI1_TWI_ReceiveData(void); +void SSI1_UART_Init(uint32_t UARTFsys, + uint32_t BaudRate, UART_Mode_TypeDef Mode, + UART_RX_TypeDef RxMode); +void SSI1_UART_SendData8(uint8_t Data); +uint8_t SSI1_UART_ReceiveData8(void); +void SSI1_UART_SendData9(uint16_t Data); +uint16_t SSI1_UART_ReceiveData9(void); +void SSI1_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +FlagStatus SSI1_GetFlagStatus(SSI_Flag_TypeDef + SSI_FLAG); +void SSI1_ClearFlag(SSI_Flag_TypeDef SSI_FLAG); +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer0.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer0.h new file mode 100644 index 0000000..5dcd8bc --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer0.h @@ -0,0 +1,139 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_tiemr0.h +// : ԪӦŶ +// ģ鹦: TIMER0̼⺯Cļ +// : 2022323 +// 汾: V1.10001 +// ˵: +//************************************************************* + +#ifndef _sc92f_TIMER0_H_ +#define _sc92f_TIMER0_H_ + +#include "sc92f.h" + +typedef enum +{ + TIM0_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER0Դϵͳʱ12Ƶ + TIM0_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER0Դϵͳʱ +} TIM0_PresSel_TypeDef; + +typedef enum +{ + TIM0_MODE_TIMER = ((uint8_t)0x01), //TIMER0ʱ + TIM0_MODE_COUNTER = ((uint8_t)0x02) //TIMER0 +} TIM0_CountMode_TypeDef; + +typedef enum +{ + TIM0_WORK_MODE0 = ((uint8_t)0x00), //TIMER0ѡģʽ0 + TIM0_WORK_MODE1 = ((uint8_t)0x01), //TIMER0ѡģʽ1 + TIM0_WORK_MODE2 = ((uint8_t)0x02), //TIMER0ѡģʽ2 + TIM0_WORK_MODE3 = ((uint8_t)0x03) //TIMER0ѡģʽ3 +} TIM0_WorkMode_TypeDef; + +/************************꺯************************/ +/************************************************** +*:void TIM0_Mode0SetReloadCounter(uint16_t TIM0_SetCounter) +*:TIMER0ģʽ0ֵغ +*ڲ: +uint16_t:TIM0_SetCounter:TIMER0ֵ +*ڲ:void +**************************************************/ +#define TIM0_Mode0SetReloadCounter(TIM0_SetCounter) \ + do{ \ + TL0 = (uint8_t)TIM0_SetCounter; \ + TH0 = (TIM0_SetCounter >> 5); \ + }while(0) + +/************************************************** +*:void TIM0_Mode1SetReloadCounter(uint16_t TIM0_SetCounter) +*:TIMER0ģʽ1ֵغ +*ڲ: +uint16_t:TIM0_SetCounter:TIMER0ֵ +*ڲ:void +**************************************************/ +#define TIM0_Mode1SetReloadCounter(TIM0_SetCounter) \ + do{ \ + TL0 = (uint8_t)TIM0_SetCounter; \ + TH0 = (TIM0_SetCounter >> 8); \ + }while(0) + +/************************************************** +*:void TIM0_SetTH0Counter(uint8_t TIM0_SetCounter) +*:TIMER0 TH0ֵ +*ڲ: +uint8_t:TIM0_SetCounter:TH0 +*ڲ:void +**************************************************/ +#define TIM0_SetTH0Counter(TIM0_SetCounter) (TH0 = TIM0_SetCounter) + +/************************************************** +*:void TIM0_SetTL0Counter(uint8_t TIM0_SetCounter) +*:TIMER0 TL0ֵ +*ڲ: +uint8_t:TIM0_SetCounter:TL0 +*ڲ:void +**************************************************/ +#define TIM0_SetTL0Counter(TIM0_SetCounter) (TL0 = TIM0_SetCounter) + +/***************************************************** +*:void TIM0_Cmd(FunctionalState NewState) +*:TIMER0ܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +#define TIM0_Cmd(NewState) (TR0 = (bit)NewState) + +/***************************************************** +*:FlagStatus TIM0_GetFlagStatus(void) +*:TIMER0жϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:TIMER0жϱ־״̬ +*****************************************************/ +#define TIM0_GetFlagStatus() (TF0) + +/***************************************************** +*:void TIM0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:TIMER1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +#define TIM0_ITConfig(NewState,Priority) \ + do{ \ + ET0 = (bit)NewState; \ + IPT0 = (bit)Priority; \ + }while(0) + +/***************************************************** +*:void TIM0_ClearFlag(void) +*:TIMER0жϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +#define TIM0_ClearFlag() (TF0 = 0) + +void TIM0_DeInit(void); +void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef + TIM0_PrescalerSelection, + TIM0_CountMode_TypeDef TIM0_CountMode); +void TIM0_WorkMode0Config(uint16_t + TIM0_SetCounter); +void TIM0_WorkMode1Config(uint16_t + TIM0_SetCounter); +void TIM0_WorkMode2Config(uint8_t + TIM0_SetCounter); +void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, + uint8_t TIM1_SetCounter); +void TIM0_WorkModeConfig(TIM0_WorkMode_TypeDef + TIM0_WorkMode, uint16_t TIM0_SetCounter1, + uint16_t TIM0_SetCounter2); + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer1.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer1.h new file mode 100644 index 0000000..bdf392f --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer1.h @@ -0,0 +1,116 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timer1.h +// : +// ģ鹦 : TIMER1̼⺯ͷļ +// ֲб: +// : 2020/8/18 +// 汾 : V1.0 +// ˵ : +//************************************************************* + +#ifndef _sc92f_TIMER1_H_ +#define _sc92f_TIMER1_H_ + +#include "sc92f.h" + +typedef enum +{ + TIM1_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER1Դϵͳʱ12Ƶ + TIM1_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER1Դϵͳʱ +} TIM1_PresSel_TypeDef; + +typedef enum +{ + TIM1_MODE_TIMER = ((uint8_t)0x01), //TIMER1ʱ + TIM1_MODE_COUNTER = ((uint8_t)0x02) //TIMER1 +} TIM1_CountMode_TypeDef; + +typedef enum +{ + TIM1_WORK_MODE0 = ((uint8_t)0x00), //TIMER1ѡģʽ0 + TIM1_WORK_MODE1 = ((uint8_t)0x01), //TIMER1ѡģʽ1 + TIM1_WORK_MODE2 = ((uint8_t)0x02), //TIMER1ѡģʽ2 +} TIM1_WorkMode_TypeDef; + +/************************꺯************************/ +/************************************************** +*:void TIM1_Mode0SetReloadCounter(uint16_t TIM1_SetCounter) +*:TIMER1ģʽ0ֵغ +*ڲ: +uint16_t:TIM1_SetCounter:TIMER0ֵ +*ڲ:void +**************************************************/ +#define TIM1_Mode0SetReloadCounter(TIM1_SetCounter) \ + do{ \ + TL1 = (uint8_t)TIM1_SetCounter; \ + TH1 = (TIM1_SetCounter >> 5); \ + }while(0) + +/************************************************** +*:void TIM1_Mode1SetReloadCounter(uint16_t TIM1_SetCounter) +*:TIMER0ģʽ1ֵغ +*ڲ: +uint16_t:TIM1_SetCounter:TIMER0ֵ +*ڲ:void +**************************************************/ +#define TIM1_Mode1SetReloadCounter(TIM1_SetCounter) \ + do{ \ + TL1 = (uint8_t)TIM1_SetCounter; \ + TH1 = (TIM1_SetCounter >> 8); \ + }while(0) + +/***************************************************** +*:void TIM1_Cmd(FunctionalState NewState) +*:TIMER1ܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +#define TIM1_Cmd(NewState) (TR1 = (bit)NewState) + +/***************************************************** +*:void TIM1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:TIMER1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +#define TIM1_ITConfig(NewState,Priority) \ + do{ \ + ET1 = (bit)NewState; \ + IPT1 = (bit)Priority; \ + }while(0) + +/***************************************************** +*:FlagStatus TIM1_GetFlagStatus(void) +*:TIMER1жϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:TIMER1жϱ־״̬ +*****************************************************/ +#define TIM1_GetFlagStatus() (TF1) + +/***************************************************** +*:void TIM1_ClearFlag(void) +*:TIMER1жϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +#define TIM1_ClearFlag() (TF1 = 0) + +void TIM1_DeInit(void); +void TIM1_TimeBaseInit(TIM1_PresSel_TypeDef + TIM1_PrescalerSelection, + TIM1_CountMode_TypeDef TIM1_CountMode); +void TIM1_WorkMode0Config(uint16_t TIM1_SetCounter); +void TIM1_WorkMode1Config(uint16_t TIM1_SetCounter); +void TIM1_WorkMode2Config(uint8_t TIM1_SetCounter); +void TIM1_WorkModeConfig(TIM1_WorkMode_TypeDef TIM1_WorkMode, + uint16_t TIM1_SetCounter); + + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer2.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer2.h new file mode 100644 index 0000000..883933b --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer2.h @@ -0,0 +1,98 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_timer2.h +// : ԪӦŶ +// ģ鹦: TIMER2̼⺯ͷļ +// : 2022323 +// 汾: V1.10003 +// ˵: ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_TIMER2_H_ +#define _sc92f_TIMER2_H_ + +#include "sc92f.h" + +typedef enum +{ + TIM2_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER2Դϵͳʱ12Ƶ + TIM2_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER2Դϵͳʱ +} TIM2_PresSel_TypeDef; + +#if defined (SC92F730x) || defined (SC92F827X) || defined (SC92F837X) || defined (SC92F725X) || defined (SC92F735X) + +typedef enum +{ + TIM2_MODE_TIMER = ((uint8_t)0x01), //TIMER2ʱ +} TIM2_CountMode_TypeDef; + +typedef enum +{ + TIM2_COUNTDIRECTION_UP = ((uint8_t)0x00), //ϼģʽ +} TIM2_CountDirection_TypeDef; + +typedef enum +{ + TIM2_FLAG_TF2 = (uint8_t)0x80, //жϱ־λTF2 +} TIM2_Flag_TypeDef; + +typedef enum +{ + TIM2_WORK_MODE1 = ((uint8_t)0x00), //TIMER2ѡģʽ1 +} TIM2_WorkMode_TypeDef; + +#else + +typedef enum +{ + TIM2_MODE_TIMER = ((uint8_t)0x01), //TIMER2ʱ + TIM2_MODE_COUNTER = ((uint8_t)0x02) //TIMER2 +} TIM2_CountMode_TypeDef; + +typedef enum +{ + TIM2_COUNTDIRECTION_UP = ((uint8_t)0x00), //ϼģʽ + TIM2_COUNTDIRECTION_DOWN_UP = ((uint8_t)0x10) ///¼ģʽ +} TIM2_CountDirection_TypeDef; + +typedef enum +{ + TIM2_FLAG_TF2 = (uint8_t)0x80, //жϱ־λTF2 + TIM2_FLAG_EXF2 = (uint8_t)0x40 //жϱ־λEXF2ⲿ +} TIM2_Flag_TypeDef; + +typedef enum +{ + TIM2_WORK_MODE0 = ((uint8_t)0x00), //TIMER2ѡģʽ0 + TIM2_WORK_MODE1 = ((uint8_t)0x01), //TIMER2ѡģʽ1 + TIM2_WORK_MODE3 = ((uint8_t)0x03), //TIMER2ѡģʽ3 +} TIM2_WorkMode_TypeDef; + +#endif + +/***************************************************** +*:void BTM_ClearFlag(void) +*:BTMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +#define BTM_ClearFlag() CLEAR_BIT(BTMCON,0x40) + +void TIM2_DeInit(); +void TIM2_PrescalerSelection(TIM2_PresSel_TypeDef TIM2_PrescalerSelection); +void TIM2_TimeBaseInit(TIM2_PresSel_TypeDef TIM2_PrescalerSelection, + TIM2_CountMode_TypeDef TIM2_CountMode, + TIM2_CountDirection_TypeDef TIM2_CountDirection); +void TIM2_WorkMode0Config(uint16_t TIM2_SetCounter); +void TIM2_WorkMode1Config(uint16_t TIM2_SetCounter); +void TIM2_WorkMode3Config(uint16_t TIM2_SetCounter); +void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef TIM2_WorkMode, uint16_t TIM2_SetCounter); +void TIM2_SetEXEN2(FunctionalState NewState); +void TIM2_Cmd(FunctionalState NewState); +void TIM2_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus TIM2_GetFlagStatus(TIM2_Flag_TypeDef TIM2_Flag); +void TIM2_ClearFlag(TIM2_Flag_TypeDef TIM2_Flag); + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer3.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer3.h new file mode 100644 index 0000000..9521c8c --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer3.h @@ -0,0 +1,63 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timer3.h +// : +// ģ鹦 : TIMER3̼⺯ͷļ +// : 2022/01/18 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_TIMER3_H_ +#define _sc92f_TIMER3_H_ + +#include "sc92f.H" + +typedef enum +{ + TIM3_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER3Դϵͳʱ12Ƶ + TIM3_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER3Դϵͳʱ +} TIM3_PresSel_TypeDef; + +typedef enum +{ + TIM3_MODE_TIMER = ((uint8_t)0x01), //TIMER3ʱ + TIM3_MODE_COUNTER = ((uint8_t)0x02) //TIMER3 +} TIM3_CountMode_TypeDef; + +typedef enum +{ + TIM3_COUNTDIRECTION_UP = ((uint8_t)0x00), //ϼģʽ + TIM3_COUNTDIRECTION_DOWN_UP = ((uint8_t)0x10) ///¼ģʽ +} TIM3_CountDirection_TypeDef; + +typedef enum +{ + TIM3_FLAG_TF3 = (uint8_t)0x80, //жϱ־λTF3 + TIM3_FLAG_EXF3 = (uint8_t)0x40 //жϱ־λEXF3 +} TIM3_Flag_TypeDef; + +typedef enum +{ + TIM3_WORK_MODE0 = ((uint8_t)0x00), //TIMER3ѡģʽ0 + TIM3_WORK_MODE1 = ((uint8_t)0x01), //TIMER3ѡģʽ1 + TIM3_WORK_MODE3 = ((uint8_t)0x03), //TIMER3ѡģʽ3 +} TIM3_WorkMode_TypeDef; + +void TIM3_DeInit(); +void TIM3_PrescalerSelection(TIM3_PresSel_TypeDef TIM3_PrescalerSelection); +void TIM3_WorkMode1Config(uint16_t TIM3_SetCounter); +void TIM3_Cmd(FunctionalState NewState); +void TIM3_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus TIM3_GetFlagStatus(TIM3_Flag_TypeDef TIM3_Flag); +void TIM3_ClearFlag(TIM3_Flag_TypeDef TIM3_Flag); + +void TIM3_TimeBaseInit(TIM3_CountMode_TypeDef TIM3_CountMode, + TIM3_CountDirection_TypeDef TIM3_CountDirection); +void TIM3_WorkMode0Config(uint16_t TIM3_SetCounter); +void TIM3_WorkMode3Config(uint16_t TIM3_SetCounter); +void TIM3_WorkModeConfig(TIM3_WorkMode_TypeDef TIM3_WorkMode, uint16_t TIM3_SetCounter); +void TIM3_SetEXEN3(FunctionalState NewState); + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer4.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer4.h new file mode 100644 index 0000000..b454786 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_timer4.h @@ -0,0 +1,62 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timerx.h +// : +// ģ鹦 : TIMER4̼⺯ͷļ +// : 2021/01/18 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_TIMER4_H_ +#define _sc92f_TIMER4_H_ + +#include "sc92f.H" + +typedef enum +{ + TIM4_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER4Դϵͳʱ12Ƶ + TIM4_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER4Դϵͳʱ +} TIM4_PresSel_TypeDef; + +typedef enum +{ + TIM4_MODE_TIMER = ((uint8_t)0x01), //TIMER2ʱ + TIM4_MODE_COUNTER = ((uint8_t)0x02) //TIMER2 +} TIM4_CountMode_TypeDef; + +typedef enum +{ + TIM4_COUNTDIRECTION_UP = ((uint8_t)0x00), //ϼģʽ + TIM4_COUNTDIRECTION_DOWN_UP = ((uint8_t)0x10) ///¼ģʽ +} TIM4_CountDirection_TypeDef; + +typedef enum +{ + TIM4_FLAG_TF4 = (uint8_t)0x80, //жϱ־λTF4 + TIM4_FLAG_EXF4 = (uint8_t)0x40 //жϱ־λEXF4 +} TIM4_Flag_TypeDef; + +typedef enum +{ + TIM4_WORK_MODE0 = ((uint8_t)0x00), //TIMER4ѡģʽ0 + TIM4_WORK_MODE1 = ((uint8_t)0x01), //TIMER4ѡģʽ1 + TIM4_WORK_MODE3 = ((uint8_t)0x03), //TIMER4ѡģʽ3 +} TIM4_WorkMode_TypeDef; + +void TIM4_DeInit(); +void TIM4_PrescalerSelection(TIM4_PresSel_TypeDef TIM4_PrescalerSelection); +void TIM4_WorkMode1Config(uint16_t TIM4_SetCounter); +void TIM4_Cmd(FunctionalState NewState); +void TIM4_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus TIM4_GetFlagStatus(TIM4_Flag_TypeDef TIM4_Flag); +void TIM4_ClearFlag(TIM4_Flag_TypeDef TIM4_Flag); + +void TIM4_TimeBaseInit(TIM4_CountMode_TypeDef TIM4_CountMode, + TIM4_CountDirection_TypeDef TIM4_CountDirection); +void TIM4_WorkMode0Config(uint16_t TIM4_SetCounter); +void TIM4_WorkMode3Config(uint16_t TIM4_SetCounter); +void TIM4_WorkModeConfig(TIM4_WorkMode_TypeDef TIM4_WorkMode, uint16_t TIM4_SetCounter); +void TIM4_SetEXEN4(FunctionalState NewState); + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_uart0.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_uart0.h new file mode 100644 index 0000000..a236e3e --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_uart0.h @@ -0,0 +1,127 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_uart0.h +// : +// ģ鹦 : UART0̼⺯ͷļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.10002 +// ˵ :ļԪ92F/93F/92LϵеƬ +//************************************************************* +#ifndef _sc92f_UART0_H_ +#define _sc92f_UART0_H_ + +#include "sc92f.h" +#if !defined (SC92F742x) && !defined (SC92F827X) && !defined (SC92F837X) + +#define UART0_BaudRate_FsysDIV12 0X00 //ģʽ0ãж˿ϵͳʱӵ1/12 +#define UART0_BaudRate_FsysDIV4 0X01 //ģʽ0ãж˿ϵͳʱӵ1/4 +#define UART0_BaudRate_FsysDIV64 0X00 //ģʽ1ãж˿ϵͳʱӵ1/64 +#define UART0_BaudRate_FsysDIV32 0X01 //ģʽ1ãж˿ϵͳʱӵ1/32 +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + UART0_PinSelection_P15P16 = (uint8_t)0x00, //UART0ΪP15P16 + UART0_PinSelection_P15 = (uint8_t)0x00, //UART0ΪP15P16RX + UART0_PinSelection_P11P20 = (uint8_t)0x10, //UART0ΪP11P20 + UART0_PinSelection_P20 = (uint8_t)0x10, //UART0ΪP20RX +} UART0_PinSelection_TypeDef; +#endif + +#if defined(SC92F725X) || defined(SC92F735X)|| defined (SC92F730x ) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + UART0_CLOCK_TIMER1 = (uint8_t)0X02, //TIMER1ʷ + UART0_CLOCK_TIMER1_FreqMcl2 = (uint8_t)0X82, //TIMER1ʷ,ҶƵ + UART0_CLOCK_TIMER1_DIV6 = (uint8_t)0X80, //TIMER1ʷ,6Ƶ + UART0_CLOCK_TIMER1_DIV12 = (uint8_t)0X00, //TIMER1ʷ,12Ƶ + UART0_CLOCK_TIMER2 = (uint8_t)0X34, //TIMER2ʷ + UART0_CLOCK_TIMER2_DIV12 = (uint8_t)0X30, //ʱ2 12Ƶģʽ13ͨ +}UART0_Clock_Typedef; +#elif defined (SC92F848x) || defined (SC92F748x) || defined(SC92F859x) || defined(SC92F759x) || defined(SC92L853x) || defined(SC92L753x) +typedef enum +{ + UART0_CLOCK_TIMER1 = (uint8_t)0X00, //TIMER1ʷ + UART0_CLOCK_TIMER2 = (uint8_t)0X30, //TIMER2ʷ + UART0_CLOCK_TIMER1_DIV16 = (uint8_t)0X80, //TIMER1ʷ + UART0_CLOCK_TIMER2_DIV16 = (uint8_t)0XB0, //TIMER2ʷ +}UART0_Clock_Typedef; +#else +typedef enum +{ + //ģʽ03Ķʱѡ + UART0_CLOCK_TIMER1 = (uint8_t)0X00, //TIMER1ʷ + UART0_CLOCK_TIMER2 = (uint8_t)0X30, //TIMER2ʷ +}UART0_Clock_Typedef; +#endif + +#if defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + UART0_Mode_8B = 0X00, //UARTģʽ:8λ˫ + UART0_Mode_10B = 0X40, //UARTģʽ:10λȫ˫ + UART0_Mode_11B = 0XC0, //UARTģʽ:11λȫ˫ + UART0_Mode_11B_BaudRateFix = 80//UARTģʽ:11λȫ˫,ʹ̶ +}UART0_Mode_Typedef; +#else +typedef enum +{ + UART0_Mode_8B = 0X00, //UARTģʽ:8λ˫ + UART0_Mode_10B = 0X40, //UARTģʽ:10λȫ˫ + UART0_Mode_11B = 0XC0, //UARTģʽ:11λȫ˫ +}UART0_Mode_Typedef; +#endif + +typedef enum +{ + UART0_RX_ENABLE = 0x10, // + UART0_RX_DISABLE = 0x00 // +} UART0_RX_Typedef; + +typedef enum +{ + UART0_FLAG_RI = 0X01, //жϱ־λRI + UART0_FLAG_TI = 0X02 //жϱ־λTI +} UART0_Flag_Typedef; + +/*******************************꺯*******************************/ +/***************************************************** +*:FlagStatus UART0_GetFlagStatus(UART0_Flag_Typedef UART0_Flag) +*:UART0жϱ־״̬ +*ڲ: +UART0_GetFlagStatus:UART0_Flag:жϱ־λѡ +*ڲ: +FlagStatus:UART0жϱ־λ״̬ +*****************************************************/ +#define UART0_GetFlagStatus(UART0_Flag) ((UART0_Flag == UART0_FLAG_TI) ? (TI):(RI)) + +/***************************************************** +*:void UART0_ClearFlag(UART0_Flag_Typedef UART0_Flag) +*:UART0жϱ־״̬ +*ڲ: +UART0_Flag_Typedef;UART0_Flag:жϱ־λѡ +*ڲ:void +*****************************************************/ +#define UART0_ClearFlag(UART0_Flag) CLEAR_BIT(SCON,UART0_Flag) + +void UART0_DeInit(void); +void UART0_Init(uint32_t Uart0Fsys, + uint32_t BaudRate, UART0_Mode_Typedef Mode, + UART0_Clock_Typedef ClockMode, + UART0_RX_Typedef RxMode); +void UART0_SendData8(uint8_t Data); +uint8_t UART0_ReceiveData8(void); +void UART0_SendData9(uint16_t Data); +uint16_t UART0_ReceiveData9(void); +void UART0_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#if defined (SC92F8003) || defined (SC92F740x) || defined (SC92F7003) +void UART0_PinSelection(UART0_PinSelection_TypeDef + PinSeletion); +#endif + +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_usci0.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_usci0.h new file mode 100644 index 0000000..32b97b4 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_usci0.h @@ -0,0 +1,171 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_usci0.h +// : +// ģ鹦 : USCI0̼⺯ͷļ +// : 2022/01/05 +// 汾 : V1.1000 +// ˵ : ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_USCI0_H_ +#define _sc92f_USCI0_H_ + +#include "sc92f.h" + +#define USCI0_UART_BaudRate_FsysDIV12 0X00 //ģʽ0ãж˿ϵͳʱӵ1/12 +#define USCI0_UART_BaudRate_FsysDIV4 0X01 //ģʽ0ãж˿ϵͳʱӵ1/4 + +#if defined(SC92L853x) || defined(SC92L753x) +typedef enum +{ + USCI0_Mode_SPI = (uint8_t)0x01, //SPI + USCI0_Mode_TWI = (uint8_t)0x02, //TWI + USCI0_Mode_UART = (uint8_t)0x03 //UART +} USCI0_CommunicationMode_TypeDef; +#endif + +typedef enum +{ + USCI0_SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + USCI0_SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} USCI0_SPI_FirstBit_TypeDef; + +typedef enum +{ + USCI0_SPI_BAUDRATEPRESCALER_1 = (uint8_t)0x00, //SPIʱΪϵͳʱӳ1 + USCI0_SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x01, //SPIʱΪϵͳʱӳ2 + USCI0_SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x02, //SPIʱΪϵͳʱӳ4 + USCI0_SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x03, //SPIʱΪϵͳʱӳ8 + USCI0_SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x04, //SPIʱΪϵͳʱӳ16 + USCI0_SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x05, //SPIʱΪϵͳʱӳ32 + USCI0_SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x06, //SPIʱΪϵͳʱӳ64 + USCI0_SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x07 //SPIʱΪϵͳʱӳ128 +} USCI0_SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + USCI0_SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + USCI0_SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} USCI0_SPI_Mode_TypeDef; + +typedef enum +{ + USCI0_SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + USCI0_SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} USCI0_SPI_ClockPolarity_TypeDef; + +typedef enum +{ + USCI0_SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + USCI0_SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} USCI0_SPI_ClockPhase_TypeDef; + +typedef enum +{ + USCI0_SPI_TXE_DISINT = (uint8_t)0x00, //TBIEΪ0ʱж + USCI0_SPI_TXE_ENINT = (uint8_t)0x01 //TBIEΪ1ʱж +} USCI0_SPI_TXE_INT_TypeDef; + +typedef enum +{ + USCI0_SPI_DATA8 = (uint8_t)0x00, //SPI 8λģʽ + USCI0_SPI_DATA16 = (uint8_t)0x02 //SPI 16λģʽ +} USCI0_TransmissionMode_TypeDef; + +typedef enum +{ + USCI0_TWI_1024 = (uint8_t)0x00, //TWIͨ Fhrc/1024 + USCI0_TWI_512 = (uint8_t)0x01, //TWIͨ Fhrc/512 + USCI0_TWI_256 = (uint8_t)0x02, //TWIͨ Fhrc/256 + USCI0_TWI_128 = (uint8_t)0x03, //TWIͨ Fhrc/128 + USCI0_TWI_64 = (uint8_t)0x04, //TWIͨ Fhrc/64 + USCI0_TWI_32 = (uint8_t)0x05, //TWIͨ Fhrc/32 + USCI0_TWI_16 = (uint8_t)0x06, //TWIͨ Fhrc/16 +} USCI0_TWI_MasterCommunicationRate_TypeDef; + +typedef enum +{ + USCI0_TWI_SlaveBusy = 0x00, //Ϊӻ + USCI0_TWI_SlaveReceivedaAddress = 0x01, + USCI0_TWI_SlaveReceivedaData = 0x02, + USCI0_TWI_SlaveSendData = 0x03, + USCI0_TWI_SlaveReceivedaUACK = 0x04, + USCI0_TWI_SlaveDisableACK = 0x05, + USCI0_TWI_SlaveAddressError = 0x06, + USCI0_TWI_MasterBusy = 0x00, //Ϊ + USCI0_TWI_MasterSendAddress = 0x01, + USCI0_TWI_MasterSendData = 0x02, + USCI0_TWI_MasterReceivedaData = 0x03, + USCI0_TWI_MasterReceivedaUACK = 0x04, +} USCI0_TWIState_TypeDef; + +typedef enum +{ + USCI0_UART_Mode_8B = 0X00, //UARTΪ8λģʽ + USCI0_UART_Mode_10B = 0X40, //UARTΪ10λģʽ + USCI0_UART_Mode_11B = 0X80 //UARTΪ11λģʽ +} USCI0_UART_Mode_TypeDef; + +typedef enum +{ + USCI0_UART_RX_ENABLE = 0X10, //UART + USCI0_UART_RX_DISABLE = 0X00 //UARTֹ +} USCI0_UART_RX_TypeDef; + +typedef enum +{ + USCI0_SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + USCI0_SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + USCI0_SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + USCI0_TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + USCI0_TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + USCI0_TWI_FLAG_MSTR = (uint8_t)0x20, //TWIӱ־λMSTR + USCI0_TWI_FLAG_TXRXnE = (uint8_t)0x80, + USCI0_UART_FLAG_RI = (uint8_t)0x01, //UARTжϱ־λRI + USCI0_UART_FLAG_TI = (uint8_t)0x02, //UARTжϱ־λTI +} USCI0_Flag_TypeDef; + +typedef enum +{ + USCI0_TWI_Write = 0x00, //д + USCI0_TWI_Read = 0x01, // +} USCI0_TWI_RWType; + +void USCI0_DeInit(void); +void USCI0_SPI_Init(USCI0_SPI_FirstBit_TypeDef FirstBit, + USCI0_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI0_SPI_Mode_TypeDef Mode, + USCI0_SPI_ClockPolarity_TypeDef ClockPolarity, USCI0_SPI_ClockPhase_TypeDef ClockPhase, + USCI0_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI0_TransmissionMode_TypeDef TransmissionMode); +void USCI0_TransmissionMode(USCI0_TransmissionMode_TypeDef TransmissionMode); +void USCI0_SPI_Cmd(FunctionalState NewState); +void USCI0_SPI_SendData_8(uint8_t Data); +uint8_t USCI0_SPI_ReceiveData_8(void); +void USCI0_SPI_SendData_16(uint16_t Data); +uint16_t USCI0_SPI_ReceiveData_16(void); +void USCI0_TWI_Slave_Init(uint8_t TWI_Address); +void USCI0_TWI_MasterCommunicationRate(USCI0_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate); +void USCI0_TWI_Start(void); +void USCI0_TWI_MasterModeStop(void); +void USCI0_TWI_SendAddr(uint8_t Addr, USCI0_TWI_RWType RW); +void USCI0_TWI_SlaveClockExtension(FunctionalState NewState); +void USCI0_TWI_AcknowledgeConfig(FunctionalState NewState); +void USCI0_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus USCI0_GetTWIStatus(USCI0_TWIState_TypeDef USCI0_TWIState); +void USCI0_TWI_Cmd(FunctionalState NewState); +void USCI0_TWI_SendData(uint8_t Data); +uint8_t USCI0_TWI_ReceiveData(void); +void USCI0_UART_Init(uint32_t UART1Fsys, uint32_t BaudRate, USCI0_UART_Mode_TypeDef Mode, + USCI0_UART_RX_TypeDef RxMode); +void USCI0_UART_SendData8(uint8_t Data); +uint8_t USCI0_UART_ReceiveData8(void); +void USCI0_UART_SendData9(uint16_t Data); +uint16_t USCI0_UART_ReceiveData9(void); +void USCI0_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus USCI0_GetFlagStatus(USCI0_Flag_TypeDef USCI0_FLAG); +void USCI0_ClearFlag(USCI0_Flag_TypeDef USCI0_FLAG); + +#endif + +/******************* (C) COPYRIGHT 2019 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_usci1.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_usci1.h new file mode 100644 index 0000000..df5ff09 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_usci1.h @@ -0,0 +1,168 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_usci1.h +// : +// ģ鹦 : USCI1̼⺯ͷļ +// : 2022/01/05 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_USCI1_H_ +#define _sc92f_USCI1_H_ + +#include "sc92f.h" + +#define USCI1_UART_BaudRate_FsysDIV12 0X00 //ģʽ0ãж˿ϵͳʱӵ1/12 +#define USCI1_UART_BaudRate_FsysDIV4 0X01 //ģʽ0ãж˿ϵͳʱӵ1/4 + +typedef enum +{ + USCI1_Mode_SPI = (uint8_t)0x01, //SPI + USCI1_Mode_TWI = (uint8_t)0x02, //TWI + USCI1_Mode_UART = (uint8_t)0x03 //UART +} USCI1_CommunicationMode_TypeDef; + +typedef enum +{ + USCI1_SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + USCI1_SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} USCI1_SPI_FirstBit_TypeDef; + +typedef enum +{ + USCI1_SPI_BAUDRATEPRESCALER_1 = (uint8_t)0x00, //SPIʱΪϵͳʱӳ1 + USCI1_SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x01, //SPIʱΪϵͳʱӳ2 + USCI1_SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x02, //SPIʱΪϵͳʱӳ4 + USCI1_SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x03, //SPIʱΪϵͳʱӳ8 + USCI1_SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x04, //SPIʱΪϵͳʱӳ16 + USCI1_SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x05, //SPIʱΪϵͳʱӳ32 + USCI1_SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x06, //SPIʱΪϵͳʱӳ64 + USCI1_SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x07 //SPIʱΪϵͳʱӳ128 +} USCI1_SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + USCI1_SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + USCI1_SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} USCI1_SPI_Mode_TypeDef; + +typedef enum +{ + USCI1_SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + USCI1_SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} USCI1_SPI_ClockPolarity_TypeDef; + +typedef enum +{ + USCI1_SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + USCI1_SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} USCI1_SPI_ClockPhase_TypeDef; + +typedef enum +{ + USCI1_SPI_TXE_DISINT = (uint8_t)0x00, //TBIEΪ0ʱж + USCI1_SPI_TXE_ENINT = (uint8_t)0x01 //TBIEΪ1ʱж +} USCI1_SPI_TXE_INT_TypeDef; + +typedef enum +{ + USCI1_SPI_DATA8 = (uint8_t)0x00, //SPI 8λģʽ + USCI1_SPI_DATA16 = (uint8_t)0x02 //SPI 16λģʽ +} USCI1_TransmissionMode_TypeDef; + +typedef enum +{ + USCI1_TWI_1024 = (uint8_t)0x00, //TWIͨ Fhrc/1024 + USCI1_TWI_512 = (uint8_t)0x01, //TWIͨ Fhrc/512 + USCI1_TWI_256 = (uint8_t)0x02, //TWIͨ Fhrc/256 + USCI1_TWI_128 = (uint8_t)0x03, //TWIͨ Fhrc/128 + USCI1_TWI_64 = (uint8_t)0x04, //TWIͨ Fhrc/64 + USCI1_TWI_32 = (uint8_t)0x05, //TWIͨ Fhrc/32 + USCI1_TWI_16 = (uint8_t)0x06, //TWIͨ Fhrc/16 +} USCI1_TWI_MasterCommunicationRate_TypeDef; + +typedef enum +{ + USCI1_TWI_SlaveBusy = 0x00, + USCI1_TWI_SlaveReceivedaAddress = 0x01, + USCI1_TWI_SlaveReceivedaData = 0x02, + USCI1_TWI_SlaveSendData = 0x03, + USCI1_TWI_SlaveReceivedaUACK = 0x04, + USCI1_TWI_SlaveDisableACK = 0x05, + USCI1_TWI_SlaveAddressError = 0x06, + USCI1_TWI_MasterBusy = 0x00, + USCI1_TWI_MasterSendAddress = 0x01, + USCI1_TWI_MasterSendData = 0x02, + USCI1_TWI_MasterReceivedaData = 0x03, + USCI1_TWI_MasterReceivedaUACK = 0x04, +} USCI1_TWIState_TypeDef; + +typedef enum +{ + USCI1_UART_Mode_8B = 0X00, //UARTΪ8λģʽ + USCI1_UART_Mode_10B = 0X40, //UARTΪ10λģʽ + USCI1_UART_Mode_11B = 0X80 //UARTΪ11λģʽ +} USCI1_UART_Mode_TypeDef; + +typedef enum +{ + USCI1_UART_RX_ENABLE = 0X10, //UART + USCI1_UART_RX_DISABLE = 0X00 //UARTֹ +} USCI1_UART_RX_TypeDef; + +typedef enum +{ + USCI1_SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + USCI1_SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + USCI1_SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + USCI1_TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + USCI1_TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + USCI1_TWI_FLAG_MSTR = (uint8_t)0x20, //TWIӱ־λMSTR + USCI1_TWI_FLAG_TXRXnE = (uint8_t)0x80, + USCI1_UART_FLAG_RI = (uint8_t)0x01, //UARTжϱ־λRI + USCI1_UART_FLAG_TI = (uint8_t)0x02, //UARTжϱ־λTI +} USCI1_Flag_TypeDef; + +typedef enum +{ + USCI1_TWI_Write = 0x00, //д + USCI1_TWI_Read = 0x01, // +} USCI1_TWI_RWType; + +void USCI1_DeInit(void); +void USCI1_SPI_Init(USCI1_SPI_FirstBit_TypeDef FirstBit, + USCI1_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI1_SPI_Mode_TypeDef Mode, + USCI1_SPI_ClockPolarity_TypeDef ClockPolarity, USCI1_SPI_ClockPhase_TypeDef ClockPhase, + USCI1_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI1_TransmissionMode_TypeDef TransmissionMode); +void USCI1_TransmissionMode(USCI1_TransmissionMode_TypeDef TransmissionMode); +void USCI1_SPI_Cmd(FunctionalState NewState); +void USCI1_SPI_SendData_8(uint8_t Data); +uint8_t USCI1_SPI_ReceiveData_8(void); +void USCI1_SPI_SendData_16(uint16_t Data); +uint16_t USCI1_SPI_ReceiveData_16(void); +void USCI1_TWI_Slave_Init(uint8_t TWI_Address); +void USCI1_TWI_MasterCommunicationRate(USCI1_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate); +void USCI1_TWI_Start(void); +void USCI1_TWI_MasterModeStop(void); +void USCI1_TWI_SlaveClockExtension(FunctionalState NewState); +void USCI1_TWI_AcknowledgeConfig(FunctionalState NewState); +void USCI1_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus USCI1_GetTWIStatus(USCI1_TWIState_TypeDef USCI1_TWIState); +void USCI1_TWI_Cmd(FunctionalState NewState); +void USCI1_TWI_SendData(uint8_t Data); +uint8_t USCI1_TWI_ReceiveData(void); +void USCI1_UART_Init(uint32_t UART1Fsys, uint32_t BaudRate, USCI1_UART_Mode_TypeDef Mode, + USCI1_UART_RX_TypeDef RxMode); +void USCI1_UART_SendData8(uint8_t Data); +uint8_t USCI1_UART_ReceiveData8(void); +void USCI1_UART_SendData9(uint16_t Data); +uint16_t USCI1_UART_ReceiveData9(void); +void USCI1_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus USCI1_GetFlagStatus(USCI1_Flag_TypeDef USCI1_FLAG); +void USCI1_ClearFlag(USCI1_Flag_TypeDef USCI1_FLAG); +void USCI1_TWI_SendAddr(uint8_t Addr, USCI1_TWI_RWType RW); +#endif + +/******************* (C) COPYRIGHT 2019 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_usci2.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_usci2.h new file mode 100644 index 0000000..9b82bf0 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_usci2.h @@ -0,0 +1,168 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_usci2.h +// : +// ģ鹦 : USCI2̼⺯ͷļ +// : 2022/01/05 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_USCI2_H_ +#define _sc92f_USCI2_H_ + +#include "sc92f.h" + +#define USCI2_UART_BaudRate_FsysDIV12 0X00 //ģʽ0ãж˿ϵͳʱӵ1/12 +#define USCI2_UART_BaudRate_FsysDIV4 0X01 //ģʽ0ãж˿ϵͳʱӵ1/4 + +typedef enum +{ + USCI2_Mode_SPI = (uint8_t)0x01, //SPI + USCI2_Mode_TWI = (uint8_t)0x02, //TWI + USCI2_Mode_UART = (uint8_t)0x03 //UART +} USCI2_CommunicationMode_TypeDef; + +typedef enum +{ + USCI2_SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + USCI2_SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} USCI2_SPI_FirstBit_TypeDef; + +typedef enum +{ + USCI2_SPI_BAUDRATEPRESCALER_1 = (uint8_t)0x00, //SPIʱΪϵͳʱӳ1 + USCI2_SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x01, //SPIʱΪϵͳʱӳ2 + USCI2_SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x02, //SPIʱΪϵͳʱӳ4 + USCI2_SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x03, //SPIʱΪϵͳʱӳ8 + USCI2_SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x04, //SPIʱΪϵͳʱӳ16 + USCI2_SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x05, //SPIʱΪϵͳʱӳ32 + USCI2_SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x06, //SPIʱΪϵͳʱӳ64 + USCI2_SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x07 //SPIʱΪϵͳʱӳ128 +} USCI2_SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + USCI2_SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + USCI2_SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} USCI2_SPI_Mode_TypeDef; + +typedef enum +{ + USCI2_SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + USCI2_SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} USCI2_SPI_ClockPolarity_TypeDef; + +typedef enum +{ + USCI2_SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + USCI2_SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} USCI2_SPI_ClockPhase_TypeDef; + +typedef enum +{ + USCI2_SPI_TXE_DISINT = (uint8_t)0x00, //TBIEΪ0ʱж + USCI2_SPI_TXE_ENINT = (uint8_t)0x01 //TBIEΪ1ʱж +} USCI2_SPI_TXE_INT_TypeDef; + +typedef enum +{ + USCI2_SPI_DATA8 = (uint8_t)0x00, //SPI 8λģʽ + USCI2_SPI_DATA16 = (uint8_t)0x01 //SPI 16λģʽ +} USCI2_TransmissionMode_TypeDef; + +typedef enum +{ + USCI2_TWI_1024 = (uint8_t)0x00, //TWIͨ Fhrc/1024 + USCI2_TWI_512 = (uint8_t)0x01, //TWIͨ Fhrc/512 + USCI2_TWI_256 = (uint8_t)0x02, //TWIͨ Fhrc/256 + USCI2_TWI_128 = (uint8_t)0x03, //TWIͨ Fhrc/128 + USCI2_TWI_64 = (uint8_t)0x04, //TWIͨ Fhrc/64 + USCI2_TWI_32 = (uint8_t)0x05, //TWIͨ Fhrc/32 + USCI2_TWI_16 = (uint8_t)0x06, //TWIͨ Fhrc/16 +} USCI2_TWI_MasterCommunicationRate_TypeDef; + +typedef enum +{ + USCI2_TWI_SlaveBusy = 0x00, + USCI2_TWI_SlaveReceivedaAddress = 0x01, + USCI2_TWI_SlaveReceivedaData = 0x02, + USCI2_TWI_SlaveSendData = 0x03, + USCI2_TWI_SlaveReceivedaUACK = 0x04, + USCI2_TWI_SlaveDisableACK = 0x05, + USCI2_TWI_SlaveAddressError = 0x06, + USCI2_TWI_MasterBusy = 0x00, + USCI2_TWI_MasterSendAddress = 0x01, + USCI2_TWI_MasterSendData = 0x02, + USCI2_TWI_MasterReceivedaData = 0x03, + USCI2_TWI_MasterReceivedaUACK = 0x04, +} USCI2_TWIState_TypeDef; + +typedef enum +{ + USCI2_UART_Mode_8B = 0X00, //UARTΪ8λģʽ + USCI2_UART_Mode_10B = 0X40, //UARTΪ10λģʽ + USCI2_UART_Mode_11B = 0X80 //UARTΪ11λģʽ +} USCI2_UART_Mode_TypeDef; + +typedef enum +{ + USCI2_UART_RX_ENABLE = 0X10, //UART + USCI2_UART_RX_DISABLE = 0X00 //UARTֹ +} USCI2_UART_RX_TypeDef; + +typedef enum +{ + USCI2_SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + USCI2_SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + USCI2_SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + USCI2_TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + USCI2_TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + USCI2_TWI_FLAG_MSTR = (uint8_t)0x20, //TWIӱ־λMSTR + USCI2_TWI_FLAG_TXRXnE = (uint8_t)0x80, + USCI2_UART_FLAG_RI = (uint8_t)0x01, //UARTжϱ־λRI + USCI2_UART_FLAG_TI = (uint8_t)0x02, //UARTжϱ־λTI +} USCI2_Flag_TypeDef; + +typedef enum +{ + USCI2_TWI_Write = 0x00, //д + USCI2_TWI_Read = 0x01, // +} USCI2_TWI_RWType; + +void USCI2_DeInit(void); +void USCI2_SPI_Init(USCI2_SPI_FirstBit_TypeDef FirstBit, + USCI2_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI2_SPI_Mode_TypeDef Mode, + USCI2_SPI_ClockPolarity_TypeDef ClockPolarity, USCI2_SPI_ClockPhase_TypeDef ClockPhase, + USCI2_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI2_TransmissionMode_TypeDef TransmissionMode); +void USCI2_TransmissionMode(USCI2_TransmissionMode_TypeDef TransmissionMode); +void USCI2_SPI_Cmd(FunctionalState NewState); +void USCI2_SPI_SendData_8(uint8_t Data); +uint8_t USCI2_SPI_ReceiveData_8(void); +void USCI2_SPI_SendData_16(uint16_t Data); +uint16_t USCI2_SPI_ReceiveData_16(void); +void USCI2_TWI_Slave_Init(uint8_t TWI_Address); +void USCI2_TWI_MasterCommunicationRate(USCI2_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate); +void USCI2_TWI_Start(void); +void USCI2_TWI_MasterModeStop(void); +void USCI2_TWI_SlaveClockExtension(FunctionalState NewState); +void USCI2_TWI_AcknowledgeConfig(FunctionalState NewState); +void USCI2_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus USCI2_GetTWIStatus(USCI2_TWIState_TypeDef USCI2_TWIState); +void USCI2_TWI_Cmd(FunctionalState NewState); +void USCI2_TWI_SendData(uint8_t Data); +uint8_t USCI2_TWI_ReceiveData(void); +void USCI2_UART_Init(uint32_t UART1Fsys, uint32_t BaudRate, USCI2_UART_Mode_TypeDef Mode, + USCI2_UART_RX_TypeDef RxMode); +void USCI2_UART_SendData8(uint8_t Data); +uint8_t USCI2_UART_ReceiveData8(void); +void USCI2_UART_SendData9(uint16_t Data); +uint16_t USCI2_UART_ReceiveData9(void); +void USCI2_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus USCI2_GetFlagStatus(USCI2_Flag_TypeDef USCI2_FLAG); +void USCI2_ClearFlag(USCI2_Flag_TypeDef USCI2_FLAG); +void USCI2_TWI_SendAddr(uint8_t Addr, USCI2_TWI_RWType RW); +#endif + +/******************* (C) COPYRIGHT 2019 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_wdt.h b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_wdt.h new file mode 100644 index 0000000..e0bdf38 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/inc/sc92f_wdt.h @@ -0,0 +1,43 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_wdt.h +// : +// ģ鹦: WDT̼⺯ͷļ +// : 2022323 +// 汾: V1.10002 +// ˵: +//************************************************************* + +#ifndef _sc92f_WDT_H_ +#define _sc92f_WDT_H_ + +#include "sc92f.h" + +typedef enum +{ + WDT_OverflowTime_500MS = (uint8_t)0x00, //ŹʱΪ500MS + WDT_OverflowTime_250MS = (uint8_t)0x01, //ŹʱΪ250MS + WDT_OverflowTime_125MS = (uint8_t)0x02, //ŹʱΪ125MS + WDT_OverflowTime_62_5MS = (uint8_t)0x03, //ŹʱΪ62.5MS + WDT_OverflowTime_31_5MS = (uint8_t)0x04, //ŹʱΪ31.5MS + WDT_OverflowTime_15_75MS = (uint8_t)0x05, //ŹʱΪ15.75MS + WDT_OverflowTime_7_88MS = (uint8_t)0x06, //ŹʱΪ7.88MS + WDT_OverflowTime_3_94MS = (uint8_t)0x07 //ŹʱΪ3.94MS +} WDT_OverflowTime_TypeDef; + +/************************꺯************************/ +/***************************************************** +*:void WDT_SetReload(void) +*:WDTι +*ڲ:void +*ڲ:void +*****************************************************/ +#define WDT_SetReload() SET_BIT(WDTCON,0x10) + +void WDT_DeInit(void); +void WDT_Init(WDT_OverflowTime_TypeDef + OverflowTime); +void WDT_Cmd(FunctionalState NewState); +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_acmp.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_acmp.c new file mode 100644 index 0000000..039b3b4 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_acmp.c @@ -0,0 +1,129 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_acmp.c +// : +// ģ鹦 : ACMP̼⺯Cļ +// ֲб: +// : 2020/8/18 +// 汾 : V1.00000 +// ˵ : +//************************************************************* + +#include "sc92f_acmp.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) +/************************************************** +*:void ACMP_DeInit(void) +*:MDUؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void ACMP_DeInit(void) +{ + CMPCON = 0X00; + CMPCFG = 0X00; +} + +/************************************************** +*:void ACMP_Init(ACMP_Vref_Typedef ACMP_Vref, ACMP_Channel_TypeDef ACMP_Channel) +*:ģȽʼú +*ڲ: +ACMP_Vref_Typedef:ACMP_Vref:ACMPοѹѡ +ACMP_Channel_TypeDef:ACMP_Channel:ACMPͨѡ +*ڲ:void +**************************************************/ +void ACMP_Init(ACMP_Vref_Typedef ACMP_Vref, + ACMP_Channel_TypeDef ACMP_Channel) +{ + CMPCON = CMPCON & 0XF0 | ACMP_Vref; + CMPCFG = CMPCFG & 0XEC | ACMP_Channel; +} + +/************************************************** +*:void ACMP_SetTriggerMode(ACMP_TriggerMode_Typedef ACMP_TriggerMode) +*:ACMPжϴʽú +*ڲ: +ACMP_TriggerMode_Typedef:ACMP_TriggerMode:жϴʽѡ +*ڲ:void +**************************************************/ +void ACMP_SetTriggerMode(ACMP_TriggerMode_Typedef + ACMP_TriggerMode) +{ + CMPCFG = CMPCFG & 0XF3 | ACMP_TriggerMode; +} + +/***************************************************** +*:void ACMP_Cmd(FunctionalState NewState) +*:ACMPܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void ACMP_Cmd(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + CMPCON &= 0X7F; + } + else + { + CMPCON |= 0x80; + } +} + +/***************************************************** +*:void ACMP_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:ACMPжϳʼ +*ڲ:FunctionalState:NewState:жʹ/رѡ + PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void ACMP_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState == DISABLE) + { + IE1 &= 0XBF; + } + else + { + IE1 |= 0X20; + } + + /************************************************************/ + if(Priority == LOW) + { + IP1 &= 0XBF; + } + else + { + IP1 |= 0X20; + } +} + +/***************************************************** +*:FlagStatus ACMP_GetFlagStatus(ACMP_Flag_TypeDef ACMP_Flag) +*:ACMP־״̬ +*ڲ:ACMP_Flag ־λѡ +*ڲ: +ACMP_Flag_TypeDef:FlagStatus:ACMP־״̬ +*****************************************************/ +FlagStatus ACMP_GetFlagStatus(ACMP_Flag_TypeDef + ACMP_Flag) +{ + return (bool)(CMPCON & ACMP_Flag); +} + +/***************************************************** +*:void ACMP_ClearFlag(void) +*:־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void ACMP_ClearFlag(void) +{ + CMPCON &= (~ACMP_FLAG_CMPIF); +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_adc.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_adc.c new file mode 100644 index 0000000..3669941 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_adc.c @@ -0,0 +1,462 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_adc.c +// : ԪӦŶ +// ģ鹦: ADC̼⺯Cļ +// : 2022323 +// 汾: V1.10005 +// ˵: +//************************************************************* + +/* ͷļ */ +#include "sc92f_adc.h" + +#if !defined(SC92F827X) && !defined(SC92F837X) +/************************************************** +*:void ADC_DeInit(void) +*:ADCؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void ADC_DeInit(void) +{ + ADCCON = 0x00; + ADCCFG0 = 0X00; + ADCCFG1 = 0X00; +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F84Ax) || defined(SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F848x) || defined(SC92F748x) || defined (SC92F859x) || defined (SC92F759x)\ + || defined (SC92L853x) || defined (SC92L753x) + ADCCFG2 = 0X00; +#endif + ADCVL = 0X00; + ADCVH = 0X00; + EADC = 0; + IPADC = 0; +} + +/************************************************** +*:void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, ADC_Cycle_TypeDef ADC_Cycle) +*:ADCʼú +*ڲ: +ADC_PresSel_TypeDef:ADC_PrescalerSelection:ԤƵѡ +ADC_Cycle_TypeDef:ADC_Cycle:ʱѡ +*ڲ:void +**************************************************/ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F84Ax) || defined(SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92FWxx) || defined(SC92F848x) || defined(SC92F748x)\ + || defined (SC92F859x) || defined (SC92F759x) +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, + ADC_Cycle_TypeDef ADC_Cycle) +{ + /* ADCʱӷƵͲ */ + ADCCFG2 = ADC_PrescalerSelection | ADC_Cycle; +} +#elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, + ADC_Cycle_TypeDef ADC_Cycle) +{ + /* ADCʱӷƵͲ */ + ADCCFG1 = ADC_PrescalerSelection | ADC_Cycle; +} +#elif defined(SC92F742x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F730x) || defined(SC92F732X) || defined(SC92F7490)\ + || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, + ADC_Cycle_TypeDef ADC_Cycle) +{ + ADC_Cycle = 0; //SC92F742x޴˹ + /* ADCʱӷƵ */ + ADCCON = (ADCCON & 0xDF) | ADC_PrescalerSelection; +} +#elif defined (SC92L853x) || defined (SC92L753x) +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, ADC_Cycle_TypeDef ADC_Cycle) +{ + ADC_Cycle = 0x00; //92LϵЧ + /* ADCʱӷƵ */ + ADCCFG2 = ADC_PrescalerSelection; +} +#endif + +/************************************************** +*:void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +*:ADCúʹع +*ڲ: +ADC_Channel_TypeDef:ADC_Channel:ADCѡ +FunctionalState:NewState:ADCxʹ/رѡ +*ڲ:void +**************************************************/ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F84Ax) || defined(SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92FWxx) || defined(SC92F848x) || defined(SC92F748x)\ + || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +{ + uint16_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0XE0) | ADC_Channel; + + /* ADCⲿͨ */ + if (ADC_Channel < ADC_CHANNEL_VDD_D4) //ڲͨ + { + TempReg = (0x0001 << ADC_Channel); + if (NewState == DISABLE)// ʹADCͨ + { + ADCCFG0 &= (~(uint8_t)TempReg); + ADCCFG1 &= (~(uint8_t)(TempReg >> 8)); + } + else // ʧADCͨ + { + ADCCFG0 |= ((uint8_t)TempReg); + ADCCFG1 |= ((uint8_t)(TempReg >> 8)); + } + } +} +#elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) || defined(SC92F7490) +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +{ + uint8_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0xE0) | ADC_Channel; + + /* ADCͨ */ + if (ADC_Channel < ADC_CHANNEL_VDD_D4) //ڲͨ + { + TempReg = (0x01 << ADC_Channel); + if (ADC_Channel < ADC_CHANNEL_VDD_D4) + { + if (NewState == DISABLE) //ʧADCͨ + { + ADCCFG0 &= (~TempReg); + } + else //ʹADCͨ + { + ADCCFG0 |= TempReg; + } + } + } +} +#elif defined(SC92F742x) || defined(SC92F730x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F732X) +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +{ + uint16_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0xF0) | ADC_Channel; + + /* ADCͨ */ + if (ADC_Channel < ADC_CHANNEL_VDD_D4) //ڲͨ + { + TempReg = (0x0001 << ADC_Channel); + if (NewState == DISABLE) + { + ADCCFG0 &= (~(uint8_t)TempReg); + ADCCFG1 &= (~(uint8_t)(TempReg >> 8)); + } + else + { + ADCCFG0 |= ((uint8_t)TempReg); + ADCCFG1 |= ((uint8_t)(TempReg >> 8)); + } + } +} +#elif defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +{ + uint16_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0xF0) | ADC_Channel; + + /* ADCͨ */ + if (ADC_Channel < ADC_CHANNEL_Temp) //ⲿͨ + { + TempReg = (0x0001 << ADC_Channel); + if (NewState == DISABLE) + { + ADCCFG0 &= (~(uint8_t)TempReg); + ADCCFG1 &= (~(uint8_t)(TempReg >> 8)); + } + else + { + ADCCFG0 |= ((uint8_t)TempReg); + ADCCFG1 |= ((uint8_t)(TempReg >> 8)); + } + } + else if (ADC_Channel == ADC_CHANNEL_Temp) //ڲ¶Ȳͨ + { + if (NewState == DISABLE) + { + TSCFG &= 0X7F; + } + else + { + /* ADCοѹѡڲ2.4VΪο */ + OPINX = 0xC2; + OPREG = OPREG & 0X7F | 0x80; + + TSCFG |= 0x80; + } + } + else if (ADC_Channel == ADC_CHANNEL_9_PGA) //ɱŴͨ + { + unsigned char code *IFBAddr = 0x3D; + if (NewState == DISABLE) + { + ADCCFG1 &= (~(uint8_t)0x02); //رͨ9 + PGACON &= 0x7F; //ʹPGA + } + /* ȡPGAڲУ׼ֵ */ + else + { + ADCCFG1 |= ((uint8_t)0x02); //PGAͨͨ9ãʹͨ9 + + IAPADE = 0x01; //ָָ IFB + PGACFG = *(IFBAddr); //ȡУ׼ֵ + IAPADE = 0x00; //ָָ ROM + + PGACON |= 0x80; //ʹPGA + } + } +} +#endif + +/************************************************** +*:void ADC_EAINConfig(uint16_t ADC_Channel, FunctionalState NewState) +*:ӦADCΪģģʽ +*ڲ: +ADC_EAIN_TypeDef:ADC_EAIN_Select:ѡҪõADC +FunctionalState:NewState:ADCͨʹ/رѡ +*ڲ:void +**************************************************/ +void ADC_EAINConfig(uint16_t ADC_EAIN_Select, + FunctionalState NewState) +{ + if (NewState == DISABLE) + { + ADCCFG0 &= (~(uint8_t)ADC_EAIN_Select); +#if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)||defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined (SC92F759x)\ + || defined (SC92L853x) || defined (SC92L753x) + ADCCFG1 &= (~(uint8_t)(ADC_EAIN_Select >> 8)); +#endif + } + else + { + ADCCFG0 |= ((uint8_t)ADC_EAIN_Select); +#if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined (SC92F759x)\ + || defined (SC92L853x) || defined (SC92L753x) + ADCCFG1 |= ((uint8_t)(ADC_EAIN_Select >> 8)); +#endif + } +} +/***************************************************** +*:void ADC_Cmd(FunctionalState NewState) +*:ADCܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void ADC_Cmd(FunctionalState NewState) +{ + if (NewState == DISABLE) + { + ADCCON &= 0X7F; + } + else + { + ADCCON |= 0x80; + } +} + +/***************************************************** +*:uint16_t ADC_GetConversionValue(void) +*:һADת +*ڲ:void +*ڲ:uint16_t +*****************************************************/ +unsigned int ADC_GetConversionValue(void) +{ + return ((ADCVH << 4) + (ADCVL >> 4)); +} + +/***************************************************** +*:FlagStatus ADC_GetFlagStatus(void) +*:ADCжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:ADCжϱ־״̬ +*****************************************************/ +FlagStatus ADC_GetFlagStatus(void) +{ +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)||defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined (SC92F83Ax) || defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) || defined (SC92FWxx)\ + || defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + return (bool)(ADCCON & 0x20); +#elif defined(SC92F742x) || defined(SC92F730x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F732X) || defined(SC92F7490) || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) + return (bool)(ADCCON & 0x10); +#endif +} + +/***************************************************** +*:void ADC_ClearFlag(void) +*:ADCжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void ADC_ClearFlag(void) +{ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F84Ax) || defined(SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F8003) || defined(SC92F740x) || defined(SC92F848x) || defined(SC92F748x)\ + || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + ADCCON &= 0xdf; +#endif +#if defined(SC92F742x) || defined(SC92F730x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F732X) || defined(SC92F7490) || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) + ADCCON &= 0xef; +#endif +} + +#if defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +unsigned int ADC_TS_StandardData = 0x8000; + +/***************************************************** +*:void ADC_TSCmd(PriorityStatus NewState) +*:ADC ¶ȴܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void ADC_TSCmd(FunctionalState NewState) +{ + if (NewState == DISABLE) + { + TSCFG &= 0X7F; + } + else + { + TSCFG |= 0X80; + } +} + +/***************************************************** +*:void ADC_CHOPConfig(PriorityStatus NewState) +*:߻͵offsetӦÿλ +*ڲ: +PriorityStatus:NewState:¶ȴ/ѡ +*ڲ:void +*****************************************************/ +void ADC_CHOPConfig(PriorityStatus NewState) +{ + if (NewState == LOW) + { + TSCFG &= 0XFE; + } + else + { + TSCFG |= 0x01; + } +} + +/***************************************************** +*:void ADC_CHOPConfig(PriorityStatus NewState) +*:ȡʱADC 25ʱתֵ +*ڲ:void +*ڲ:void +*****************************************************/ +uint16_t ADC_Get_TS_StandardData(void) +{ + unsigned int code *IFBAddr = 0x3E; + IAPADE = 0x01; //ָָ IFB + ADC_TS_StandardData = *(IFBAddr); + IAPADE = 0x00; //ָָ ROM + return ADC_TS_StandardData; +} + +/***************************************************** +*:void ADC_GetTSValue(void) +*:ֱӻȡfloat¶ֵȡ¶ʱرж +*ڲ:void +*ڲ: +float:¶ֵ +*****************************************************/ +float ADC_GetTSValue(void) +{ + unsigned char EADC_Flag = EADC; //ȡEA־λ״̬ + unsigned int ADC_Value1 = 0, ADC_Value2 = 0, ADC_Value = 0; + unsigned int code *IFBAddr = 0x3E; + + ADC_Get_TS_StandardData(); + disableInterrupts(); //رж + ADC_CHOPConfig(LOW); //͵offsetӦÿλ + ADC_StartConversion(); //ʼADת + while(!ADC_GetFlagStatus()); //ȴת + ADC_ClearFlag(); //ת־λ + ADC_Value1 = ADC_GetConversionValue(); //ȡһADתֵ + ADC_CHOPConfig(HIGH); //ߵoffsetӦÿλ + ADC_StartConversion(); //ʼADת + while(!ADC_GetFlagStatus()); //ȴת + ADC_ClearFlag(); //ת־λ + ADC_Value2 = ADC_GetConversionValue(); //ȡڶADתֵ + ADC_Value = (ADC_Value1 + ADC_Value2) / 2; //ȡADƽֵ + + if (EADC_Flag) //ԭǰEA־λ + { + enableInterrupts(); + } + return (25 + ((float)ADC_Value - (float)ADC_TS_StandardData) / 8); +} + +/***************************************************** +*:ADC_PGAConfig(ADC_PGACOM_TypeDef ADC_PGACOM,ADC_PGAGAN_TypeDef ADC_PGAGAN,ADC_PGAIPT_TypeDef ADC_PGAIPT) +*:PGA +*ڲ: +ADC_PGACOM_TypeDef:ADC_PGACOM:PGAģѹѡ +ADC_PGAGAN_TypeDef:ADC_PGAGAN:PGAŴ +ADC_PGAIPT_TypeDef:ADC_PGAIPT:PGAͬ/ѡ +*ڲ:void +*****************************************************/ +void ADC_PGAConfig(ADC_PGACOM_TypeDef ADC_PGACOM, ADC_PGAGAN_TypeDef ADC_PGAGAN, ADC_PGAIPT_TypeDef ADC_PGAIPT) +{ + PGACON &= 0x8F; + PGACON |= (ADC_PGACOM | ADC_PGAGAN | ADC_PGAIPT); +} + +/***************************************************** +*:void ADC_PGACmd(PriorityStatus NewState) +*:ADC PGAܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void ADC_PGACmd(PriorityStatus NewState) +{ + if (NewState == LOW) + { + PGACON &= 0XFE; + } + else + { + PGACON |= 0x01; + } +} +#endif + + +/***************************************************** +*:void ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) +*:ADC οѹѡ +*ڲ: +ADC_Vref_TypeDef:ADC_Vref:ѡADCοѹ +*ڲ:void +*****************************************************/ +void ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) +{ + OPINX = 0xC2; + OPREG = OPREG & 0X7F | ADC_Vref; +} +#endif + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_btm.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_btm.c new file mode 100644 index 0000000..e14a5ad --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_btm.c @@ -0,0 +1,78 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_btm.c +// : ԪӦŶ +// ģ鹦: BTM̼⺯Cļ +// ֲб: +// : 202242 +// 汾: V1.10002 +// ˵: +//************************************************************* + +#include "sc92f_btm.h" + + +/************************************************** +*:void BTM_Init(BTM_Timebase_TypeDef BTM_Timebase) +*:BTMʼú +*ڲ: +BTM_Timebase_TypeDef:BTM_Timebase:BTMʱѡ +*ڲ:void +**************************************************/ +void BTM_Init(BTM_Timebase_TypeDef BTM_Timebase) +{ + BTMCON = (BTMCON & 0xF0) | BTM_Timebase; //ʱ +} + +/***************************************************** +*:void BTM_Cmd(FunctionalState NewState) +*:BTMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void BTM_Cmd(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + BTMCON &= 0x7f; //ʧBTM + } + else + { + BTMCON |= 0x80; //ʹBTM + } +} + +/***************************************************** +*:void BTM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:BTMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void BTM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + //жʹ + if(NewState == DISABLE) + { + IE1 &= 0xfb; + } + else + { + IE1 |= 0x04; + } + + //жȼ + if(Priority == LOW) + { + IP1 &= 0xfb; + } + else + { + IP1 |= 0x04; + } +} + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_chksum.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_chksum.c new file mode 100644 index 0000000..24412e7 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_chksum.c @@ -0,0 +1,59 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_chksum.c +// : +// ģ鹦 : CHKSUM̼⺯Cļ +// : 2021/08/20 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#include "sc92f_chksum.h" + +#if defined(SC92F7003) || defined(SC92F8003) || defined(SC92F736xB) || defined(SC92F836xB) || defined(SC92F740x) || defined(SC92F742x)\ + || defined(SC92F73Ax) || defined(SC92F83Ax) || defined(SC92F744xB) || defined(SC92F844xB) || defined(SC92F746xB) || defined(SC92F846xB)\ + || defined(SC92F748x) || defined(SC92F848x) || defined(SC92F74Ax) || defined(SC92F84Ax) || defined(SC92F74Ax_2) || defined(SC92F84Ax_2)\ + || defined(SC92F754x) || defined (SC92F854x) || defined (SC92F759x) || defined(SC92F859x) || defined (SC92F7490) || defined(SC92FWxx)\ + || defined(SC92F827X) || defined(SC92F847X) +/************************************************** +*:void CHKSUM_DeInit(void) +*:CHKSUMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void CHKSUM_DeInit(void) +{ + OPERCON &= 0XFE; + CHKSUML = 0X00; + CHKSUMH = 0X00; +} + +/************************************************** +*:void CHKSUM_StartOperation(void) +*:һcheck sum +*ڲ:void +*ڲ:void +**************************************************/ +void CHKSUM_StartOperation(void) +{ + OPERCON |= 0X01; + + while(OPERCON & 0x01); +} + +/************************************************** +*:uint16_t CHKSUM_GetCheckValue(void) +*:ȡһcheck sumֵ +*ڲ:void +*ڲ: +uint16_t:check sumֵ +**************************************************/ +uint16_t CHKSUM_GetCheckValue(void) +{ + uint16_t checktemp; + checktemp = (uint16_t)(CHKSUMH << 8) + + (uint16_t)CHKSUML; + return checktemp; +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_crc.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_crc.c new file mode 100644 index 0000000..73fac1d --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_crc.c @@ -0,0 +1,97 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_CRC.c +// : +// ģ鹦 : CRC̼⺯Cļ +// : 2020/8/13 +// 汾 : V1.0000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_CRC.h" +#include "intrins.H" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:unsigned long CRC_All() +*:󱾹HEXCRC32УֵüOPTIONIAR Rangeͬ仯 +*ڲ:void +*ڲ: +uint32_t:CRC +**************************************************/ +uint32_t CRC_All() +{ + uint32_t CRC_Result; + OPERCON |= 0x01; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + CRCINX = 0x00; + CRC_Result = CRCREG; + CRC_Result = CRCREG * 256 + CRC_Result; + CRC_Result = CRCREG * 65536 + CRC_Result; + CRC_Result = CRCREG * 16777216 + CRC_Result; + return CRC_Result; +} + +/************************************************** +*:uint32_t CRC_Frame(uint8_t* buff,uint8_t Length) +*:֡CRCУֵ +*ڲ: +uint8_t*:buff:ҪCRC +uint8_t:Length:Ҫ鳤 +*ڲ: +uint32_t:CRC +**************************************************/ +uint32_t CRC_Frame(uint8_t *buff, uint8_t Length) +{ + uint8_t i; + uint32_t CRC_Result = 0; + + EA = 0; + OPERCON |= 0x02; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + + for (i = 0; i < Length; i++) + { + CRC_Result = *(buff + i); + CRCREG = CRC_Result; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + } + + CRCINX = 0x00; + CRC_Result = CRCREG; + CRC_Result = CRCREG * 256 + CRC_Result; + CRC_Result = CRCREG * 65536 + CRC_Result; + CRC_Result = CRCREG * 16777216 + CRC_Result; + EA = 1; + + return CRC_Result; +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ddic.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ddic.c new file mode 100644 index 0000000..eaf69f8 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ddic.c @@ -0,0 +1,228 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ddic.c +// : +// ģ鹦 : DDIC̼⺯Cļ +// ֲб: +// : 2022/01/20 +// 汾 : V1.10002 +// ˵ : +//************************************************************* + +#include "sc92f_ddic.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + +#if defined (SC92L853x) || defined (SC92L753x) +uint8_t xdata LCDRAM[30] _at_ 0xF00; +#else +uint8_t xdata LCDRAM[30] _at_ 0x700; +#endif + +/************************************************** +*:void DDIC_DeInit(void) +*:DDICؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void DDIC_DeInit(void) +{ + DDRCON = 0X00; + P0VO = 0X00; + P1VO = 0X00; + P2VO = 0X00; +#if defined (SC92L853x) || defined (SC92L753x) + P5VO = 0X00; +#else + P3VO = 0X00; +#endif + OTCON &= 0XF0; +} + +/************************************************** +*:void DDIC_Init(uint8_t P0OutputPin) +*:DDICʼú +*ڲ: +DDIC_DutyCycle_TypeDef:DDIC_DutyCylce:LCD/LEDʾռձȿ +DDIC_Pin_TypeDef:P0OutputPin:P0ΪLCDѹ,ʹûöٵĶԱ +DDIC_Pin_TypeDef:P1OutputPin:P1ΪLCDѹ,ʹûöٵĶԱ +DDIC_Pin_TypeDef:P2OutputPin:P2ΪLCDѹ,ʹûöٵĶԱ +DDIC_Pin_TypeDef:P3OutputPin:P3ΪLCDѹ,ʹûöٵĶԱ + ע:ͺΪSC92L853xSC92L753xʱʵΪP5 +*ڲ:void +**************************************************/ +void DDIC_Init(DDIC_DutyCycle_TypeDef DDIC_DutyCylce, + uint8_t P0OutputPin, uint8_t P1OutputPin, + uint8_t P2OutputPin, uint8_t P3OutputPin) +{ + DDRCON = DDRCON & 0XCF | DDIC_DutyCylce; + P0VO = P0OutputPin; + P1VO = P1OutputPin; + P2VO = P2OutputPin; +#if defined (SC92L853x) || defined (SC92L753x) + P5VO = P3OutputPin; +#else + P3VO = P3OutputPin; +#endif +} + +/************************************************** +*:void DDIC_LEDConfig(void) +*:LEDú +*ڲ:void +*ڲ:void +**************************************************/ +void DDIC_LEDConfig(void) +{ + DDRCON |= 0X40; +} + +/************************************************** +*:void DDIC_LCDConfig(uint8_t LCDVoltage, + DDIC_ResSel_Typedef DDIC_ResSel, + DDIC_BiasVoltage_Typedef DDIC_BiasVoltage) +*:LCDú +*ڲ: +uint8_t:LCDVoltage:LCDѹ +DDIC_ResSel_Typedef:DDIC_ResSel:LCDѹڵѡ +DDIC_BiasVoltage_Typedef:DDIC_BiasVoltage:LCDʾƫõѹ +*ڲ:void +**************************************************/ +void DDIC_LCDConfig(uint8_t LCDVoltage, + DDIC_ResSel_Typedef DDIC_ResSel, + DDIC_BiasVoltage_Typedef DDIC_BiasVoltage) +{ + DDRCON = DDRCON & 0XB0 | LCDVoltage; + OTCON = OTCON & 0XF2 | DDIC_ResSel | DDIC_BiasVoltage; +} +/************************************************** +*:void DDIC_DMOD_Selcet(DDIC_DMOD_TypeDef DDIC_DMOD) +*:ʾģʽѡ +*ڲ: +DDIC_DMOD_TypeDef:DDIC_DMOD:ѡʾģʽ +*ڲ:void +**************************************************/ +void DDIC_DMOD_Selcet(DDIC_DMOD_TypeDef DDIC_DMOD) +{ + if(DDIC_DMOD == DMOD_LED) + { + DDRCON |= 0X40; + } + else + { + DDRCON &= 0XBF; + } +} +/***************************************************** +*:void DDIC_OutputPinOfDutycycleD4(DDIC_OutputPin_TypeDef DDIC_OutputPin) +*:1/4ռձʱsegmentcommonùܽѡ +*ڲ: +DDIC_OutputPin_TypeDef:DDIC_OutputPin:ܽѡ +*ڲ:void +*****************************************************/ +void DDIC_OutputPinOfDutycycleD4( + DDIC_OutputPin_TypeDef DDIC_OutputPin) +{ + OTCON &= ~0X02; + OTCON = DDIC_OutputPin<<1; +} + +/***************************************************** +*:void DDIC_Cmd(FunctionalState NewState) +*:ʾܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void DDIC_Cmd(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + DDRCON &= 0X7F; + } + else + { + DDRCON |= 0x80; + } +} + +/***************************************************** +*:void DDIC_Control(DDIC_Control_SEG_TypeDef DDIC_Seg,DDIC_Control_COM_TypeDef DDIC_Com,DDIC_Control_Status DDIC_Contr) +*:SEGCOMŶӦLCD/LED +*ڲ:DDIC_Control_SEG_TypeDef DDIC_Seg ѡƵSEG + DDIC_Control_COM_TypeDef DDIC_Com ѡƵCOM + DDIC_Control_Status DDIC_Contr ״̬ +*ڲ:void +*****************************************************/ +void DDIC_Control(DDIC_Control_SEG_TypeDef DDIC_Seg, + uint8_t DDIC_Com, + DDIC_Control_Status DDIC_Contr) +{ + if(DDIC_Contr) + { + LCDRAM[DDIC_Seg] |= DDIC_Com; + } + else + { + LCDRAM[DDIC_Seg] &= (~DDIC_Com); + } +} +#endif + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X)\ + || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92F848x) || defined (SC92F748x) +/************************************************** +*:void DDIC_DeInit(void) +*:DDICؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void DDIC_DeInit(void) +{ + P0VO = 0X00; + OTCON &= 0XF3; +} + +/************************************************** +*:void DDIC_Init(uint8_t P0OutputPin) +*:DDICʼú +*ڲ: +DDIC_Pin_TypeDef:P0OutputPin:P0ΪLCDѹڣʹûöٵĶԱ +*ڲ:void +**************************************************/ +void DDIC_Init(uint8_t P0OutputPin) +{ + P0VO = P0OutputPin; +} + +/************************************************** +*:void DDIC_LCDConfig(DDIC_ResSel_Typedef DDIC_ResSel) +*:LCDú +*ڲ: +DDIC_ResSel_Typedef:DDIC_ResSel:LCDѹڵѡ +*ڲ:void +**************************************************/ +void DDIC_LCDConfig(DDIC_ResSel_Typedef DDIC_ResSel) +{ + OTCON = (OTCON & 0XF3) | DDIC_ResSel; +} + +/************************************************** +*:void DDIC_Config_Init(uint8_t P0OutputPin,DDIC_ResSel_Typedef DDIC_ResSel) +*:LCDʼú +*ڲ: +DDIC_Pin_TypeDef:P0OutputPin:P0ΪLCDѹڣʹûöٵĶԱ +DDIC_ResSel_Typedef:DDIC_ResSel:LCDѹڵѡ +*ڲ:void +**************************************************/ +void DDIC_Config_Init(uint8_t P0OutputPin, + DDIC_ResSel_Typedef DDIC_ResSel) +{ + P0VO = P0OutputPin; + OTCON = (OTCON & 0XF3) | DDIC_ResSel; +} + +#endif +/******************* (C) COPYRIGHT 2019 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_gpio.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_gpio.c new file mode 100644 index 0000000..d18e543 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_gpio.c @@ -0,0 +1,539 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_gpio.c +// : +// ģ鹦 : GPIO̼⺯Cļ +// ֲб : +// : 2022/01/11 +// 汾 : V1.10004 +// ˵ : ļԪ92F/93F/92LϵеƬ +//************************************************************* + + +#include "sc92f_gpio.h" + +/************************************************** +*:void GPIO_DeInit(void) +*:GPIOؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void GPIO_DeInit(void) +{ + P0CON = 0x00; + P0PH = 0x00; + P0 = 0; + P1CON = 0x00; + P1PH = 0x00; + P1 = 0; + P2CON = 0x00; + P2PH = 0x00; + P2 = 0; +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + P3CON = 0x00; + P3PH = 0x00; + P3 = 0; + P4CON = 0x00; + P4PH = 0x00; + P4 = 0; +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F7003) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) + P5CON = 0x00; + P5PH = 0x00; + P5 = 0; +#endif +} + +/************************************************** +*:void GPIO_Init(GPIO_TypeDef GPIOx, uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode) +*:GPIOģʽóʼ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOܽPxy +GPIO_Mode_TypeDef:GPIO_Mode:ѡGPIOģʽ롢롢 +*ڲ:void +**************************************************/ +void GPIO_Init(GPIO_TypeDef GPIOx, + uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode) +{ + if (GPIOx == GPIO0) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P0CON &= ~PortPins; + P0PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P0CON &= ~PortPins; + P0PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P0CON |= PortPins; + } + } + else if (GPIOx == GPIO1) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P1CON &= ~PortPins; + P1PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P1CON &= ~PortPins; + P1PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P1CON |= PortPins; + } + } + else if (GPIOx == GPIO2) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P2CON &= ~PortPins; + P2PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P2CON &= ~PortPins; + P2PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P2CON |= PortPins; + } + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + else if (GPIOx == GPIO3) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P3CON &= ~PortPins; + P3PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P3CON &= ~PortPins; + P3PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P3CON |= PortPins; + } + } + else if (GPIOx == GPIO4) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P4CON &= ~PortPins; + P4PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P4CON &= ~PortPins; + P4PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P4CON |= PortPins; + } + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F7003) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) + else if (GPIOx == GPIO5) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P5CON &= ~PortPins; + P5PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P5CON &= ~PortPins; + P5PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P5CON |= PortPins; + } + } + +#endif +} + +/************************************************** +*:void GPIO_Write(GPIO_TypeDef GPIOx, uint8_t PortVal) +*:GPIOڸֵ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +uint8_t:PortVal:GPIOڵֵ +*ڲ:void +**************************************************/ +void GPIO_Write(GPIO_TypeDef GPIOx, + uint8_t PortVal) +{ + if (GPIOx == GPIO0) + { + P0 = PortVal; + } + + if (GPIOx == GPIO1) + { + P1 = PortVal; + } + + if (GPIOx == GPIO2) + { + P2 = PortVal; + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + + if (GPIOx == GPIO3) + { + P3 = PortVal; + } + + if (GPIOx == GPIO4) + { + P4 = PortVal; + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + + if (GPIOx == GPIO5) + { + P5 = PortVal; + } + +#endif +} + +/************************************************** +*:void GPIO_WriteHigh(GPIO_TypeDef GPIOx, uint8_t PortPins) +*:GPIOڹܽPxyλ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy +*ڲ:void +**************************************************/ +void GPIO_WriteHigh(GPIO_TypeDef GPIOx, + uint8_t PortPins) +{ + if (GPIOx == GPIO0) + { + P0 |= PortPins; + } + + if (GPIOx == GPIO1) + { + P1 |= PortPins; + } + + if (GPIOx == GPIO2) + { + P2 |= PortPins; + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + + if (GPIOx == GPIO3) + { + P3 |= PortPins; + } + + if (GPIOx == GPIO4) + { + P4 |= PortPins; + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + + if (GPIOx == GPIO5) + { + P5 |= PortPins; + } + +#endif +} + +/************************************************** +*:void GPIO_WriteLow(GPIO_TypeDef GPIOx, uint8_t PortPins) +*:GPIOڹܽPxyλ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy +*ڲ:void +**************************************************/ +void GPIO_WriteLow(GPIO_TypeDef GPIOx, + uint8_t PortPins) +{ + if (GPIOx == GPIO0) + { + P0 &= ~PortPins; + } + + if (GPIOx == GPIO1) + { + P1 &= ~PortPins; + } + + if (GPIOx == GPIO2) + { + P2 &= ~PortPins; + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + + if (GPIOx == GPIO3) + { + P3 &= ~PortPins; + } + + if (GPIOx == GPIO4) + { + P4 &= ~PortPins; + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + + if (GPIOx == GPIO5) + { + P5 &= ~PortPins; + } + +#endif +} + +/************************************************** +*:uint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx) +*:GPIOPxֵ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +*ڲ:uint8_t Pxֵ +**************************************************/ +uint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx) +{ + if (GPIOx == GPIO0) + { + return P0; + } + else if (GPIOx == GPIO1) + { + return P1; + } + else if (GPIOx == GPIO2) + { + return P2; + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + else if (GPIOx == GPIO3) + { + return P3; + } + else if (GPIOx == GPIO4) + { + return P4; + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + else if (GPIOx == GPIO5) + { + return P5; + } + +#endif + else + { + return 0; + } +} + +/************************************************** +*:BitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, uint8_t PortPins) +*:GPIOڹܽPxyֵ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy +*ڲ:BitStatus Pxyֵ +**************************************************/ +BitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, + uint8_t PortPins) +{ + if (GPIOx == GPIO0) + { + return ((bit)(P0 & PortPins)); + } + else if (GPIOx == GPIO1) + { + return ((bit)(P1 & PortPins)); + } + else if (GPIOx == GPIO2) + { + return ((bit)(P2 & PortPins)); + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + else if (GPIOx == GPIO3) + { + return ((bit)(P3 & PortPins)); + } + else if (GPIOx == GPIO4) + { + return ((bit)(P4 & PortPins)); + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + else if (GPIOx == GPIO5) + { + return ((bit)(P5 & PortPins)); + } + +#endif + return 0; +} + + +/************************************************** +*:void GPIO_IOH_Config(GPIO_TypeDef GPIOx, uint8_t PortPins,GPIO_IOH_Grade_TypeDef GPIO_IOH_Grade) +*:GPIOڹܽIOH +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy +GPIO_IOH_Grade_TypeDef:GPIO_IOH_Grade:IOȼ +*ڲ:BitStatus Pxyֵ +**************************************************/ +#if !defined(SC92F7003) && !defined(SC92F8003) && !defined(SC92F740x) +void GPIO_IOH_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef PortPins, GPIO_IOH_Grade_TypeDef GPIO_IOH_Grade) +{ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + switch (GPIOx) + { + case GPIO0: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON0 &= 0xFC; + IOHCON0 |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON0 &= 0xF3; + IOHCON0 |= GPIO_IOH_Grade << 2; + } + break; + case GPIO1: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON0 &= 0xCF; + IOHCON0 |= GPIO_IOH_Grade << 4; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON0 &= 0x3F; + IOHCON0 |= GPIO_IOH_Grade << 6; + } + break; + case GPIO2: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON1 &= 0xFC; + IOHCON1 |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON1 &= 0xF3; + IOHCON1 |= GPIO_IOH_Grade << 2; + } + break; +#if defined (SC92L853x) || defined (SC92L753x) + case GPIO5: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON1 &= 0xCF; + IOHCON1 |= GPIO_IOH_Grade << 4; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON1 &= 0x3f; + IOHCON1 |= GPIO_IOH_Grade << 6; + } + break; +#else + case GPIO3: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON1 &= 0xCF; + IOHCON1 |= GPIO_IOH_Grade << 4; + } + break; +#endif + default: + break; + } +#else + switch (GPIOx) + { + case GPIO0: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON &= 0xFC; + IOHCON |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON &= 0xF3; + IOHCON |= GPIO_IOH_Grade << 2; + } + break; + case GPIO2: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON &= 0xFC; + IOHCON |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON &= 0xF3; + IOHCON |= GPIO_IOH_Grade << 2; + } + break; + default: + break; + } +#endif +} +#endif + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_iap.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_iap.c new file mode 100644 index 0000000..71d92fa --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_iap.c @@ -0,0 +1,172 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_iap.c +// : +// ģ鹦 : IAP̼⺯Cļ +// : 2022/01/24 +// 汾 : V1.10002 +// ˵ :ļԪ92F/93F/92LϵеƬ +//************************************************************* + +#include "sc92f_iap.h" + +/************************************************** +*:void IAP_DeInit(void) +*:IAPؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void IAP_DeInit(void) +{ + IAPKEY = 0X00; + IAPADL = 0X00; + IAPADH = 0X00; + IAPADE = 0X00; + IAPDAT = 0X00; + IAPCTL = 0X00; +} + +/************************************************** +*:void IAP_SetHoldTime(IAP_HoldTime_TypeDef IAP_HoldTime) +*:IAPCPU Hold Timeú +*ڲ: +IAP_HoldTime_TypeDef:IAP_HoldTimed:Hold TimeTimeѡ +*ڲ:void +**************************************************/ +void IAP_SetHoldTime(IAP_HoldTime_TypeDef + IAP_HoldTime) +{ + IAPCTL = IAPCTL & 0XF3 | IAP_HoldTime; +} + +/************************************************** +*:void IAP_ProgramByte(uint16_t Address, uint8_t Data, IAP_MemType_TypeDef IAP_MemType, uint8_t WriteTimeLimit) +*:IAPдһֽ +*ڲ: +uint16_t:Address:IAPַ +uint8_t:Data:д +IAP_MemType_TypeDef:IAP_MemType:IAPROMEEPROM +עIAP_MEMTYPE_UIDдUIDдЧ +uint8_t:WriteTimeLimit:IAPʱ (ֵ) +*ڲ:void +**************************************************/ +void IAP_ProgramByte(uint16_t Address, + uint8_t Data, IAP_MemType_TypeDef IAP_MemType, + uint8_t WriteTimeLimit) +{ + BitStatus tmpbit; + + /* UIDд */ + if(IAP_MemType == IAP_MEMTYPE_UID) + return; + + tmpbit = (BitStatus)EA; + if(tmpbit != RESET) + { + disableInterrupts(); + } + + IAPADE = IAP_MemType; + IAPDAT = Data; + IAPADH = (uint8_t)(Address >> 8); + IAPADL = (uint8_t)Address; + IAPKEY = WriteTimeLimit; +#if defined (SC92F848x) || defined (SC92F748x) || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + IAPCTL |= 0x10; +#endif + IAPCTL |= 0x02; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + IAPADE = IAP_MEMTYPE_ROM; + + if(tmpbit != RESET) + { + enableInterrupts(); + } +} + +/************************************************** +*:uint8_t IAP_ReadByte(uint16_t Address, IAP_MemType_TypeDef IAP_MemType) +*:IAPһֽ +*ڲ: +uint16_t:Address:IAPַ +IAP_MemType_TypeDef:FLASH_MemType:IAPROMUIDEEPROM +*ڲ:uint8_t ֽ +**************************************************/ +uint8_t IAP_ReadByte(uint16_t Address, + IAP_MemType_TypeDef IAP_MemType) +{ + uint8_t tmpbyte; + BitStatus tmpbit; + tmpbit = (BitStatus)EA; + + if(tmpbit != RESET) + { + disableInterrupts(); + } + + IAPADE = IAP_MemType; + tmpbyte = *((uint8_t code*)Address); + IAPADE = IAP_MEMTYPE_ROM; + + if(tmpbit != RESET) + { + enableInterrupts(); + } + + return tmpbyte; +} + +#if defined (SC92F848x) || defined (SC92F748x) || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void IAP_SectorErase(IAP_MemType_TypeDef IAP_MemType, uint16_t IAP_SectorEraseAddress) +*:IAP +*ڲ: +IAP_MemType_TypeDef:IAP_MemType:IAPROM +uint32_t:IAP_SectorEraseAddress:IAPĿַ +uint8_t:WriteTimeLimit:IAPʱ(ֵڵ0x40) +*ڲ:void +**************************************************/ +void IAP_SectorErase(IAP_MemType_TypeDef IAP_MemType, uint32_t IAP_SectorEraseAddress, + uint8_t WriteTimeLimit) +{ + /* UID */ + if((IAP_MemType == IAP_MEMTYPE_UID) || (IAP_MemType == IAP_MEMTYPE_EEPROM)) + return; + + IAPADE = IAP_MemType; + IAPADH = (uint8_t)(IAP_SectorEraseAddress >> 8); //IAPĿַλֵ + IAPADL = (uint8_t)IAP_SectorEraseAddress; //IAPĿַλֵ + IAPKEY = WriteTimeLimit; + IAPCTL = 0x20; + IAPCTL |= 0x02; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + IAPADE = IAP_MEMTYPE_ROM; +} + +/************************************************** +*:void IAP_BootLoaderControl(IAP_BTLDType_TypeDef IAP_BTLDType) +*:MCUλǸ +*ڲ: +IAP_BTLDType_TypeDef:IAP_BTLDType:ѡ +*ڲ:void +**************************************************/ +void IAP_BootLoaderControl(IAP_BTLDType_TypeDef IAP_BTLDType) +{ + IAPCTL = (IAPCTL & ~IAP_BTLDType_LDROM) | IAP_BTLDType; +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_int.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_int.c new file mode 100644 index 0000000..e0e08ae --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_int.c @@ -0,0 +1,284 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_int.c +// : +// ģ鹦 : INT̼⺯Cļ +// ֲб: +// : 2022/01/05 +// 汾 : V1.10003 +// ˵ : +//************************************************************* + +#include "sc92f_int.h" + +/************************************************** +*:void INT_DeInit(INTx_Typedef INTx) +*:INTxؼĴλȱʡֵ +*ڲ: +INTx_Typedef:INTx:INTxѡ +*ڲ:void +**************************************************/ +#if !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F730x) && !defined (SC92F725X) && !defined (SC92F735X) && !defined (SC92F7490) +void INT_DeInit(INTx_Typedef INTx) +{ + switch(INTx) + { + case INT0: + INT0R = 0x00; + INT0F = 0x00; + IE &= (~0X01); + IP &= ~0X01; + TCON &= (~0X02); + break; + + case INT1: + INT1R = 0x00; + INT1F = 0x00; + IE &= (~0X04); + IP &= ~0X04; + TCON &= (~0X08); + break; + + case INT2: + INT2R = 0x00; + INT2F = 0x00; + IE1 &= (~0X08); + IP1 &= ~0X08; + break; + + default: + break; + } +} +#else +void INT_DeInit(INTx_Typedef INTx) +{ + switch(INTx) + { + case INT0: + INT0R = 0x00; + INT0F = 0x00; + IE &= (~0X01); + IP &= ~0X01; + TCON &= (~0X02); + break; + + case INT2: + INT2R = 0x00; + INT2F = 0x00; + IE1 &= (~0X08); + IP1 &= ~0X08; + break; + + default: + break; + } +} +#endif + +/************************************************** +*:void INT0_SetTriggerMode(uint8_t INT0x, INT_TriggerMode_Typedef TriggerMode) +*:INT0xжϴʽú +*ڲ: +INT0x_Typedef:INT0x:INT0xѡ +INT_TriggerMode_Typedef:TriggerMode:жϴʽѡ +*ڲ:void +**************************************************/ +void INT0_SetTriggerMode(uint8_t INT0x, + INT_TriggerMode_Typedef TriggerMode) +{ + switch(TriggerMode) + { + case INT_TRIGGER_RISE_ONLY: + INT0R |= INT0x; + INT0F &= (~INT0x); + break; + + case INT_TRIGGER_FALL_ONLY: + INT0R &= (~INT0x); + INT0F |= INT0x; + break; + + case INT_TRIGGER_RISE_FALL: + INT0R |= INT0x; + INT0F |= INT0x; + break; + + case INT_TRIGGER_DISABLE: + INT0R &= (~INT0x); + INT0F &= (~INT0x); + + default: + break; + } +} + + +/************************************************** +*:void INT1_SetTriggerMode(uint8_t INT1x, INT_TriggerMode_Typedef TriggerMode) +*:INT1xжϴʽú +*ڲ: +INT1x_Typedef:INT1x:INT1xѡ +INT_TriggerMode_Typedef:TriggerMode:жϴʽѡ +*ڲ:void +**************************************************/ +#if !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F730x) && !defined (SC92F725X) && !defined (SC92F735X) && !defined (SC92F7490) +void INT1_SetTriggerMode(uint8_t INT1x, + INT_TriggerMode_Typedef TriggerMode) +{ + switch(TriggerMode) + { + case INT_TRIGGER_RISE_ONLY: + INT1R |= INT1x; + INT1F &= (~INT1x); + break; + + case INT_TRIGGER_FALL_ONLY: + INT1R &= (~INT1x); + INT1F |= INT1x; + break; + + case INT_TRIGGER_RISE_FALL: + INT1R |= INT1x; + INT1F |= INT1x; + break; + + case INT_TRIGGER_DISABLE: + INT1R &= (~INT1x); + INT1F &= (~INT1x); + + default: + break; + } +} +#endif + +/************************************************** +*:void INT2_SetTriggerMode(uint8_t INT2x, INT_TriggerMode_Typedef TriggerMode) +*:INT2xжϴʽú +*ڲ: +INT2x_Typedef:INT2x:INT2xѡ +INT_TriggerMode_Typedef:TriggerMode:жϴʽѡ +*ڲ:void +**************************************************/ +void INT2_SetTriggerMode(uint8_t INT2x, + INT_TriggerMode_Typedef TriggerMode) +{ + switch(TriggerMode) + { + case INT_TRIGGER_RISE_ONLY: + INT2R |= INT2x; + INT2F &= (~INT2x); + break; + + case INT_TRIGGER_FALL_ONLY: + INT2R &= (~INT2x); + INT2F |= INT2x; + break; + + case INT_TRIGGER_RISE_FALL: + INT2R |= INT2x; + INT2F |= INT2x; + break; + + case INT_TRIGGER_DISABLE: + INT2R &= (~INT2x); + INT2F &= (~INT2x); + + default: + break; + } +} + +/***************************************************** +*:void INT0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:INT0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void INT0_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState != DISABLE) + { + IE |= 0X01; + } + else + { + IE &= (~0X01); + } + + if(Priority == LOW) + { + IP &= ~0X01; + } + else + { + IP |= 0X01; + } +} + +/***************************************************** +*:void INT1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:INT1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void INT1_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState != DISABLE) + { + IE |= 0X04; + } + else + { + IE &= (~0X04); + } + + if(Priority == LOW) + { + IP &= ~0X04; + } + else + { + IP |= 0X04; + } +} + +/***************************************************** +*:void INT2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:INT0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void INT2_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState != DISABLE) + { + IE1 |= 0X08; + } + else + { + IE1 &= (~0X08); + } + + if(Priority == LOW) + { + IP1 &= ~0X08; + } + else + { + IP1 |= 0X08; + } +} + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ + diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_lpd.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_lpd.c new file mode 100644 index 0000000..c562f5c --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_lpd.c @@ -0,0 +1,94 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92F_LPD.c +// : ԪӦŶ +// ģ鹦: LPD̼⺯Cļ +// : 2022323 +// 汾: V1.100002 +// ˵: ļSC92LϵоƬ +//************************************************************* + +#include "sc92f_lpd.h" + +#if defined (SC92L853x) || defined (SC92L753x) + +/************************************************** +*:void USCI1_DeInit(void) +*:USCI1ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void LPD_DeInit(void) +{ + /* ؼĴλ */ + LPDCFG = 0x00; + /* жؼĴλ */ + IE2 &= 0x7F; + IP2 &= 0x7F; +} + +/************************************************** +*:void LPD_VtripConfig(LPD_Vtrip_TypeDef LPD_Vtrip) +*:LPD޵ѹֵ +*ڲ: +LPD_Vtrip_TypeDef:LPD_Vtrip:LPD޵ѹֵ +*ڲ:void +**************************************************/ +void LPD_VtripConfig(LPD_Vtrip_TypeDef LPD_Vtrip) +{ + LPDCFG &= 0xF1; //λ޵ѹֵĴ + LPDCFG = LPD_Vtrip << 1; //޵ѹֵĴ +} + +/************************************************** +*:void LPD_Cmd(FunctionalState NewState) +*:ʹLPD +*ڲ: +FunctionalState:NewState:ʹ/ʧ +*ڲ:void +**************************************************/ +void LPD_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + LPDCFG &= 0xFE; + } + else + { + LPDCFG |= 0x01; + } +} + +/***************************************************** +*:void LPD_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:LPDжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void LPD_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + /* жϿ */ + if (NewState != DISABLE) + { + IE2 |= 0x01; + } + else + { + IE2 &= 0xFE; + } + + /* жȼ */ + if (Priority != LOW) + { + IP2 |= 0x01; + } + else + { + IP2 &= 0xFE; + } +} + + +#endif \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_mdu.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_mdu.c new file mode 100644 index 0000000..0301ee8 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_mdu.c @@ -0,0 +1,132 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_mdu.c +// : +// ģ鹦 : MDU̼⺯Cļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#include "sc92f_mdu.h" + +#if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F848x) || defined (SC92F748x)\ + || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void MDU_DeInit(void) +*:MDUؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void MDU_DeInit(void) +{ + OPERCON &= 0X3F; + EXA0 = 0X00; + EXA1 = 0X00; + EXA2 = 0X00; + EXA3 = 0X00; + EXBL = 0X00; + EXBH = 0X00; +} + +/************************************************** +*:void MDU_MultiplicationConfig(uint16_t Multiplicand, uint16_t Multiplier) +*:MDU˷ú +*ڲ: +uint32_t:Multiplicand: +uint32_t:Multiplier: +*ڲ:void +**************************************************/ +void MDU_MultiplicationConfig(uint16_t + Multiplicand, uint16_t Multiplier) +{ + OPERCON &= 0XBF; + EXBL = Multiplier ; + EXBH = Multiplier >> 8; + EXA0 = Multiplicand ; + EXA1 = Multiplicand >> 8; +} + +/************************************************** +*:void MDU_DivisionConfig(uint32_t Dividend, uint16_t Divisor) +*:MDUú +*ڲ: +uint32_t:Dividend: +uint32_t:Divisor: +*ڲ:void +**************************************************/ +void MDU_DivisionConfig(uint32_t Dividend, + uint16_t Divisor) +{ + MDU_Temp_Union MDU_DivisionTemp; + MDU_DivisionTemp.MDU_Temp = Dividend; + OPERCON |= 0X40; + EXA0 = MDU_DivisionTemp.MDU_EXAxReg.MDU_EXA0Reg; + EXA1 = MDU_DivisionTemp.MDU_EXAxReg.MDU_EXA1Reg; + EXA2 = MDU_DivisionTemp.MDU_EXAxReg.MDU_EXA2Reg; + EXA3 = MDU_DivisionTemp.MDU_EXAxReg.MDU_EXA3Reg; + EXBL = Divisor; + EXBH = Divisor >> 8; +} + +/************************************************** +*:void MDU_StartOperation(void) +*:MDUһ +*ڲ:void +*ڲ:void +**************************************************/ +void MDU_StartOperation(void) +{ + OPERCON |= 0x80; + + while(OPERCON & 0x80); +} + +/************************************************** +*:uint32_t MDU_GetProduct(void) +*:ȡ˻ +*ڲ:void +*ڲ:uint32_t:˻ +**************************************************/ +uint32_t MDU_GetProduct(void) +{ + MDU_Temp_Union MDU_ProductTemp; + MDU_ProductTemp.MDU_EXAxReg.MDU_EXA0Reg = EXA0; + MDU_ProductTemp.MDU_EXAxReg.MDU_EXA1Reg = EXA1; + MDU_ProductTemp.MDU_EXAxReg.MDU_EXA2Reg = EXA2; + MDU_ProductTemp.MDU_EXAxReg.MDU_EXA3Reg = EXA3; + return MDU_ProductTemp.MDU_Temp; +} + +/************************************************** +*:uint32_t MDU_GetQuotient(void) +*:ȡ +*ڲ:void +*ڲ:uint32_t: +**************************************************/ +uint32_t MDU_GetQuotient(void) +{ + MDU_Temp_Union MDU_QuotientTemp; + MDU_QuotientTemp.MDU_EXAxReg.MDU_EXA0Reg = EXA0; + MDU_QuotientTemp.MDU_EXAxReg.MDU_EXA1Reg = EXA1; + MDU_QuotientTemp.MDU_EXAxReg.MDU_EXA2Reg = EXA2; + MDU_QuotientTemp.MDU_EXAxReg.MDU_EXA3Reg = EXA3; + return MDU_QuotientTemp.MDU_Temp; +} + +/************************************************** +*:uint16_t MDU_GetRemainder(void) +*:ȡ +*ڲ:void +*ڲ:uint16_t: +**************************************************/ +uint16_t MDU_GetRemainder(void) +{ + uint16_t MDU_RemainderTemp; + MDU_RemainderTemp = EXBH * 256 + EXBL; + return MDU_RemainderTemp; +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_option.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_option.c new file mode 100644 index 0000000..f93b338 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_option.c @@ -0,0 +1,178 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_option.c +// : +// ģ鹦 : Customer OptionĴCļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.0005 +// ˵ : +//************************************************************* + +#include "sc92f_option.h" + +/***************************************************** +*:void OPTION_WDT_Cmd(FunctionalState NewState) +*:WDTܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void OPTION_WDT_Cmd(FunctionalState NewState) +{ + OPINX = 0XC1; + + if(NewState == DISABLE) + { + OPREG &= 0X7F; + } + else + { + OPREG |= 0X80; + } +} + +/***************************************************** +*:void OPTION_XTIPLL_Cmd(FunctionalState NewState) +*:Ӿʹ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +#if !defined(SC92F848x) && !defined(SC92F748x) +void OPTION_XTIPLL_Cmd(FunctionalState NewState) +{ + OPINX = 0XC1; + + if(NewState == DISABLE) + { + OPREG &= 0XBF; + } + else + { + OPREG |= 0X40; + } +} +#endif +/***************************************************** +*:void OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef SYSCLK_PresSel) +*:ϵͳʱӷƵʼ +*ڲ: +SYSCLK_PresSel_TypeDef:SYSCLK_PresSel:ѡϵͳʱӷƵ +*ڲ:void +*****************************************************/ +void OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef + SYSCLK_PresSel) +{ + OPINX = 0XC1; + OPREG = OPREG & 0XCF | SYSCLK_PresSel; +} + +/***************************************************** +*:void OPTION_RST_PIN_Cmd(FunctionalState NewState) +*:ⲿλܽţP17ʹ +*ڲ: +FunctionalState:NewState:ʹ/رѡ +*ڲ:void +*****************************************************/ +#if !defined(SC92F848x) && !defined(SC92F748x) && !defined(SC92F859x) && !defined (SC92F759x) && !defined(SC92L853x) && !defined (SC92L753x) +void OPTION_RST_PIN_Cmd(FunctionalState NewState) +{ + OPINX = 0XC1; + + if(NewState == DISABLE) + { + OPREG |= 0X08; + } + else + { + OPREG &= 0XF7; + } +} +#endif + +/***************************************************** +*:void OPTION_LVR_Init(LVR_Config_TypeDef LVR_Config) +*:LVR ѹѡ +*ڲ: +LVR_Config_TypeDef:LVR_Config:ѡLVRѹ +*ڲ:void +*****************************************************/ +void OPTION_LVR_Init(LVR_Config_TypeDef + LVR_Config) +{ + OPINX = 0XC1; + OPREG = OPREG & 0XF8 | LVR_Config; +} + +/***************************************************** +*:void OPTION_ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) +*:ADC οѹѡ +*ڲ: +ADC_Vref_TypeDef:ADC_Vref:ѡADCοѹ +*ڲ:void +*****************************************************/ +void OPTION_ADC_VrefConfig(ADC_Vref_TypeDef + ADC_Vref) +{ + OPINX = 0xC2; + OPREG = OPREG & 0X7F | ADC_Vref; +} + +/************************************************** +*:void OPTION_IAP_SetOperateRange(IAP_OperateRange_TypeDef IAP_OperateRange) +*:IAPķΧ +*ڲ: +IAP_OperateRange_TypeDef:IAP_OperateRange:IAPΧ +*ڲ:void +**************************************************/ +void OPTION_IAP_SetOperateRange( + IAP_OperateRange_TypeDef IAP_OperateRange) +{ + OPINX = 0xC2; + OPREG = (OPREG & 0xF3) | IAP_OperateRange; +} + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax)\ + || defined (SC92F73Ax) || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F740x)\ + || defined (SC92F8003) || defined (SC92F7003) +/***************************************************** +*:void OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef XTIPLL_Range) +*:ⲿƵƵʷΧ +*ڲ: +XTIPLL_Range_TypeDef:XTIPLL_Range:ⲿƵѡ +*ڲ:void +*****************************************************/ +void OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef + XTIPLL_Range) +{ + OPINX = 0XC2; + OPREG = OPREG & 0XBF | XTIPLL_Range; +} +#endif + +#if defined (SC92F742x)||defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) \ + ||defined (SC92F74Ax_2)||defined (SC92F84Ax_2)||defined (SC92F844xB)||defined (SC92F744xB) \ + ||defined (SC92F859x) || defined (SC92F759x) ||defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void OPTION_JTG_Cmd(FunctionalState NewState) +*:JTAGģʽʹܿ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +**************************************************/ +void OPTION_JTG_Cmd(FunctionalState NewState) +{ + OPINX = 0xC2; + + if(NewState == DISABLE) + { + OPREG |= 0X10; //1 JTAGЧ + } + else + { + OPREG &= 0XEF; //0 JTAGЧ + } +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_pwm.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_pwm.c new file mode 100644 index 0000000..8d2e174 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_pwm.c @@ -0,0 +1,2086 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_pwm.c +// : +// ģ鹦 : PWM̼⺯Cļ +// ֲб: +// : 202262 +// 汾 : V1.10004 +// ˵ :ļԪ92F/93F/92LϵеƬ +//************************************************************* + +#include "sc92f_pwm.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ +||defined (SC92F859x) || defined (SC92F759x) +uint16_t xdata PWMREG[8] _at_ +0x740; //PWMռձȵڼĴ +uint16_t pwm_tmpreg[8] = {0, 0, 0, 0, 0, 0, 0, 0}; //PWMռձȵڼĴ + +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + static uint8_t i; + PWMCFG = 0X00; + PWMCON = 0X00; + IE1 &= 0XFD; + IP1 &= 0XFD; + + for(i = 0; i < 8; i++) + { + PWMREG[i] = 0; + } +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCFG = (PWMCFG & 0XCF) | + PWM_PresSel; //ԤƵ + PWMCFG = (PWMCFG & 0XF0) | (uint8_t)( + PWM_Period / 256); //ڸ4λ + PWMCON = (uint8_t)(PWM_Period & + 0X00FF); //ڵ8λ +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +uint8_t:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + uint8_t i; + + for(i = 0; i < 8; i++) + { + if(PWM_OutputPin & (0x01 << i)) + { + if(PWM_OutputState == PWM_OUTPUTSTATE_DISABLE) + { + pwm_tmpreg[i] &= 0X7FFF; + } + else + { + pwm_tmpreg[i] |= 0X8000; + } + + PWMREG[i] = pwm_tmpreg[i]; + } + } +} + + +/************************************************** +*:void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +uint8_t:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + uint8_t i; + + for(i = 0; i < 8; i++) + { + if(PWM_OutputPin & (0x01 << i)) + { + if(PWM_Polarity == PWM_POLARITY_NON_INVERT) + { + pwm_tmpreg[i] &= 0XBFFF; + } + else + { + pwm_tmpreg[i] |= 0X4000; + } + + PWMREG[i] = pwm_tmpreg[i]; + } + } +} +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + uint8_t i; + + for(i = 0; i < 8; i++) + { + if(PWM_OutputPin & (0x01 << i)) + { + pwm_tmpreg[i] = pwm_tmpreg[i] & 0XF000 | + PWM_DutyCycle; + PWMREG[i] = pwm_tmpreg[i]; + } + } +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCFG |= 0X80; + } + else + { + PWMCFG &= 0X7F; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCFG & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCFG &= 0XBF; +} +#endif + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMDTYA = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; + PWMDTYB = 0X00; + PWMDTY3 = 0X00; + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; + IE1 &= ~0X02; + IP1 &= ~0X02; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCFG = (PWMCFG & 0X3F) | (PWM_PresSel << 6); //ԤƵ + PWMDTYA = (PWMDTYA & 0X3F) | ((uint8_t)( PWM_Period % 4) << 6); //ڵλ + PWMPRD = (uint8_t)(PWM_Period >> 2); //ڸ߰λ +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON |= PWM_OutputPin; + } + else + { + PWMCON &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= PWM_OutputPin; + } + else + { + PWMCFG &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + PWMDTYB &= 0X7F; //PWMΪģʽ + + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTYA = PWMDTYA & 0xfc | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM1: + PWMDTYA = PWMDTYA & 0xf3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM2: + PWMDTYA = PWMDTYA & 0xcf | ((PWM_DutyCycle % 4) << + 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM3: + PWMDTYB = PWMDTYB & 0xfc | (PWM_DutyCycle % 4); + PWMDTY3 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM4: + PWMDTYB = PWMDTYB & 0xf3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY4 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM5: + PWMDTYB = PWMDTYB & 0xcf | ((PWM_DutyCycle % 4) << + 4); + PWMDTY5 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + default: + break; + } +} + +/************************************************** +*:void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t PWM_DutyCycle) +*:PWMxPWMyģʽú +*ڲ: +PWM_ComplementaryOutputPin_TypeDef:PWM_ComplementaryOutputPin:PWMxPWMyͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle) +{ + PWMDTYB |= 0X80; //PWMΪģʽ + + switch(PWM_ComplementaryOutputPin) //ռձ + { + case PWM0PWM3: + PWMDTYA = PWMDTYA & 0xfc | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM1PWM4: + PWMDTYA = PWMDTYA & 0xf3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM2PWM5: + PWMDTYA = PWMDTYA & 0xcf | ((PWM_DutyCycle % 4) << + 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + default: + break; + } +} + +/************************************************** +*:void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) +*:PWMģʽʱú +*ڲ: +uint8_t:PWM012_RisingDeadTime:PWMʱ +uint8_t:PWM345_fallingDeadTime:PWM½ʱ +*ڲ:void +**************************************************/ +void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, + uint8_t PWM345_fallingDeadTime) +{ + PWMDTY3 = (PWM012_RisingDeadTime | + (PWM345_fallingDeadTime << 4)); +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= 0XFD; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON &= 0XBF; +} +#endif + +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG = 0X00; + PWMCON0 = 0X00; + PWMPRD = 0X00; + PWMDTYA = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; + PWMCON1 = 0X00; + PWMDTYB = 0X00; + PWMDTY3 = 0X00; + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; + PWMDTY6 = 0X00; + IE1 &= 0XFD; + IP1 &= 0XFD; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCON0 = (PWMCON0 & 0XCC) | PWM_PresSel | + (uint8_t)(PWM_Period & + 0X0003); //ԤƵڵĵ2λ + PWMPRD = (uint8_t)(PWM_Period >> + 2); //ڸ߰λ +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON1 |= PWM_OutputPin; + } + else + { + PWMCON1 &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_PWM2Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin) +*:PWM2ܽѡ +*ڲ: +PWM2_OutputPin_TypeDef:PWM2_OutputPin:PWM2ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM2Selection(PWM2_OutputPin_TypeDef + PWM2_OutputPin) +{ + PWMCON0 = PWMCON0 & 0XFB | PWM2_OutputPin; +} + +/************************************************** +*:void PWM_PWM5Selection(PWM5_OutputPin_TypeDef PWM5_OutputPin) +*:PWM5ܽѡ +*ڲ: +PWM5_OutputPin_TypeDef:PWM5_OutputPin:PWM5ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM5Selection(PWM5_OutputPin_TypeDef + PWM5_OutputPin) +{ + PWMCON0 = PWMCON0 & 0XF7 | PWM5_OutputPin; +} + +/************************************************** +*:void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= PWM_OutputPin; + } + else + { + PWMCFG &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + if(PWM_OutputPin != PWM6) + { + PWMCON1 &= 0X7F; //PWMΪģʽ + } + + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTYA = PWMDTYA & 0XFC | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM1: + PWMDTYA = PWMDTYA & 0XF3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM2: + PWMDTYA = PWMDTYA & 0XCF | ((PWM_DutyCycle % 4) << + 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM3: + PWMDTYA = PWMDTYA & 0X3F | ((PWM_DutyCycle % 4) << + 6); + PWMDTY3 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM4: + PWMDTYB = PWMDTYB & 0XFC | (PWM_DutyCycle % 4); + PWMDTY4 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM5: + PWMDTYB = PWMDTYB & 0XF3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY5 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM6: + PWMDTYB = PWMDTYB & 0XCF | ((PWM_DutyCycle % 4) << + 4); + PWMDTY6 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + default: + break; + } +} + +/************************************************** +*:void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t PWM_DutyCycle) +*:PWMxPWMyģʽú +*ڲ: +PWM_ComplementaryOutputPin_TypeDef:PWM_ComplementaryOutputPin:PWMxPWMyͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle) +{ + PWMCON1 |= 0X80; //PWMΪģʽ + + switch(PWM_ComplementaryOutputPin) //ռձ + { + case PWM0PWM3: + PWMDTYA = PWMDTYA & 0XFC | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM1PWM4: + PWMDTYA = PWMDTYA & 0XF3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM2PWM5: + PWMDTYA = PWMDTYA & 0XCF | ((PWM_DutyCycle % 4) << + 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + default: + break; + } +} + +/************************************************** +*:void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) +*:PWMģʽʱú +*ڲ: +uint8_t:PWM012_RisingDeadTime:PWMʱ +uint8_t:PWM345_fallingDeadTime:PWM½ʱ +*ڲ:void +**************************************************/ +void PWM_DeadTimeConfig(uint8_t + PWM012_RisingDeadTime, + uint8_t PWM345_fallingDeadTime) +{ + PWMDTY3 = (PWM012_RisingDeadTime | + (PWM345_fallingDeadTime << 4)); +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON0 |= 0X80; + } + else + { + PWMCON0 &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= 0XFD; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON0 & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON0 &= 0XBF; +} +#endif + +#if defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined(SC92F735X) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG0 = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMCFG1 = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; +#if !defined (SC92F730x) + PWMDTY3 = 0X00; +#endif + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; + IE1 &= ~0X02; + IP1 &= ~0X02; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCON = (PWMCON & 0XF8) | PWM_PresSel; //ԤƵ + PWMPRD = PWM_Period; // +} + +/************************************************** +*:void PWM_OutputStateConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +uint8_t:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_DISABLE) + { + PWMCON = PWMCON & (~((PWM_OutputPin & 0x07) << 3)); + PWMCON = PWMCON | (PWM_OutputPin & 0x07) << 3; + } + else + { + PWMCON = PWMCON | (PWM_OutputPin & 0x07) << 3; + PWMCFG0 = PWMCFG0 | (PWM_OutputPin & 0x38) >> 3; + } +} + +/************************************************** +*:void PWM_PolarityConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_PolarityConfig:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_NON_INVERT) + { + PWMCFG0 = PWMCFG0 & ~((PWM_OutputPin & 0x07) << 3); + PWMCFG1 = PWMCFG1 & ~((PWM_OutputPin & 0x38)); + } + else + { + PWMCFG0 = PWMCFG0 | (PWM_OutputPin & 0x07) << 3; + PWMCFG1 = PWMCFG1 | (PWM_OutputPin & 0x38); + } + +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig( + PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTY0 = PWM_DutyCycle; + break; + + case PWM1: + PWMDTY1 = PWM_DutyCycle; + break; + + case PWM2: + PWMDTY2 = PWM_DutyCycle; + break; +#if !defined (SC92F730x) + + case PWM3: + PWMDTY3 = PWM_DutyCycle; + break; +#endif + + case PWM4: + PWMDTY4 = PWM_DutyCycle; + break; + + case PWM5: + PWMDTY5 = PWM_DutyCycle; + break; + + default: + break; + } +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= ~0X02; + } + + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON &= 0XBF; +} +#endif + +#if defined (SC92F827X) || defined (SC92F837X) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; +#if !defined (SC92F827X) + PWMDTY2 = 0X00; + PWMDTY3 = 0X00; +#if !defined (SC92F837X) + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; +#endif +#endif + IE1 &= ~0X02; + IP1 &= ~0X02; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCON = (PWMCON & 0XF8) | PWM_PresSel; //ԤƵ + PWMPRD = PWM_Period; // +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON |= PWM_OutputPin; + } + else + { + PWMCON &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= PWM_OutputPin; + } + else + { + PWMCFG &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig( + PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTY0 = PWM_DutyCycle; + break; + + case PWM1: + PWMDTY1 = PWM_DutyCycle; + break; +#if !defined (SC92F827X) + + case PWM2: + PWMDTY2 = PWM_DutyCycle; + break; + + case PWM3: + PWMDTY3 = PWM_DutyCycle; + break; +#if !defined (SC92F837X) + + case PWM4: + PWMDTY4 = PWM_DutyCycle; + break; + + case PWM5: + PWMDTY5 = PWM_DutyCycle; + break; +#endif +#endif + + default: + break; + } +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= 0XFD; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:FlagStatus PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON &= 0XBF; +} +#endif + +#if defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMDTYA = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; + IE1 &= ~0X02; + IP1 &= ~0X02; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCON = (PWMCON & 0XF8) | PWM_PresSel; //ԤƵ + PWMPRD = PWM_Period; // +} + +/************************************************** +*:void PWM_OutputStateConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_DISABLE) + { + PWMCON = PWMCON & (~(PWM_OutputPin << 3)); + } + else + { + PWMCON = PWMCON | (PWM_OutputPin << 3); + } +} + +/************************************************** +*:void PWM_PolarityConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:WM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_NON_INVERT) + { + PWMCFG = PWMCFG & (~PWM_OutputPin<<3); + } + else + { + PWMCFG = PWMCFG | (PWM_OutputPin<<3); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig( + PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTY0 = PWM_DutyCycle; + break; + + case PWM1: + PWMDTY1 = PWM_DutyCycle; + break; + + case PWM2: + PWMDTY2 = PWM_DutyCycle; + break; + + default: + break; + } +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= ~0X02; + } + + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON &= 0XBF; +} + +/************************************************** +*:void PWM_PWM0Selection(PWM0_OutputPin_TypeDef PWM0_OutputPin) +*:PWM0ܽѡ +*ڲ: +PWM0_OutputPin_TypeDef:PWM0_OutputPin:PWM0ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM0Selection(PWM0_OutputPin_TypeDef + PWM0_OutputPin) +{ + PWMCFG = PWMCFG & 0XFE | PWM0_OutputPin; +} + +/************************************************** +*:void PWM_PWM1Selection(PWM1_OutputPin_TypeDef PWM1_OutputPin) +*:PWM1ܽѡ +*ڲ: +PWM1_OutputPin_TypeDef:PWM1_OutputPin:PWM1ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM1Selection(PWM1_OutputPin_TypeDef + PWM1_OutputPin) +{ + PWMCFG = PWMCFG & 0XFD | PWM1_OutputPin; +} + +/************************************************** +*:void PWM_PWM1Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin) +*:PWM2ܽѡ +*ڲ: +PWM2_OutputPin_TypeDef:PWM2_OutputPin:PWM1ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM2Selection(PWM2_OutputPin_TypeDef + PWM2_OutputPin) +{ + PWMCFG = PWMCFG & 0XFB | PWM2_OutputPin; +} + +/************************************************** +*:void PMM_DutyModeSelection(PWM_DutyMode_TypeDef PWM_DutyMode) +*:PWMռձ΢ģʽѡ +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMͨ +PWM_DutyMode_TypeDef:PWM_DutyMode:PWM΢ģʽ +*ڲ:void +**************************************************/ +void PMM_DutyModeSelection(PWM_OutputPin_TypeDef + PWM_OutputPin, PWM_DutyMode_TypeDef PWM_DutyMode) +{ + PWMDTYA = PWMDTYA & (~(0x03 << (PWM_OutputPin - + 1))) | (PWM_DutyMode << (PWM_OutputPin - 1)); +} +#endif + +#if defined (SC92FWxx) + +uint8_t xdata PWMREG[80] _at_ +0x700; //PWMռձȵڼĴ +uint8_t PWMREG_Status[10]; +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + static uint8_t i; + PWMCFG0 = 0X00; + PWMCON0 = 0X00; + PWMCFG1 = 0X00; + PWMCON1 = 0X00; + IE1 &= 0XFD; + IP1 &= 0XFD; + + for(i = 0; i < 80; i++) + { + PWMREG[i] = 0; + } +} + +/************************************************** +*:PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + if((PWM_PresSel & 0X0F) == PWM0_Type) + { + PWM_Period -= 1; + PWMCFG0 = (PWMCFG0 & 0XCF) | (PWM_PresSel & + 0XF0); //ԤƵ + PWMCFG0 = (PWMCFG0 & 0XF0) | (uint8_t)( + PWM_Period / 256); //ڸ4λ + PWMCON0 = (uint8_t)(PWM_Period & + 0X00FF); //ڵ8λ + } + else + if ((PWM_PresSel & 0X0F) == PWM1_Type) + { + PWM_Period -= 1; + PWMCFG1 = (PWMCFG1 & 0XCF) | (PWM_PresSel & + 0XF0); //ԤƵ + PWMCFG1 = (PWMCFG1 & 0XF0) | (uint8_t)( + PWM_Period / 256); //ڸ4λ + PWMCON1 = (uint8_t)(PWM_Period & + 0X00FF); //ڵ8λ + } +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ(ͺβ֧Χδ) +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == ENABLE) + { + PWMREG[PWM_OutputPin] |= 0x80; + } + else + { + PWMREG[PWM_OutputPin] &= 0x7F; + } +} + +/************************************************** +*:void PWM_PolarityConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ(ͺβ֧Χδ) +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMREG[PWM_OutputPin] |= 0x40; + } + else + { + PWMREG[PWM_OutputPin] &= 0xBF; + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ(ͺβ֧Χδ) +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + PWMREG[PWM_OutputPin + 1] = PWM_DutyCycle; + PWMREG[PWM_OutputPin] = (PWMREG[PWM_OutputPin] * 0xF0) |(PWM_DutyCycle / 256); +} + +/***************************************************** +*:void PWM_Cmd(PWM_Type_TypeDef PWM_Type,FunctionalState NewState) +*:PWMܿغ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_CmdEX(PWM_Type_TypeDef PWM_Type, + FunctionalState NewState) +{ + if(PWM_Type == PWM0_Type) + { + if (NewState != DISABLE) + { + PWMCFG0 |= 0X80; + } + else + { + PWMCFG0 &= 0X7F; + } + } + else + { + if (NewState != DISABLE) + { + PWMCFG1 |= 0X80; + } + else + { + PWMCFG1 &= 0X7F; + } + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM1_Type_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +*ڲ:FlagStatus PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatusEX(PWM_Type_TypeDef + PWM_Type) +{ + if(PWM_Type == PWM0_Type) + { + return (bool)(PWMCFG0 & 0X40); + } + else + { + return (bool)(PWMCFG1 & 0X40); + } +} + +/***************************************************** +*:void PWM1_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +*ڲ:void +*****************************************************/ +void PWM_ClearFlagEX(PWM_Type_TypeDef PWM_Type) +{ + if(PWM_Type == PWM0_Type) + { + PWMCFG0 &= 0XBF; + } + else + { + PWMCFG1 &= 0XBF; + } +} + +/***************************************************** +*:void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMжϱ־״̬ +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == ENABLE) + { + PWMREG[PWM_OutputPin] = (PWMREG[PWM_OutputPin] * 0xF0) | (0x80 | (PWM_DutyCycle / + 256)); + PWMREG[PWM_OutputPin + 1] = PWM_DutyCycle; + } + else + { + PWMREG[PWM_OutputPin] &= 0x7F; + } +} + +#endif + +#if defined (SC92L853x) || defined (SC92L753x) +uint8_t xdata PWMREG[28] _at_ 0x0F40; //PWMռձȵڼĴ +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + static uint8_t i; + + //PWM0ؼĴ + PWMCON0 = 0X00; + PWMCFG = 0X00; + PWMCON1 = 0X00; + PWMPDL = 0x00; + PWMPDH = 0x00; + IE1 &= 0XFD; + IP1 &= 0XFD; + + //ռձȼĴ + for (i = 0; i < 14; i++) + { + PWMREG[i] = 0; + } +} + +/************************************************** +*:PWM_Init(PWM_Type_TypeDef PWM_Type,PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +{ + /* PWM0ʱʼ */ + PWM_Period -= 1; + PWMCON0 = ((PWMCON0 & 0XCF) | PWM_PresSel); //ԤƵ + PWMPDH = (uint8_t)(PWM_Period >> 8); //ڸ8λ + PWMPDL = (uint8_t)(PWM_Period & 0X00FF); //ڵ8λ +} + +/***************************************************** +*:void PWM_Aligned_Mode_Select(void) +*:ѡPWMĶģʽ +*ڲ: +PWM_Aligned_Mode_TypeDef:PWM_Aligned_Mode:ѡģʽ +*ڲ:void +*****************************************************/ +void PWM_Aligned_Mode_Select(PWM_Aligned_Mode_TypeDef PWM_Aligned_Mode) +{ + PWMCON0 &= ~0x01; //PWMģʽ + PWMCON0 |= (PWM_Aligned_Mode<<1); //PWMģʽ +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡuint8_tΪΣλ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + /* PWM0ͨʹ */ + if (PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON1 |= 1 << ((PWM_OutputPin >> 1) & 0x0F); + } + else + { + PWMCON1 &= ~(1 << ((PWM_OutputPin >> 1) & 0x0F)); + } +} + +/************************************************** +*:void PWM_PolarityConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡuint8_tΪΣλ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if (PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= 1 << ((PWM_OutputPin >> 1) & 0x0F); + } + else + { + PWMCFG &= ~(1 << ((PWM_OutputPin >> 1) & 0x0F)); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +{ + PWMCON0 &= ~0x02; //PWMΪģʽ + /* PWM */ + PWMREG[ PWM_ComplementaryOutputPin] = PWM_DutyCycle; + PWMREG[ PWM_ComplementaryOutputPin+1] = PWM_DutyCycle >> 8; +} + +/************************************************** +*:void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t PWM_DutyCycle) +*:PWMxPWMyģʽú +*ڲ: +PWM_ComplementaryOutputPin_TypeDef:PWM_ComplementaryOutputPin:PWMxPWMyͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle) +{ + PWMCON0 |= 0x02; + PWMREG[ PWM_ComplementaryOutputPin] = PWM_DutyCycle; + PWMREG[ PWM_ComplementaryOutputPin+1] = PWM_DutyCycle >> 8; +} + +/************************************************** +*:PWM_DeadTimeConfigEX(PWM_Type_TypeDef PWM_Type,uint8_t PWM_RisingDeadTime, uint8_t PWM_FallingDeadTime) +*:PWMģʽʱú +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMԴѡ +uint8_t:PWM_RisingDeadTime:PWMʱ 00-FF +uint8_t:PWM_FallingDeadTime:PWM½ʱ 00-FF +*ڲ:void +**************************************************/ +void PWM_DeadTimeConfigEX(PWM_Type_TypeDef PWM_Type, uint8_t PWM_RisingDeadTime, uint8_t PWM_FallingDeadTime) +{ + if (PWM_Type == PWM0_Type) + { + PWMDFR = (PWM_RisingDeadTime | (PWM_FallingDeadTime << 4)); + } +} + +/***************************************************** +*:void PWM_Cmd(PWM_Type_TypeDef PWM_Type,FunctionalState NewState) +*:PWMܿغ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_CmdEX(PWM_Type_TypeDef PWM_Type, + FunctionalState NewState) +{ + if (PWM_Type == PWM0_Type) + { + if (NewState != DISABLE) + { + PWMCON0 |= 0X80; + } + else + { + PWMCON0 &= 0X7F; + } + } + else + { + TXINX = PWM_Type; + if (NewState != DISABLE) + { + TXCON |= 0X04; + } + else + { + TXCON &= ~0X04; + } + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if (Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMģʽ +*ڲ: +PWM_OutputPin_TypeDef:PWM_ComplementaryOutputPin:PWMͨ +uint16_t:PWM_DutyCycle:PWMռձ +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle, + PWM_OutputState_TypeDef PWM_OutputState) +{ + PWM_IndependentModeConfig(PWM_ComplementaryOutputPin, PWM_DutyCycle); //ռձ + PWM_OutputStateConfig(PWM_ComplementaryOutputPin, PWM_OutputState); //IOPWMú + if (PWM_OutputState == ENABLE) + { + PWM_CmdEX(PWM_ComplementaryOutputPin >> 4, ENABLE); //PWM + } +} + +/***************************************************** +*:void PWM_ComplementaryModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle, PWM_OutputState_TypeDef PWM_OutputState) +*:PWM +*ڲ: +PWM_ComplementaryOutputPin_TypeDef:PWM_OutputPin:PWMͨ +uint16_t:PWM_DutyCycle:PWMռձ +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_ComplementaryModeConfigEX(PWM_ComplementaryOutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle, + PWM_OutputState_TypeDef PWM_OutputState) +{ + PWM_ComplementaryModeConfig(PWM_OutputPin, PWM_DutyCycle); //ռձ + PWM_OutputStateConfig(PWM_OutputPin, PWM_OutputState); //IOPWMú + PWM_OutputStateConfig(PWM_OutputPin + 2, PWM_OutputState); //IOPWMú + if (PWM_OutputState == ENABLE) + { + PWM_CmdEX(PWM_OutputPin >> 4, ENABLE); //PWM + } +} + +/***************************************************** +*:PWM_GetFlagStatusEX(PWM_Type_TypeDef PWM_Type) +*:ȡPWMжϱ־λ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMԴѡ +*ڲ:void +*****************************************************/ +FlagStatus PWM_GetFlagStatusEX(PWM_Type_TypeDef PWM_Type) +{ + if ((PWM_Type == PWM0_Type)) + { + return (bool)(PWMCON0 & 0X40); + } + + return RESET; +} + +/***************************************************** +*:void PWM_ClearFlagEX(PWM_Type_TypeDef PWM_Type) +*:PWMж +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMԴѡ +*ڲ:void +*****************************************************/ +void PWM_ClearFlagEX(PWM_Type_TypeDef PWM_Type) +{ + if ((PWM_Type == PWM0_Type)) + { + PWMCON0 &= ~0X40; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFaultDetectionFlagStatus(void) +*:PWMϼ־λ״̬ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +*ڲ: +FlagStatus:PWMϼ־λ״̬ +*****************************************************/ +FlagStatus PWM_GetFaultDetectionFlagStatusEX(PWM_Type_TypeDef PWM_Type) +{ + if (PWM_Type == PWM0_Type) + { + return (bool)(PWMFLT & 0X40); + } + return RESET; +} + +/***************************************************** +*:void PWM_ClearFaultDetectionFlag(void) +*:PWMϼ־λ״̬ // ע,ģʽ£λ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +*ڲ:void +*****************************************************/ +void PWM_ClearFaultDetectionFlagEX(PWM_Type_TypeDef PWM_Type) +{ + if (PWM_Type == PWM0_Type) + { + PWMFLT &= 0XBF; + } +} + +/***************************************************** +*:void PWM_FaultDetectionFunctionConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState) +*:PWMϼ⹦ܿ/ر-չ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMѡ +FunctionalState:NewState:ϼ⹦ܿ/ر +*ڲ:void +*****************************************************/ +void PWM_FaultDetectionConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState) +{ + if (PWM_Type == PWM0_Type) + { + if (NewState != DISABLE) + { + PWMFLT |= 0X80; + } + else + { + PWMFLT &= 0X7F; + } + } +} + +/***************************************************** +*:void PWM_FaultDetectionModeConfigEX(PWM_Type_TypeDef PWM_Type, PWM_FaultDetectionMode_TypeDef FaultDetectionMode, PWM_FaultDetectionVoltageSelect_TypeDef FaultDetectionVoltageSelect, PWM_FaultDetectionWaveFilteringTime_TypeDef FaultDetectionWaveFilteringTime) +*:PWMϼģʽ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMѡ +PWM_FaultDetectionMode_TypeDef:FaultDetectionMode:ϼ⹦ģʽ: ģʽ/ģʽ +PWM_FaultDetectionVoltageSelect_TypeDef:FaultDetectionVoltageSelect:ϼƽѡ +PWM_FaultDetectionWaveFilteringTime_TypeDef:FaultDetectionWaveFilteringTime:ϼź˲ʱѡ +*ڲ:void +*****************************************************/ +void PWM_FaultDetectionModeConfigEX(PWM_Type_TypeDef PWM_Type, + PWM_FaultDetectionMode_TypeDef FaultDetectionMode, + PWM_FaultDetectionVoltageSelect_TypeDef FaultDetectionVoltageSelect, + PWM_FaultDetectionWaveFilteringTime_TypeDef FaultDetectionWaveFilteringTime) +{ + if (PWM_Type == PWM0_Type) + { + PWMFLT = (PWMFLT & 0XC0) | FaultDetectionMode | FaultDetectionVoltageSelect | + FaultDetectionWaveFilteringTime; + } +} + +/***************************************************** +*:void PWM_ITConfigEX(PWM_Type_TypeDef PWM_Type,FunctionalState NewState, PriorityStatus Priority) +*:PWMжú-չ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMԴѡ +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState, PriorityStatus Priority) +{ + + if ((PWM_Type == PWM0_Type)) + { + PWM_ITConfig(NewState, Priority); + } + else + { + TXINX = PWM_Type; + + if (NewState == DISABLE) + { + ET2 = 0; + } + else + { + ET2 = 1; + } + + if (Priority == LOW) + { + IPT2 = 0; + } + else + { + IPT2 = 1; + } + } +} + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_pwr.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_pwr.c new file mode 100644 index 0000000..285df16 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_pwr.c @@ -0,0 +1,62 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_pwr.c +// : +// ģ鹦 : PWR̼⺯Cļ +// ֲб: +// : 2020/8/18 +// 汾 : V1.0 +// ˵ :ļԪ92FϵеƬ +//************************************************************* +#include "sc92f_pwr.h" + +/************************************************** +*:void PWR_DeInit(void) +*:PWRؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWR_DeInit(void) +{ + PCON &= 0XFC; +} + +/************************************************** +*:void PWR_EnterSTOPMode(void) +*:MCUSTOPģʽ +*ڲ:void +*ڲ:void +**************************************************/ +void PWR_EnterSTOPMode(void) +{ + PCON |= 0X02; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); +} + +/************************************************** +*:void PWR_EnterIDLEMode(void) +*:MCUIDLEģʽ +*ڲ:void +*ڲ:void +**************************************************/ +void PWR_EnterIDLEMode(void) +{ + PCON |= 0X01; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); +} + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ssi.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ssi.c new file mode 100644 index 0000000..8399abf --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ssi.c @@ -0,0 +1,420 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ssi.c +// : +// ģ鹦 : SSI̼⺯Cļ +// ֲб: +// : 2021/08/20 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#include "sc92f_ssi.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined (SC92F83Ax) || defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) || defined (SC92F827X)\ + || defined (SC92F837X) || defined (SC92FWxx) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92F848x) || defined (SC92F748x)\ + || defined (SC92F859x) || defined (SC92F759x) +/************************************************** +*:void SSI_DeInit(void) +*:SSIؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void SSI_DeInit(void) +{ + OTCON &= 0X3F; + SSCON0 = 0X00; + SSCON1 = 0X00; + SSCON2 = 0X00; + SSDAT = 0X00; + IE1 &= (~0X01); + IP1 &= (~0X01); +} + +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +/************************************************** +*:SSI_PinSelection(SSI_PinSelection_TypeDef PinSeletion) +*:SSIѡ +*ڲ: +SSI_PinSelection_TypeDef:PinSeletion:ѡSSIΪP10P27P26P21P22P23 +*ڲ:void +**************************************************/ +void SSI_PinSelection(SSI_PinSelection_TypeDef + PinSeletion) +{ + OTCON = OTCON & 0XDF | PinSeletion; +} +#endif + +/************************************************** +*:void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase,SPI_TXE_INT_TypeDef SPI_TXE_INT) +*:SPIʼú +*ڲ: +SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +SPI_Mode_TypeDef:Mode:SPIģʽѡ +SPI_ClockPolarity_TypeDef:ClockPolarity:SPIʱӼѡ +SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ +*ڲ:void +**************************************************/ +void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT) +{ + OTCON = (OTCON & 0X3F) | 0X40; + SSCON1 = SSCON1 & (~0X05) | FirstBit | + SPI_TXE_INT; + SSCON0 = SSCON0 & 0X80 | BaudRatePrescaler | Mode + | ClockPolarity | ClockPhase; +} + +/***************************************************** +*:void SSI_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI_SPI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SSCON0 |= 0X80; + } + else + { + SSCON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI_SPI_SendData(uint8_t Data) +*:SPI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void SSI_SPI_SendData(uint8_t Data) +{ + SSDAT = Data; +} + +/***************************************************** +*:uint8_t SSI_SPI_ReceiveData(void) +*:SSDATеֵ +*ڲ:void +*ڲ: +uint8_t:SPIյ8λ +*****************************************************/ +uint8_t SSI_SPI_ReceiveData(void) +{ + return SSDAT; +} + +/************************************************** +*:void SSI_TWI_Init(uint8_t TWI_Address) +*:TWIʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void SSI_TWI_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0X3F | 0X80; + SSCON1 = TWI_Address << 1; +} + +/************************************************** +*:void SSI_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI_TWI_AcknowledgeConfig(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SSCON0 |= 0X08; + } + else + { + SSCON0 &= 0XF7; + } +} + +/************************************************** +*:void SSI_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:ͨõַӦʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI_TWI_GeneralCallCmd(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SSCON1 |= 0X01; + } + else + { + SSCON1 &= 0XFE; + } +} + +/************************************************** +*:FlagStatus SSI_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +*:ȡTWI״̬ +*ڲ: +SSI_TWIState_TypeDef:SSI_TWIState:TWI״̬״̬ +*ڲ:void +**************************************************/ +FlagStatus SSI_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +{ + if((SSCON0&0x07) == SSI_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void SSI_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ:FunctionalState NewState /رѡ +*ڲ:void +*****************************************************/ +void SSI_TWI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SSCON0 |= 0X80; + } + else + { + SSCON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void SSI_TWI_SendData(uint8_t Data) +{ + SSDAT = Data; +} + +/***************************************************** +*:uint8_t SSI_TWI_ReceiveData(void) +*:SSDATеֵ +*ڲ:void +*ڲ: +uint8_t:TWIյ8λ +*****************************************************/ +uint8_t SSI_TWI_ReceiveData(void) +{ + return SSDAT; +} + +/************************************************** +*:void SSI_UART1_Init(uint32_t UART1Fsys, uint32_t BaudRate, UART1_Mode_TypeDef Mode, UART1_RX_TypeDef RxMode) +*:UART1ʼú +*ڲ: +uint32_t:UART1Fsys:ϵͳʱƵ +uint32_t:BaudRate: +UART1_Mode_TypeDef:Mode:UART1ģʽ +UART1_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void SSI_UART1_Init(uint32_t UART1Fsys, + uint32_t BaudRate, UART1_Mode_TypeDef Mode, + UART1_RX_TypeDef RxMode) +{ + + #if defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) + OTCON |= 0xC0; + SSCON0 = SSCON0 & 0X0F | Mode | RxMode; + SSCON2 = UART1Fsys / 16 / BaudRate / 256; + SSCON1 = UART1Fsys / 16 / BaudRate % 256; + + #else + OTCON |= 0xC0; + SSCON0 = SSCON0 & 0X0F | Mode | RxMode; + SSCON2 = UART1Fsys / BaudRate / 256; + SSCON1 = UART1Fsys / BaudRate % 256; + + #endif + + +} + +/***************************************************** +*:void SSI_UART1_SendData8(uint8_t Data) +*:UART18λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void SSI_UART1_SendData8(uint8_t Data) +{ + SSDAT = Data; +} + +/***************************************************** +*:uint8_t SSI_UART1_ReceiveData8(void) +*:SSDATеֵ +*ڲ:void +*ڲ: +uint8_t:UARTյ8λ +*****************************************************/ +uint8_t SSI_UART1_ReceiveData8(void) +{ + return SSDAT; +} + +/***************************************************** +*:void SSI_UART1_SendData9(uint16_t Data) +*:UART19λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void SSI_UART1_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if(Data_9Bit) + { + SSCON0 |= 0x08; + } + else + { + SSCON0 &= 0xf7; + } + + SSDAT = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t SSI_UART1_ReceiveData9(void) +*:SSDATеֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t SSI_UART1_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = SSDAT + ((uint16_t)(SSCON0 & 0X04) << 6); + SSCON0 &= 0XFB; + return Data9; +} + +/***************************************************** +*:void SSI_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:SSIжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void SSI_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState != DISABLE) + { + IE1 |= 0x01; + } + else + { + IE1 &= 0xFE; + } + + /************************************************************/ + if(Priority != LOW) + { + IP1 |= 0x01; + } + else + { + IP1 &= 0xFE; + } +} + +/***************************************************** +*:FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG) +*:SSI־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ȡı־λ +*ڲ: +FlagStatus:SSI־λ״̬ +*****************************************************/ +FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef + SSI_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + if((SSI_FLAG & SSCON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((SSI_FLAG & SSCON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +*:SSI־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +{ + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + SSCON1 &= (~SSI_FLAG); + } + else + { + SSCON0 &= (~SSI_FLAG); + } +} +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ssi0.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ssi0.c new file mode 100644 index 0000000..e9ec582 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ssi0.c @@ -0,0 +1,392 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ssi0.c +// : +// ģ鹦 : SSI0̼⺯Cļ +// ֲб: +// : 2021/07/23 +// 汾 : V1.10000 +// ˵ : +//************************************************************* + +#include "sc92f_ssi.h" + +#if defined (SC92F742x) || defined (SC92F7490) +/************************************************** +*:void SSI0_DeInit(void) +*:SSI0ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void SSI0_DeInit(void) +{ + OTCON &= 0XCF; + SS0CON0 = 0X00; + SS0CON1 = 0X00; + SS0CON2 = 0X00; + SS0DAT = 0X00; + IE &= (~0X10); + IP &= (~0X10); +} + +/************************************************** +*:void SSI0_SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase,SPI_TXE_INT_TypeDef SPI_TXE_INT) +*:SPIʼú +*ڲ: +SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +SPI_Mode_TypeDef:Mode:SPIģʽѡ +SPI_ClockPolarity_TypeDef:ClockPolarityLSPIʱӼѡ +SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ +*ڲ:void +**************************************************/ +void SSI0_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT) +{ + OTCON = (OTCON & 0XCF) | 0X10; + SS0CON1 = SS0CON1 & (~0X05) | FirstBit | + SPI_TXE_INT; + SS0CON0 = SS0CON0 & 0X80 | BaudRatePrescaler | + Mode | ClockPolarity | ClockPhase; +} + +/***************************************************** +*:void SSI0_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI0_SPI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SS0CON0 |= 0X80; + } + else + { + SS0CON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI0_SPI_SendData(uint8_t Data) +*:SPI +*ڲ: +uint8_t:Data:S{PI͵8λ +*ڲ:void +*****************************************************/ +void SSI0_SPI_SendData(uint8_t Data) +{ + SS0DAT = Data; +} + +/***************************************************** +*:uint8_t SSI0_SPI_ReceiveData(void) +*:SS0DATеֵ +*ڲ:void +*ڲ: +uint8_t:SPIյ8λ +*****************************************************/ +uint8_t SSI0_SPI_ReceiveData(void) +{ + return SS0DAT; +} + +/************************************************** +*:void SSI0_TWI_Init(uint8_t TWI_Address) +*:TWIʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void SSI0_TWI_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0XCF | 0X20; + SS0CON1 = TWI_Address << 1; +} + +/************************************************** +*:void SSI0_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI0_TWI_AcknowledgeConfig(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SS0CON0 |= 0X08; + } + else + { + SS0CON0 &= 0XF7; + } +} + +/************************************************** +*:void SSI0_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:ͨõַӦʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI0_TWI_GeneralCallCmd(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SS0CON1 |= 0X01; + } + else + { + SS0CON1 &= 0XFE; + } +} + +/************************************************** +*:FlagStatus SSI0_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +*:ȡTWI״̬ +*ڲ: +SSI_TWIState_TypeDef:SSI_TWIState:TWI״̬״̬ +*ڲ:void +**************************************************/ +FlagStatus SSI0_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +{ + if((SS0CON0&0x07) == SSI_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void SSI0_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI0_TWI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SS0CON0 |= 0X80; + } + else + { + SS0CON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI0_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:TWI͵8λ +*ڲ:void +*****************************************************/ +void SSI0_TWI_SendData(uint8_t Data) +{ + SS0DAT = Data; +} + +/***************************************************** +*:uint8_t SSI0_TWI_ReceiveData(void) +*:SS0DATеֵ +*ڲ:void +*ڲ: +uint8_t:TWIյ8λ +*****************************************************/ +uint8_t SSI0_TWI_ReceiveData(void) +{ + return SS0DAT; +} + +/************************************************** +*:void SSI0_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, UART_Mode_TypeDef Mode, UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +UART_Mode_TypeDef:Mode:UART1ģʽ +UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void SSI0_UART_Init(uint32_t UARTFsys, + uint32_t BaudRate, UART_Mode_TypeDef Mode, + UART_RX_TypeDef RxMode) +{ + OTCON |= 0x30; + SS0CON0 = SS0CON0 & 0X0F | Mode | RxMode; + SS0CON2 = UARTFsys / BaudRate / 256; + SS0CON1 = UARTFsys / BaudRate % 256; +} + +/***************************************************** +*:void SSI0_UART_SendData8(uint8_t Data) +*:UART8λ +*ڲ: +uint8_t:Data:UART͵8λ +*ڲ:void +*****************************************************/ +void SSI0_UART_SendData8(uint8_t Data) +{ + SS0DAT = Data; +} + +/***************************************************** +*:uint8_t SSI0_UART_ReceiveData8(void) +*:SS0DATеֵ +*ڲ:void +*ڲ: +uint8_t:UARTյ8λ +*****************************************************/ +uint8_t SSI0_UART_ReceiveData8(void) +{ + return SS0DAT; +} + +/***************************************************** +*:void SSI0_UART_SendData9(uint16_t Data) +*:UART9λ +*ڲ: +Data:͵ +*ڲ:void +*****************************************************/ +void SSI0_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if(Data_9Bit) + { + SS0CON0 |= 0x08; + } + else + { + SS0CON0 &= 0xf7; + } + + SS0DAT = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t SSI0_UART_ReceiveData9(void) +*:SS0DATеֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t SSI0_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = SS0DAT + ((uint16_t)(SS0CON0 & 0X04) << + 6); + SS0CON0 &= 0XFB; + return Data9; +} + +/***************************************************** +*:void SSI0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:SSI0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void SSI0_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + //жʹ/ر + if(NewState != DISABLE) + { + IE |= 0x10; + } + else + { + IE &= ~0x10; + } + + //жȼ + if(Priority != LOW) + { + IP |= 0x10; + } + else + { + IP &= ~0x10; + } +} + +/***************************************************** +*:FlagStatus SSI0_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG) +*:SSI0־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ȡı־λ +*ڲ: +FlagStatus:SSI־λ״̬ +*****************************************************/ +FlagStatus SSI0_GetFlagStatus(SSI_Flag_TypeDef + SSI_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + if((SSI_FLAG & SS0CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((SSI_FLAG & SS0CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void SSI0_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +*:SSI0־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void SSI0_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +{ + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + SS0CON1 &= (~SSI_FLAG); + } + else + { + SS0CON0 &= (~SSI_FLAG); + } +} +#endif + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ssi1.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ssi1.c new file mode 100644 index 0000000..afb2d84 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_ssi1.c @@ -0,0 +1,392 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ssi1.c +// : +// ģ鹦 : SSI1̼⺯Cļ +// ֲб: +// : 2021/09/06 +// 汾 : V1.0001 +// ˵ : +//************************************************************* + +#include "sc92f_ssi.h" + +#if defined (SC92F742x) || defined (SC92F7490) +/************************************************** +*:void SSI1_DeInit(void) +*:SSI1ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void SSI1_DeInit(void) +{ + OTCON &= 0X3F; + SS1CON0 = 0X00; + SS1CON1 = 0X00; + SS1CON2 = 0X00; + SS1DAT = 0X00; + IE1 &= (~0X01); + IP1 &= (~0X01); +} + +/************************************************** +*:void SSI1_SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase,SPI_TXE_INT_TypeDef SPI_TXE_INT) +*:SPIʼú +*ڲ: +SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +SPI_Mode_TypeDef:Mode:SPIģʽѡ +SPI_ClockPolarity_TypeDef:ClockPolarityLSPIʱӼѡ +SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ +*ڲ:void +**************************************************/ +void SSI1_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT) +{ + OTCON = (OTCON & 0X3F) | 0X40; + SS1CON1 = SS1CON1 & (~0X05) | FirstBit | + SPI_TXE_INT; + SS1CON0 = SS1CON0 & 0X80 | BaudRatePrescaler | + Mode | ClockPolarity | ClockPhase; +} + +/***************************************************** +*:void SSI1_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI1_SPI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SS1CON0 |= 0X80; + } + else + { + SS1CON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI1_SPI_SendData(uint8_t Data) +*:SPI +*ڲ: +uint8_t:Data:S{PI͵8λ +*ڲ:void +*****************************************************/ +void SSI1_SPI_SendData(uint8_t Data) +{ + SS1DAT = Data; +} + +/***************************************************** +*:uint8_t SSI1_SPI_ReceiveData(void) +*:SS1DATеֵ +*ڲ:void +*ڲ: +uint8_t:SPIյ8λ +*****************************************************/ +uint8_t SSI1_SPI_ReceiveData(void) +{ + return SS1DAT; +} + +/************************************************** +*:void SSI1_TWI_Init(uint8_t TWI_Address) +*:TWIʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void SSI1_TWI_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0X3F | 0X80; + SS1CON1 = TWI_Address << 1; +} + +/************************************************** +*:void SSI1_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI1_TWI_AcknowledgeConfig(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SS1CON0 |= 0X08; + } + else + { + SS1CON0 &= 0XF7; + } +} + +/************************************************** +*:void SSI1_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:ͨõַӦʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI1_TWI_GeneralCallCmd(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SS1CON1 |= 0X01; + } + else + { + SS1CON1 &= 0XFE; + } +} + +/***************************************************** +*:void SSI1_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI1_TWI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SS1CON0 |= 0X80; + } + else + { + SS1CON0 &= (~0X80); + } +} + +/************************************************** +*:FlagStatus SSI0_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +*:ȡTWI״̬ +*ڲ: +SSI_TWIState_TypeDef:SSI_TWIState:TWI״̬״̬ +*ڲ:void +**************************************************/ +FlagStatus SSI1_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +{ + if((SS1CON0&0x07) == SSI_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void SSI1_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:TWI͵8λ +*ڲ:void +*****************************************************/ +void SSI1_TWI_SendData(uint8_t Data) +{ + SS1DAT = Data; +} + +/***************************************************** +*:uint8_t SSI1_TWI_ReceiveData(void) +*:SS1DATеֵ +*ڲ:void +*ڲ: +uint8_t:TWIյ8λ +*****************************************************/ +uint8_t SSI1_TWI_ReceiveData(void) +{ + return SS1DAT; +} + +/************************************************** +*:void SSI1_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, UART_Mode_TypeDef Mode, UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +UART_Mode_TypeDef:Mode:UART1ģʽ +UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void SSI1_UART_Init(uint32_t UARTFsys, + uint32_t BaudRate, UART_Mode_TypeDef Mode, + UART_RX_TypeDef RxMode) +{ + OTCON |= 0xC0; + SS1CON0 = SS1CON0 & 0X0F | Mode | RxMode; + SS1CON2 = UARTFsys / BaudRate / 256; + SS1CON1 = UARTFsys / BaudRate % 256; +} + +/***************************************************** +*:void SSI1_UART_SendData8(uint8_t Data) +*:UART8λ +*ڲ: +uint8_t:Data:UART͵8λ +*ڲ:void +*****************************************************/ +void SSI1_UART_SendData8(uint8_t Data) +{ + SS1DAT = Data; +} + +/***************************************************** +*:uint8_t SSI1_UART_ReceiveData8(void) +*:SS0DATеֵ +*ڲ:void +*ڲ: +uint8_t:UARTյ8λ +*****************************************************/ +uint8_t SSI1_UART_ReceiveData8(void) +{ + return SS1DAT; +} + +/***************************************************** +*:void SSI1_UART_SendData9(uint16_t Data) +*:UART9λ +*ڲ: +Data:͵ +*ڲ:void +*****************************************************/ +void SSI1_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if(Data_9Bit) + { + SS1CON0 |= 0x08; + } + else + { + SS1CON0 &= 0xf7; + } + + SS1DAT = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t SSI1_UART_ReceiveData9(void) +*:SS1DATеֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t SSI1_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = SS1DAT + ((uint16_t)(SS1CON0 & 0X04) << + 6); + SS1CON0 &= 0XFB; + return Data9; +} + +/***************************************************** +*:void SSI1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:SSI1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void SSI1_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + //жʹ/ر + if(NewState != DISABLE) + { + IE1 |= 0x01; + } + else + { + IE1 &= 0xFE; + } + + //жȼ + if(Priority != LOW) + { + IP1 |= 0x01; + } + else + { + IP1 &= 0xFE; + } +} + +/***************************************************** +*:FlagStatus SSI1_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG) +*:SSI1־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ȡı־λ +*ڲ: +FlagStatus:SSI־λ״̬ +*****************************************************/ +FlagStatus SSI1_GetFlagStatus(SSI_Flag_TypeDef + SSI_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + if((SSI_FLAG & SS1CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((SSI_FLAG & SS1CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void SSI1_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +*:SSI1־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void SSI1_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +{ + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + SS1CON1 &= (~SSI_FLAG); + } + else + { + SS1CON0 &= (~SSI_FLAG); + } +} +#endif + +/******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer0.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer0.c new file mode 100644 index 0000000..a178d70 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer0.c @@ -0,0 +1,165 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_tiemr0.c +// : ԪӦŶ +// ģ鹦: TIMER0̼⺯Cļ +// : 2022323 +// 汾: V1.10002 +// ˵: +//************************************************************* + +#include "sc92f_timer0.h" + +/************************************************** +*:void TIM0_DeInit(void) +*:TIMER0ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void TIM0_DeInit(void) +{ + TMOD &= 0XF0; + TCON &= 0XCD; + TMCON &= 0XFE; + TH0 = 0X00; + TL0 = 0X00; + ET0 = 0; + IPT0 = 0; +} + +/************************************************** +*:void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef TIM0_PrescalerSelection, TIM0_CountMode_TypeDef TIM0_CountMode) +*:TIMER0ú +*ڲ: +TIM0_PresSel_TypeDef:TIM0_PrescalerSelection:ԤƵѡ +TIM0_CountMode_TypeDef:TIM0_CountMode:/ʱģʽѡ +*ڲ:void +**************************************************/ +void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef + TIM0_PrescalerSelection, + TIM0_CountMode_TypeDef TIM0_CountMode) +{ + if(TIM0_PrescalerSelection == + TIM0_PRESSEL_FSYS_D12) + { + TMCON &= 0XFE; + } + else + if(TIM0_PrescalerSelection == + TIM0_PRESSEL_FSYS_D1) + { + TMCON |= 0X01; + } + + if(TIM0_CountMode == TIM0_MODE_TIMER) + { + TMOD &= 0xFB; + } + else + if(TIM0_CountMode == TIM0_MODE_COUNTER) + { + TMOD |= 0x04; + } +} + +/************************************************** +*:void TIM0_WorkMode0Config(uint16_t TIM0_SetCounter) +*:TIMER0ģʽ0ú +*ڲ: +uint16_t:TIM0_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM0_WorkMode0Config(uint16_t + TIM0_SetCounter) +{ + TMOD &= 0XFC; + TL0 = (uint8_t)TIM0_SetCounter; + TH0 = (TIM0_SetCounter >> 5); +} + +/************************************************** +*:void TIM0_WorkMode1Config(uint16_t TIM0_SetCounter) +*:TIMER0ģʽ1ú +*ڲ: +uint16_t:TIM0_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM0_WorkMode1Config(uint16_t + TIM0_SetCounter) +{ + TMOD &= 0XFC; + TMOD |= 0X01; + TL0 = TIM0_SetCounter % 256; + TH0 = TIM0_SetCounter / 256; +} + +/************************************************** +*:void TIM0_WorkMode2Config(uint8_t TIM0_SetCounter) +*:TIMER0ģʽ2ú +*ڲ: +uint8_t:TIM0_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM0_WorkMode2Config(uint8_t TIM0_SetCounter) +{ + TMOD &= 0XFC; + TMOD |= 0X02; + TL0 = TIM0_SetCounter; + TH0 = TIM0_SetCounter; +} + +/************************************************** +*:void TIM0_WorkModeConfig(TIM0_WorkMode_TypeDef TIM0_WorkMode, uint16_t TIM0_SetCounter1, uint16_t TIM0_SetCounter2) +*:TIMER0ģʽú +*ڲ: +TIM0_WorkMode_TypeDef:TIM0_WorkMode:TIMER0ģʽѡ +uint16_t:TIM0_SetCounter1:TIMER0ֵ1 +uint16_t:TIM0_SetCounter2:TIMER0ֵ2 +*ڲ:void +**************************************************/ +void TIM0_WorkModeConfig(TIM0_WorkMode_TypeDef + TIM0_WorkMode, uint16_t TIM0_SetCounter1, + uint16_t TIM0_SetCounter2) +{ + switch (TIM0_WorkMode) + { + case TIM0_WORK_MODE0: + TIM0_WorkMode0Config(TIM0_SetCounter1); + break; + + case TIM0_WORK_MODE1: + TIM0_WorkMode1Config(TIM0_SetCounter1); + break; + + case TIM0_WORK_MODE2: + TIM0_WorkMode2Config(TIM0_SetCounter1); + break; + + case TIM0_WORK_MODE3: + TIM0_WorkMode3Config(TIM0_SetCounter1, + TIM0_SetCounter2); + break; + default: + break; + } +} + +/************************************************** +*:void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, uint8_t TIM1_SetCounter) +*:TIMER0ģʽ3ú +*ڲ: +uint8_t:TIM0_SetCounter:TIMER0_TL0ֵ +uint8_t:TIM1_SetCounter +TIMER0_TH0ֵ +*ڲ:void +**************************************************/ +void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, + uint8_t TIM1_SetCounter) +{ + TMOD |= 0X03; + TL0 = TIM0_SetCounter; + TH0 = TIM1_SetCounter; +} + + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer1.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer1.c new file mode 100644 index 0000000..cc1974b --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer1.c @@ -0,0 +1,140 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_timer1.c +// : ԪӦŶ +// ģ鹦: TIMER1̼⺯Cļ +// ֲб: +// : 2022323 +// 汾: V1.10001 +// ˵:ļSC92FϵоƬ +//************************************************************* +#include "sc92f_timer1.h" + +/************************************************** +*:void TIM1_DeInit(void) +*:TIMER1ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void TIM1_DeInit(void) +{ + TMOD &= 0X0F; + TCON &= 0X37; + TMCON &= 0XFD; + TH1 = 0X00; + TL1 = 0X00; + ET1 = 0; + IPT1 = 0; +} + +/************************************************** +*:void TIM1_TimeBaseInit(TIM1_PresSel_TypeDef TIM1_PrescalerSelection, TIM1_CountMode_TypeDef TIM1_CountMode) +*:TIMER1ú +*ڲ: +TIM1_PresSel_TypeDef:TIM1_PrescalerSelection:ԤƵѡ +TIM1_CountMode_TypeDef:TIM1_CountMode:/ʱģʽѡ +*ڲ:void +**************************************************/ +void TIM1_TimeBaseInit(TIM1_PresSel_TypeDef TIM1_PrescalerSelection, + TIM1_CountMode_TypeDef TIM1_CountMode) +{ + //жǷҪзƵ + if(TIM1_PrescalerSelection == TIM1_PRESSEL_FSYS_D12) + { + TMCON &= 0xFD; + } + else if(TIM1_PrescalerSelection == TIM1_PRESSEL_FSYS_D1) + { + TMCON |= 0x02; + } + + //TIM1ģʽ + if(TIM1_CountMode == TIM1_MODE_TIMER) + { + TMOD &= 0xBF; + } + else if(TIM1_CountMode == TIM1_MODE_COUNTER) + { + TMOD |= 0x40; + } +} + +/************************************************** +*:void TIM1_WorkMode0Config(uint16_t TIM1_SetCounter) +*:TIMER1ģʽ0ú +*ڲ: +uint16_t:TIM1_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM1_WorkMode0Config(uint16_t + TIM1_SetCounter) +{ + TMOD &= 0XCF; + TL1 = (uint8_t)TIM1_SetCounter; + TH1 = (TIM1_SetCounter >> 5); +} + +/************************************************** +*:void TIM1_WorkMode1Config(uint16_t TIM1_SetCounter) +*:TIMER1ģʽ1ú +*ڲ: +uint16_t:TIM1_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM1_WorkMode1Config(uint16_t + TIM1_SetCounter) +{ + TMOD &= 0XCF; + TMOD |= 0X10; + TL1 = TIM1_SetCounter % 256; + TH1 = TIM1_SetCounter / 256; +} + +/************************************************** +*:void TIM1_WorkMode2Config(uint8_t TIM1_SetCounter) +*:TIMER1ģʽ2ú +*ڲ: +uint8_t:TIM1_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM1_WorkMode2Config(uint8_t TIM1_SetCounter) +{ + TMOD &= 0XCF; + TMOD |= 0X20; + TL1 = TIM1_SetCounter; + TH1 = TIM1_SetCounter; +} + +/************************************************** +*:void TIM1_WorkModeConfig(TIM1_WorkMode_TypeDef TIM1_WorkMode, uint16_t TIM1_SetCounter) +*:TIMER1ģʽú +*ڲ: +TIM1_WorkMode_TypeDef:TIM1_WorkMode:TIMER1ģʽѡ +uint16_t:TIM1_SetCounter:TIMER1ֵ +*ڲ:void +**************************************************/ +void TIM1_WorkModeConfig(TIM1_WorkMode_TypeDef + TIM1_WorkMode, uint16_t TIM1_SetCounter) +{ + switch(TIM1_WorkMode) + { + case TIM1_WORK_MODE0: + TIM1_WorkMode0Config(TIM1_SetCounter); + break; + + case TIM1_WORK_MODE1: + TIM1_WorkMode1Config(TIM1_SetCounter); + break; + + case TIM1_WORK_MODE2: + TIM1_WorkMode2Config(TIM1_SetCounter); + break; + + default: + break; + } +} + + + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer2.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer2.c new file mode 100644 index 0000000..a9ea6a1 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer2.c @@ -0,0 +1,541 @@ +//************************************************************ +// Copyright (c) 深圳市赛元微电子有限公司 +// 文件名称: sc92f_timer2.c +// 作者: 赛元应用团队 +// 模块功能: TIMER2固件库函数C文件 +// 最后更正日期: 2022年3月23日 +// 版本: V1.10004 +// 说明: 该文件仅适用于SC92F系列芯片 +//************************************************************* + +#include "sc92f_timer2.h" + +#if !defined (SC92L853x) && !defined(SC92L753x) + +/************************************************** +*函数名称:void TIM2_DeInit(void) +*函数功能:TIMER2相关寄存器复位至缺省值 +*入口参数:void +*出口参数:void +**************************************************/ +void TIM2_DeInit(void) +{ + T2CON = 0X00; +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) && !defined (SC92F735X) + T2MOD = 0X00; +#endif + TMCON &= 0XFB; + TH2 = 0X00; + TL2 = 0X00; + RCAP2H = 0X00; + RCAP2L = 0X00; + ET2 = 0; + IPT2 = 0; +} + +/************************************************** +*函数名称:void TIM2_TimeBaseInit(TIM2_PresSel_TypeDef TIM2_PrescalerSelection,TIM2_CountMode_TypeDef TIM2_CountMode, TIM2_CountDirection_TypeDef TIM2_CountDirection) +*函数功能:TIMER2基本设置配置函数 +*入口参数: +TIM2_PresSel_TypeDef:TIM2_PrescalerSelection:预分频选择 +TIM2_CountMode_TypeDef:TIM2_CountMode:计数/定时模式选择 +TIM2_CountDirection_TypeDef:TIM2_CountDirection:计数方向选择 +*出口参数:void +**************************************************/ +void TIM2_TimeBaseInit(TIM2_PresSel_TypeDef + TIM2_PrescalerSelection, + TIM2_CountMode_TypeDef TIM2_CountMode, + TIM2_CountDirection_TypeDef TIM2_CountDirection) +{ + if(TIM2_PrescalerSelection == TIM2_PRESSEL_FSYS_D12) + { + TMCON &= 0XFB; + } + else if(TIM2_PrescalerSelection == TIM2_PRESSEL_FSYS_D1) + { + TMCON |= 0X04; + } + + + +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) && !defined (SC92F735X)\ + && !defined (SC92F825X) && !defined (SC92F835X) + + if(TIM2_CountDirection == TIM2_COUNTDIRECTION_UP) + { + T2MOD &= 0XFE; + } + else if(TIM2_CountDirection == + TIM2_COUNTDIRECTION_DOWN_UP) + { + T2MOD |= 0X01; + } + + if(TIM2_CountMode == TIM2_MODE_TIMER) + { + T2CON &= 0XFD; + } + else if(TIM2_CountMode == TIM2_MODE_COUNTER) + { + T2CON |= 0X02; + } + + +#else + TIM2_CountMode = 1; + TIM2_CountDirection = 0; +#endif + +} + + +/************************************************** +*函数名称:void TIM2_WorkMode1Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式1配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode1Config(uint16_t + TIM2_SetCounter) +{ + RCAP2L = TIM2_SetCounter % 256; + RCAP2H = TIM2_SetCounter / 256; + TL2 = RCAP2L; + TH2 = RCAP2H; +} + +/************************************************** +*函数名称:void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef TIM2_WorkMode, uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式配置函数 +*入口参数: +TIM2_WorkMode_TypeDef:TIM2_WorkMode:TIMER2工作模式选择 +uint16_t:TIM2_SetCounter:TIMER2计数初值配置 +*出口参数:void +**************************************************/ +void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef + TIM2_WorkMode, uint16_t TIM2_SetCounter) +{ + switch(TIM2_WorkMode) + { + case TIM2_WORK_MODE1: + TIM2_WorkMode1Config(TIM2_SetCounter); + break; +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) && !defined (SC92F735X) && !defined (SC92F725X) + case TIM2_WORK_MODE0: + TIM2_WorkMode0Config(TIM2_SetCounter); + break; + + case TIM2_WORK_MODE3: + TIM2_WorkMode3Config(TIM2_SetCounter); + break; +#endif + default: + break; + } +} + +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) && !defined (SC92F735X) +/************************************************** +*函数名称:void TIM2_WorkMode0Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式0配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode0Config(uint16_t + TIM2_SetCounter) +{ + T2CON |= 0x09; + TL2 = TIM2_SetCounter % 256; + TH2 = TIM2_SetCounter / 256; +} + +/************************************************** +*函数名称:void TIM2_WorkMode3Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式3配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode3Config(uint16_t + TIM2_SetCounter) +{ + RCAP2L = TIM2_SetCounter % 256; + RCAP2H = TIM2_SetCounter / 256; + T2MOD |= 0X02; +} + +/***************************************************** +*函数名称:void TIM2_SetEXEN2(FunctionalState NewState) +*函数功能:TIMER2_EXEN2配置函数 +*入口参数: +FunctionalState:NewState:EXEN2使能选择 +*出口参数:void +*****************************************************/ +void TIM2_SetEXEN2(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + EXEN2 = 0; + } + else + { + EXEN2 = 1; + } +} +#endif + +/***************************************************** +*函数名称:void TIM2_Cmd(FunctionalState NewState) +*函数功能:TIMER2功能开关函数 +*入口参数: +FunctionalState:NewState:功能启动/关闭选择 +*出口参数:void +*****************************************************/ +void TIM2_Cmd(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + TR2 = 0; + } + else + { + TR2 = 1; + } +} + +/***************************************************** +*函数名称:void TIM2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*函数功能:TIMER2中断初始化 +*入口参数: +FunctionalState:NewState:中断使能/关闭选择 +PriorityStatus:Priority:中断优先级选择 +*出口参数:void +*****************************************************/ +void TIM2_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState == DISABLE) + { + ET2 = 0; + } + else + { + ET2 = 1; + } + + /************************************************************/ + if(Priority == LOW) + { + IPT2 = 0; + } + else + { + IPT2 = 1; + } +} + +/***************************************************** +*函数名称:FlagStatus TIM2_GetFlagStatus(void) +*函数功能:获得TIMER2中断标志状态 +*入口参数:void +*出口参数: +FlagStatus:TIMER2中断标志状态 +*****************************************************/ +FlagStatus TIM2_GetFlagStatus(TIM2_Flag_TypeDef + TIM2_Flag) +{ + FlagStatus status = RESET; + + if((TIM2_Flag & T2CON) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/***************************************************** +*函数名称:void TIM2_ClearFlag(void) +*函数功能:清除TIMER2中断标志状态 +*入口参数:void +*出口参数:void +*****************************************************/ +void TIM2_ClearFlag(TIM2_Flag_TypeDef TIM2_Flag) +{ + T2CON &= (~TIM2_Flag); +} + +#else + +/************************************************** +*函数名称:void TIM2_DeInit(void) +*函数功能:TIMER2相关寄存器复位至初始值 +*入口参数:void +*出口参数:void +**************************************************/ +void TIM2_DeInit() +{ + TXINX = 0x02; //TIMER2选择 + TXCON = 0X00; + TXMOD = 0X00; + RCAPXH = 0X00; + RCAPXL = 0X00; + THX = 0X00; + TLX = 0X00; + IE1 &= 0X3F; + IP1 &= 0X3F; + ET2 = 0; + IPT2 = 0; +} + +/************************************************** +*函数名称:void TIM2_PrescalerSelection(TIM2_PresSel_TypeDef TIM2_PrescalerSelection) +*函数功能:TIMER2 预分频选择 +*入口参数: +TIM2_PresSel_TypeDef:TIM2_PrescalerSelection:预分频选择 +*出口参数:void +**************************************************/ +void TIM2_PrescalerSelection(TIM2_PresSel_TypeDef TIM2_PrescalerSelection) +{ + TXINX = 0x02; + + if (TIM2_PrescalerSelection == TIM2_PRESSEL_FSYS_D12) + { + TXMOD &= 0X7F; + } + else if (TIM2_PrescalerSelection == TIM2_PRESSEL_FSYS_D1) + { + TXMOD |= 0X80; + } +} + +/************************************************** +*函数名称:void TIM2_TimeBaseInit(TIM2_CountMode_TypeDef TIM2_CountMode, TIM2_CountDirection_TypeDef TIM2_CountDirection) +*函数功能:TIM2基本设置配置函数 +*入口参数: +TIM2_CountMode_TypeDef:TIM2_CountMode:计数/定时模式选择 +TIM2_CountDirection_TypeDef:TIM2_CountDirection:计数方向选择 +*出口参数:void +**************************************************/ +void TIM2_TimeBaseInit(TIM2_PresSel_TypeDef TIM2_PrescalerSelection, + TIM2_CountMode_TypeDef TIM2_CountMode, + TIM2_CountDirection_TypeDef TIM2_CountDirection) +{ + TXINX = 0x02; + + TXMOD &= 0X7F; + TXMOD = TIM2_PrescalerSelection<<7; + + if (TIM2_CountMode == TIM2_MODE_TIMER) + { + TXCON &= 0XFD; + } + else if (TIM2_CountMode == TIM2_MODE_COUNTER) + { + TXCON |= 0X02; + } + + if (TIM2_CountDirection == TIM2_COUNTDIRECTION_UP) + { + TXMOD &= 0XFE; + } + else if (TIM2_CountDirection == TIM2_COUNTDIRECTION_DOWN_UP) + { + TXMOD |= 0X01; + } +} + +/************************************************** +*函数名称:void TIM2_WorkMode0Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式0配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode0Config(uint16_t TIM2_SetCounter) +{ + TXINX = 0x02; + CP = 1; + TLX = TIM2_SetCounter % 256; + THX = TIM2_SetCounter / 256; +} + +/************************************************** +*函数名称:void TIM2_WorkMode1Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式1配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode1Config(uint16_t TIM2_SetCounter) +{ + TXINX = 0x02; + RCAPXL = TIM2_SetCounter % 256; + RCAPXH = TIM2_SetCounter / 256; + + TLX = RCAPXL; + THX = RCAPXH; +} + +/************************************************** +*函数名称:void TIM2_WorkMode3Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式3配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode3Config(uint16_t TIM2_SetCounter) +{ + TXINX = 0x02; + RCAPXL = TIM2_SetCounter % 256; + RCAPXH = TIM2_SetCounter / 256; + TXMOD |= 0X02; +} +/************************************************** +*函数名称:void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef TIM2_WorkMode, uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式配置函数 +*入口参数: +TIM2_WorkMode_TypeDef:TIM2_WorkMode:TIMER2工作模式选择 +uint16_t:TIM2_SetCounter:TIMER2计数初值配置 +*出口参数:void +**************************************************/ +void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef TIM2_WorkMode, uint16_t TIM2_SetCounter) +{ + switch (TIM2_WorkMode) + { + case TIM2_WORK_MODE0: + TIM2_WorkMode0Config(TIM2_SetCounter); + break; + + case TIM2_WORK_MODE1: + TIM2_WorkMode1Config(TIM2_SetCounter); + break; + + case TIM2_WORK_MODE3: + TIM2_WorkMode3Config(TIM2_SetCounter); + break; + + default: + break; + } +} +/***************************************************** +*函数名称:void TIM2_SetEXEN2(FunctionalState NewState) +*函数功能:TIMER2_EXEN2配置函数 +*入口参数: +FunctionalState:NewState:EXEN2使能选择 +*出口参数:void +*****************************************************/ +void TIM2_SetEXEN2(FunctionalState NewState) +{ + TXINX = 0x02; + + if (NewState == DISABLE) + { + EXENX = 0; + } + else + { + EXENX = 1; + } +} + +/***************************************************** +*函数名称:void TIM2_Cmd(FunctionalState NewState) +*函数功能:TIMER2功能开关函数 +*入口参数: +FunctionalState:NewState:功能启动/关闭选择 +*出口参数:void +*****************************************************/ +void TIM2_Cmd(FunctionalState NewState) +{ + TXINX = 0x02; + + if (NewState == DISABLE) + { + TRX = 0; + } + else + { + TRX = 1; + } +} + +/***************************************************** +*函数名称:void TIM2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*函数功能:TIMER2 +*入口参数: +FunctionalState:NewState:中断使能/关闭选择 +PriorityStatus:Priority:中断优先级选择 +*出口参数:void +*****************************************************/ +void TIM2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + TXINX = 0x02; + + if (NewState == DISABLE) + { + ET2 = 0; + } + else + { + ET2 = 1; + } + + if (Priority == LOW) + { + IPT2 = 0; + } + else + { + IPT2 = 1; + } +} + +/***************************************************** +*函数名称:FlagStatus TIM2_GetFlagStatus(void) +*函数功能:获得TIMER2中断标志状态 +*入口参数: +TIM2_Flag_TypeDef:TIM2_Flag:TIMER2标志选择 +*出口参数: +FlagStatus:TIMER2中断标志状态 +*****************************************************/ +FlagStatus TIM2_GetFlagStatus(TIM2_Flag_TypeDef TIM2_Flag) +{ + FlagStatus status = RESET; + TXINX = 0x02; + + if ((TIM2_Flag & TXCON) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/***************************************************** +*函数名称:void TIMX_ClearFlag(void) +*函数功能:清除TIMER2中断标志状态 +*入口参数: +TIM2_Flag_TypeDef:TIM2_Flag:TIMER2标志选择 +*出口参数:void +*****************************************************/ +void TIM2_ClearFlag(TIM2_Flag_TypeDef TIM2_Flag) +{ + TXINX = 0x02; + TXCON &= (~TIM2_Flag); +} + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer3.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer3.c new file mode 100644 index 0000000..4adab11 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer3.c @@ -0,0 +1,280 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timerx.c +// : +// ģ鹦 : TIMER3̼⺯Cļ +// : 2022/01/14 +// 汾 : V1.1000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_timer3.h" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void TIMX_DeInit(void) +*:TIMER3ؼĴλʼֵ +*ڲ:void +*ڲ:void +**************************************************/ +void TIM3_DeInit() +{ + TXINX = 0x03; //TIMER3 ѡ + TXCON = 0X00; + TXMOD = 0X00; + RCAPXH = 0X00; + RCAPXL = 0X00; + THX = 0X00; + TLX = 0X00; + IE1 &= 0X3F; + IP1 &= 0X3F; + ET2 = 0; + IPT2 = 0; +} + +/************************************************** +*:void TIM3_PrescalerSelection(TIMX_TimerSelect_TypeDef TIMX_TimerSelect, TIMX_PresSel_TypeDef TIMX_PrescalerSelection) +*:TIMER3 ԤƵѡ +*ڲ: +TIM3_PresSel_TypeDef:TIM3_PrescalerSelection:ԤƵѡ +*ڲ:void +**************************************************/ +void TIM3_PrescalerSelection(TIM3_PresSel_TypeDef TIM3_PrescalerSelection) +{ + TXINX = 0x03; + + if(TIM3_PrescalerSelection == TIM3_PRESSEL_FSYS_D12) + { + TXMOD &= 0X7F; + } + else + if(TIM3_PrescalerSelection == TIM3_PRESSEL_FSYS_D1) + { + TXMOD |= 0X80; + } +} + +/************************************************** +*:void TIM3_WorkMode1Config(uint16_t TIM3_SetCounter) +*:TIMER3ģʽ1ú +*ڲ: +uint16_t TIM3_SetCounter üֵ +*ڲ:void +**************************************************/ +void TIM3_WorkMode1Config(uint16_t TIM3_SetCounter) +{ + TXINX = 0x03; + RCAPXL = TIM3_SetCounter % 256; + RCAPXH = TIM3_SetCounter / 256; + + TLX = RCAPXL; + THX = RCAPXH; +} + +/***************************************************** +*:void TIM3_Cmd(FunctionalState NewState) +*:TIMER3ܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void TIM3_Cmd(FunctionalState NewState) +{ + TXINX = 0x03; + + if (NewState == DISABLE) + { + TRX = 0; + } + else + { + TRX = 1; + } +} + +/***************************************************** +*:void TIM3_ITConfig(TIM3_TimerSelect_TypeDef TIM3_TimerSelect, FunctionalState NewState, PriorityStatus Priority) +*:TIMER3жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void TIM3_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + TXINX = 0x03; + + if(NewState == DISABLE) + { + IE1 &= 0XBF; + } + else + { + IE1 |= 0X40; + } + + if(Priority == LOW) + { + IP1 &= 0XBF; + } + else + { + IP1 |= 0X40; + } +} + +/***************************************************** +*:FlagStatus TIM3_GetFlagStatus(void) +*:TIMER3жϱ־״̬ +*ڲ: +TIM3_Flag_TypeDef:TIM3_Flag:TIMER3־ѡ +*ڲ: +FlagStatus:TIMER3жϱ־״̬ +*****************************************************/ +FlagStatus TIM3_GetFlagStatus(TIM3_Flag_TypeDef TIM3_Flag) +{ + FlagStatus status = RESET; + TXINX = 0x03; + + if((TIM3_Flag & TXCON) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/***************************************************** +*:void TIM3_ClearFlag(TIM3_Flag_TypeDef TIM3_Flag) +*:TIMER3жϱ־״̬ +*ڲ: +TIM3_Flag_TypeDef:TIM3_Flag:TIMER3־ѡ +*ڲ:void +*****************************************************/ +void TIM3_ClearFlag(TIM3_Flag_TypeDef TIM3_Flag) +{ + TXINX = 0x03; + TXCON &= (~TIM3_Flag); +} + + +/************************************************** +*:void TIM3_TimeBaseInit(TIM3_CountMode_TypeDef TIM3_CountMode, TIM3_CountDirection_TypeDef TIM3_CountDirection) +*:TIM3ú +*ڲ: +TIM3_CountMode_TypeDef:TIM3_CountMode:/ʱģʽѡ +TIM3_CountDirection_TypeDef:TIM3_CountDirection:ѡ +*ڲ:void +**************************************************/ +void TIM3_TimeBaseInit(TIM3_CountMode_TypeDef TIM3_CountMode, + TIM3_CountDirection_TypeDef TIM3_CountDirection) +{ + TXINX = 0x03; + + if(TIM3_CountMode == TIM3_MODE_TIMER) + { + TXCON &= 0XFD; + } + else + if(TIM3_CountMode == TIM3_MODE_COUNTER) + { + TXCON |= 0X02; + } + + /************************************************************/ + if(TIM3_CountDirection == TIM3_COUNTDIRECTION_UP) + { + TXMOD &= 0XFE; + } + else + if(TIM3_CountDirection == TIM3_COUNTDIRECTION_DOWN_UP) + { + TXMOD |= 0X01; + } +} + +/************************************************** +*:void TIM3_WorkMode0Config(uint16_t TIM3_SetCounter) +*:TIMER3ģʽ0ú +*ڲ: +uint16_t:TIM3_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM3_WorkMode0Config(uint16_t TIM3_SetCounter) +{ + TXINX = 0x03; + CP = 1; + TLX = TIM3_SetCounter % 256; + THX = TIM3_SetCounter / 256; +} +/************************************************** +*:void TIM3_WorkMode3Config(uint16_t TIM3_SetCounter) +*:TIMER3ģʽ3ú +*ڲ: +uint16_t:TIM3_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM3_WorkMode3Config(uint16_t TIM3_SetCounter) +{ + TXINX = 0x03; + RCAPXL = TIM3_SetCounter % 256; + RCAPXH = TIM3_SetCounter / 256; + TXMOD |= 0X02; +} +/************************************************** +*:void TIM3_WorkModeConfig(TIM3_WorkMode_TypeDef TIM3_WorkMode, uint16_t TIM3_SetCounter) +*:TIMER3ģʽú +*ڲ: +TIM3_WorkMode_TypeDef:TIM3_WorkMode:TIMER3ģʽѡ +uint16_t:TIM3_SetCounter:TIMER3ֵ +*ڲ:void +**************************************************/ +void TIM3_WorkModeConfig(TIM3_WorkMode_TypeDef TIM3_WorkMode, uint16_t TIM3_SetCounter) +{ + switch (TIM3_WorkMode) + { + case TIM3_WORK_MODE0: + TIM3_WorkMode0Config(TIM3_SetCounter); + break; + + case TIM3_WORK_MODE1: + TIM3_WorkMode1Config(TIM3_SetCounter); + break; + + case TIM3_WORK_MODE3: + TIM3_WorkMode3Config(TIM3_SetCounter); + break; + + default: + break; + } +} +/***************************************************** +*:void TIM3_SetEXEN3(FunctionalState NewState) +*:TIMER3_EXEN3ú +*ڲ: +FunctionalState:NewState:EXEN3ʹѡ +*ڲ:void +*****************************************************/ +void TIM3_SetEXEN3(FunctionalState NewState) +{ + TXINX = 0x03; + + if (NewState == DISABLE) + { + EXENX = 0; + } + else + { + EXENX = 1; + } +} + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer4.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer4.c new file mode 100644 index 0000000..6c649b7 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_timer4.c @@ -0,0 +1,278 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timer4.c +// : +// ģ鹦 : TIMER4̼⺯Cļ +// : 2022/01/18 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_timer4.h" + + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void TIM4_DeInit(void) +*:TIMER4ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void TIM4_DeInit() +{ + TXINX = 0x04; //TIMER4 ѡ + TXCON = 0X00; + TXMOD = 0X00; + RCAPXH = 0X00; + RCAPXL = 0X00; + THX = 0X00; + TLX = 0X00; + IE1 &= 0X3F; + IP1 &= 0X3F; + ET2 = 0; + IPT2 = 0; +} + +/************************************************** +*:void TIM4_PrescalerSelection(TIM4_PresSel_TypeDef TIM4_PrescalerSelection) +*:TIMER4 ԤƵѡ +*ڲ: +TIM4_PresSel_TypeDef:TIM4_PrescalerSelection:ԤƵѡ +*ڲ:void +**************************************************/ +void TIM4_PrescalerSelection(TIM4_PresSel_TypeDef TIM4_PrescalerSelection) +{ + TXINX = 0x04; + + if (TIM4_PrescalerSelection == TIM4_PRESSEL_FSYS_D12) + { + TXMOD &= 0X7F; + } + else if (TIM4_PrescalerSelection == TIM4_PRESSEL_FSYS_D1) + { + TXMOD |= 0X80; + } +} + +/************************************************** +*:void TIM4_WorkMode1Config(uint16_t TIM4_SetCounter) +*:TIMER4ģʽ1ú +*ڲ: +uint16_t:TIM4_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM4_WorkMode1Config(uint16_t TIM4_SetCounter) +{ + TXINX = 0x04; + RCAPXL = TIM4_SetCounter % 256; + RCAPXH = TIM4_SetCounter / 256; + + TLX = RCAPXL; + THX = RCAPXH; +} + +/***************************************************** +*:void TIM4_Cmd(FunctionalState NewState) +*:TIMER4ܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void TIM4_Cmd(FunctionalState NewState) +{ + TXINX = 0x04; + + if (NewState == DISABLE) + { + TRX = 0; + } + else + { + TRX = 1; + } +} + +/***************************************************** +*:void TIMX_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:TIMER4жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void TIM4_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + TXINX = 0x04; + + if (NewState == DISABLE) + { + IE1 &= 0X7F; + } + else + { + IE1 |= 0X80; + } + + if (Priority == LOW) + { + IP1 &= 0X7F; + } + else + { + IP1 |= 0X80; + } +} + +/***************************************************** +*:FlagStatus TIM4_GetFlagStatus(TIM4_Flag_TypeDef TIM4_Flag) +*:TIMER4жϱ־״̬ +*ڲ: +TIM4_Flag_TypeDef:TIM4_Flag:TIMER4־ѡ +*ڲ: +FlagStatus:TIMER4жϱ־״̬ +*****************************************************/ +FlagStatus TIM4_GetFlagStatus(TIM4_Flag_TypeDef TIM4_Flag) +{ + FlagStatus status = RESET; + TXINX = 0x04; + + if ((TIM4_Flag & TXCON) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/***************************************************** +*:void TIM4_ClearFlag(TIM4_Flag_TypeDef TIM4_Flag) +*:TIMER4жϱ־״̬ +*ڲ: +TIM4_Flag_TypeDef:TIM4_Flag:TIMER4־ѡ +*ڲ:void +*****************************************************/ +void TIM4_ClearFlag(TIM4_Flag_TypeDef TIM4_Flag) +{ + TXINX = 0x04; + TXCON &= (~TIM4_Flag); +} + +/************************************************** +*:void TIM4_TimeBaseInit(TIM4_CountMode_TypeDef TIM4_CountMode, TIM4_CountDirection_TypeDef TIM4_CountDirection) +*:TIM4ú +*ڲ: +TIM4_CountMode_TypeDef:TIM4_CountMode:/ʱģʽѡ +TIM4_CountDirection_TypeDef:TIM4_CountDirection:ѡ +*ڲ:void +**************************************************/ +void TIM4_TimeBaseInit(TIM4_CountMode_TypeDef TIM4_CountMode, + TIM4_CountDirection_TypeDef TIM4_CountDirection) +{ + TXINX = 0x04; + + if (TIM4_CountMode == TIM4_MODE_TIMER) + { + TXCON &= 0XFD; + } + else if (TIM4_CountMode == TIM4_MODE_COUNTER) + { + TXCON |= 0X02; + } + + /************************************************************/ + if (TIM4_CountDirection == TIM4_COUNTDIRECTION_UP) + { + TXMOD &= 0XFE; + } + else if (TIM4_CountDirection == TIM4_COUNTDIRECTION_DOWN_UP) + { + TXMOD |= 0X01; + } +} + +/************************************************** +*:void TIM4_WorkMode0Config(uint16_t TIM4_SetCounter) +*:TIMER4ģʽ0ú +*ڲ: +uint16_t:TIM4_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM4_WorkMode0Config(uint16_t TIM4_SetCounter) +{ + TXINX = 0x04; + CP = 1; + TLX = TIM4_SetCounter % 256; + THX = TIM4_SetCounter / 256; +} + +/************************************************** +*:void TIM4_WorkMode3Config(uint16_t TIM4_SetCounter) +*:TIMER2ģʽ3ú +*ڲ: +uint16_t:TIM2_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM4_WorkMode3Config(uint16_t TIM4_SetCounter) +{ + TXINX = 0x04; + RCAPXL = TIM4_SetCounter % 256; + RCAPXH = TIM4_SetCounter / 256; + TXMOD |= 0X02; +} + +/************************************************** +*:void TIM4_WorkModeConfig(TIM4_WorkMode_TypeDef TIM4_WorkMode, uint16_t TIM4_SetCounter) +*:TIMER4ģʽú +*ڲ: +TIM4_WorkMode_TypeDef:TIM4_WorkMode:TIMER2ģʽѡ +uint16_t:TIM4_SetCounter:TIMER2ֵ +*ڲ:void +**************************************************/ +void TIM4_WorkModeConfig(TIM4_WorkMode_TypeDef TIM4_WorkMode, uint16_t TIM4_SetCounter) +{ + switch (TIM4_WorkMode) + { + case TIM4_WORK_MODE0: + TIM4_WorkMode0Config(TIM4_SetCounter); + break; + + case TIM4_WORK_MODE1: + TIM4_WorkMode1Config(TIM4_SetCounter); + break; + + case TIM4_WORK_MODE3: + TIM4_WorkMode3Config(TIM4_SetCounter); + break; + + default: + break; + } +} + +/***************************************************** +*:void TIM4_SetEXEN4(FunctionalState NewState) +*:TIMER4_EXEN4ú +*ڲ: +FunctionalState:NewState:EXEN4ʹѡ +*ڲ:void +*****************************************************/ +void TIM4_SetEXEN4(FunctionalState NewState) +{ + TXINX = 0x04; + + if (NewState == DISABLE) + { + EXENX = 0; + } + else + { + EXENX = 1; + } +} + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_uart0.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_uart0.c new file mode 100644 index 0000000..b26511f --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_uart0.c @@ -0,0 +1,388 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_uart0.c +// : +// ģ鹦 : UART0̼⺯Cļ +// ֲб: +// : 2022/01/01 +// 汾 : V1.10005 +// ˵ :ļԪ92F/93F/92LϵеƬ +//************************************************************* + +#include "sc92f_uart0.h" + +#if !defined (SC92F742x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F7490) + +/************************************************** +*:void UART0_DeInit(void) +*:UART0ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void UART0_DeInit(void) +{ +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) + OTCON &= 0XEF; +#endif + SCON = 0X00; + PCON &= 0X7F; + IE &= 0XEF; + IP &= 0XEF; +} + +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +/************************************************** +*:UART0_PinSelection(UART0_PinSelection_TypeDef PinSeletion) +*:UART0ѡ +*ڲ: +UART0_PinSelection_TypeDef:PinSeletion:ѡUART0ΪP15P16P11P20 +*ڲ:void +**************************************************/ +void UART0_PinSelection(UART0_PinSelection_TypeDef + PinSeletion) +{ + OTCON = OTCON & 0XDF | PinSeletion; +} +#endif + +/************************************************** +*:void UART0_Init(uint32_t Uart0Fsys, uint32_t BaudRate, UART0_Mode_Typedef Mode,UART0_Clock_Typedef ClockMode, UART0_RX_Typedef RxMode) +*:UART0ʼú +*ڲ: +uint32_t:Uart0Fsys:ϵͳʱƵ +uint32_t:BaudRate: +UART0_Mode_Typedef:Mode:UART0ģʽ +UART0_Clock_Typedef:ClockMode:ʱԴTIMER1/TIMER2 +UART0_RX_Typedef:RxMode:ѡ +*ڲ:void +**************************************************/ +void UART0_Init(uint32_t Uart0Fsys, uint32_t BaudRate, + UART0_Mode_Typedef Mode, UART0_Clock_Typedef ClockMode, + UART0_RX_Typedef RxMode) +{ +#if defined (SC92F725X) || defined (SC92F735X) || defined (SC92F730x ) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) + { + SCON = SCON & 0X2F | Mode | RxMode; //UARTģʽ,ýλ + + if(Mode == UART0_Mode_8B || + Mode == UART0_Mode_11B_BaudRateFix) + { + if(BaudRate == UART0_BaudRate_FsysDIV12 || + BaudRate == UART0_BaudRate_FsysDIV64) + { + PCON &= 0X7F; + } + else if(BaudRate == UART0_BaudRate_FsysDIV4 || + BaudRate == UART0_BaudRate_FsysDIV32) + { + PCON |= 0X80; + } + } + else + { + T2CON = (T2CON & 0xCF) | (ClockMode & + 0X30); //òʱԴ + + if((ClockMode & 0X70) == 0X00) + { + TMOD |= 0X20; + if(ClockMode & 0x80) + { + PCON |= 0X80; + Uart0Fsys = Uart0Fsys * 2; + } + else + { + PCON &= 0X7F; + } + + if(ClockMode & 0x0F) + { + TMCON |= 0x02; + } + else + { + TMCON &= 0xFD; + Uart0Fsys = Uart0Fsys / 12; + } + + TH1 = 256 - (Uart0Fsys / 32 / BaudRate); + TL1 = TH1; + TR1 = 1; + } + else if((ClockMode & 0X70) == 0X30) + { + if(ClockMode & 0x0F) + { + TMCON |= 0x04; + } + else + { + TMCON &= 0xFB; + Uart0Fsys = Uart0Fsys / 12; + } + + RCAP2H = (65536 - Uart0Fsys / 32 / BaudRate) / + 256; + RCAP2L = (65536 - Uart0Fsys / 32 / BaudRate) % + 256; + TR2 = 1; + } + } + } +#elif defined (SC92F848x) || defined (SC92F748x) || defined (SC92F859x) || defined (SC92F759x) + { + SCON = (SCON & 0X2F) | Mode | RxMode; //UARTģʽ,ýλ + + if(Mode == UART0_Mode_8B) + { + if(BaudRate == UART0_BaudRate_FsysDIV12) + { + PCON &= 0X7F; + } + else if(BaudRate == UART0_BaudRate_FsysDIV4) + { + PCON |= 0X80; + } + } + else + { + T2CON = (T2CON & 0xCF) | + (ClockMode & 0x30); //òʱԴ + + if(ClockMode & 0x80) + { + PCON |= 0x80; + Uart0Fsys = Uart0Fsys / 16; + } + else + { + PCON &= 0x7F; + } + + if((ClockMode & 0x7F) == UART0_CLOCK_TIMER1) + { + TH1 = (Uart0Fsys / BaudRate) / 256; + TL1 = (Uart0Fsys / BaudRate) % 256; + TR1 = 0; + } + else if((ClockMode & 0x7F) == UART0_CLOCK_TIMER2) + { + RCAP2H = (Uart0Fsys / BaudRate) / 256; + RCAP2L = (Uart0Fsys / BaudRate) % 256; + TR2 = 1; + } + } + } +#elif defined (SC92L853x) || defined (SC92L753x) + { + SCON = (SCON & 0X2F) | Mode | RxMode; //UARTģʽ,ýλ + + /* UART0ѡΪ8λ˫ͬͨģʽж˿ϵͳʱӵ12Ƶ4Ƶ*/ + if(Mode == UART0_Mode_8B) + { + if(BaudRate == UART0_BaudRate_FsysDIV12) + { + PCON &= 0X7F; + } + else if(BaudRate == UART0_BaudRate_FsysDIV4) + { + PCON |= 0X80; + } + } + /* UART0ѡģʽ1/3Ϊɱ */ + else + { + TXCON = (TXCON & 0xCF) | ClockMode; //òʱԴ + + /* ģʽ1/3ϵͳʱӵ1Ƶ16Ƶ */ + if(ClockMode & 0x80) + { + PCON |= 0x80; + Uart0Fsys = Uart0Fsys / 16; + } + else + { + PCON &= 0x7F; + } + + /* UART0ʱԴ */ + if((ClockMode & 0x7F) == UART0_CLOCK_TIMER1)//UART0ʱԴΪTIMER1 + { + TH1 = (Uart0Fsys / BaudRate) / 256; + TL1 = (Uart0Fsys / BaudRate) % 256; + TR1 = 0; + } + else if((ClockMode & 0x7F) == UART0_CLOCK_TIMER2)//UART0ʱԴΪTIMER2 + { + RCAPXH = (Uart0Fsys / BaudRate) / 256; + RCAPXL = (Uart0Fsys / BaudRate) % 256; + TRX = 1; + } + } + } + +#else + { + SCON = (SCON & 0X2F) | Mode | + RxMode; //UARTģʽ,ýλ + + if(Mode == UART0_Mode_8B) + { + if(BaudRate == UART0_BaudRate_FsysDIV12) + { + PCON &= 0X7F; + } + else if(BaudRate == UART0_BaudRate_FsysDIV4) + { + PCON |= 0X80; + } + } + else + { + T2CON = (T2CON & 0xCF) | + (ClockMode & 0x30); //òʱԴ + + if(ClockMode == UART0_CLOCK_TIMER1) + { + TH1 = (Uart0Fsys / BaudRate) / 256; + TL1 = (Uart0Fsys / BaudRate) % 256; + TR1 = 0; + } + else if(ClockMode == UART0_CLOCK_TIMER2) + { + RCAP2H = (Uart0Fsys / BaudRate) / 256; + RCAP2L = (Uart0Fsys / BaudRate) % 256; +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) + TR2 = 1; +#endif + } + } + } +#endif +} + +/***************************************************** +*:void UART0_SendData8(uint8_t Data) +*:UART08λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void UART0_SendData8(uint8_t Data) +{ + SBUF = Data; +} + +/************************************************** +*:uint8_t UART0_ReceiveData8(void) +*:SBUFеֵ +*ڲ:void +*ڲ: +uint8_t:UARTյ8λ +**************************************************/ +uint8_t UART0_ReceiveData8(void) +{ + return SBUF; +} + +/***************************************************** +*:void UART0_SendData9(uint16_t Data) +*:UART09λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void UART0_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if(Data_9Bit) + { + SCON |= 0X08; + } + else + { + SCON &= 0XF7; + } + + SBUF = (uint8_t)Data; +} + +/************************************************** +*:uint16_t UART0_ReceiveData9(void) +*:SBUFеֵھλֵ +*ڲ:void +*ڲ: +uint16_t:UARTյ +**************************************************/ +uint16_t UART0_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = SBUF + ((uint16_t)(SCON & 0X04) << 6); + SCON &= 0XFB; + return Data9; +} + +/***************************************************** +*:void UART0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:UART0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void UART0_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState == DISABLE) + { + EUART = 0; + } + else + { + EUART = 1; + } + + //жȼ + if(Priority == LOW) + { + IPUART = 0; + } + else + { + IPUART = 1; + } +} + +/***************************************************** +*:FlagStatus UART0_GetFlagStatus(UART0_Flag_Typedef UART0_Flag) +*:UART0жϱ־״̬ +*ڲ: +UART0_GetFlagStatus:UART0_Flag:жϱ־λѡ +*ڲ: +FlagStatus:UART0жϱ־λ״̬ +*****************************************************/ +//FlagStatus UART0_GetFlagStatus(UART0_Flag_Typedef +// UART0_Flag) +//{ +// return (bool)(SCON & UART0_Flag); +//} + +/***************************************************** +*:void UART0_ClearFlag(UART0_Flag_Typedef UART0_Flag) +*:UART0жϱ־״̬ +*ڲ: +UART0_Flag_Typedef;UART0_Flag:жϱ־λѡ +*ڲ:void +*****************************************************/ +//void UART0_ClearFlag(UART0_Flag_Typedef +// UART0_Flag) +//{ +// SCON &= (~UART0_Flag); +//} + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_usci0.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_usci0.c new file mode 100644 index 0000000..16a302a --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_usci0.c @@ -0,0 +1,529 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_usci0.c +// : +// ģ鹦 : USCI0̼⺯Cļ +// : 2022/01/05 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_usci0.h" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void USCI0_DeInit(void) +*:USCI0ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI0_DeInit(void) +{ + OTCON &= 0XCF; + US0CON0 = 0X00; + US0CON1 = 0X00; + US0CON2 = 0X00; + US0CON3 = 0X00; + IE1 &= (~0X01); + IP1 &= (~0X01); +} + +/************************************************** +*:void USCI0_SPI_Init(USCI0_SPI_FirstBit_TypeDef FirstBit, USCI0_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,USCI0_SPI_Mode_TypeDef Mode, + USCI0_SPI_ClockPolarity_TypeDef ClockPolarity, USCI0_SPI_ClockPhase_TypeDef ClockPhase,USCI0_SPI_TXE_INT_TypeDef SPI_TXE_INT,USCI0_TransmissionMode_TypeDef TransmissionMode) +*:SPIʼú +*ڲ: +USCI0_SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +USCI0_SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +USCI0_SPI_Mode_TypeDef:Mode:SPIģʽѡ +USCI0_SPI_ClockPolarity_TypeDef:ClockPolarity:SPIʱӼѡ +USCI0_SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +USCI0_SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ,ùSC92FXX1XоƬЧ +USCI0_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16λ +*ڲ:void +**************************************************/ +void USCI0_SPI_Init(USCI0_SPI_FirstBit_TypeDef FirstBit, + USCI0_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI0_SPI_Mode_TypeDef Mode, + USCI0_SPI_ClockPolarity_TypeDef ClockPolarity, USCI0_SPI_ClockPhase_TypeDef ClockPhase, + USCI0_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI0_TransmissionMode_TypeDef TransmissionMode) +{ + + OTCON = (OTCON & 0XCF) | 0X10; +#if defined(SC92L853x) || defined(SC92L753x) + SPI_TXE_INT = USCI0_SPI_TXE_DISINT; //SPI_TXE_INTùڸоƬЧ + US0CON1 = US0CON1 & (~0X05) | FirstBit | TransmissionMode; +#endif + US0CON0 = US0CON0 & 0X80 | BaudRatePrescaler | Mode | ClockPolarity | ClockPhase; +} + +/************************************************** +*:void USCI0_TransmissionMode(USCI0_TransmissionMode_TypeDef TransmissionMode) +*:SPI ģʽú +*ڲ: +USCI0_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16eλ +*ڲ:void +**************************************************/ +void USCI0_TransmissionMode(USCI0_TransmissionMode_TypeDef TransmissionMode) +{ + if (TransmissionMode == USCI0_SPI_DATA8) + { + US0CON1 &= 0xFD; + } + else + { + US0CON1 |= 0x02; + } +} + +/***************************************************** +*:void USCI0_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI0_SPI_Cmd(FunctionalState NewState) +{ + OTCON = (OTCON & 0XCF) | 0X10; + + if (NewState != DISABLE) + { + US0CON0 |= 0X80; + } + else + { + US0CON0 &= (~0X80); + } +} +/***************************************************** +*:void USCI0_SPI_SendData_8(uint8_t Data) +*:USCI0 SPI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_SPI_SendData_8(uint8_t Data) +{ + US0CON2 = Data; +} + +/***************************************************** +*:uint8_t USCI0_SPI_ReceiveData_8(void) +*:US0CON2еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI0_SPI_ReceiveData_8(void) +{ + return US0CON2; +} + +/***************************************************** +*:void USCI0_SPI_SendData_16(uint16_t Data) +*:US0CON2 SPI +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_SPI_SendData_16(uint16_t Data) +{ + US0CON3 = (uint8_t)(Data >> 8); + US0CON2 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI0_SPI_ReceiveData_16(void) +*:US0CON2еֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI0_SPI_ReceiveData_16(void) +{ + uint16_t SPI_data; + SPI_data = (uint16_t)((US0CON3 << 8) | US0CON2); + return SPI_data; +} + +/************************************************** +*:void USCI0_TWI_Slave_Init(uint8_t TWI_Address) +*:USCI0 TWIӻʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void USCI0_TWI_Slave_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0XCF | 0X20; + US0CON2 = TWI_Address << 1; +} + +/************************************************** +*:void USCI0_TWI_MasterCommunicationRate(USCI0_TWI_MasterCommunicationRate_TypeDef TWI_MasterCommunicationRate) +*:USCI0 TWIģʽͨѶ趨 +*ڲ: +USCI0_TWI_MasterCommunicationRate_TypeDef:TWI_MasterCommunicationRate:TWIģʽͨѶ +*ڲ:void +**************************************************/ +void USCI0_TWI_MasterCommunicationRate(USCI0_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate) +{ + OTCON = OTCON & 0XCF | 0X20; + US0CON1 |= TWI_MasterCommunicationRate; +} + +/************************************************** +*:void USCI0_TWI_Start(void) +*:USCI0 TWI ʼλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI0_TWI_Start(void) +{ + US0CON1 |= 0x20; +} + +/************************************************** +*:void USCI0_TWI_MasterModeStop(void) +*:USCI0 TWIģʽֹͣλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI0_TWI_MasterModeStop(void) +{ + US0CON1 |= 0x10; +} + +/************************************************** +*:void USCI0_TWI_SlaveClockExtension(void) +*:USCI0 TWIӻģʽʱӳλ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +**************************************************/ +void USCI0_TWI_SlaveClockExtension(FunctionalState NewState) +{ + OTCON = OTCON & 0XCF | 0X20; + + if (NewState != DISABLE) + { + US0CON1 |= 0x40; + } + else + { + US0CON1 &= 0XBF; + } +} + +/************************************************** +*:void USCI0_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI0_TWI_AcknowledgeConfig(FunctionalState NewState) +{ + OTCON = OTCON & 0XCF | 0X20; + + if (NewState != DISABLE) + { + US0CON0 |= 0X08; + } + else + { + US0CON0 &= 0XF7; + } +} + +/************************************************** +*:void USCI0_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:ͨõַӦʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI0_TWI_GeneralCallCmd(FunctionalState NewState) +{ + OTCON = OTCON & 0XCF | 0X20; + + if (NewState != DISABLE) + { + US0CON2 |= 0X01; + } + else + { + US0CON2 &= 0XFE; + } +} + +/***************************************************** +*:FlagStatus USCI0_GetTWIStatus(USCI0_TWIState_TypeDef USCI0_TWIState) +*:ȡTWI״̬ +*ڲ: +USCI0_TWIState_TypeDef:USCI0_TWIState:TWI״̬ +*ڲ: +FlagStatus:USCI0_SC־״̬ +*****************************************************/ +FlagStatus USCI0_GetTWIStatus(USCI0_TWIState_TypeDef USCI0_TWIState) +{ + if ((US0CON0 & 0x07) == USCI0_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void USCI0_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI0_TWI_Cmd(FunctionalState NewState) +{ + OTCON = OTCON & 0XCF | 0X20; + + if (NewState != DISABLE) + { + US0CON0 |= 0X80; + } + else + { + US0CON0 &= (~0X80); + } +} + +/***************************************************** +*:void USCI0_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_TWI_SendData(uint8_t Data) +{ + US0CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI0_TWI_SendData(void) +*:US0CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI0_TWI_ReceiveData(void) +{ + return US0CON3; +} + +/************************************************** +*:void USCI0_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI0_UART_Mode_TypeDef Mode, USCI0_UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +USCI0_UART_Mode_TypeDef:Mode:UART1ģʽ +USCI0_UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void USCI0_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI0_UART_Mode_TypeDef Mode, + USCI0_UART_RX_TypeDef RxMode) +{ + OTCON |= 0x30; + US0CON0 = US0CON0 & 0X0F | Mode | RxMode; + + if (Mode == USCI0_UART_Mode_8B) + { + if (BaudRate == USCI0_UART_BaudRate_FsysDIV12) + { + US0CON0 &= 0XDF; + } + else if (BaudRate == USCI0_UART_BaudRate_FsysDIV4) + { + US0CON0 |= 0X20; + } + } + else + { + US0CON2 = UARTFsys / BaudRate / 256; + US0CON1 = UARTFsys / BaudRate % 256; + } +} + +/***************************************************** +*:void USCI0_UART_SendData8(uint8_t Data) +*:USCI0 UART18λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_UART_SendData8(uint8_t Data) +{ + US0CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI0_UART_ReceiveData8(void) +*:US0CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI0_UART_ReceiveData8(void) +{ + return US0CON3; +} + +/***************************************************** +*:void USCI0_UART_SendData9(uint16_t Data) +*:UART19λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if (Data_9Bit) + { + US0CON0 |= 0x08; + } + else + { + US0CON0 &= 0xf7; + } + + US0CON3 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI0_UART_ReceiveData9(void) +*:US0CON3еֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI0_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = US0CON3 + ((uint16_t)(US0CON0 & 0X04) << 6); + return Data9; +} + +/***************************************************** +*:void USCI0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:USCI0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void USCI0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0x01; + } + else + { + IE1 &= 0xFE; + } + + /************************************************************/ + if (Priority != LOW) + { + IP1 |= 0x01; + } + else + { + IP1 &= 0xFE; + } +} + +/***************************************************** +*:FlagStatus USCI0_GetFlagStatus(USCI0_Flag_TypeDef USCI0_FLAG) +*:USCI0־״̬ +*ڲ: +USCI0_Flag_TypeDef:USCI0_FLAG:ȡı־λ +*ڲ: +FlagStatus:USCI0־״̬ +*****************************************************/ +FlagStatus USCI0_GetFlagStatus(USCI0_Flag_TypeDef USCI0_FLAG) +{ + FlagStatus bitstatus = RESET; +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI0_FLAG == USCI0_SPI_FLAG_SPIF) || (USCI0_FLAG == USCI0_SPI_FLAG_WCOL) || (USCI0_FLAG == USCI0_TWI_FLAG_TXRXnE)) +#endif + { + if ((USCI0_FLAG & US0CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((USCI0_FLAG & US0CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void USCI0_ClearFlag(USCI0_Flag_TypeDef USCI0_FLAG) +*:USCI0־״̬ +*ڲ: +USCI0_Flag_TypeDef:USCI0_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void USCI0_ClearFlag(USCI0_Flag_TypeDef USCI0_FLAG) +{ +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI0_FLAG == USCI0_SPI_FLAG_SPIF) || (USCI0_FLAG == USCI0_SPI_FLAG_WCOL) || (USCI0_FLAG == USCI0_TWI_FLAG_TXRXnE)) +#endif + { + US0CON1 &= (~USCI0_FLAG); //ĴUS0CON1 + } + else if ((USCI0_FLAG == USCI0_UART_FLAG_TI) || (USCI0_FLAG == USCI0_UART_FLAG_RI)) + { +#if defined(SC92L853x) || defined(SC92L753x) + US0CON0 = US0CON0 & 0xFC | USCI0_FLAG;//д1 +#endif + } + else + { + US0CON0 &= (~USCI0_FLAG); //ĴUS0CON0 + } +} + +/***************************************************** +*:void USCI0_TWI_SendAddr(uint8_t Addr,USCI0_TWI_RWType RW) +*:TWI͵ַд +*ڲ: +uint8_t:Addr:͵ĵַ 0~127 +USCI0_TWI_RWType:RW:д +*ڲ:void +*****************************************************/ +void USCI0_TWI_SendAddr(uint8_t Addr, USCI0_TWI_RWType RW) +{ + US0CON3 = (Addr << 1) | RW; +} + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_usci1.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_usci1.c new file mode 100644 index 0000000..95e0773 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_usci1.c @@ -0,0 +1,528 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_USCI1.c +// : +// ģ鹦 : USCI1̼⺯Cļ +// : 2022/01/05 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_usci1.h" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void USCI1_DeInit(void) +*:USCI1ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI1_DeInit(void) +{ + OTCON &= 0X3F; + US1CON0 = 0X00; + US1CON1 = 0X00; + US1CON2 = 0X00; + US1CON3 = 0X00; + IE2 &= (~0X01); + IP2 &= (~0X01); +} + +/************************************************** +*:void USCI1_SPI_Init(USCI1_SPI_FirstBit_TypeDef FirstBit, USCI1_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,USCI1_SPI_Mode_TypeDef Mode, + USCI1_SPI_ClockPolarity_TypeDef ClockPolarity, USCI1_SPI_ClockPhase_TypeDef ClockPhase,USCI1_SPI_TXE_INT_TypeDef SPI_TXE_INT,USCI1_TransmissionMode_TypeDef TransmissionMode) +*:SPIʼú +*ڲ: +USCI1_SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +USCI1_SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +USCI1_SPI_Mode_TypeDef:Mode:SPIģʽѡ +USCI1_SPI_ClockPolarity_TypeDef:ClockPolarity:SPIʱӼѡ +USCI1_SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +USCI1_SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ,ùSC92FXX1XоƬЧ +USCI1_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16λ +*ڲ:void +**************************************************/ +void USCI1_SPI_Init(USCI1_SPI_FirstBit_TypeDef FirstBit, + USCI1_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI1_SPI_Mode_TypeDef Mode, + USCI1_SPI_ClockPolarity_TypeDef ClockPolarity, USCI1_SPI_ClockPhase_TypeDef ClockPhase, + USCI1_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI1_TransmissionMode_TypeDef TransmissionMode) +{ + + OTCON = (OTCON & 0X3F) | 0X40; +#if defined(SC92L853x) || defined(SC92L753x) + SPI_TXE_INT = USCI1_SPI_TXE_DISINT; //SPI_TXE_INTùЧ + US1CON1 = US1CON1 & (~0X05) | FirstBit | TransmissionMode; +#endif + US1CON0 = US1CON0 & 0X80 | BaudRatePrescaler | Mode | ClockPolarity | ClockPhase; +} + +/************************************************** +*:void USCI1_TransmissionMode(USCI1_TransmissionMode_TypeDef TransmissionMode) +*:SPI ģʽú +*ڲ: +USCI1_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16eλ +*ڲ:void +**************************************************/ +void USCI1_TransmissionMode(USCI1_TransmissionMode_TypeDef TransmissionMode) +{ + if (TransmissionMode == USCI1_SPI_DATA8) + { + US1CON1 &= 0xFD; + } + else + { + US1CON1 |= 0x02; + } +} + +/***************************************************** +*:void USCI1_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI1_SPI_Cmd(FunctionalState NewState) +{ + OTCON = (OTCON & 0X3F) | 0X40; + + if (NewState != DISABLE) + { + US1CON0 |= 0X80; + } + else + { + US1CON0 &= (~0X80); + } +} +/***************************************************** +*:void USCI1_SPI_SendData_8(uint8_t Data) +*:USCI1 SPI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_SPI_SendData_8(uint8_t Data) +{ + US1CON2 = Data; +} + +/***************************************************** +*:uint8_t USCI1_SPI_ReceiveData_8(void) +*:US1CON2еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI1_SPI_ReceiveData_8(void) +{ + return US1CON2; +} + +/***************************************************** +*:void USCI1_SPI_SendData_16(uint16_t Data) +*:US1CON2 SPI +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_SPI_SendData_16(uint16_t Data) +{ + US1CON3 = (uint8_t)(Data >> 8); + US1CON2 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI1_SPI_ReceiveData_16(void) +*:US1CON2еֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI1_SPI_ReceiveData_16(void) +{ + uint16_t SPI_data; + SPI_data = (uint16_t)((US1CON3 << 8) | US1CON2); + return SPI_data; +} + +/************************************************** +*:void USCI1_TWI_Slave_Init(uint8_t TWI_Address) +*:USCI1 TWIӻʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void USCI1_TWI_Slave_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0X3F | 0X80; + US1CON2 = TWI_Address << 1; +} + +/************************************************** +*:void USCI1_TWI_MasterCommunicationRate(USCI1_TWI_MasterCommunicationRate_TypeDef TWI_MasterCommunicationRate) +*:USCI1 TWIģʽͨѶ趨 +*ڲ: +USCI1_TWI_MasterCommunicationRate_TypeDef:TWI_MasterCommunicationRate:TWIģʽͨѶ +*ڲ:void +**************************************************/ +void USCI1_TWI_MasterCommunicationRate(USCI1_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate) +{ + OTCON = OTCON & 0X3F | 0X80; + US1CON1 |= TWI_MasterCommunicationRate; +} + +/************************************************** +*:void USCI1_TWI_Start(void) +*:USCI1 TWI ʼλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI1_TWI_Start(void) +{ + US1CON1 |= 0x20; +} + +/************************************************** +*:void USCI1_TWI_MasterModeStop(void) +*:USCI1 TWIģʽֹͣλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI1_TWI_MasterModeStop(void) +{ + US1CON1 |= 0x10; +} + +/************************************************** +*:void USCI1_TWI_SlaveClockExtension(FunctionalState NewState) +*:USCI1 TWIӻģʽʱӳλ +*ڲ: +FunctionalState:NewState:ʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI1_TWI_SlaveClockExtension(FunctionalState NewState) +{ + OTCON = OTCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US1CON1 |= 0x40; + } + else + { + US1CON1 &= 0XBF; + } +} + +/************************************************** +*:void USCI1_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI1_TWI_AcknowledgeConfig(FunctionalState NewState) +{ + OTCON = OTCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US1CON0 |= 0X08; + } + else + { + US1CON0 &= 0XF7; + } +} + +/************************************************** +*:void USCI1_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI1_TWI_GeneralCallCmd(FunctionalState NewState) +{ + OTCON = OTCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US1CON2 |= 0X01; + } + else + { + US1CON2 &= 0XFE; + } +} + +/***************************************************** +*:FlagStatus USCI1_GetTWIStatus(USCI1_TWIState_TypeDef USCI1_TWIState) +*:ȡTWI״̬ +*ڲ: +USCI1_TWIState_TypeDef:USCI1_TWIState:TWI״̬ +*ڲ: +FlagStatus:USCI1_TWI־״̬ +*****************************************************/ +FlagStatus USCI1_GetTWIStatus(USCI1_TWIState_TypeDef USCI1_TWIState) +{ + if ((US1CON0 & 0x07) == USCI1_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void USCI1_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI1_TWI_Cmd(FunctionalState NewState) +{ + OTCON = OTCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US1CON0 |= 0X80; + } + else + { + US1CON0 &= (~0X80); + } +} + +/***************************************************** +*:void USCI1_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_TWI_SendData(uint8_t Data) +{ + US1CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI1_TWI_SendData(void) +*:US1CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI1_TWI_ReceiveData(void) +{ + return US1CON3; +} + +/************************************************** +*:void USCI1_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI1_UART_Mode_TypeDef Mode, USCI1_UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +USCI1_UART_Mode_TypeDef:Mode:UART1ģʽ +USCI1_UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void USCI1_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI1_UART_Mode_TypeDef Mode, + USCI1_UART_RX_TypeDef RxMode) +{ + OTCON |= 0xC0; + US1CON0 = US1CON0 & 0X0F | Mode | RxMode; + + if (Mode == USCI1_UART_Mode_8B) + { + if (BaudRate == USCI1_UART_BaudRate_FsysDIV12) + { + US1CON0 &= 0XDF; + } + else if (BaudRate == USCI1_UART_BaudRate_FsysDIV4) + { + US1CON0 |= 0X20; + } + } + else + { + US1CON2 = UARTFsys / BaudRate / 256; + US1CON1 = UARTFsys / BaudRate % 256; + } +} + +/***************************************************** +*:void USCI1_UART_SendData8(uint8_t Data) +*:USCI1 UART18λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_UART_SendData8(uint8_t Data) +{ + US1CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI1_UART_ReceiveData8(void) +*:US1CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI1_UART_ReceiveData8(void) +{ + return US1CON3; +} + +/***************************************************** +*:void USCI1_UART_SendData9(uint16_t Data) +*:UART19λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if (Data_9Bit) + { + US1CON0 |= 0x08; + } + else + { + US1CON0 &= 0xf7; + } + + US1CON3 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI1_UART_ReceiveData9(void) +*:US1CON3еֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI1_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = US1CON3 + ((uint16_t)(US1CON0 & 0X04) << 6); + return Data9; +} + +/***************************************************** +*:void USCI1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:USCI1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void USCI1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE2 |= 0x01; + } + else + { + IE2 &= 0xFE; + } + + /************************************************************/ + if (Priority != LOW) + { + IP2 |= 0x01; + } + else + { + IP2 &= 0xFE; + } +} + +/***************************************************** +*:FlagStatus USCI1_GetFlagStatus(USCI1_Flag_TypeDef USCI1_FLAG) +*:USCI1־״̬ +*ڲ: +USCI1_Flag_Typedef:USCI1_Flag:жϱ־λѡ +*ڲ: +FlagStatus:USCI1־״̬ +*****************************************************/ +FlagStatus USCI1_GetFlagStatus(USCI1_Flag_TypeDef USCI1_FLAG) +{ + FlagStatus bitstatus = RESET; +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI1_FLAG == USCI1_SPI_FLAG_SPIF) || (USCI1_FLAG == USCI1_SPI_FLAG_WCOL) || (USCI1_FLAG == USCI1_TWI_FLAG_TXRXnE)) +#endif + { + if ((USCI1_FLAG & US1CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((USCI1_FLAG & US1CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void USCI1_ClearFlag(USCI1_Flag_TypeDef USCI1_FLAG) +*:USCI1־״̬ +*ڲ: +USCI1_Flag_TypeDef:USCI1_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void USCI1_ClearFlag(USCI1_Flag_TypeDef USCI1_FLAG) +{ +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI1_FLAG == USCI1_SPI_FLAG_SPIF) || (USCI1_FLAG == USCI1_SPI_FLAG_WCOL) || (USCI1_FLAG == USCI1_TWI_FLAG_TXRXnE)) +#endif + { + US1CON1 &= (~USCI1_FLAG); //ĴUS1CON1 + } + else if ((USCI1_FLAG == USCI1_UART_FLAG_TI) || (USCI1_FLAG == USCI1_UART_FLAG_RI)) + { +#if defined(SC92L853x) || defined(SC92L753x) + US1CON0 = US1CON0 & 0xFC | USCI1_FLAG; //д1 +#endif + } + else + { + US1CON0 &= (~USCI1_FLAG); //ĴUS1CON0 + } +} + +/***************************************************** +*:void USCI1_TWI_SendAddr(uint8_t Addr,USCI1_TWI_RWType RW) +*:TWI͵ַд +*ڲ: +uint8_t:Addr:͵ĵַ 0~127 +USCI1_TWI_RWType:RW:д +*ڲ:void +*****************************************************/ +void USCI1_TWI_SendAddr(uint8_t Addr, USCI1_TWI_RWType RW) +{ + US1CON3 = (Addr << 1) | RW; +} + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_usci2.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_usci2.c new file mode 100644 index 0000000..4059545 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_usci2.c @@ -0,0 +1,535 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92F_usci2.c +// : ԪӦŶ +// ģ鹦: USCI2̼⺯Cļ +// : 2022/01/05 +// 汾: V1.10001 +// ˵: ļSC92ϵоƬ +//************************************************************* + +/* ͷļ */ +#include "sc92f_usci2.h" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void USCI2_DeInit(void) +*:USCI2ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI2_DeInit(void) +{ + TMCON &= 0X3F; + US2CON0 = 0X00; + US2CON1 = 0X00; + US2CON2 = 0X00; + US2CON3 = 0X00; + IE2 &= (~0X02); + IP2 &= (~0X02); +} + +/************************************************** +*:void USCI2_SPI_Init(USCI2_SPI_FirstBit_TypeDef FirstBit, USCI2_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,USCI2_SPI_Mode_TypeDef Mode, + USCI2_SPI_ClockPolarity_TypeDef ClockPolarity, USCI2_SPI_ClockPhase_TypeDef ClockPhase,USCI2_SPI_TXE_INT_TypeDef SPI_TXE_INT,USCI2_TransmissionMode_TypeDef TransmissionMode) +*:SPIʼú +*ڲ: +USCI2_SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +USCI2_SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +USCI2_SPI_Mode_TypeDef:Mode:SPIģʽѡ +USCI2_SPI_ClockPolarity_TypeDef:ClockPolarity:SPIʱӼѡ +USCI2_SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +USCI2_SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ,ùSC92FXX1XоƬЧ +USCI2_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16λ +*ڲ:void +**************************************************/ +void USCI2_SPI_Init(USCI2_SPI_FirstBit_TypeDef FirstBit, + USCI2_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI2_SPI_Mode_TypeDef Mode, + USCI2_SPI_ClockPolarity_TypeDef ClockPolarity, USCI2_SPI_ClockPhase_TypeDef ClockPhase, + USCI2_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI2_TransmissionMode_TypeDef TransmissionMode) +{ + TMCON = (TMCON & 0X3F) | 0X40; +#if defined(SC92L853x) || defined(SC92L753x) + SPI_TXE_INT = USCI2_SPI_TXE_DISINT; //SPI_TXE_INTùSC92FXX1XоƬЧ + US2CON1 = US2CON1 & (~0X05) | FirstBit | TransmissionMode; + +#endif +#if defined(SC92L853x) || defined(SC92L753x) + US2CON1 = US2CON1 & (~0X05) | FirstBit | SPI_TXE_INT | TransmissionMode; +#endif + US2CON0 = US2CON0 & 0X80 | BaudRatePrescaler | Mode | ClockPolarity | ClockPhase; +} + +/************************************************** +*:void USCI2_TransmissionMode(USCI2_TransmissionMode_TypeDef TransmissionMode) +*:SPI ģʽú +*ڲ: +USCI2_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16eλ +*ڲ:void +**************************************************/ +void USCI2_TransmissionMode(USCI2_TransmissionMode_TypeDef TransmissionMode) +{ + + TMCON = (TMCON & 0X3F) | 0X40; + if (TransmissionMode == USCI2_SPI_DATA8) + { + US2CON1 &= 0xFD; + } + else + { + US2CON1 |= 0x02; + } +} + +/***************************************************** +*:void USCI2_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI2_SPI_Cmd(FunctionalState NewState) +{ + TMCON = (TMCON & 0X3F) | 0X40; + + if (NewState != DISABLE) + { + US2CON0 |= 0X80; + } + else + { + US2CON0 &= (~0X80); + } +} + +/***************************************************** +*:void USCI2_SPI_SendData_8(uint8_t Data) +*:USCI2 SPI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_SPI_SendData_8(uint8_t Data) +{ + US2CON2 = Data; +} + +/***************************************************** +*:uint8_t USCI2_SPI_ReceiveData_8(void) +*:US2CON2еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI2_SPI_ReceiveData_8(void) +{ + return US2CON2; +} + +/***************************************************** +*:void USCI2_SPI_SendData_16(uint16_t Data) +*:US2CON2 SPI +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_SPI_SendData_16(uint16_t Data) +{ + US2CON3 = (uint8_t)(Data >> 8); + US2CON2 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI2_SPI_ReceiveData_16(void) +*:US2CON2еֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI2_SPI_ReceiveData_16(void) +{ + uint16_t SPI_data; + SPI_data = (uint16_t)((US2CON3 << 8) | US2CON2); + return SPI_data; +} + +/************************************************** +*:void USCI2_TWI_Slave_Init(uint8_t TWI_Address) +*:USCI2 TWI ӻʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void USCI2_TWI_Slave_Init(uint8_t TWI_Address) +{ + TMCON = TMCON & 0X3F | 0X80; + US2CON2 = TWI_Address << 1; +} + +/************************************************** +*:void USCI2_TWI_MasterCommunicationRate(USCI2_TWI_MasterCommunicationRate_TypeDef TWI_MasterCommunicationRate) +*:USCI2 TWIģʽͨѶ趨 +*ڲ: +USCI2_TWI_MasterCommunicationRate_TypeDef:TWI_MasterCommunicationRate:TWIģʽͨѶ +*ڲ:void +**************************************************/ +void USCI2_TWI_MasterCommunicationRate(USCI2_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate) +{ + TMCON = TMCON & 0X3F | 0X80; //ѡusci2ΪTWI + + US2CON1 = TWI_MasterCommunicationRate; +} + +/************************************************** +*:void USCI2_TWI_Start(void) +*:USCI2 TWI ʼλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI2_TWI_Start(void) +{ + US2CON1 |= 0x20; +} + +/************************************************** +*:void USCI2_TWI_MasterModeStop(void) +*:USCI2 TWIģʽֹͣλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI2_TWI_MasterModeStop(void) +{ + US2CON1 |= 0x10; +} + +/************************************************** +*:void USCI2_TWI_SlaveClockExtension(void) +*:USCI2 TWIӻģʽʱӳλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI2_TWI_SlaveClockExtension(FunctionalState NewState) +{ + TMCON = TMCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US2CON1 |= 0x40; + } + else + { + US2CON1 &= 0XBF; + } +} + +/************************************************** +*:void USCI2_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI2_TWI_AcknowledgeConfig(FunctionalState NewState) +{ + TMCON = TMCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US2CON0 |= 0X08; + } + else + { + US2CON0 &= 0XF7; + } +} + +/************************************************** +*:void USCI2_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI2_TWI_GeneralCallCmd(FunctionalState NewState) +{ + TMCON = TMCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US2CON2 |= 0X01; + } + else + { + US2CON2 &= 0XFE; + } +} + +/***************************************************** +*:FlagStatus USCI2_GetTWIStatus(USCI2_TWIState_TypeDef USCI2_TWIState) +*:ȡTWI״̬ +*ڲ: +USCI2_TWIState_TypeDef:USCI2_TWIState:TWI״̬ +*ڲ: +FlagStatus:USCI2_TWI־״̬ +*****************************************************/ +FlagStatus USCI2_GetTWIStatus(USCI2_TWIState_TypeDef USCI2_TWIState) +{ + if ((US2CON0 & 0x07) == USCI2_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void USCI2_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI2_TWI_Cmd(FunctionalState NewState) +{ + TMCON = TMCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US2CON0 |= 0X80; + } + else + { + US2CON0 &= (~0X80); + } +} + +/***************************************************** +*:void USCI2_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_TWI_SendData(uint8_t Data) +{ + US2CON3 = Data; +} +/***************************************************** +*:void USCI2_TWI_SendAddr(uint8_t Addr,USCI2_TWI_RWType RW) +*:TWI͵ַд +*ڲ: +uint8_t:Addr:͵ĵַ +USCI2_TWI_RWType:RW:д +*ڲ:void +*****************************************************/ +void USCI2_TWI_SendAddr(uint8_t Addr, USCI2_TWI_RWType RW) +{ + US2CON3 = (Addr << 1) | RW; +} +/***************************************************** +*:uint8_t USCI2_TWI_ReceiveData(void) +*:US2CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI2_TWI_ReceiveData(void) +{ + return US2CON3; +} + +/************************************************** +*:void USCI2_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI2_UART_Mode_TypeDef Mode, USCI2_UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +USCI2_UART_Mode_TypeDef:Mode:UART1ģʽ +USCI2_UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void USCI2_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI2_UART_Mode_TypeDef Mode, + USCI2_UART_RX_TypeDef RxMode) +{ + TMCON |= 0xC0; + US2CON0 = US2CON0 & 0X0F | Mode | RxMode; + + if (Mode == USCI2_UART_Mode_8B) + { + if (BaudRate == USCI2_UART_BaudRate_FsysDIV12) + { + US2CON0 &= 0XDF; + } + else if (BaudRate == USCI2_UART_BaudRate_FsysDIV4) + { + US2CON0 |= 0X20; + } + } + else + { + US2CON2 = UARTFsys / BaudRate / 256; + US2CON1 = UARTFsys / BaudRate % 256; + } +} + +/***************************************************** +*:void USCI2_UART_SendData8(uint8_t Data) +*:USCI2 UART18λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_UART_SendData8(uint8_t Data) +{ + US2CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI2_UART_ReceiveData8(void) +*:US2CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI2_UART_ReceiveData8(void) +{ + return US2CON3; +} + +/***************************************************** +*:void USCI2_UART_SendData9(uint16_t Data) +*:UART9λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if (Data_9Bit) + { + US2CON0 |= 0x08; + } + else + { + US2CON0 &= 0xf7; + } + + US2CON3 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI2_UART_ReceiveData9(void) +*:US2CON3еֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI2_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = US2CON3 + ((uint16_t)(US2CON0 & 0X04) << 6); + return Data9; +} + +/***************************************************** +*:void USCI2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:USCI2жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void USCI2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE2 |= 0x02; + } + else + { + IE2 &= 0xFD; + } + + /************************************************************/ + if (Priority != LOW) + { + IP2 |= 0x02; + } + else + { + IP2 &= 0xFD; + } +} + +/***************************************************** +*:FlagStatus USCI2_GetFlagStatus(USCI2_Flag_TypeDef USCI2_FLAG) +*:USCI2־״̬ +*ڲ: +USCI2_Flag_Typedef:USCI2_Flag:ȡı־λ +*ڲ: +FlagStatus:USCI2־״̬ +*****************************************************/ +FlagStatus USCI2_GetFlagStatus(USCI2_Flag_TypeDef USCI2_FLAG) +{ + FlagStatus bitstatus = RESET; + +#if defined(SC92L853x) || defined(SC92L753x) + + if ((USCI2_FLAG == USCI2_SPI_FLAG_SPIF) || (USCI2_FLAG == USCI2_SPI_FLAG_WCOL)) +#endif + { + if ((USCI2_FLAG & US2CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((USCI2_FLAG & US2CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void USCI2_ClearFlag(USCI2_Flag_TypeDef USCI2_FLAG) +*:USCI2־״̬ +*ڲ: +USCI2_Flag_TypeDef:USCI2_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void USCI2_ClearFlag(USCI2_Flag_TypeDef USCI2_FLAG) +{ +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI2_FLAG == USCI2_SPI_FLAG_SPIF) || (USCI2_FLAG == USCI2_SPI_FLAG_WCOL) || (USCI2_FLAG == USCI2_TWI_FLAG_TXRXnE)) +#endif + { + US2CON1 &= (~USCI2_FLAG); //ĴUS2CON1 + } + else if ((USCI2_FLAG == USCI2_UART_FLAG_TI) || (USCI2_FLAG == USCI2_UART_FLAG_RI)) + { +#if defined(SC92L853x) || defined(SC92L753x) + US2CON0 = US2CON0 & 0xFC | USCI2_FLAG; //д1 +#endif + } + else + { + US2CON0 &= (~USCI2_FLAG); //ĴUS2CON0 + } +} + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_wdt.c b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_wdt.c new file mode 100644 index 0000000..c5737c2 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/FWLib/SC92F_Lib/src/sc92f_wdt.c @@ -0,0 +1,58 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_wdt.c +// : +// ģ鹦: WDT̼⺯Cļ +// : 2022323 +// 汾: V1.10002 +// ˵: +//************************************************************* + +#include "sc92f_wdt.h" + +/************************************************** +*:void WDT_DeInit(void) +*:WDTؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void WDT_DeInit(void) +{ + WDTCON = 0X00; +} + +/************************************************** +*:void WDT_Init(WDT_OverflowTime_TypeDef OverflowTime) +*:WDTʼú +*ڲ: +WDT_OverflowTime_TypeDef:OverflowTime:WDTʱѡ +*ڲ:void +**************************************************/ +void WDT_Init(WDT_OverflowTime_TypeDef + OverflowTime) +{ + WDTCON = (WDTCON & 0XF8) | OverflowTime; +} + +/***************************************************** +*:void WDT_Cmd(FunctionalState NewState) +*:WDTܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void WDT_Cmd(FunctionalState NewState) +{ + OPINX = 0XC1; + + if(NewState == DISABLE) + { + OPREG &= 0X7F; + } + else + { + OPREG |= 0X80; + } +} + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/List/SC_Init.lst b/CFG/SC92F8363B/Keil_Mould/List/SC_Init.lst new file mode 100644 index 0000000..017c4bc --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/List/SC_Init.lst @@ -0,0 +1,284 @@ +C51 COMPILER V9.01 SC_INIT 09/11/2020 09:48:38 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE SC_INIT +OBJECT MODULE PLACED IN ..\Output\SC_Init.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\User\SC_Init.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User) DEBUG + -PRINT(..\List\SC_Init.lst) OBJECT(..\Output\SC_Init.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : SC_Init.c + 4 // ģ鹦 : MCUʼCļ + 5 // ˵ : + 6 //************************************************************* + 7 + 8 #include "SC_Init.h" //MCUʼͷļ̼ͷļ + 9 + 10 /***************************************************** + 11 *: SC_Init + 12 *: MCUʼ + 13 *ڲvoid + 14 *ڲvoid + 15 *****************************************************/ + 16 void SC_Init(void) + 17 { + 18 1 /*write initial function here*/ + 19 1 + 20 1 EA = 1; + 21 1 } + 22 + 23 /***************************************************** + 24 *: SC_OPTION_Init + 25 *: OPTIONóʼ + 26 *ڲvoid + 27 *ڲvoid + 28 *****************************************************/ + 29 void SC_OPTION_Init(void) + 30 { + 31 1 /*OPTION_Init write here*/ + 32 1 } + 33 + 34 /***************************************************** + 35 *: SC_GPIO_Init + 36 *: GPIOʼ + 37 *ڲvoid + 38 *ڲvoid + 39 *****************************************************/ + 40 void SC_GPIO_Init(void) + 41 { + 42 1 /*GPIO_Init write here*/ + 43 1 } + 44 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + -(SC92F736xB) || defined (SC92F8003)||defined (SC92F84Ax) || defined (SC92F74Ax)||defined (SC92F83Ax) || defined (SC92F + -73Ax) + 45 /***************************************************** + 46 *: SC_UART0_Init + 47 *: UART0ʼ + 48 *ڲvoid + 49 *ڲvoid + 50 *****************************************************/ + 51 void SC_UART0_Init(void) + C51 COMPILER V9.01 SC_INIT 09/11/2020 09:48:38 PAGE 2 + + 52 { + 53 1 /*UART0_Init write here*/ + 54 1 } + 55 #endif + 56 /***************************************************** + 57 *: SC_TIM0_Init + 58 *: TIMER0ʼ + 59 *ڲvoid + 60 *ڲvoid + 61 *****************************************************/ + 62 void SC_TIM0_Init(void) + 63 { + 64 1 /*TIM0_Init write here*/ + 65 1 } + 66 + 67 /***************************************************** + 68 *: SC_TIM1_Init + 69 *: TIMER1ʼ + 70 *ڲvoid + 71 *ڲvoid + 72 *****************************************************/ + 73 void SC_TIM1_Init(void) + 74 { + 75 1 /*TIM1_Init write here*/ + 76 1 } + 77 + 78 /***************************************************** + 79 *: SC_TIM2_Init + 80 *: TIMER2ʼ + 81 *ڲvoid + 82 *ڲvoid + 83 *****************************************************/ + 84 void SC_TIM2_Init(void) + 85 { + 86 1 /*TIM2_Init write here*/ + 87 1 } + 88 + 89 + 90 /***************************************************** + 91 *: SC_PWM_Init + 92 *: PWMʼ + 93 *ڲvoid + 94 *ڲvoid + 95 *****************************************************/ + 96 void SC_PWM_Init(void) + 97 { + 98 1 /*PWM_Init write here*/ + 99 1 } + 100 + 101 /***************************************************** + 102 *: SC_INT_Init + 103 *: INTʼ + 104 *ڲvoid + 105 *ڲvoid + 106 *****************************************************/ + 107 void SC_INT_Init(void) + 108 { + 109 1 /*INT_Init write here*/ + 110 1 } + 111 + 112 /***************************************************** + 113 *: SC_ADC_Init + C51 COMPILER V9.01 SC_INIT 09/11/2020 09:48:38 PAGE 3 + + 114 *: ADCʼ + 115 *ڲvoid + 116 *ڲvoid + 117 *****************************************************/ + 118 void SC_ADC_Init(void) + 119 { + 120 1 /*ADC_Init write here*/ + 121 1 } + 122 + 123 /***************************************************** + 124 *: SC_IAP_Init + 125 *: IAPʼ + 126 *ڲvoid + 127 *ڲvoid + 128 *****************************************************/ + 129 void SC_IAP_Init(void) + 130 { + 131 1 /*IAP_Init write here*/ + 132 1 } + 133 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + -(SC92F736xB) || defined (SC92F8003)||defined (SC92F84Ax) || defined (SC92F74Ax)||defined (SC92F83Ax) || defined (SC92F + -73Ax) + 134 /***************************************************** + 135 *: SC_SSI_Init + 136 *: SSIʼ + 137 *ڲvoid + 138 *ڲvoid + 139 *****************************************************/ + 140 void SC_SSI_Init(void) + 141 { + 142 1 /*SSI_Init write here*/ + 143 1 } + 144 #endif + 145 #if defined (SC92F742x) + /***************************************************** + *: SC_SSI0_Init + *: SSIʼ + *ڲvoid + *ڲvoid + *****************************************************/ + void SC_SSI0_Init(void) + { + /*SSI0_Init write here*/ + } + /***************************************************** + *: SC_SSI1_Init + *: SSIʼ + *ڲvoid + *ڲvoid + *****************************************************/ + void SC_SSI1_Init(void) + { + /*SSI1_Init write here*/ + } + #endif + 167 /***************************************************** + 168 *: SC_BTM_Init + 169 *: ƵʱӶʱʼ + 170 *ڲvoid + 171 *ڲvoid + 172 *****************************************************/ + C51 COMPILER V9.01 SC_INIT 09/11/2020 09:48:38 PAGE 4 + + 173 void SC_BTM_Init(void) + 174 { + 175 1 /*BTM_Init write here*/ + 176 1 } + 177 + 178 /***************************************************** + 179 *: SC_CHKSUM_Init + 180 *: check sum ʼ + 181 *ڲvoid + 182 *ڲvoid + 183 *****************************************************/ + 184 void SC_CHKSUM_Init(void) + 185 { + 186 1 /*CHKSUM_Init write here*/ + 187 1 } + 188 + 189 /***************************************************** + 190 *: SC_WDT_Init + 191 *: Źʼ + 192 *ڲvoid + 193 *ڲvoid + 194 *****************************************************/ + 195 void SC_WDT_Init(void) + 196 { + 197 1 /*WDT_Init write here*/ + 198 1 } + 199 + 200 /***************************************************** + 201 *: SC_PWR_Init + 202 *: Դ/ĿƳʼ + 203 *ڲvoid + 204 *ڲvoid + 205 *****************************************************/ + 206 void SC_PWR_Init(void) + 207 { + 208 1 /*PWR_Init write here*/ + 209 1 } + 210 /***************************************************** + 211 *: SC_DDIC_Init + 212 *: ʾƳʼ + 213 *ڲvoid + 214 *ڲvoid + 215 *****************************************************/ + 216 void SC_DDIC_Init(void) + 217 { + 218 1 /*DDIC_Init write here*/ + 219 1 } + 220 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2) + /***************************************************** + *: SC_ACMP_Init + *: ˷ųʼ + *ڲvoid + *ڲvoid + *****************************************************/ + void SC_ACMP_Init(void) + { + /*ACMP_Init write here*/ + } + #endif + 232 /***************************************************** + 233 *: SC_MDU_Init + C51 COMPILER V9.01 SC_INIT 09/11/2020 09:48:38 PAGE 5 + + 234 *: ˳ʼ + 235 *ڲvoid + 236 *ڲvoid + 237 *****************************************************/ + 238 void SC_MDU_Init(void) + 239 { + 240 1 /*MDU_Init write here*/ + 241 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 20 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/CFG/SC92F8363B/Keil_Mould/List/SC_it.lst b/CFG/SC92F8363B/Keil_Mould/List/SC_it.lst new file mode 100644 index 0000000..c873d06 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/List/SC_it.lst @@ -0,0 +1,124 @@ +C51 COMPILER V9.01 SC_IT 09/11/2020 09:48:38 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE SC_IT +OBJECT MODULE PLACED IN ..\Output\SC_it.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\User\SC_it.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User) DEBUG PR + -INT(..\List\SC_it.lst) OBJECT(..\Output\SC_it.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : SC_it.c + 4 // : + 5 // ģ鹦 : sc92f жϷ + 6 // ֲб: + 7 // : 2020/8/18 + 8 // 汾 : V1.0 + 9 //************************************************************* + 10 #include "SC_it.h" + 11 #include "..\Drivers\SCDriver_List.h" + 12 void INT0Interrupt() interrupt 0 + 13 { + 14 1 TCON &= 0XFD;//жϱ־λ + 15 1 /*INT0_it write here*/ + 16 1 + 17 1 } + 18 + 19 void Timer0Interrupt() interrupt 1 + 20 { + 21 1 /*TIM0_it write here*/ + 22 1 } + 23 + 24 void INT1Interrupt() interrupt 2 + 25 { + 26 1 TCON &= 0XF7;//жϱ־λ + 27 1 /*INT1_it write here*/ + 28 1 + 29 1 } + 30 + 31 void Timer1Interrupt() interrupt 3 + 32 { + 33 1 /*TIM1_it write here*/ + 34 1 } + 35 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + -(SC92F736xB) || defined (SC92F8003)||defined (SC92F84Ax) || defined (SC92F74Ax)||defined (SC92F83Ax) || defined (SC92F + -73Ax) + 36 void UART0Interrupt() interrupt 4 + 37 { + 38 1 /*UART0_it write here*/ + 39 1 } + 40 #endif + 41 #if defined(SC92F742x) + void SSI0Interrupt() interrupt 4 + { + /*SSI0_it write here*/ + } + #endif + 47 void Timer2Interrupt() interrupt 5 + 48 { + 49 1 /*TIM2_it write here*/ + 50 1 } + 51 + C51 COMPILER V9.01 SC_IT 09/11/2020 09:48:38 PAGE 2 + + 52 void ADCInterrupt() interrupt 6 + 53 { + 54 1 /*ADC_it write here*/ + 55 1 } + 56 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + -(SC92F736xB) || defined (SC92F8003)||defined (SC92F84Ax) || defined (SC92F74Ax)||defined (SC92F83Ax) || defined (SC92F + -73Ax) + 57 void SSIInterrupt() interrupt 7 + 58 { + 59 1 /*SSI_it write here*/ + 60 1 } + 61 #endif + 62 #if defined (SC92F742x) + void SSI1Interrupt() interrupt 7 + { + /*SSI1_it write here*/ + } + #endif + 68 void PWMInterrupt() interrupt 8 + 69 { + 70 1 /*PWM_it write here*/ + 71 1 } + 72 + 73 void BTMInterrupt() interrupt 9 + 74 { + 75 1 /*BTM_it write here*/ + 76 1 } + 77 + 78 void INT2Interrupt() interrupt 10 + 79 { + 80 1 /*INT2_it write here*/ + 81 1 } + 82 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2) + void ACMPInterrupt() interrupt 12 + { + /*ACMP_it write here*/ + } + #endif + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 50 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/CFG/SC92F8363B/Keil_Mould/List/STARTUP.lst b/CFG/SC92F8363B/Keil_Mould/List/STARTUP.lst new file mode 100644 index 0000000..f460d8f --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/List/STARTUP.lst @@ -0,0 +1,254 @@ +A51 MACRO ASSEMBLER STARTUP 09/11/2020 09:13:24 PAGE 1 + + +MACRO ASSEMBLER A51 V8.02 +OBJECT MODULE PLACED IN ..\Output\STARTUP.obj +ASSEMBLER INVOKED BY: E:\Keil\C51\BIN\A51.EXE STARTUP.A51 SET(SMALL) DEBUG PRINT(..\List\STARTUP.lst) OBJECT(..\Output\S + TARTUP.obj) EP + +LOC OBJ LINE SOURCE + + 1 $nomod51 + 2 ;------------------------------------------------------------------------------ + 3 ; This file is part of the C51 Compiler package + 4 ; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc. + 5 ; Version 8.01 + 6 ; + 7 ; *** <<< Use Configuration Wizard in Context Menu >>> *** + 8 ;------------------------------------------------------------------------------ + 9 ; STARTUP.A51: This code is executed after processor reset. + 10 ; + 11 ; To translate this file use A51 with the following invocation: + 12 ; + 13 ; A51 STARTUP.A51 + 14 ; + 15 ; To link the modified STARTUP.OBJ file to your application use the following + 16 ; Lx51 invocation: + 17 ; + 18 ; Lx51 your object file list, STARTUP.OBJ controls + 19 ; + 20 ;------------------------------------------------------------------------------ + 21 ; + 22 ; User-defined Power-On Initialization of Memory + 23 ; + 24 ; With the following EQU statements the initialization of memory + 25 ; at processor reset can be defined: + 26 ; + 27 ; IDATALEN: IDATA memory size <0x0-0x100> + 28 ; Note: The absolute start-address of IDATA memory is always 0 + 29 ; The IDATA space overlaps physically the DATA and BIT areas. + 0100 30 IDATALEN EQU 100H + 31 ; + 32 ; XDATASTART: XDATA memory start address <0x0-0xFFFF> + 33 ; The absolute start address of XDATA memory + 0000 34 XDATASTART EQU 0 + 35 ; + 36 ; XDATALEN: XDATA memory size <0x0-0xFFFF> + 37 ; The length of XDATA memory in bytes. + 0100 38 XDATALEN EQU 100H + 39 ; + 40 ; PDATASTART: PDATA memory start address <0x0-0xFFFF> + 41 ; The absolute start address of PDATA memory + 0000 42 PDATASTART EQU 0H + 43 ; + 44 ; PDATALEN: PDATA memory size <0x0-0xFF> + 45 ; The length of PDATA memory in bytes. + 0000 46 PDATALEN EQU 0H + 47 ; + 48 ; + 49 ;------------------------------------------------------------------------------ + 50 ; + 51 ; Reentrant Stack Initialization + 52 ; + 53 ; The following EQU statements define the stack pointer for reentrant + 54 ; functions and initialized it: + 55 ; + 56 ; Stack Space for reentrant functions in the SMALL model. + 57 ; IBPSTACK: Enable SMALL model reentrant stack + A51 MACRO ASSEMBLER STARTUP 09/11/2020 09:13:24 PAGE 2 + + 58 ; Stack space for reentrant functions in the SMALL model. + 0000 59 IBPSTACK EQU 0 ; set to 1 if small reentrant is used. + 60 ; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF> + 61 ; Set the top of the stack to the highest location. + 0100 62 IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 + 63 ; + 64 ; + 65 ; Stack Space for reentrant functions in the LARGE model. + 66 ; XBPSTACK: Enable LARGE model reentrant stack + 67 ; Stack space for reentrant functions in the LARGE model. + 0000 68 XBPSTACK EQU 0 ; set to 1 if large reentrant is used. + 69 ; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF> + 70 ; Set the top of the stack to the highest location. + 0000 71 XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1 + 72 ; + 73 ; + 74 ; Stack Space for reentrant functions in the COMPACT model. + 75 ; PBPSTACK: Enable COMPACT model reentrant stack + 76 ; Stack space for reentrant functions in the COMPACT model. + 0000 77 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. + 78 ; + 79 ; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF> + 80 ; Set the top of the stack to the highest location. + 0100 81 PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 + 82 ; + 83 ; + 84 ;------------------------------------------------------------------------------ + 85 ; + 86 ; Memory Page for Using the Compact Model with 64 KByte xdata RAM + 87 ; Compact Model Page Definition + 88 ; + 89 ; Define the XDATA page used for PDATA variables. + 90 ; PPAGE must conform with the PPAGE set in the linker invocation. + 91 ; + 92 ; Enable pdata memory page initalization + 0000 93 PPAGEENABLE EQU 0 ; set to 1 if pdata object are used. + 94 ; + 95 ; PPAGE number <0x0-0xFF> + 96 ; uppermost 256-byte address of the page used for PDATA variables. + 0000 97 PPAGE EQU 0 + 98 ; + 99 ; SFR address which supplies uppermost address byte <0x0-0xFF> + 100 ; most 8051 variants use P2 as uppermost address byte + 00A0 101 PPAGE_SFR DATA 0A0H + 102 ; + 103 ; + 104 ;------------------------------------------------------------------------------ + 105 + 106 ; Standard SFR Symbols + 00E0 107 ACC DATA 0E0H + 00F0 108 B DATA 0F0H + 0081 109 SP DATA 81H + 0082 110 DPL DATA 82H + 0083 111 DPH DATA 83H + 112 + 113 NAME ?C_STARTUP + 114 + 115 + 116 ?C_C51STARTUP SEGMENT CODE + 117 ?STACK SEGMENT IDATA + 118 +---- 119 RSEG ?STACK +0000 120 DS 1 + 121 + 122 EXTRN CODE (?C_START) + 123 PUBLIC ?C_STARTUP + A51 MACRO ASSEMBLER STARTUP 09/11/2020 09:13:24 PAGE 3 + + 124 +---- 125 CSEG AT 0 +0000 020000 F 126 ?C_STARTUP: LJMP STARTUP1 + 127 +---- 128 RSEG ?C_C51STARTUP + 129 +0000 130 STARTUP1: + 131 + 132 IF IDATALEN <> 0 +0000 78FF 133 MOV R0,#IDATALEN - 1 +0002 E4 134 CLR A +0003 F6 135 IDATALOOP: MOV @R0,A +0004 D8FD 136 DJNZ R0,IDATALOOP + 137 ENDIF + 138 + 139 IF XDATALEN <> 0 +0006 900000 140 MOV DPTR,#XDATASTART +0009 7F00 141 MOV R7,#LOW (XDATALEN) + 142 IF (LOW (XDATALEN)) <> 0 + MOV R6,#(HIGH (XDATALEN)) +1 + ELSE +000B 7E01 145 MOV R6,#HIGH (XDATALEN) + 146 ENDIF +000D E4 147 CLR A +000E F0 148 XDATALOOP: MOVX @DPTR,A +000F A3 149 INC DPTR +0010 DFFC 150 DJNZ R7,XDATALOOP +0012 DEFA 151 DJNZ R6,XDATALOOP + 152 ENDIF + 153 + 154 IF PPAGEENABLE <> 0 + MOV PPAGE_SFR,#PPAGE + ENDIF + 157 + 158 IF PDATALEN <> 0 + MOV R0,#LOW (PDATASTART) + MOV R7,#LOW (PDATALEN) + CLR A + PDATALOOP: MOVX @R0,A + INC R0 + DJNZ R7,PDATALOOP + ENDIF + 166 + 167 IF IBPSTACK <> 0 + EXTRN DATA (?C_IBP) + + MOV ?C_IBP,#LOW IBPSTACKTOP + ENDIF + 172 + 173 IF XBPSTACK <> 0 + EXTRN DATA (?C_XBP) + + MOV ?C_XBP,#HIGH XBPSTACKTOP + MOV ?C_XBP+1,#LOW XBPSTACKTOP + ENDIF + 179 + 180 IF PBPSTACK <> 0 + EXTRN DATA (?C_PBP) + MOV ?C_PBP,#LOW PBPSTACKTOP + ENDIF + 184 +0014 758100 F 185 MOV SP,#?STACK-1 + 186 + 187 ; This code is required if you use L51_BANK.A51 with Banking Mode 4 + 188 ; Code Banking + 189 ; Select Bank 0 for L51_BANK.A51 Mode 4 + A51 MACRO ASSEMBLER STARTUP 09/11/2020 09:13:24 PAGE 4 + + 190 + + + + + 195 ; +0017 020000 F 196 LJMP ?C_START + 197 + 198 END + A51 MACRO ASSEMBLER STARTUP 09/11/2020 09:13:24 PAGE 5 + +SYMBOL TABLE LISTING +------ ----- ------- + + +N A M E T Y P E V A L U E ATTRIBUTES + +?C_C51STARTUP. . . C SEG 001AH REL=UNIT +?C_START . . . . . C ADDR ----- EXT +?C_STARTUP . . . . C ADDR 0000H A +?STACK . . . . . . I SEG 0001H REL=UNIT +ACC. . . . . . . . D ADDR 00E0H A +B. . . . . . . . . D ADDR 00F0H A +DPH. . . . . . . . D ADDR 0083H A +DPL. . . . . . . . D ADDR 0082H A +IBPSTACK . . . . . N NUMB 0000H A +IBPSTACKTOP. . . . N NUMB 0100H A +IDATALEN . . . . . N NUMB 0100H A +IDATALOOP. . . . . C ADDR 0003H R SEG=?C_C51STARTUP +PBPSTACK . . . . . N NUMB 0000H A +PBPSTACKTOP. . . . N NUMB 0100H A +PDATALEN . . . . . N NUMB 0000H A +PDATASTART . . . . N NUMB 0000H A +PPAGE. . . . . . . N NUMB 0000H A +PPAGEENABLE. . . . N NUMB 0000H A +PPAGE_SFR. . . . . D ADDR 00A0H A +SP . . . . . . . . D ADDR 0081H A +STARTUP1 . . . . . C ADDR 0000H R SEG=?C_C51STARTUP +XBPSTACK . . . . . N NUMB 0000H A +XBPSTACKTOP. . . . N NUMB 0000H A +XDATALEN . . . . . N NUMB 0100H A +XDATALOOP. . . . . C ADDR 000EH R SEG=?C_C51STARTUP +XDATASTART . . . . N NUMB 0000H A + + +REGISTER BANK(S) USED: 0 + + +ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/CFG/SC92F8363B/Keil_Mould/List/main.lst b/CFG/SC92F8363B/Keil_Mould/List/main.lst new file mode 100644 index 0000000..f6a422d --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/List/main.lst @@ -0,0 +1,52 @@ +C51 COMPILER V9.01 MAIN 09/11/2020 09:48:37 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE MAIN +OBJECT MODULE PLACED IN ..\Output\main.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\User\main.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User) DEBUG PRI + -NT(..\List\main.lst) OBJECT(..\Output\main.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : main.c + 4 // ģ鹦 : + 5 // ˵ : MCUʼͷļ + 6 //************************************************************ + 7 + 8 #include "SC_Init.h" //MCUʼͷļ̼ͷļ + 9 #include "SC_it.h" + 10 #include "..\Drivers\SCDriver_List.h" + 11 + 12 int main(void) + 13 { + 14 1 + 15 1 /*** MCUʼ ***/ + 16 1 SC_Init(); + 17 1 while(1) + 18 1 { + 19 2 + 20 2 } + 21 1 + 22 1 } + 23 + 24 + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 5 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/CFG/SC92F8363B/Keil_Mould/List/sc92f_chksum.lst b/CFG/SC92F8363B/Keil_Mould/List/sc92f_chksum.lst new file mode 100644 index 0000000..6abe113 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/List/sc92f_chksum.lst @@ -0,0 +1,86 @@ +C51 COMPILER V9.01 SC92F_CHKSUM 09/11/2020 09:49:58 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE SC92F_CHKSUM +OBJECT MODULE PLACED IN ..\Output\sc92f_chksum.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_chksum.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib + -\inc;..\User) DEBUG PRINT(..\List\sc92f_chksum.lst) OBJECT(..\Output\sc92f_chksum.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : sc92f_chksum.c + 4 // : + 5 // ģ鹦 : CHKSUM̼⺯Cļ + 6 // ֲб: + 7 // : 2020/8/18 + 8 // 汾 : V1.0 + 9 // ˵ + 10 //************************************************************* + 11 + 12 #include "sc92f_chksum.h" + 13 + 14 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + -(SC92F736xB) || defined (SC92F8003)|| defined (SC92F742x) + 15 /************************************************** + 16 *ƣvoid CHKSUM_DeInit(void) + 17 *ܣCHKSUMؼĴλȱʡֵ + 18 *ڲvoid + 19 *ڲvoid + 20 **************************************************/ + 21 void CHKSUM_DeInit(void) + 22 { + 23 1 OPERCON &= 0XFE; + 24 1 CHKSUML = 0X00; + 25 1 CHKSUMH = 0X00; + 26 1 } + 27 + 28 /************************************************** + 29 *ƣvoid CHKSUM_StartOperation(void) + 30 *ܣһcheck sum + 31 *ڲvoid + 32 *ڲvoid + 33 **************************************************/ + 34 void CHKSUM_StartOperation(void) + 35 { + 36 1 OPERCON |= 0X01; + 37 1 while(OPERCON & 0x01); + 38 1 } + 39 + 40 /************************************************** + 41 *ƣuint16_t CHKSUM_GetCheckValue(void) + 42 *ܣȡһcheck sumֵ + 43 *ڲvoid + 44 *ڲuint16_t check sumֵ + 45 **************************************************/ + 46 uint16_t CHKSUM_GetCheckValue(void) + 47 { + 48 1 uint16_t checktemp; + 49 1 + 50 1 checktemp = (uint16_t)(CHKSUMH << 8)+ (uint16_t)CHKSUML; + 51 1 return checktemp; + 52 1 } + C51 COMPILER V9.01 SC92F_CHKSUM 09/11/2020 09:49:58 PAGE 2 + + 53 #endif + 54 /******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 33 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/CFG/SC92F8363B/Keil_Mould/List/sc92f_gpio.lst b/CFG/SC92F8363B/Keil_Mould/List/sc92f_gpio.lst new file mode 100644 index 0000000..57237fb --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/List/sc92f_gpio.lst @@ -0,0 +1,433 @@ +C51 COMPILER V9.01 SC92F_GPIO 09/11/2020 09:48:38 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE SC92F_GPIO +OBJECT MODULE PLACED IN ..\Output\sc92f_gpio.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_gpio.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib\i + -nc;..\User) DEBUG PRINT(..\List\sc92f_gpio.lst) OBJECT(..\Output\sc92f_gpio.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : sc92f_gpio.c + 4 // : + 5 // ģ鹦 : GPIO̼⺯Cļ + 6 // ֲб: + 7 // : 2020/4/20 + 8 // 汾 : V1.0 + 9 // ˵ ļԪ92FϵеƬ + 10 //************************************************************* + 11 + 12 + 13 #include "sc92f_gpio.h" + 14 + 15 /************************************************** + 16 *ƣvoid GPIO_DeInit(void) + 17 *ܣGPIOؼĴλȱʡֵ + 18 *ڲvoid + 19 *ڲvoid + 20 **************************************************/ + 21 void GPIO_DeInit(void) + 22 { + 23 1 P0CON = 0x00; + 24 1 P1CON = 0x00; + 25 1 P2CON = 0x00; + 26 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2) + P3CON = 0x00; + P4CON = 0x00; + #endif + 30 1 P0PH = 0x00; + 31 1 P1PH = 0x00; + 32 1 P2PH = 0x00; + 33 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2) + P3PH = 0x00; + P4PH = 0x00; + #endif + 37 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + - (SC92F736xB) + P5CON = 0x00; + P5PH = 0x00; + P5 = 0; + #endif + 42 1 P0=0; + 43 1 P1=0; + 44 1 P2=0; + 45 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2) + P3=0; + P4=0; + #endif + 49 1 + C51 COMPILER V9.01 SC92F_GPIO 09/11/2020 09:48:38 PAGE 2 + + 50 1 } + 51 + 52 /************************************************** + 53 *ƣvoid GPIO_Init(GPIO_TypeDef GPIOx, uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode) + 54 *ܣGPIOģʽóʼ + 55 *ڲGPIOx ѡGPIO + 56 PortPins ѡGPIOܽPxy + 57 GPIO_Mode ѡGPIOģʽ롢롢 + 58 *ڲvoid + 59 **************************************************/ + 60 void GPIO_Init(GPIO_TypeDef GPIOx, uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode) + 61 { + 62 1 if(GPIOx == GPIO0) + 63 1 { + 64 2 if(GPIO_Mode == GPIO_MODE_IN_HI) + 65 2 { + 66 3 P0CON &= ~PortPins; + 67 3 P0PH &= ~PortPins; + 68 3 } + 69 2 if(GPIO_Mode == GPIO_MODE_IN_PU) + 70 2 { + 71 3 P0CON &= ~PortPins; + 72 3 P0PH |= PortPins; + 73 3 } + 74 2 if(GPIO_Mode == GPIO_MODE_OUT_PP) + 75 2 { + 76 3 P0CON |= PortPins; + 77 3 } + 78 2 } + 79 1 else if(GPIOx == GPIO1) + 80 1 { + 81 2 if(GPIO_Mode == GPIO_MODE_IN_HI) + 82 2 { + 83 3 P1CON &= ~PortPins; + 84 3 P1PH &= ~PortPins; + 85 3 } + 86 2 if(GPIO_Mode == GPIO_MODE_IN_PU) + 87 2 { + 88 3 P1CON &= ~PortPins; + 89 3 P1PH |= PortPins; + 90 3 } + 91 2 if(GPIO_Mode == GPIO_MODE_OUT_PP) + 92 2 { + 93 3 P1CON |= PortPins; + 94 3 } + 95 2 } + 96 1 + 97 1 else if(GPIOx == GPIO2) + 98 1 { + 99 2 if(GPIO_Mode == GPIO_MODE_IN_HI) + 100 2 { + 101 3 P2CON &= ~PortPins; + 102 3 P2PH &= ~PortPins; + 103 3 } + 104 2 if(GPIO_Mode == GPIO_MODE_IN_PU) + 105 2 { + 106 3 P2CON &= ~PortPins; + 107 3 P2PH |= PortPins; + 108 3 } + 109 2 if(GPIO_Mode == GPIO_MODE_OUT_PP) + 110 2 { + 111 3 P2CON |= PortPins; + C51 COMPILER V9.01 SC92F_GPIO 09/11/2020 09:48:38 PAGE 3 + + 112 3 } + 113 2 } + 114 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2) + else if(GPIOx == GPIO3) + { + if(GPIO_Mode == GPIO_MODE_IN_HI) + { + P3CON &= ~PortPins; + P3PH &= ~PortPins; + } + if(GPIO_Mode == GPIO_MODE_IN_PU) + { + P3CON &= ~PortPins; + P3PH |= PortPins; + } + if(GPIO_Mode == GPIO_MODE_OUT_PP) + { + P3CON |= PortPins; + } + } + else if(GPIOx == GPIO4) + { + if(GPIO_Mode == GPIO_MODE_IN_HI) + { + P4CON &= ~PortPins; + P4PH &= ~PortPins; + } + if(GPIO_Mode == GPIO_MODE_IN_PU) + { + P4CON &= ~PortPins; + P4PH |= PortPins; + } + if(GPIO_Mode == GPIO_MODE_OUT_PP) + { + P4CON |= PortPins; + } + } + #endif + 150 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + - (SC92F736xB) + else + { + if(GPIOx == GPIO5) + { + if(GPIO_Mode == GPIO_MODE_IN_HI) + { + P5CON &= ~PortPins; + P5PH &= ~PortPins; + } + if(GPIO_Mode == GPIO_MODE_IN_PU) + { + P5CON &= ~PortPins; + P5PH |= PortPins; + } + if(GPIO_Mode == GPIO_MODE_OUT_PP) + { + P5CON |= PortPins; + } + } + } + C51 COMPILER V9.01 SC92F_GPIO 09/11/2020 09:48:38 PAGE 4 + + #endif + 172 1 } + 173 + 174 /************************************************** + 175 *ƣvoid GPIO_Write(GPIO_TypeDef GPIOx, uint8_t PortVal) + 176 *ܣGPIOڸֵ + 177 *ڲGPIOx ѡGPIO + 178 PortVal GPIOڵֵ + 179 *ڲvoid + 180 **************************************************/ + 181 void GPIO_Write(GPIO_TypeDef GPIOx, uint8_t PortVal) + 182 { + 183 1 if(GPIOx == GPIO0) + 184 1 { + 185 2 P0 = PortVal; + 186 2 } + 187 1 if(GPIOx == GPIO1) + 188 1 { + 189 2 P1 = PortVal; + 190 2 } + 191 1 if(GPIOx == GPIO2) + 192 1 { + 193 2 P2 = PortVal; + 194 2 } + 195 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2) + if(GPIOx == GPIO3) + { + P3 = PortVal; + } + if(GPIOx == GPIO4) + { + P4 = PortVal; + } + #endif + 205 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + - (SC92F736xB) + if(GPIOx == GPIO5) + { + P5 = PortVal; + } + #endif + 211 1 } + 212 + 213 /************************************************** + 214 *ƣvoid GPIO_WriteHigh(GPIO_TypeDef GPIOx, uint8_t PortPins) + 215 *ܣGPIOڹܽPxyλ + 216 *ڲGPIOx ѡGPIO + 217 PortPins ѡGPIOڹܽPxy + 218 *ڲvoid + 219 **************************************************/ + 220 void GPIO_WriteHigh(GPIO_TypeDef GPIOx, uint8_t PortPins) + 221 { + 222 1 if(GPIOx == GPIO0) + 223 1 { + 224 2 P0 |= PortPins; + 225 2 } + 226 1 if(GPIOx == GPIO1) + 227 1 { + 228 2 P1 |= PortPins; + 229 2 } + C51 COMPILER V9.01 SC92F_GPIO 09/11/2020 09:48:38 PAGE 5 + + 230 1 if(GPIOx == GPIO2) + 231 1 { + 232 2 P2 |= PortPins; + 233 2 } + 234 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2) + if(GPIOx == GPIO3) + { + P3 |= PortPins; + } + if(GPIOx == GPIO4) + { + P4 |= PortPins; + } + #endif + 244 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + - (SC92F736xB) + if(GPIOx == GPIO5) + { + P5 |= PortPins; + } + #endif + 250 1 } + 251 + 252 /************************************************** + 253 *ƣvoid GPIO_WriteLow(GPIO_TypeDef GPIOx, uint8_t PortPins) + 254 *ܣGPIOڹܽPxyλ + 255 *ڲGPIOx ѡGPIO + 256 PortPins ѡGPIOڹܽPxy + 257 *ڲvoid + 258 **************************************************/ + 259 void GPIO_WriteLow(GPIO_TypeDef GPIOx, uint8_t PortPins) + 260 { + 261 1 if(GPIOx == GPIO0) + 262 1 { + 263 2 P0 &= ~PortPins; + 264 2 } + 265 1 if(GPIOx == GPIO1) + 266 1 { + 267 2 P1 &= ~PortPins; + 268 2 } + 269 1 if(GPIOx == GPIO2) + 270 1 { + 271 2 P2 &= ~PortPins; + 272 2 } + 273 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2) + if(GPIOx == GPIO3) + { + P3 &= ~PortPins; + } + if(GPIOx == GPIO4) + { + P4 &= ~PortPins; + } + #endif + 283 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + - (SC92F736xB) + if(GPIOx == GPIO5) + { + C51 COMPILER V9.01 SC92F_GPIO 09/11/2020 09:48:38 PAGE 6 + + P5 &= ~PortPins; + } + #endif + 289 1 } + 290 + 291 /************************************************** + 292 *ƣuint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx) + 293 *ܣGPIOPxֵ + 294 *ڲGPIOx ѡGPIO + 295 *ڲuint8_t Pxֵ + 296 **************************************************/ + 297 uint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx) + 298 { + 299 1 if(GPIOx == GPIO0) + 300 1 { + 301 2 return P0; + 302 2 } + 303 1 else if(GPIOx == GPIO1) + 304 1 { + 305 2 return P1; + 306 2 } + 307 1 else if(GPIOx == GPIO2) + 308 1 { + 309 2 return P2; + 310 2 } + 311 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2) + else if(GPIOx == GPIO3) + { + return P3; + } + else if(GPIOx == GPIO4) + { + return P4; + } + #endif + 321 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + - (SC92F736xB) + else + { + return P5; + } + #endif + 327 1 return 0; + 328 1 } + 329 + 330 /************************************************** + 331 *ƣBitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, uint8_t PortPins) + 332 *ܣGPIOڹܽPxyֵ + 333 *ڲGPIOx ѡGPIO + 334 PortPins ѡGPIOڹܽPxy + 335 *ڲBitStatus Pxyֵ + 336 **************************************************/ + 337 BitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, uint8_t PortPins) + 338 { + 339 1 if(GPIOx == GPIO0) + 340 1 { + 341 2 return ((BitStatus)(P0 & PortPins)); + 342 2 } + 343 1 else if(GPIOx == GPIO1) + 344 1 { + C51 COMPILER V9.01 SC92F_GPIO 09/11/2020 09:48:38 PAGE 7 + + 345 2 return ((BitStatus)(P1 & PortPins)); + 346 2 } + 347 1 else if(GPIOx == GPIO2) + 348 1 { + 349 2 return ((BitStatus)(P2 & PortPins)); + 350 2 } + 351 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2) + else if(GPIOx == GPIO3) + { + return ((BitStatus)(P3 & PortPins)); + } + else if(GPIOx == GPIO4) + { + return ((BitStatus)(P4 & PortPins)); + } + #endif + 361 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined + -(SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + - (SC92F736xB) + else if(GPIOx == GPIO5) + { + return ((BitStatus)(P5 & PortPins)); + } + #endif + 367 1 return 0; + 368 1 } + 369 + 370 /******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 220 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/CFG/SC92F8363B/Keil_Mould/List/sc92f_option.lst b/CFG/SC92F8363B/Keil_Mould/List/sc92f_option.lst new file mode 100644 index 0000000..07dd1ad --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/List/sc92f_option.lst @@ -0,0 +1,187 @@ +C51 COMPILER V9.01 SC92F_OPTION 09/11/2020 09:48:38 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE SC92F_OPTION +OBJECT MODULE PLACED IN ..\Output\sc92f_option.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_option.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib + -\inc;..\User) DEBUG PRINT(..\List\sc92f_option.lst) OBJECT(..\Output\sc92f_option.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : sc92f_option.c + 4 // : + 5 // ģ鹦 : Customer OptionĴCļ + 6 // ֲб: + 7 // : 2020/8/18 + 8 // 汾 : V1.0 + 9 // ˵ + 10 //************************************************************* + 11 + 12 #include "sc92f_option.h" + 13 + 14 /***************************************************** + 15 *ƣvoid OPTION_WDT_Cmd(FunctionalState NewState) + 16 *ܣWDTܿغ + 17 *ڲFunctionalState NewState /رѡ + 18 *ڲvoid + 19 *****************************************************/ + 20 void OPTION_WDT_Cmd(FunctionalState NewState) + 21 { + 22 1 OPINX = 0XC1; + 23 1 if(NewState == DISABLE) + 24 1 { + 25 2 OPREG &= 0X7F; + 26 2 } + 27 1 else + 28 1 { + 29 2 OPREG |= 0X80; + 30 2 } + 31 1 } + 32 + 33 /***************************************************** + 34 *ƣvoid OPTION_XTIPLL_Cmd(FunctionalState NewState) + 35 *ܣⲿƵʹ + 36 *ڲFunctionalState NewState /رѡ + 37 *ڲvoid + 38 *****************************************************/ + 39 void OPTION_XTIPLL_Cmd(FunctionalState NewState) + 40 { + 41 1 OPINX = 0XC1; + 42 1 if(NewState == DISABLE) + 43 1 { + 44 2 OPREG &= 0XBF; + 45 2 } + 46 1 else + 47 1 { + 48 2 OPREG |= 0X40; + 49 2 } + 50 1 } + 51 + 52 /***************************************************** + 53 *ƣvoid OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef SYSCLK_PresSel) + 54 *ܣϵͳʱӷƵʼ + C51 COMPILER V9.01 SC92F_OPTION 09/11/2020 09:48:38 PAGE 2 + + 55 *ڲSYSCLK_PresSel ѡϵͳʱӷƵ + 56 *ڲvoid + 57 *****************************************************/ + 58 void OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef SYSCLK_PresSel) + 59 { + 60 1 OPINX = 0XC1; + 61 1 OPREG = OPREG & 0XCF | SYSCLK_PresSel; + 62 1 } + 63 + 64 /***************************************************** + 65 *ƣvoid OPTION_RST_PIN_Cmd(FunctionalState NewState) + 66 *ܣⲿλܽţP17ʹ + 67 *ڲFunctionalState NewState ʹ/رѡ + 68 *ڲvoid + 69 *****************************************************/ + 70 void OPTION_RST_PIN_Cmd(FunctionalState NewState) + 71 { + 72 1 OPINX = 0XC1; + 73 1 if(NewState == DISABLE) + 74 1 { + 75 2 OPREG |= 0X08; + 76 2 } + 77 1 else + 78 1 { + 79 2 OPREG &= 0XF7; + 80 2 } + 81 1 } + 82 + 83 /***************************************************** + 84 *ƣvoid OPTION_LVR_Init(LVR_Config_TypeDef LVR_Config) + 85 *ܣLVR ѹѡ + 86 *ڲLVR_Config ѡLVRѹ + 87 *ڲvoid + 88 *****************************************************/ + 89 void OPTION_LVR_Init(LVR_Config_TypeDef LVR_Config) + 90 { + 91 1 OPINX = 0XC1; + 92 1 OPREG = OPREG & 0XF8 | LVR_Config; + 93 1 } + 94 + 95 /***************************************************** + 96 *ƣvoid OPTION_ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) + 97 *ܣADC οѹѡ + 98 *ڲADC_Vref ѡADCοѹ + 99 *ڲvoid + 100 *****************************************************/ + 101 void OPTION_ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) + 102 { + 103 1 OPINX = 0xC2; + 104 1 OPREG = OPREG & 0X7F | ADC_Vref; + 105 1 } + 106 + 107 /************************************************** + 108 *ƣvoid OPTION_IAP_SetOperateRange(IAP_OperateRange_TypeDef IAP_OperateRange) + 109 *ܣIAPķΧ + 110 *ڲIAP_OperateRange IAPΧ + 111 *ڲvoid + 112 **************************************************/ + 113 void OPTION_IAP_SetOperateRange(IAP_OperateRange_TypeDef IAP_OperateRange) + 114 { + 115 1 OPINX = 0xC2; + 116 1 OPREG = (OPREG & 0xF3) | IAP_OperateRange; + C51 COMPILER V9.01 SC92F_OPTION 09/11/2020 09:48:38 PAGE 3 + + 117 1 } + 118 + 119 #if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined + - (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax)|| defined (SC92F8003)|| defined (SC92F7 + -42x) + 120 /***************************************************** + 121 *ƣvoid OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef XTIPLL_Range) + 122 *ܣⲿƵƵʷΧ + 123 *ڲXTIPLL_Range ⲿƵѡ + 124 *ڲvoid + 125 *****************************************************/ + 126 void OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef XTIPLL_Range) + 127 { + 128 1 OPINX = 0XC2; + 129 1 OPREG = OPREG & 0XBF | XTIPLL_Range; + 130 1 } + 131 #endif + 132 + 133 #if defined (SC92F742x)||defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92 + -F74Ax) ||defined (SC92F74Ax_2)||defined (SC92F84Ax_2) + /************************************************** + *ƣvoid OPTION_JTAG_Cmd(FunctionalState NewState) + *ܣJTAGģʽʹܿ + *ڲFunctionalState NewState /رѡ + *ڲvoid + **************************************************/ + void OPTION_JTAG_Cmd(FunctionalState NewState) + { + OPINX = 0xC2; + if(NewState == DISABLE) + { + OPREG |= 0X10; //1 JTAGЧ + } + else + { + OPREG &= 0XEF; //0 JTAGЧ + } + } + #endif + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 97 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/CFG/SC92F8363B/Keil_Mould/List/sc92f_pwm.lst b/CFG/SC92F8363B/Keil_Mould/List/sc92f_pwm.lst new file mode 100644 index 0000000..ec3ad96 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/List/sc92f_pwm.lst @@ -0,0 +1,945 @@ +C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE SC92F_PWM +OBJECT MODULE PLACED IN ..\Output\sc92f_pwm.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_pwm.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib\in + -c;..\User) DEBUG PRINT(..\List\sc92f_pwm.lst) OBJECT(..\Output\sc92f_pwm.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : sc92f_pwm.c + 4 // : + 5 // ģ鹦 : PWM̼⺯Cļ + 6 // ֲб: + 7 // : 2020/8/18 + 8 // 汾 : V1.0 + 9 // ˵ ļԪ92FϵеƬ + 10 //************************************************************* + 11 + 12 #include "sc92f_pwm.h" + 13 + 14 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2) + uint16_t xdata PWMREG[8] _at_ 0x740; //PWMռձȵڼĴ + uint16_t pwm_tmpreg[8] = {0,0,0,0,0,0,0,0}; //PWMռձȵڼĴ + + /************************************************** + *ƣvoid PWM_DeInit(void) + *ܣPWMؼĴλȱʡֵ + *ڲvoid + *ڲvoid + **************************************************/ + void PWM_DeInit(void) + { + static uint8_t i; + PWMCFG = 0X00; + PWMCON = 0X00; + IE1 &= 0XFD; + IP1 &= 0XFD; + for(i=0;i<8;i++) + { + PWMREG[i] = 0; + } + } + + /************************************************** + *ƣvoid PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) + *ܣPWMʼú + *ڲPWM_PresSel ԤƵѡ + PWM_Period PWM + *ڲvoid + **************************************************/ + void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) + { + PWM_Period -= 1; + PWMCFG = (PWMCFG & 0XCF) | PWM_PresSel; //ԤƵ + PWMCFG = (PWMCFG & 0XF0) | (uint8_t)(PWM_Period / 256); //ڸ4λ + PWMCON = (uint8_t)(PWM_Period & 0X00FF); //ڵ8λ + } + + /************************************************** + *ƣvoid PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 2 + + *ܣPWMxʹ/ʧú + *ڲPWM_OutputPin PWMxѡ + PWM_OutputState PWM״̬ + *ڲvoid + **************************************************/ + void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + { + uint8_t i; + for(i=0;i<8;i++) + { + if(PWM_OutputPin&(0x01<> 2); //ڸ߰λ + } + + /************************************************** + *ƣvoid PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + *ܣPWMxʹ/ʧú + *ڲPWM_OutputPin PWMxѡ + PWM_OutputState PWM״̬ + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 5 + + *ڲvoid + **************************************************/ + void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + { + if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON |= PWM_OutputPin; + } + else + { + PWMCON &= (~PWM_OutputPin); + } + } + + /************************************************** + *ƣvoid PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) + *ܣPWMx/ú + *ڲPWM_OutputPin PWMxѡ + PWM_Polarity PWM/ + *ڲvoid + **************************************************/ + void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) + { + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= PWM_OutputPin; + } + else + { + PWMCFG &= (~PWM_OutputPin); + } + } + + /************************************************** + *ƣvoid PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) + *ܣPWMxģʽú + *ڲPWM_OutputPin PWMxͨѡ + PWM_DutyCycle PWMռձ + *ڲvoid + **************************************************/ + void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) + { + PWMDTYB &= 0X7F; //PWMΪģʽ + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTYA = PWMDTYA & 0xfc | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM1: + PWMDTYA = PWMDTYA & 0xf3 | ((PWM_DutyCycle % 4) << 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM2: + PWMDTYA = PWMDTYA & 0xcf | ((PWM_DutyCycle % 4) << 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM3: + PWMDTYB = PWMDTYB & 0xfc | (PWM_DutyCycle % 4); + PWMDTY3 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM4: + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 6 + + PWMDTYB = PWMDTYB & 0xf3 | ((PWM_DutyCycle % 4) << 2); + PWMDTY4 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM5: + PWMDTYB = PWMDTYB & 0xcf | ((PWM_DutyCycle % 4) << 4); + PWMDTY5 = (uint8_t)(PWM_DutyCycle >> 2); + break; + default: + break; + } + } + + /************************************************** + *ƣvoid PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, + - uint16_t PWM_DutyCycle) + *ܣPWMxPWMyģʽú + *ڲPWM_ComplementaryOutputPin PWMxPWMyͨѡ + PWM_DutyCycle PWMռձ + *ڲvoid + **************************************************/ + void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t P + -WM_DutyCycle) + { + PWMDTYB |= 0X80; //PWMΪģʽ + switch(PWM_ComplementaryOutputPin) //ռձ + { + case PWM0PWM3: + PWMDTYA = PWMDTYA & 0xfc | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM1PWM4: + PWMDTYA = PWMDTYA & 0xf3 | ((PWM_DutyCycle % 4) << 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM2PWM5: + PWMDTYA = PWMDTYA & 0xcf | ((PWM_DutyCycle % 4) << 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + default: + break; + } + } + + /************************************************** + *ƣvoid PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) + *ܣPWMģʽʱú + *ڲPWM012_RisingDeadTime PWMʱ + PWM345_fallingDeadTime PWM½ʱ + *ڲvoid + **************************************************/ + void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) + { + PWMDTY3 = (PWM012_RisingDeadTime | (PWM345_fallingDeadTime << 4)); + } + + /***************************************************** + *ƣvoid PWM_Cmd(FunctionalState NewState) + *ܣPWMܿغ + *ڲFunctionalState NewState /رѡ + *ڲvoid + *****************************************************/ + void PWM_Cmd(FunctionalState NewState) + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 7 + + { + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } + } + + /***************************************************** + *ƣvoid PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) + *ܣPWMжϳʼ + *ڲFunctionalState NewState жʹ/رѡ + PriorityStatus Priority жȼѡ + *ڲvoid + *****************************************************/ + void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) + { + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= 0XFD; + } + else + { + IP1 |= 0X02; + } + } + + /***************************************************** + *ƣFlagStatus PWM_GetFlagStatus(void) + *ܣPWMжϱ־״̬ + *ڲvoid + *ڲFlagStatus PWMжϱ־״̬ + *****************************************************/ + FlagStatus PWM_GetFlagStatus(void) + { + return (FlagStatus)(PWMCON & 0X40); + } + + /***************************************************** + *ƣvoid PWM_ClearFlag(void) + *ܣPWMжϱ־״̬ + *ڲvoid + *ڲvoid + *****************************************************/ + void PWM_ClearFlag(void) + { + PWMCON &= 0XBF; + } + #endif + 422 + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 8 + + 423 + 424 + 425 + 426 + 427 + 428 + 429 + 430 + 431 #if defined (SC92F8003) + 432 /************************************************** + 433 *ƣvoid PWM_DeInit(void) + 434 *ܣPWMؼĴλȱʡֵ + 435 *ڲvoid + 436 *ڲvoid + 437 **************************************************/ + 438 void PWM_DeInit(void) + 439 { + 440 1 PWMCFG = 0X00; + 441 1 PWMCON0 = 0X00; + 442 1 PWMPRD = 0X00; + 443 1 PWMDTYA = 0X00; + 444 1 PWMDTY0 = 0X00; + 445 1 PWMDTY1 = 0X00; + 446 1 PWMDTY2 = 0X00; + 447 1 PWMCON1 = 0X00; + 448 1 PWMDTYB = 0X00; + 449 1 PWMDTY3 = 0X00; + 450 1 PWMDTY4 = 0X00; + 451 1 PWMDTY5 = 0X00; + 452 1 PWMDTY6 = 0X00; + 453 1 IE1 &= 0XFD; + 454 1 IP1 &= 0XFD; + 455 1 } + 456 + 457 /************************************************** + 458 *ƣvoid PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) + 459 *ܣPWMʼú + 460 *ڲPWM_PresSel ԤƵѡ + 461 PWM_Period PWM + 462 *ڲvoid + 463 **************************************************/ + 464 void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) + 465 { + 466 1 PWM_Period -= 1; + 467 1 PWMCON0 = (PWMCON0 & 0XCC) | PWM_PresSel | (uint8_t)(PWM_Period & 0X0003); //ԤƵڵĵ2λ + 468 1 PWMPRD = (uint8_t)(PWM_Period >> 2); //ڸ߰λ + 469 1 } + 470 + 471 /************************************************** + 472 *ƣvoid PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + 473 *ܣPWMxʹ/ʧú + 474 *ڲPWM_OutputPin PWMxѡ + 475 PWM_OutputState PWM״̬ + 476 *ڲvoid + 477 **************************************************/ + 478 void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + 479 { + 480 1 if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + 481 1 { + 482 2 PWMCON1 |= PWM_OutputPin; + 483 2 } + 484 1 else + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 9 + + 485 1 { + 486 2 PWMCON1 &= (~PWM_OutputPin); + 487 2 } + 488 1 } + 489 + 490 /************************************************** + 491 *ƣvoid PWM_PWM2Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin) + 492 *ܣPWM2ܽѡ + 493 *ڲPWM2_OutputPin PWM2ܽѡ + 494 *ڲvoid + 495 **************************************************/ + 496 void PWM_PWM2Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin) + 497 { + 498 1 PWMCON0 = PWMCON0 & 0XFB | PWM2_OutputPin; + 499 1 } + 500 + 501 /************************************************** + 502 *ƣvoid PWM_PWM5Selection(PWM5_OutputPin_TypeDef PWM5_OutputPin) + 503 *ܣPWM5ܽѡ + 504 *ڲPWM5_OutputPin PWM5ܽѡ + 505 *ڲvoid + 506 **************************************************/ + 507 void PWM_PWM5Selection(PWM5_OutputPin_TypeDef PWM5_OutputPin) + 508 { + 509 1 PWMCON0 = PWMCON0 & 0XF7 | PWM5_OutputPin; + 510 1 } + 511 + 512 /************************************************** + 513 *ƣvoid PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) + 514 *ܣPWMx/ú + 515 *ڲPWM_OutputPin PWMxѡ + 516 PWM_Polarity PWM/ + 517 *ڲvoid + 518 **************************************************/ + 519 void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) + 520 { + 521 1 if(PWM_Polarity == PWM_POLARITY_INVERT) + 522 1 { + 523 2 PWMCFG |= PWM_OutputPin; + 524 2 } + 525 1 else + 526 1 { + 527 2 PWMCFG &= (~PWM_OutputPin); + 528 2 } + 529 1 } + 530 + 531 /************************************************** + 532 *ƣvoid PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) + 533 *ܣPWMxģʽú + 534 *ڲPWM_OutputPin PWMxͨѡ + 535 PWM_DutyCycle PWMռձ + 536 *ڲvoid + 537 **************************************************/ + 538 void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) + 539 { + 540 1 if(PWM_OutputPin!=PWM6) + 541 1 { + 542 2 PWMCON1 &= 0X7F; //PWMΪģʽ + 543 2 } + 544 1 switch(PWM_OutputPin) //ռձ + 545 1 { + 546 2 case PWM0: + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 10 + + 547 2 PWMDTYA = PWMDTYA & 0XFC | (PWM_DutyCycle % 4); + 548 2 PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + 549 2 break; + 550 2 case PWM1: + 551 2 PWMDTYA = PWMDTYA & 0XF3 | ((PWM_DutyCycle % 4) << 2); + 552 2 PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + 553 2 break; + 554 2 case PWM2: + 555 2 PWMDTYA = PWMDTYA & 0XCF | ((PWM_DutyCycle % 4) << 4); + 556 2 PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + 557 2 break; + 558 2 case PWM3: + 559 2 PWMDTYA = PWMDTYA & 0X3F | ((PWM_DutyCycle % 4) << 6); + 560 2 PWMDTY3 = (uint8_t)(PWM_DutyCycle >> 2); + 561 2 break; + 562 2 case PWM4: + 563 2 PWMDTYB = PWMDTYB & 0XFC | (PWM_DutyCycle % 4); + 564 2 PWMDTY4 = (uint8_t)(PWM_DutyCycle >> 2); + 565 2 break; + 566 2 case PWM5: + 567 2 PWMDTYB = PWMDTYB & 0XF3 | ((PWM_DutyCycle % 4) << 2); + 568 2 PWMDTY5 = (uint8_t)(PWM_DutyCycle >> 2); + 569 2 break; + 570 2 case PWM6: + 571 2 PWMDTYB = PWMDTYB & 0XCF | ((PWM_DutyCycle % 4) << 4); + 572 2 PWMDTY6 = (uint8_t)(PWM_DutyCycle >> 2); + 573 2 break; + 574 2 default: + 575 2 break; + 576 2 } + 577 1 } + 578 + 579 /************************************************** + 580 *ƣvoid PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, + - uint16_t PWM_DutyCycle) + 581 *ܣPWMxPWMyģʽú + 582 *ڲPWM_ComplementaryOutputPin PWMxPWMyͨѡ + 583 PWM_DutyCycle PWMռձ + 584 *ڲvoid + 585 **************************************************/ + 586 void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t P + -WM_DutyCycle) + 587 { + 588 1 PWMCON1 |= 0X80; //PWMΪģʽ + 589 1 switch(PWM_ComplementaryOutputPin) //ռձ + 590 1 { + 591 2 case PWM0PWM3: + 592 2 PWMDTYA = PWMDTYA & 0XFC | (PWM_DutyCycle % 4); + 593 2 PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + 594 2 break; + 595 2 case PWM1PWM4: + 596 2 PWMDTYA = PWMDTYA & 0XF3 | ((PWM_DutyCycle % 4) << 2); + 597 2 PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + 598 2 break; + 599 2 case PWM2PWM5: + 600 2 PWMDTYA = PWMDTYA & 0XCF | ((PWM_DutyCycle % 4) << 4); + 601 2 PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + 602 2 break; + 603 2 default: + 604 2 break; + 605 2 } + 606 1 } + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 11 + + 607 + 608 /************************************************** + 609 *ƣvoid PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) + 610 *ܣPWMģʽʱú + 611 *ڲPWM012_RisingDeadTime PWMʱ + 612 PWM345_fallingDeadTime PWM½ʱ + 613 *ڲvoid + 614 **************************************************/ + 615 void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) + 616 { + 617 1 PWMDTY3 = (PWM012_RisingDeadTime | (PWM345_fallingDeadTime << 4)); + 618 1 } + 619 + 620 /***************************************************** + 621 *ƣvoid PWM_Cmd(FunctionalState NewState) + 622 *ܣPWMܿغ + 623 *ڲFunctionalState NewState /رѡ + 624 *ڲvoid + 625 *****************************************************/ + 626 void PWM_Cmd(FunctionalState NewState) + 627 { + 628 1 if (NewState != DISABLE) + 629 1 { + 630 2 PWMCON0 |= 0X80; + 631 2 } + 632 1 else + 633 1 { + 634 2 PWMCON0 &= ~0X80; + 635 2 } + 636 1 } + 637 + 638 /***************************************************** + 639 *ƣvoid PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) + 640 *ܣPWMжϳʼ + 641 *ڲFunctionalState NewState жʹ/رѡ + 642 PriorityStatus Priority жȼѡ + 643 *ڲvoid + 644 *****************************************************/ + 645 void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) + 646 { + 647 1 if (NewState != DISABLE) + 648 1 { + 649 2 IE1 |= 0X02; + 650 2 } + 651 1 else + 652 1 { + 653 2 IE1 &= 0XFD; + 654 2 } + 655 1 + 656 1 if(Priority == LOW) + 657 1 { + 658 2 IP1 &= 0XFD; + 659 2 } + 660 1 else + 661 1 { + 662 2 IP1 |= 0X02; + 663 2 } + 664 1 } + 665 + 666 /***************************************************** + 667 *ƣFlagStatus PWM_GetFlagStatus(void) + 668 *ܣPWMжϱ־״̬ + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 12 + + 669 *ڲvoid + 670 *ڲFlagStatus PWMжϱ־״̬ + 671 *****************************************************/ + 672 FlagStatus PWM_GetFlagStatus(void) + 673 { + 674 1 return (FlagStatus)(PWMCON0 & 0X40); + 675 1 } + 676 + 677 /***************************************************** + 678 *ƣvoid PWM_ClearFlag(void) + 679 *ܣPWMжϱ־״̬ + 680 *ڲvoid + 681 *ڲvoid + 682 *****************************************************/ + 683 void PWM_ClearFlag(void) + 684 { + 685 1 PWMCON0 &= 0XBF; + 686 1 } + 687 #endif + 688 + 689 + 690 + 691 + 692 + 693 + 694 + 695 + 696 + 697 + 698 + 699 + 700 #if defined (SC92F742x) + /************************************************** + *ƣvoid PWM_DeInit(void) + *ܣPWMؼĴλȱʡֵ + *ڲvoid + *ڲvoid + **************************************************/ + void PWM_DeInit(void) + { + PWMCFG0 = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMCFG1 = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; + PWMDTY3 = 0X00; + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; + IE1 &= ~0X02; + IP1 &= ~0X02; + } + + /************************************************** + *ƣvoid PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) + *ܣPWMʼú + *ڲPWM_PresSel ԤƵѡ + PWM_Period PWM + *ڲvoid + **************************************************/ + void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 13 + + { + PWM_Period -= 1; + PWMCON = (PWMCON & 0XF8) | PWM_PresSel; //ԤƵ + PWMPRD = PWM_Period; // + } + + /************************************************** + *ƣvoid PWM_OutputStateConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_OutputState_TypeDef PWM_Out + -putState) + *ܣPWMxʹ/ʧú + *ڲPWM_OutputPin PWMxѡ + PWM_OutputState PWM״̬ + *ڲvoid + **************************************************/ + void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + { + if(PWM_OutputState==PWM_OUTPUTSTATE_DISABLE) + { + PWMCON = PWMCON & (~(PWM_OutputPin&0x38)); + PWMCFG0 = PWMCFG0 & (~(PWM_OutputPin&0x07)); + } + else + { + PWMCON = PWMCON | (PWM_OutputPin&0x38); + PWMCFG0 = PWMCFG0 |(PWM_OutputPin&0x07); + } + } + + /************************************************** + *ƣvoid PWM_PolarityConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) + *ܣPWMx/ú + *ڲPWM_OutputPin PWMxѡ + PWM_Polarity PWM/ + *ڲvoid + **************************************************/ + void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) + { + if(PWM_Polarity==PWM_POLARITY_NON_INVERT) + { + PWMCFG0 = PWMCFG0 & (~(PWM_OutputPin&0x38)); + PWMCFG1 = PWMCFG1 & (~((PWM_OutputPin<<3)&0x38)); + } + else + { + PWMCFG0 = PWMCFG0 | (PWM_OutputPin&0x38); + PWMCFG1 = PWMCFG1 |((PWM_OutputPin<<3)&0x38); + } + } + + /************************************************** + *ƣvoid PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) + *ܣPWMxģʽú + *ڲPWM_OutputPin PWMxͨѡ + PWM_DutyCycle PWMռձ + *ڲvoid + **************************************************/ + void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) + { + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTY0 = PWM_DutyCycle; + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 14 + + break; + case PWM1: + PWMDTY1 = PWM_DutyCycle; + break; + case PWM2: + PWMDTY2 = PWM_DutyCycle; + break; + case PWM3: + PWMDTY3 = PWM_DutyCycle; + break; + case PWM4: + PWMDTY4 = PWM_DutyCycle; + break; + case PWM5: + PWMDTY5 = PWM_DutyCycle; + break; + default: + break; + } + } + + /***************************************************** + *ƣvoid PWM_Cmd(FunctionalState NewState) + *ܣPWMܿغ + *ڲFunctionalState NewState /رѡ + *ڲvoid + *****************************************************/ + void PWM_Cmd(FunctionalState NewState) + { + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } + } + + /***************************************************** + *ƣvoid PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) + *ܣPWMжϳʼ + *ڲFunctionalState NewState жʹ/رѡ + PriorityStatus Priority жȼѡ + *ڲvoid + *****************************************************/ + void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) + { + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= ~0X02; + } + + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 15 + + { + IP1 |= 0X02; + } + } + + /***************************************************** + *ƣFlagStatus PWM_GetFlagStatus(void) + *ܣPWMжϱ־״̬ + *ڲvoid + *ڲFlagStatus PWMжϱ־״̬ + *****************************************************/ + FlagStatus PWM_GetFlagStatus(void) + { + return (FlagStatus)(PWMCON & 0X40); + } + + /***************************************************** + *ƣvoid PWM_ClearFlag(void) + *ܣPWMжϱ־״̬ + *ڲvoid + *ڲvoid + *****************************************************/ + void PWM_ClearFlag(void) + { + PWMCON &= 0XBF; + } + #endif + 881 + 882 /******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 504 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/CFG/SC92F8363B/Keil_Mould/List/sc92f_pwr.lst b/CFG/SC92F8363B/Keil_Mould/List/sc92f_pwr.lst new file mode 100644 index 0000000..d994f8e --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/List/sc92f_pwr.lst @@ -0,0 +1,92 @@ +C51 COMPILER V9.01 SC92F_PWR 09/11/2020 09:48:39 PAGE 1 + + +C51 COMPILER V9.01, COMPILATION OF MODULE SC92F_PWR +OBJECT MODULE PLACED IN ..\Output\sc92f_pwr.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_pwr.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib\in + -c;..\User) DEBUG PRINT(..\List\sc92f_pwr.lst) OBJECT(..\Output\sc92f_pwr.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : sc92f_pwr.c + 4 // : + 5 // ģ鹦 : PWR̼⺯Cļ + 6 // ֲб: + 7 // : 2020/8/18 + 8 // 汾 : V1.0 + 9 // ˵ ļԪ92FϵеƬ + 10 //************************************************************* + 11 #include "sc92f_pwr.h" + 12 + 13 /************************************************** + 14 *ƣvoid PWR_DeInit(void) + 15 *ܣPWRؼĴλȱʡֵ + 16 *ڲvoid + 17 *ڲvoid + 18 **************************************************/ + 19 void PWR_DeInit(void) + 20 { + 21 1 PCON &= 0XFC; + 22 1 } + 23 + 24 /************************************************** + 25 *ƣvoid PWR_EnterSTOPMode(void) + 26 *ܣMCUSTOPģʽ + 27 *ڲvoid + 28 *ڲvoid + 29 **************************************************/ + 30 void PWR_EnterSTOPMode(void) + 31 { + 32 1 PCON |= 0X02; + 33 1 _nop_(); + 34 1 _nop_(); + 35 1 _nop_(); + 36 1 _nop_(); + 37 1 _nop_(); + 38 1 _nop_(); + 39 1 _nop_(); + 40 1 _nop_(); + 41 1 } + 42 + 43 /************************************************** + 44 *ƣvoid PWR_EnterIDLEMode(void) + 45 *ܣMCUIDLEģʽ + 46 *ڲvoid + 47 *ڲvoid + 48 **************************************************/ + 49 void PWR_EnterIDLEMode(void) + 50 { + 51 1 PCON |= 0X01; + 52 1 _nop_(); + 53 1 _nop_(); + 54 1 _nop_(); + C51 COMPILER V9.01 SC92F_PWR 09/11/2020 09:48:39 PAGE 2 + + 55 1 _nop_(); + 56 1 _nop_(); + 57 1 _nop_(); + 58 1 _nop_(); + 59 1 _nop_(); + 60 1 } + 61 + 62 /******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 28 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/CFG/SC92F8363B/Keil_Mould/Output/project name b/CFG/SC92F8363B/Keil_Mould/Output/project name new file mode 100644 index 0000000000000000000000000000000000000000..a71e9d91d911722566c37ae4f0926bbc2f121838 GIT binary patch literal 169072 zcmeFa34C1DbwB=QELpOwk!)lzUZ&o$wo*D4K-~NNYm1!S^E1mzh-SA1jr5{TmMO#t-mH|l4fhtqzMVX^S$?-_wIRb z?zsIS_5Vvg%;)3fzI*Sv+qvhS?Vfw^WA)E0_I9K;p4HkqHZngsH+G;rHPbqA*2dw% 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+
Vision Build Log

+
Project:

+E:\\Ŀ\BSP\SC92FϵͨBSPV0.0.1\Keil_Mould\Project\project name.uvproj
+Project File Date:  09/02/2020
+
+
Output:

+
+ + diff --git a/CFG/SC92F8363B/Keil_Mould/Output/project name.lnp b/CFG/SC92F8363B/Keil_Mould/Output/project name.lnp new file mode 100644 index 0000000..cb1c9ce --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/Output/project name.lnp @@ -0,0 +1,11 @@ +"..\Output\main.obj", +"..\Output\SC_Init.obj", +"..\Output\SC_it.obj", +"..\Output\sc92f_gpio.obj", +"..\Output\sc92f_option.obj", +"..\Output\STARTUP.obj" +TO "..\Output\project name" + +PRINT("..\List\project name.map") REMOVEUNUSED +CLASSES (CODE(C:0X100), +CONST(C:0X100)) diff --git a/CFG/SC92F8363B/Keil_Mould/Output/sc92f_chksum.__i b/CFG/SC92F8363B/Keil_Mould/Output/sc92f_chksum.__i new file mode 100644 index 0000000..5ef1a8f --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/Output/sc92f_chksum.__i @@ -0,0 +1 @@ +"..\FWLib\SC92F_Lib\src\sc92f_chksum.c" OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User) DEBUG PRINT(..\List\sc92f_chksum.lst) OBJECT(..\Output\sc92f_chksum.obj) \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/Project/STARTUP.A51 b/CFG/SC92F8363B/Keil_Mould/Project/STARTUP.A51 new file mode 100644 index 0000000..7cf4ad8 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/Project/STARTUP.A51 @@ -0,0 +1,198 @@ +$NOMOD51 +;------------------------------------------------------------------------------ +; This file is part of the C51 Compiler package +; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc. +; Version 8.01 +; +; *** <<< Use Configuration Wizard in Context Menu >>> *** +;------------------------------------------------------------------------------ +; STARTUP.A51: This code is executed after processor reset. +; +; To translate this file use A51 with the following invocation: +; +; A51 STARTUP.A51 +; +; To link the modified STARTUP.OBJ file to your application use the following +; Lx51 invocation: +; +; Lx51 your object file list, STARTUP.OBJ controls +; +;------------------------------------------------------------------------------ +; +; User-defined Power-On Initialization of Memory +; +; With the following EQU statements the initialization of memory +; at processor reset can be defined: +; +; IDATALEN: IDATA memory size <0x0-0x100> +; Note: The absolute start-address of IDATA memory is always 0 +; The IDATA space overlaps physically the DATA and BIT areas. +IDATALEN EQU 100H +; +; XDATASTART: XDATA memory start address <0x0-0xFFFF> +; The absolute start address of XDATA memory +XDATASTART EQU 0 +; +; XDATALEN: XDATA memory size <0x0-0xFFFF> +; The length of XDATA memory in bytes. +XDATALEN EQU 100H +; +; PDATASTART: PDATA memory start address <0x0-0xFFFF> +; The absolute start address of PDATA memory +PDATASTART EQU 0H +; +; PDATALEN: PDATA memory size <0x0-0xFF> +; The length of PDATA memory in bytes. +PDATALEN EQU 0H +; +; +;------------------------------------------------------------------------------ +; +; Reentrant Stack Initialization +; +; The following EQU statements define the stack pointer for reentrant +; functions and initialized it: +; +; Stack Space for reentrant functions in the SMALL model. +; IBPSTACK: Enable SMALL model reentrant stack +; Stack space for reentrant functions in the SMALL model. +IBPSTACK EQU 0 ; set to 1 if small reentrant is used. +; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF> +; Set the top of the stack to the highest location. +IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +; Stack Space for reentrant functions in the LARGE model. +; XBPSTACK: Enable LARGE model reentrant stack +; Stack space for reentrant functions in the LARGE model. +XBPSTACK EQU 0 ; set to 1 if large reentrant is used. +; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1 +; +; +; Stack Space for reentrant functions in the COMPACT model. +; PBPSTACK: Enable COMPACT model reentrant stack +; Stack space for reentrant functions in the COMPACT model. +PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. +; +; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +;------------------------------------------------------------------------------ +; +; Memory Page for Using the Compact Model with 64 KByte xdata RAM +; Compact Model Page Definition +; +; Define the XDATA page used for PDATA variables. +; PPAGE must conform with the PPAGE set in the linker invocation. +; +; Enable pdata memory page initalization +PPAGEENABLE EQU 0 ; set to 1 if pdata object are used. +; +; PPAGE number <0x0-0xFF> +; uppermost 256-byte address of the page used for PDATA variables. +PPAGE EQU 0 +; +; SFR address which supplies uppermost address byte <0x0-0xFF> +; most 8051 variants use P2 as uppermost address byte +PPAGE_SFR DATA 0A0H +; +; +;------------------------------------------------------------------------------ + +; Standard SFR Symbols +ACC DATA 0E0H +B DATA 0F0H +SP DATA 81H +DPL DATA 82H +DPH DATA 83H + + NAME ?C_STARTUP + + +?C_C51STARTUP SEGMENT CODE +?STACK SEGMENT IDATA + + RSEG ?STACK + DS 1 + + EXTRN CODE (?C_START) + PUBLIC ?C_STARTUP + + CSEG AT 0 +?C_STARTUP: LJMP STARTUP1 + + RSEG ?C_C51STARTUP + +STARTUP1: + +IF IDATALEN <> 0 + MOV R0,#IDATALEN - 1 + CLR A +IDATALOOP: MOV @R0,A + DJNZ R0,IDATALOOP +ENDIF + +IF XDATALEN <> 0 + MOV DPTR,#XDATASTART + MOV R7,#LOW (XDATALEN) + IF (LOW (XDATALEN)) <> 0 + MOV R6,#(HIGH (XDATALEN)) +1 + ELSE + MOV R6,#HIGH (XDATALEN) + ENDIF + CLR A +XDATALOOP: MOVX @DPTR,A + INC DPTR + DJNZ R7,XDATALOOP + DJNZ R6,XDATALOOP +ENDIF + +IF PPAGEENABLE <> 0 + MOV PPAGE_SFR,#PPAGE +ENDIF + +IF PDATALEN <> 0 + MOV R0,#LOW (PDATASTART) + MOV R7,#LOW (PDATALEN) + CLR A +PDATALOOP: MOVX @R0,A + INC R0 + DJNZ R7,PDATALOOP +ENDIF + +IF IBPSTACK <> 0 +EXTRN DATA (?C_IBP) + + MOV ?C_IBP,#LOW IBPSTACKTOP +ENDIF + +IF XBPSTACK <> 0 +EXTRN DATA (?C_XBP) + + MOV ?C_XBP,#HIGH XBPSTACKTOP + MOV ?C_XBP+1,#LOW XBPSTACKTOP +ENDIF + +IF PBPSTACK <> 0 +EXTRN DATA (?C_PBP) + MOV ?C_PBP,#LOW PBPSTACKTOP +ENDIF + + MOV SP,#?STACK-1 + +; This code is required if you use L51_BANK.A51 with Banking Mode 4 +; Code Banking +; Select Bank 0 for L51_BANK.A51 Mode 4 +#if 0 +; Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4. +EXTRN CODE (?B_SWITCH0) + CALL ?B_SWITCH0 ; init bank mechanism to code bank 0 +#endif +; + LJMP ?C_START + + END diff --git a/CFG/SC92F8363B/Keil_Mould/Project/SinOne.soc b/CFG/SC92F8363B/Keil_Mould/Project/SinOne.soc new file mode 100644 index 0000000000000000000000000000000000000000..b1ac53340d45b009b2163c9fae7db151b9968399 GIT binary patch literal 254 zcmeZc@MBP52xmxT$YaQ2C}l8WFaSam1_p+|KyddiBaj6YU + + + -4.1 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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-16776800
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### uVision Project, (C) Keil Software
+ + + + <project name> + 0x0 + MCS-51 + + + SC92F8003 + SC92Fxx Series + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0-0xFF) CLOCK(16000000) + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 0 + SC92F8003.H + + + + + + + + + + 0 + + + + SOC\ + SOC\ + + 0 + 0 + 0 + 0 + 1 + + ..\Output\ + project name + 1 + 0 + 1 + 1 + 1 + ..\List\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 65535 + + + S8051.DLL + + DP51.DLL + -p51 + S8051.DLL + + TP51.DLL + -p51 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 9 + + + + + + + + + + + + + + SinOne_Chip\SOC_Debug_Driver\SinOne_Chip_Debug_Driver.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4101 + + SinOne_Chip\SOC_Debug_Driver\SinOne_Chip_Debug_Driver.dll + "" () + + + + + 2 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 0 + 0x0 + 0x100 + + + 0 + 0x0 + 0x100 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 8 + 2 + 0 + 1 + 1 + 0 + + + SC92F836xB + + ..\FWLib\SC92F_Lib\inc;..\User + + + + 0 + 1 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 2 + 1 + + REMOVEUNUSED + + + + + + CODE(C:0X100), +CONST(C:0X100) + + + + + + + + + + + + + + + + + + + + + User + + + main.c + 1 + ..\User\main.c + + + SC_Init.c + 1 + ..\User\SC_Init.c + + + SC_it.c + 1 + ..\User\SC_it.c + + + SysFunVarDefine.c + 1 + ..\User\SysFunVarDefine.c + + + CompCtrlDefine.c + 1 + ..\User\CompCtrlDefine.c + + + CallBackFunction.c + 1 + ..\User\CallBackFunction.c + + + + + Apps + + + Drivers + + + FWLib + + + sc92f_gpio.c + 1 + ..\FWLib\SC92F_Lib\src\sc92f_gpio.c + + + sc92f_option.c + 1 + ..\FWLib\SC92F_Lib\src\sc92f_option.c + + + + + Startup + + + STARTUP.A51 + 2 + .\STARTUP.A51 + + + + + + + + diff --git a/CFG/SC92F8363B/Keil_Mould/Project/project name_uvopt.bak b/CFG/SC92F8363B/Keil_Mould/Project/project name_uvopt.bak new file mode 100644 index 0000000..17da3b7 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/Project/project name_uvopt.bak @@ -0,0 +1,1683 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + + + + 0 + 0 + + + + <project name> + 0x0 + MCS-51 + + 16000000 + + 1 + 1 + 1 + 0 + + + 0 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + ..\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + S8051.DLL + + DP51.DLL + -p51 + S8051.DLL + + TP51.DLL + -p51 + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 9 + + + + + + + + + + + SinOne_Chip\SOC_Debug_Driver\SinOne_Chip_Debug_Driver.dll + + + + 0 + DLGDP51 + (98=-1,-1,-1,-1,0)(82=-1,-1,-1,-1,0)(83=-1,-1,-1,-1,0)(84=-1,-1,-1,-1,0)(85=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(91=-1,-1,-1,-1,0)(92=-1,-1,-1,-1,0) + + + 0 + DLGTP51 + (98=-1,-1,-1,-1,0)(82=-1,-1,-1,-1,0)(83=-1,-1,-1,-1,0)(84=-1,-1,-1,-1,0)(85=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(91=-1,-1,-1,-1,0)(92=-1,-1,-1,-1,0) + + + 0 + SinOne_Chip_Debug_Driver + + + + + + 0 + 0 + 20 + 1 +
-16776800
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sc92f_gpio.c + + + 4 + 7 + 1 + 0 + 0 + 16793171 + 0 + 63189640 + 7280300 + 0 + ..\FWLib\SC92F_Lib\src\sc92f_option.c + sc92f_option.c + + + + + Startup + 1 + 0 + 0 + + 5 + 8 + 2 + 0 + 0 + 16793171 + 0 + 63189560 + 7280300 + 0 + .\STARTUP.A51 + STARTUP.A51 + + + + + + 0 + + 0 + + Default + 1 + + 59392 + 1 + File + 0 + + 0 + + 1 + 2 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 100 + 0 + 1 + 0 + + + 59398 + 2 + Build + 0 + + 0 + + 1 + 2 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 100 + 0 + 0 + 0 + + + 59399 + 3 + Debug + 0 + + 0 + + 1 + 2 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 100 + 0 + 1 + 0 + + + 197 + 4 + Build Output + 0 + + 0 + + 1 + 2 + 4 + 0 + 0 + 0 + 210 + 600 + 0 + 0 + 250 + 600 + 100 + 1 + 0 + 0 + + + 198 + 5 + Command + 197 + + 197 + + 1 + 4 + 2 + 0 + 0 + 0 + 210 + 600 + 0 + 0 + 250 + 600 + 100 + 1 + 1 + 0 + + + 199 + 6 + Find in Files + 197 + + 197 + + 1 + 4 + 2 + 0 + 0 + 0 + 210 + 600 + 0 + 0 + 250 + 600 + 100 + 0 + 0 + 0 + + + 38007 + 7 + Browse + 197 + + 197 + + 1 + 4 + 2 + 0 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### uVision Project, (C) Keil Software
+ + + + <project name> + 0x0 + MCS-51 + 8 + + + SC92F8003 + SC92Fxx Series + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0-0xFF) CLOCK(16000000) + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 0 + SC92F8003.H + + + + + + + + + + + 0 + 0 + + + + SOC\ + SOC\ + + 0 + 0 + 0 + 0 + 1 + + ..\Output\ + project name + 1 + 0 + 1 + 1 + 1 + ..\List\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -p51 + S8051.DLL + + TP51.DLL + -p51 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 9 + + + + + + + + + + + + + + SinOne_Chip\SOC_Debug_Driver\SinOne_Chip_Debug_Driver.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4101 + + 0 + SinOne_Chip\SOC_Debug_Driver\SinOne_Chip_Debug_Driver.dll + "" () + + + + + 0 + + + + 2 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 0 + 0x0 + 0x100 + + + 0 + 0x0 + 0x100 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 9 + 2 + 0 + 1 + 1 + 0 + + + + + ..\FWLib\SC92F_Lib\inc;..\User + + + + 0 + 1 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 2 + 1 + + REMOVEUNUSED + + + + + + CODE(C:0X100), +CONST(C:0X100) + + + + + + + + + + + + + + + + + + + + + User + + + main.c + 1 + ..\User\main.c + + + SC_Init.c + 1 + ..\User\SC_Init.c + + + SC_it.c + 1 + ..\User\SC_it.c + + + SysFunVarDefine.c + 1 + ..\User\SysFunVarDefine.c + + + CompCtrlDefine.c + 1 + ..\User\CompCtrlDefine.c + + + + + Apps + + + Drivers + + + FWLib + + + sc92f_gpio.c + 1 + ..\FWLib\SC92F_Lib\src\sc92f_gpio.c + + + sc92f_option.c + 1 + ..\FWLib\SC92F_Lib\src\sc92f_option.c + + + + + Startup + + + STARTUP.A51 + 2 + .\STARTUP.A51 + + + + + + + + diff --git a/CFG/SC92F8363B/Keil_Mould/User/CallBackFunction.c b/CFG/SC92F8363B/Keil_Mould/User/CallBackFunction.c new file mode 100644 index 0000000..0502a44 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/CallBackFunction.c @@ -0,0 +1,14 @@ +//*************************************************************************************************** +// CopyRight (c) +// File Name : CallBackFunction.c +// Function : Write the logic you want to implement in the function body +// Version : V3.0 +// Date : 2022.07.14 +//*************************************************************************************************** +#include "SC_Init.h" +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/CFG/SC92F8363B/Keil_Mould/User/CompCtrlDefine.c b/CFG/SC92F8363B/Keil_Mould/User/CompCtrlDefine.c new file mode 100644 index 0000000..b57b2a5 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/CompCtrlDefine.c @@ -0,0 +1,14 @@ +//********************************************************************** +// CopyRight (c) +// File Name : CompCtrlDefine.C +// Function : Store composite control define +// Version : V3.2.0 +// Date : 2022.02.16 +///********************************************************************* +#include "SC_Init.h" +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/CompCtrlDefine.h b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/CompCtrlDefine.h new file mode 100644 index 0000000..dc8da2a --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/CompCtrlDefine.h @@ -0,0 +1,14 @@ +//********************************************************************** +// CopyRight (c) +// File Name : CompCtrlDefine.h +// Function : Store composite control define +// Version : V3.2.0 +// Date : 2022.02.16 +///********************************************************************* +#ifndef COMP_CTRL_DEFINE_H + #define COMP_CTRL_DEFINE_H +#endif + +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/CustomType.h b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/CustomType.h new file mode 100644 index 0000000..358033d --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/CustomType.h @@ -0,0 +1,14 @@ +//********************************************************************** +// CopyRight (c) +// File Name : CustomType.h +// Function : +// Version : V3.2.0 +// Date : 2022.02.16 +//********************************************************************** +#ifndef CUSTOM_TYPE_H + #define CUSTOM_TYPE_H +#endif + +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/FunctionType.h b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/FunctionType.h new file mode 100644 index 0000000..a2823fe --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/FunctionType.h @@ -0,0 +1,14 @@ +//********************************************************************** +// CopyRight (c) +// File Name : Function.h +// Function : Store quote of the function +// Version : V3.2.0 +// Date : 2022.02.16 +//********************************************************************** +#ifndef FUNCTION_H + #define FUNCTION_H +#endif + +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/SC_itExtern.h b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/SC_itExtern.h new file mode 100644 index 0000000..405cdc5 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/SC_itExtern.h @@ -0,0 +1,15 @@ +///**********************************************************************/ +// CopyRight (c) +// File Name : SC_itExtern.h +// Function : store extern var code +// Version : V3.2.0 +// Date : 2022.02.16 +///**********************************************************************/ +#ifndef SC_IT_EXTERN_H + #define SC_IT_EXTERN_H +#include "HeadFiles\SysFunVarDefine.h" +#endif + +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/SysFunVarDefine.h b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/SysFunVarDefine.h new file mode 100644 index 0000000..4aaf151 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/SysFunVarDefine.h @@ -0,0 +1,19 @@ +//********************************************************************** +// CopyRight (c) +// File Name : SysFunVarDefine.h +// Function : Store var control and function control extern +// Version : V3.2.0 +// Date : 2022.02.16 +//********************************************************************** +#ifndef SYS_FUN_VAR_DEFINE + #define SYS_FUN_VAR_DEFINE +#include "HeadFiles\CustomType.h" +#include "HeadFiles\UserExport.h" +#include "HeadFiles\FunctionType.h" +#include "HeadFiles\CompCtrlDefine.h" +#endif + +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ + diff --git a/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/UserExport.h b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/UserExport.h new file mode 100644 index 0000000..b8a383c --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/HeadFiles/UserExport.h @@ -0,0 +1,15 @@ +//********************************************************************** +// CopyRight (c) +// File Name : UserExport.h +// Function : Store head files +// Version : V3.2.0 +// Date : 2022.02.16 +//********************************************************************** +#ifndef USER_EXPORT_H + #define USER_EXPORT_H +#endif + +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ + diff --git a/CFG/SC92F8363B/Keil_Mould/User/SC_Init.c b/CFG/SC92F8363B/Keil_Mould/User/SC_Init.c new file mode 100644 index 0000000..0598243 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/SC_Init.c @@ -0,0 +1,419 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_Init.c +// Function : Contains the MCU initialization function and its C file +// Instructions : +//************************************************************* + +#include "SC_Init.h" // MCU initialization header file, including all firmware library header files +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SC_itExtern.h" + +//************************************************************* + +/***************************************************** +*: SC_Init +*: MCUʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_Init(void) +{ + /*write initial function here*/ + EA = 1; +} + +/***************************************************** +*: SC_OPTION_Init +*: OPTIONóʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_OPTION_Init(void) +{ + /*OPTION_Init write here*/ +} + +/***************************************************** +*: SC_GPIO_Init +*: GPIOʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_GPIO_Init(void) +{ + /*GPIO_Init write here*/ +} + +/***************************************************** +*: SC_UART0_Init +*: UART0ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_UART0_Init(void) +{ + /*UART0_Init write here*/ +} + +/***************************************************** +*: SC_TIM0_Init +*: TIMER0ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_TIM0_Init(void) +{ + /*TIM0_Init write here*/ +} + +/***************************************************** +*: SC_TIM1_Init +*: TIMER1ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_TIM1_Init(void) +{ + /*TIM1_Init write here*/ +} + +/***************************************************** +*: SC_TIM2_Init +*: TIMER2ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_TIM2_Init(void) +{ + /*TIM2_Init write here*/ +} + +/***************************************************** +*: SC_TIM3_Init +*: TIMER3ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_TIM3_Init(void) +{ + /*TIM3_Init write here*/ +} + +/***************************************************** +*: SC_TIM4_Init +*: TIMER4ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_TIM4_Init(void) +{ + /*TIM4_Init write here*/ +} + +/***************************************************** +*: SC_PWM_Init +*: PWMʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_PWM_Init(void) +{ + /*PWM_Init write here*/ +} + +/***************************************************** +*: SC_PWM0_Init +*: PWM0ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_PWM0_Init(void) +{ + /*PWM0_Init write here*/ +} + +/***************************************************** +*: SC_PWM1_Init +*: PWM1ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_PWM1_Init(void) +{ + /*PWM1_Init write here*/ +} + +/***************************************************** +*: SC_PWM2_Init +*: PWM1ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_PWM2_Init(void) +{ + /*PWM2_Init write here*/ +} + +/***************************************************** +*: SC_PWM3_Init +*: PWM1ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_PWM3_Init(void) +{ + /*PWM3_Init write here*/ +} + +/***************************************************** +*: SC_PWM4_Init +*: PWM1ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_PWM4_Init(void) +{ + /* + PWM4_Init write here*/ +} +/***************************************************** +*: SC_INT_Init +*: INTʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_INT_Init(void) +{ + /*INT_Init write here*/ +} + +/***************************************************** +*: SC_ADC_Init +*: ADCʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_ADC_Init(void) +{ + /*ADC_Init write here*/ +} + +/***************************************************** +*: SC_PGA_Init +*: PGAʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_PGA_Init(void) +{ + /*PGA_Init write here*/ +} + +/***************************************************** +*: SC_IAP_Init +*: IAPʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_IAP_Init(void) +{ + /*IAP_Init write here*/ +} + +/***************************************************** +*: SC_USCI0_Init +*: USCI0ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_USCI0_Init(void) +{ + /*USCI0_Init write here*/ +} + +/***************************************************** +*: SC_USCI1_Init +*: USCI1ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_USCI1_Init(void) +{ + /*USCI1_Init write here*/ +} + +/***************************************************** +*: SC_USCI2_Init +*: USCI2ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_USCI2_Init(void) +{ + /*USCI2_Init write here*/ +} + +/***************************************************** +*: SC_USCI3_Init +*: USCI3ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_USCI3_Init(void) +{ + /*USCI3_Init write here*/ +} + +/***************************************************** +*: SC_USCI4_Init +*: USCI4ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_USCI4_Init(void) +{ + /*USCI4_Init write here*/ +} + +/***************************************************** +*: SC_USCI5_Init +*: USCI5ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_USCI5_Init(void) +{ + /*USCI5_Init write here*/ +} + +/***************************************************** +*: SC_SSI_Init +*: SSIʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_SSI_Init(void) +{ + /*SSI_Init write here*/ +} + +/***************************************************** +*: SC_SSI0_Init +*: SSIʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_SSI0_Init(void) +{ + /*SSI0_Init write here*/ +} + +/***************************************************** +*: SC_SSI1_Init +*: SSIʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_SSI1_Init(void) +{ + /*SSI1_Init write here*/ +} + +/***************************************************** +*: SC_BTM_Init +*: ƵʱӶʱʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_BTM_Init(void) +{ + /*BTM_Init write here*/ +} + +/***************************************************** +*: SC_CRC_Init +*: check sum ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_CRC_Init(void) +{ + /*CRC_Init write here*/ +} + +/***************************************************** +*: SC_CHKSUM_Init +*: check sum ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_CHKSUM_Init(void) +{ + /*CHKSUM_Init write here*/ +} + +/***************************************************** +*: SC_WDT_Init +*: Źʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_WDT_Init(void) +{ + /*WDT_Init write here*/ +} + +/***************************************************** +*: SC_PWR_Init +*: Դ/ĿƳʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_PWR_Init(void) +{ + /*PWR_Init write here*/ +} +/***************************************************** +*: SC_DDIC_Init +*: ʾƳʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_DDIC_Init(void) +{ + /*DDIC_Init write here*/ +} + +/***************************************************** +*: SC_ACMP_Init +*: ˷ųʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_ACMP_Init(void) +{ + /*ACMP_Init write here*/ +} + +/***************************************************** +*: SC_MDU_Init +*: ˳ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_MDU_Init(void) +{ + /*MDU_Init write here*/ +} + +/***************************************************** +*: SC_LPD_Init +*: LPDʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_LPD_Init(void) +{ + /*LPD_Init write here*/ +} diff --git a/CFG/SC92F8363B/Keil_Mould/User/SC_Init.h b/CFG/SC92F8363B/Keil_Mould/User/SC_Init.h new file mode 100644 index 0000000..69d233c --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/SC_Init.h @@ -0,0 +1,58 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_Init.h +// Function : Contains the MCU initialization function and its H file +// Instructions : +//************************************************************* + +#ifndef _SC_INIT_H_ +#define _SC_INIT_H_ + +#if defined (SC95F8x1x) || defined (SC95F7x1x) || defined (SC95F8x2x) || defined (SC95F7x2x) || defined (SC95F8x3x) || defined (SC95F7x3x) \ + || defined (SC95F8x6x) || defined (SC95F7x6x) || defined (SC95F8x1xB) || defined (SC95F7x1xB) +#include "sc95f_conf.h" +#else +#include "sc92f_conf.h" +#endif + +void SC_Init(void); + +void SC_OPTION_Init(void); +void SC_GPIO_Init(void); +void SC_UART0_Init(void); +void SC_TIM0_Init(void); +void SC_TIM1_Init(void); +void SC_TIM2_Init(void); +void SC_TIM3_Init(void); +void SC_TIM4_Init(void); +void SC_PWM_Init(void); +void SC_PWM0_Init(void); +void SC_PWM1_Init(void); +void SC_INT_Init(void); +void SC_ADC_Init(void); +void SC_IAP_Init(void); +void SC_USCI0_Init(void); +void SC_USCI1_Init(void); +void SC_USCI2_Init(void); +void SC_BTM_Init(void); +void SC_CRC_Init(void); +void SC_WDT_Init(void); +void SC_PWR_Init(void); +void SC_DDIC_Init(void); +void SC_MDU_Init(void); +void SC_ACMP_Init(void); +void SC_USCI3_Init(void); +void SC_USCI4_Init(void); +void SC_USCI5_Init(void); +void SC_PWM2_Init(void); +void SC_PWM3_Init(void); +void SC_PWM4_Init(void); + +void SC_PGA_Init(void); +void SC_SSI_Init(void); +void SC_SSI0_Init(void); +void SC_SSI1_Init(void); +void SC_CHKSUM_Init(void); +void SC_LPD_Init(void); +#endif + diff --git a/CFG/SC92F8363B/Keil_Mould/User/SC_it.c b/CFG/SC92F8363B/Keil_Mould/User/SC_it.c new file mode 100644 index 0000000..f46d202 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/SC_it.c @@ -0,0 +1,237 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_it.c +// Function : Interrupt Service Routine +// Instructions : +// Date : 2022/03/03 +// Version : V1.0002 +//************************************************************* +/********************Includes************************************************************************/ +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SC_itExtern.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ + +void INT0Interrupt() interrupt 0 +{ + TCON &= 0XFD;//Clear interrupt flag bit + /*INT0_it write here begin*/ + /*INT0_it write here*/ + /**/ + /**/ + /*INT0Interrupt Flag Clear begin*/ + /*INT0Interrupt Flag Clear end*/ +} +void Timer0Interrupt() interrupt 1 +{ + /*TIM0_it write here begin*/ + /*TIM0_it write here*/ + /**/ + /**/ + /*Timer0Interrupt Flag Clear begin*/ + /*Timer0Interrupt Flag Clear end*/ +} +void INT1Interrupt() interrupt 2 +{ + TCON &= 0XF7;//Clear interrupt flag bit + /*INT1_it write here begin*/ + /*INT1_it write here*/ + /**/ + /**/ + /*INT1Interrupt Flag Clear begin*/ + /*INT1Interrupt Flag Clear end*/ +} +void Timer1Interrupt() interrupt 3 +{ + /*TIM1_it write here begin*/ + /*TIM1_it write here*/ + /**/ + /**/ + /*Timer1Interrupt Flag Clear begin*/ + /*Timer1Interrupt Flag Clear end*/ +} +#if defined (SC92F742x) || defined (SC92F7490) +void SSI0Interrupt() interrupt 4 +{ + /*SSI0_it write here begin*/ + /*SSI0_it write here*/ + /**/ + /**/ + /*SSI0Interrupt Flag Clear begin*/ + /*SSI0Interrupt Flag Clear end*/ +} +#else +void UART0Interrupt() interrupt 4 +{ + /*UART0_it write here begin*/ + /*UART0_it write here*/ + /**/ + /**/ + /*UART0Interrupt Flag Clear begin*/ + /*UART0Interrupt Flag Clear end*/ +} +#endif +void Timer2Interrupt() interrupt 5 +{ + /*TIM2_it write here begin*/ + /*TIM2_it write here*/ + /**/ + /**/ + /*Timer2Interrupt Flag Clear begin*/ + /*Timer2Interrupt Flag Clear end*/ +} +void ADCInterrupt() interrupt 6 +{ + /*ADC_it write here begin*/ + /*ADC_it write here*/ + /**/ + /**/ + /*ADCInterrupt Flag Clear begin*/ + /*ADCInterrupt Flag Clear end*/ +} +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) \ +|| defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F8003)||defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F83Ax) \ +|| defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F740x) || defined (SC92FWxx) || defined (SC93F743x) || defined (SC93F833x) || defined (SC93F843x)\ +|| defined (SC92F848x) || defined (SC92F748x)|| defined (SC92F859x) || defined (SC92F759x) +void SSIInterrupt() interrupt 7 +{ + /*SSI_it write here begin*/ + /*SSI_it write here*/ + /**/ + /**/ + /*SSIInterrupt Flag Clear begin*/ + /*SSIInterrupt Flag Clear end*/ +} +#elif defined (SC92F742x) || defined (SC92F7490) +void SSI1Interrupt() interrupt 7 +{ + /*SSI1_it write here begin*/ + /*SSI1_it write here*/ + /**/ + /**/ + /*SSI1Interrupt Flag Clear begin*/ + /*SSI1Interrupt Flag Clear end*/ +} +#else +void USCI0Interrupt() interrupt 7 +{ + /*USCI0_it write here begin*/ + /*USCI0_it write here*/ + /**/ + /**/ + /*USCI0Interrupt Flag Clear begin*/ + /*USCI0Interrupt Flag Clear end*/ +} +#endif +void PWMInterrupt() interrupt 8 +{ + /*PWM_it write here begin*/ + /*PWM_it write here*/ + /**/ + /**/ + /*PWMInterrupt Flag Clear begin*/ + /*PWMInterrupt Flag Clear end*/ +} +#if !defined (TK_USE_BTM) +void BTMInterrupt() interrupt 9 +{ + /*BTM_it write here begin*/ + /*BTM_it write here*/ + /**/ + /**/ + /*BTMInterrupt Flag Clear begin*/ + /*BTMInterrupt Flag Clear end*/ +} +#endif +void INT2Interrupt() interrupt 10 +{ + /*INT2_it write here begin*/ + /*INT2_it write here*/ + /**/ + /**/ + /*INT2Interrupt Flag Clear begin*/ + /*INT2Interrupt Flag Clear end*/ +} +void ACMPInterrupt() interrupt 12 +{ + /*ACMP_it write here begin*/ + /*ACMP_it write here*/ + /**/ + /**/ + /*ACMPInterrupt Flag Clear begin*/ + /*ACMPInterrupt Flag Clear end*/ +} +void Timer3Interrupt() interrupt 13 +{ + /*Timer3_it write here begin*/ + /*Timer3_it write here*/ + /**/ + /**/ + /*Timer3Interrupt Flag Clear begin*/ + /*Timer3Interrupt Flag Clear end*/ +} +void Timer4Interrupt() interrupt 14 +{ + /*Timer4_it write here begin*/ + /*Timer4_it write here*/ + /**/ + /**/ + /*Timer4Interrupt Flag Clear begin*/ + /*Timer4Interrupt Flag Clear end*/ +} +void USCI1Interrupt() interrupt 15 +{ + /*USCI1_it write here begin*/ + /*USCI1_it write here*/ + /**/ + /**/ + /*USCI1Interrupt Flag Clear begin*/ + /*USCI1Interrupt Flag Clear end*/ +} +void USCI2Interrupt() interrupt 16 +{ + /*USCI2_it write here begin*/ + /*USCI2_it write here*/ + /**/ + /**/ + /*USCI2Interrupt Flag Clear begin*/ + /*USCI2Interrupt Flag Clear end*/ +} +void USCI3Interrupt() interrupt 17 +{ + /*USCI3_it write here begin*/ + /*USCI3_it write here*/ + /**/ + /**/ + /*USCI3Interrupt Flag Clear begin*/ + /*USCI3Interrupt Flag Clear end*/ +} +void USCI4Interrupt() interrupt 18 +{ + /*USCI4_it write here begin*/ + /*USCI4_it write here*/ + /**/ + /**/ + /*USCI4Interrupt Flag Clear begin*/ + /*USCI4Interrupt Flag Clear end*/ +} +void USCI5Interrupt() interrupt 19 +{ + /*USCI5_it write here begin*/ + /*USCI5_it write here*/ + /**/ + /**/ + /*USCI5Interrupt Flag Clear begin*/ + /*USCI5Interrupt Flag Clear end*/ +} +void LPDInterrupt() interrupt 22 +{ + /*LPD_it write here begin*/ + /*LPD_it write here*/ + /**/ + /**/ + /*LPDInterrupt Flag Clear begin*/ + /*LPDInterrupt Flag Clear end*/ +} diff --git a/CFG/SC92F8363B/Keil_Mould/User/SC_it.h b/CFG/SC92F8363B/Keil_Mould/User/SC_it.h new file mode 100644 index 0000000..0f0580b --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/SC_it.h @@ -0,0 +1,20 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_it.h +// Author : +// Function : Interrupt service program header file +// Local Functions: +// Date : 2022/04/07 +// Version : V1.3 +//************************************************************* +#ifndef _SC_IT_H_ +#define _SC_IT_H_ + +#if defined (SC95F8x1x) || defined (SC95F7x1x) || defined (SC95F8x2x) || defined (SC95F7x2x) || defined (SC95F8x3x) || defined (SC95F7x3x) \ + || defined (SC95F8x6x) || defined (SC95F7x6x) || defined (SC95F8x1xB) || defined (SC95F7x1xB) +#include "sc95f_conf.h" +#else +#include "sc92f_conf.h" +#endif + +#endif diff --git a/CFG/SC92F8363B/Keil_Mould/User/SysFunVarDefine.c b/CFG/SC92F8363B/Keil_Mould/User/SysFunVarDefine.c new file mode 100644 index 0000000..f55d0bd --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/SysFunVarDefine.c @@ -0,0 +1,15 @@ +//********************************************************************** +// CopyRight (c) +// File Name : SysFunVarDefine.c +// Function : Store var control and function control define +// Version : V2.0 +// Date : 2021.08.04 +//********************************************************************** +#include "SC_Init.h" +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" + +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ \ No newline at end of file diff --git a/CFG/SC92F8363B/Keil_Mould/User/main.c b/CFG/SC92F8363B/Keil_Mould/User/main.c new file mode 100644 index 0000000..4e29cb3 --- /dev/null +++ b/CFG/SC92F8363B/Keil_Mould/User/main.c @@ -0,0 +1,31 @@ +//************************************************************ +// Copyright (c) +// FileName : main.c +// Module Function : +// Instructions : Contains the MCU initialization function and its H file +//************************************************************ +/********************Includes************************************************************************/ +#include "SC_Init.h" //MCU Init headerInclude all IC resource headers +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" + +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ +/***************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +******************************************************************************************************/ +void main(void) +{ + + /**/ + + /**/ + +} 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zcB@(3#niiqqLMtBwA!~fdD&DaCL+gt-*A!l_R?pT-w|@AlkYc50`?fs4@*gT@i=`o zeyH`{h~z>qQj|b7N!5~##fKv6V+sL5VLMlmvN8pBR@1FDG@)AW&xolf^^_mh!3lqX i6SS&h7t(rCz(e#A*$Zr%LV621fGmd?B*`8nfBz58LcZVt literal 0 HcmV?d00001 diff --git a/CFG/SC92F8363B/Temp/Function_Temp/ADC.txt b/CFG/SC92F8363B/Temp/Function_Temp/ADC.txt new file mode 100644 index 0000000..a46fa12 --- /dev/null +++ b/CFG/SC92F8363B/Temp/Function_Temp/ADC.txt @@ -0,0 +1,2 @@ +//gpiomode write here +//functions write here diff --git a/CFG/SC92F8363B/Temp/Function_Temp/OPTION.txt b/CFG/SC92F8363B/Temp/Function_Temp/OPTION.txt new file mode 100644 index 0000000..a46fa12 --- /dev/null +++ b/CFG/SC92F8363B/Temp/Function_Temp/OPTION.txt @@ -0,0 +1,2 @@ +//gpiomode write here +//functions write here diff --git a/CFG/SC92F8363B/Temp/Function_Temp/TIM0.txt b/CFG/SC92F8363B/Temp/Function_Temp/TIM0.txt new file mode 100644 index 0000000..a46fa12 --- /dev/null +++ b/CFG/SC92F8363B/Temp/Function_Temp/TIM0.txt @@ -0,0 +1,2 @@ +//gpiomode write here +//functions write here diff --git a/CFG/SC92F8363B/Temp/Function_Temp/UART1.txt b/CFG/SC92F8363B/Temp/Function_Temp/UART1.txt new file mode 100644 index 0000000..a46fa12 --- /dev/null +++ b/CFG/SC92F8363B/Temp/Function_Temp/UART1.txt @@ -0,0 +1,2 @@ +//gpiomode write here +//functions write here diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/ADC.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/ADC.txt new file mode 100644 index 0000000..6203f00 --- /dev/null +++ b/CFG/SC92F8363B/Temp/PEPCFG_Temp/ADC.txt @@ -0,0 +1,19 @@ +ʱԴԤƵ=0 +ʱ=0 +AIN0=True +AIN1=True +AIN2=True +AIN3=False +AIN4=False +AIN5=False +AIN6=False +AIN7=False +AIN8=False +AIN9=False +ѡ=1 +ж=0 +ADCܿѡ=True +ж־λ=True +$16$AIN2 +$17$AIN1 +$18$AIN0 diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/GPIO.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/GPIO.txt new file mode 100644 index 0000000..8f65cc9 --- /dev/null +++ b/CFG/SC92F8363B/Temp/PEPCFG_Temp/GPIO.txt @@ -0,0 +1,2 @@ +[PinNumber]19[/PinNumber][UpperIndex]3[/UpperIndex][Iindex]0[/Iindex][PinName]RX1[/PinName] +[PinNumber]20[/PinNumber][UpperIndex]3[/UpperIndex][Iindex]0[/Iindex][PinName]TX1[/PinName] diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/OPTION.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/OPTION.txt new file mode 100644 index 0000000..d066119 --- /dev/null +++ b/CFG/SC92F8363B/Temp/PEPCFG_Temp/OPTION.txt @@ -0,0 +1,9 @@ +ϵͳʱFsys=0 +Ƶ(Hz)=[24000000] +Optionʹ=0 +ѡ=0 +ƵʷΧ=0 +οѹѡ=0 +λܽ=0 +LVR ѹѡ=0 +IAPΧ=0 diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/TIM0.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/TIM0.txt new file mode 100644 index 0000000..ee3a0cd --- /dev/null +++ b/CFG/SC92F8363B/Temp/PEPCFG_Temp/TIM0.txt @@ -0,0 +1,13 @@ +ʱ/ģʽ=0 +ʱģʽ=True +ʱ(us)=[1000] +ԤƵѡ=1 +ģʽ=1 +ֵ0=[53536] +ֵ1=[10] +Mode0ֵ=[8000] +Mode1ֵ=[53536] +Mode3ֵL=[100] +Mode3ֵH=[100] +ж=0 +TIM0ʹ=True diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/UART1.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/UART1.txt new file mode 100644 index 0000000..1c247ea --- /dev/null +++ b/CFG/SC92F8363B/Temp/PEPCFG_Temp/UART1.txt @@ -0,0 +1,8 @@ +Ƶ=[12000000] +UART1=1 +BaudRate=[9600] +ģʽ=0 +ж=0 +ж־λ=True +$19$RX1ģʽ: +$20$TX1ģʽ: diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/ADC.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/ADC.txt new file mode 100644 index 0000000..6203f00 --- /dev/null +++ b/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/ADC.txt @@ -0,0 +1,19 @@ +ʱԴԤƵ=0 +ʱ=0 +AIN0=True +AIN1=True +AIN2=True +AIN3=False +AIN4=False +AIN5=False +AIN6=False +AIN7=False +AIN8=False +AIN9=False +ѡ=1 +ж=0 +ADCܿѡ=True +ж־λ=True +$16$AIN2 +$17$AIN1 +$18$AIN0 diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/GPIO.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/GPIO.txt new file mode 100644 index 0000000..8f65cc9 --- /dev/null +++ b/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/GPIO.txt @@ -0,0 +1,2 @@ +[PinNumber]19[/PinNumber][UpperIndex]3[/UpperIndex][Iindex]0[/Iindex][PinName]RX1[/PinName] +[PinNumber]20[/PinNumber][UpperIndex]3[/UpperIndex][Iindex]0[/Iindex][PinName]TX1[/PinName] diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/OPTION.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/OPTION.txt new file mode 100644 index 0000000..d066119 --- /dev/null +++ b/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/OPTION.txt @@ -0,0 +1,9 @@ +ϵͳʱFsys=0 +Ƶ(Hz)=[24000000] +Optionʹ=0 +ѡ=0 +ƵʷΧ=0 +οѹѡ=0 +λܽ=0 +LVR ѹѡ=0 +IAPΧ=0 diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/TIM0.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/TIM0.txt new file mode 100644 index 0000000..ee3a0cd --- /dev/null +++ b/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/TIM0.txt @@ -0,0 +1,13 @@ +ʱ/ģʽ=0 +ʱģʽ=True +ʱ(us)=[1000] +ԤƵѡ=1 +ģʽ=1 +ֵ0=[53536] +ֵ1=[10] +Mode0ֵ=[8000] +Mode1ֵ=[53536] +Mode3ֵL=[100] +Mode3ֵH=[100] +ж=0 +TIM0ʹ=True diff --git a/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/UART1.txt b/CFG/SC92F8363B/Temp/PEPCFG_Temp/backup/UART1.txt new file mode 100644 index 0000000..1c247ea --- /dev/null +++ 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zNg91SWpnUrG2{vcp4VLOA7ESBQDQJZ45gDf;~iv|F{cr9{nI{cIc;22CT%A)aM)|QDGRgK zI6HlXNqdNgjgXx>fOZ6hy=b_wQ^rk6DA%@6Y4l(@B8sE`yghXBV`#dX!O*5Hcd9tnQ2Tlh7erWt*yGWYm8=(Eh z6rQ1I&CA4~mDIJ1{sDDK7ahZvnE?|PcnZrcyPmp@#4Lk=)Xqa_db0II?G|RoN|Yzk z7Yy`V*2DcCyNTn6$ZkITU`GCJjlnas{Jx0&YQV_(ij`P&o0a!9UEcx|g8SOz6TtAY zNnwB&Xc5BbAhG^M`Jt NqO9soxU`Y~{{z9kAg=%b literal 0 HcmV?d00001 diff --git a/Keil_C/Apps/Uart1.c b/Keil_C/Apps/Uart1.c new file mode 100644 index 0000000..3e85d13 --- /dev/null +++ b/Keil_C/Apps/Uart1.c @@ -0,0 +1,780 @@ +/********************************Copyright (c)**********************************\ +** +** (c) Copyright 2019, China, JS. +** All Rights Reserved +** +** +**----------------------------------ļϢ------------------------------------ +** ļ: ttl_usart.c +** : 2022-05-11 +** ĵ: ttl_usart +** +**----------------------------------汾Ϣ------------------------------------ +** 汾: V0.1 +** 汾˵: ʼ汾 +** +********************************End of Head************************************/ + +/* Includes ------------------------------------------------------------------*/ + +/** + * @file uart.c + * @author Nations + * @version v1.0.0 + * + * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ + +#include + + +#include "SC_Init.h" //MCU Init headerInclude all IC resource headers +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" + +#include "Uart1.h" +#include "Motor.h" + +//΢ʱ +void DelayUs(unsigned int delay) +{ + unsigned int i = 0, j = 0; + for(i = 0; i < delay; i++) + { + for(j = 0; j < 125; j++); + } +} + +//ʱ +void DelayMs(unsigned int delay) +{ + unsigned int i = 0; + for(i = 0; i < delay; i++) + { + DelayUs(1000); + } +} + +#define HD_VER 0001 //Ӳ汾 +#define SW_VER 0001 //汾 + +#define TTL_SEND_BUFF_LEN 60 //ݳ +#define TTL_RECEIVE_BUFF_LEN 60 //ݳ + +//---------------------------------------------------------------- +//uart1ڽusbתttlĴ +//---------------------------------------------------------------- + +//ŷ͵ +uint8_t xdata motor_data[10]; + +//buff +uint8_t xdata ttl_send_len = 0; +uint8_t xdata ttl_send_buff[TTL_SEND_BUFF_LEN] = {0}; + +//buff +uint8_t xdata ttl_receive_len = 0; +uint8_t xdata ttl_receive_buff[TTL_RECEIVE_BUFF_LEN] = {0}; + +//ճʱ +uint8_t xdata ttl_receive_flag = 0; +uint8_t xdata ttl_receive_cnt = 0; +uint8_t xdata ttl_receive_interval = 0; + +#define DATA_LEN TTL_RECEIVE_BUFF_LEN //һݳ +#define UART_ORDER_SOF 0x05 //ʼ +#define UART_ORDER_END 0x1B // +#define FIXED_LEN 0x0B //̶ //ȡRW + +uint16_t xdata SUR_DEVICE_ADDR = 0x00A1; //PC //0x00A1; //豸 +uint16_t xdata OBJ_DEVICE_ADDR = 0x00B1; // //0x00B1; //PCȺ FFFF 0000 + +uint8_t xdata order_flag = 0; +unsigned int xdata checksum = 0, re_status = 0, rec_len = 0, data_len = 0, shouldaccept = 0; + +// +void UART1_SendData(uint8_t dat) +{ + SSI_UART1_SendData8(dat); +} + +// +void UART1_Send_Char(uint8_t dat) +{ + SSI_UART1_SendData8(dat); +} + +//ʼ +void InitUart_Data(void) +{ + order_flag = 0; + rec_len = 0; + re_status = 0; + shouldaccept = 0; + + ttl_receive_flag = 0; + ttl_receive_cnt = 0; + + checksum = 0; + + for(data_len = 0; data_len < DATA_LEN; data_len++) + { + ttl_receive_buff[data_len] = 0; + } + + data_len = 0; + +// UART_Send_Char(0xdd); +} + + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +//---------------------------------------------------------------- +//մ1 +//---------------------------------------------------------------- +/**************************************************************************************************** + * @brief Download a file via serial port + * @param None + * @retval None + **************************************************************************************************/ +void start_ttl_receive_timer(uint32_t ms) +{ + if(ms == 0) + { + return; + } + + ttl_receive_flag = 1; + ttl_receive_cnt = 0; + ttl_receive_interval = ms; +} + +/**************************************************************************************************** + * @brief Upload a file via serial port. + * @param None + * @retval None + **************************************************************************************************/ +void over_ttl_receive_timer(void) +{ + ttl_receive_flag = 0; + ttl_receive_cnt = 0; + ttl_receive_interval = 0; + + InitUart_Data(); + +// UART2_Send_Char(0xed); +} + +/**************************************************************************************************** + * @brief Display the Main Menu on HyperTerminal + * @param None + * @retval None + **************************************************************************************************/ +void clear_ttl_receive_timer(void) +{ + uint16_t i = 0; + ttl_receive_len = 0; + ttl_receive_flag = 0; + ttl_receive_cnt = 0; + ttl_receive_interval = 0; + + for(i = 0; i < TTL_RECEIVE_BUFF_LEN; i++) + { + ttl_receive_buff[i] = 0; + } +} + +//شӦǷɵĽ +//0ûʱ 1ʱ +uint8_t judge_ttl_receive_timer(void) +{ + if(ttl_receive_flag == 2) + { + return 1; + } + else + { + return 0; + } +} + +/**************************************************************************************************** + * @brief Display the Main Menu on HyperTerminal + * @param None + * @retval None + **************************************************************************************************/ +//ڴѭеļʱ +void process_ttl_receive_timer(void) +{ + if(ttl_receive_flag == 1) + { + ttl_receive_cnt++; + } + + if((ttl_receive_interval > 0) && (ttl_receive_cnt >= ttl_receive_interval)) + { + over_ttl_receive_timer(); + } +} + +#define TTL_OVER_TIME 10 +/**************************************************************************************************** + * @brief Display the Main Menu on HyperTerminal + * @param None + * @retval None + **************************************************************************************************/ +//Ŵжڣ +void receive_ttl_data(uint8_t rx_data) +{ + //ܳ󳤶 + if(ttl_receive_len < TTL_RECEIVE_BUFF_LEN) + { + //ʼʱ + start_ttl_receive_timer(TTL_OVER_TIME); + + //ڽݷ + Do_Receive_Uart_For_Module(rx_data); + } + else // + { + //ʱ + over_ttl_receive_timer(); + + InitUart_Data(); + + //UART_Send_Char(0xcc); + } +} + +#define CRC_PRESET 0xFFFF +#define CRC_POLYNOM 0x4204 +/*--------------------------------------------------------------------------- +÷ʽunsigned int ModbusCRC16(unsigned char *data_value, unsigned char length) +˵CRCУ +---------------------------------------------------------------------------*/ +unsigned int ModbusCRC16(unsigned char *data_value, unsigned char length) +{ + unsigned int crc_value = CRC_PRESET; + unsigned char i; + data_value++; + while(length-- != 0) + {//ModbusCRC16(PData, Num + FIXED_LEN - 3); + for(i = 0x01; i != 0; i <<= 1) + { + if((crc_value & 0x0001) != 0) + { + crc_value >>= 1; + crc_value ^= CRC_POLYNOM; + } + else + { + crc_value >>= 1; + } + + if((*data_value & i) != 0) + { + crc_value ^= CRC_POLYNOM; + } + } + data_value++; + } + return(crc_value); +} + +/*--------------------------------------------------------------------------- +÷ʽunsigned int VerfiyRC(unsigned char *data_value, unsigned char length) +˵У +ͷβ̶У⣬У +-----------------------------------------------------------------------------*/ +unsigned char VerfiyRC(unsigned char data_value[], unsigned char length) //У飬crcУ +{ + unsigned char i; + unsigned char V_b = data_value[1]; + + for(i = 0x00; i < length; i++) + { + //У + V_b ^= data_value[i]; + } + + return(V_b); +} + +//ʱ +void Uart_Send_Delay(unsigned int delay) +{ + unsigned int i = 0, j = 0; + + for(i = 0; i < delay; i++) + { + for(j = 0; j < 125; j++); + } +} + +//У + 0X1B +#define VERFIY_TYPE 0 + +/* +SOF 1ֽ 0x05 ʼֽ +Len 2ֽ +Fou_adr 2ֽ Դַ +Com_adr 2ֽ Ŀַ0ffΪ㲥ַ +Cmd16 2ֽ +Request-data Nֽ +XOR 2ֽ У +END 0x1B ֽ +*/ + +// +void send_set_resp(unsigned int OrderNum, unsigned int addr, unsigned char Num, unsigned char sData[]) +{ + unsigned int xdata xor_data = 0; + unsigned char xdata PData[TTL_SEND_BUFF_LEN]; + unsigned char xdata i = 0; + + PData[0] = UART_ORDER_SOF; //һֽ + PData[1] = (Num + FIXED_LEN) / 0x100; // 8λ + PData[2] = (Num + FIXED_LEN) % 0x100; // 8λ + PData[3] = (addr >> 8) & 0xff; //Դַ + PData[4] = addr & 0xff; //Դַ + PData[5] = (SUR_DEVICE_ADDR >> 8) & 0xff; //Ŀַ + PData[6] = SUR_DEVICE_ADDR & 0xff; //Ŀַ + PData[7] = (OrderNum >> 8) & 0xff; // -1 + PData[8] = OrderNum & 0xff; // -2 + +// PData[6] = RW_Flag; //д־ + + for(i = 0; i < Num; i++) // + { + PData[FIXED_LEN - 2 + i] = sData[i]; // + } + + //У + if(VERFIY_TYPE) //У + ĩβֽ 2ֽ + { + xor_data = VerfiyRC(PData, Num + FIXED_LEN - 2); + PData[FIXED_LEN + Num - 2] = xor_data; + PData[FIXED_LEN + Num - 1] = 00; + } + else //CRCУ 2ֽ + { + xor_data = ModbusCRC16(PData, Num + FIXED_LEN - 3); + PData[FIXED_LEN + Num - 2] = (xor_data) & 0xff; + PData[FIXED_LEN + Num - 1] = (xor_data >> 8) & 0xff; + } + + PData[FIXED_LEN + Num] = UART_ORDER_END; // ĩβֽ + + //ȫ + for(i = 0; i < (Num + FIXED_LEN + 1); i++) //һԷ + { + UART1_Send_Char(PData[i]); + //ʱ + Uart_Send_Delay(50); + } +} + + + +//ַǷΪַ +uint8_t Check_Resive_Addr(uint16_t addr) +{ + //ȷǷΪյַ + if((OBJ_DEVICE_ADDR == addr) || (0xFFFF == addr) || (0x0000 == addr) || (0x00B1 == addr)) + { + return 1; + } + else + { + InitUart_Data(); //2 + return 0; + } +} + + +//жϣôڽڣ +void Do_Receive_Uart_For_Module(unsigned char ch) +{ + switch(re_status) + { + case 0 : //0x05 1ֽ ʼ + { + if(ch == UART_ORDER_SOF) + { + rec_len = 0; + ttl_receive_buff[rec_len] = ch; + re_status = 1; + shouldaccept = 0; +// UART2_Send_Char(0xaa); + } + } + break; + case 1: // 2ֽ + { + rec_len++; + ttl_receive_buff[rec_len] = ch; + + if(rec_len >= 2) + { + re_status = 2; + shouldaccept = ttl_receive_buff[1] * 0x100 + ttl_receive_buff[2]; + + if(shouldaccept >= TTL_RECEIVE_BUFF_LEN - 1) + { + InitUart_Data(); + return; + } + } + } + break; + case 2: // 2ֽ 05 00 0B 00 C1 00 A1 F0 01 87 1B + { + rec_len++; + + if(rec_len >= TTL_RECEIVE_BUFF_LEN - 1) + { + InitUart_Data(); + return; + } + + ttl_receive_buff[rec_len] = ch; // + + if(rec_len >= shouldaccept) //жǷ + { +// uint8_t i = 0; +// UART2_Send_Char(0x30); +// UART2_Send_Char(rec_len); +// UART2_Send_Char(shouldaccept); +// UART2_Send_Char(FIXED_LEN - 1); + +// UART2_Send_Char(rec_len); +// for( i = 0;i < shouldaccept;i++) UART2_Send_Char(ttl_receive_buff[i]); + + //ȴҪڹ̶ +// if(rec_len >= FIXED_LEN - 1) +// { + //жϽĿַǷԼ +// int adr = ttl_receive_buff[3]; +// adr = adr << 8; +// adr |= ttl_receive_buff[4]; + int adr = ttl_receive_buff[5]; + adr = adr << 8; + adr |= ttl_receive_buff[6]; + +//UART2_TxByte(0xAA); +//UART2_TxByte(ttl_receive_buff[3]); +//UART2_TxByte(ttl_receive_buff[4]); +// + if(Check_Resive_Addr(adr)) + { + // + unsigned int order = 0; + order = ttl_receive_buff[7]; + order = order << 8; + order += ttl_receive_buff[8]; + +// //Ŀַ +// OBJ_DEVICE_ADDR = ttl_receive_buff[3]; +// OBJ_DEVICE_ADDR <<= 8; +// OBJ_DEVICE_ADDR += ttl_receive_buff[4]; + +//UART2_Send_Char(order / 0x100); +//UART2_Send_Char(order % 0x100); +//UART2_TxByte(0xBB); +//UART2_TxByte(ttl_receive_buff[7]); +//UART2_TxByte(ttl_receive_buff[8]); + + switch(order) + { + //=================== =================================================== + //豸 + //====================================================================== + case 0xF001 : // + { + order_flag = 1; + } + break; + + case 0xF0C1 : //豸Ϣ + { + order_flag = 2; + } + break; + + //====================================================================== + //豸Ϣ + //====================================================================== + case 0xF111 : //Ʋ + { + order_flag = 3; +// UART2_Send_Char(0x33); + } + break; + + //====================================================================== + //豸Ϣ + //====================================================================== + case 0xF112 : // ״̬¶ + { + order_flag = 4; + } + break; + case 0xF102 : // ״̬¶ + { + order_flag = 4; + } + break; + + //====================================================================== + // + //====================================================================== + default : + { + InitUart_Data(); + } + break; + } + } + else + { + InitUart_Data(); + return; + } + } +// } + } + break; + + default : + InitUart_Data(); + break; + } +} + +//ݳ +uint8_t Get_Data_Len(void) +{ + uint16_t Re_Len = 0; + Re_Len = (ttl_receive_buff[1] * 0x100 + ttl_receive_buff[2]) - FIXED_LEN; + return Re_Len; +} + +//У +unsigned char Check_VerfiyData(void) +{ + return 1; //ڼ䣬֤ + + if(VERFIY_TYPE) //У + ĩβֽ + { + unsigned char v_A = 0; + unsigned char v_B = 0; + v_A = ttl_receive_buff[shouldaccept]; + v_B = VerfiyRC(ttl_receive_buff, shouldaccept - 2); + + if(v_A == v_B) //ݵ + { + //βͬ + if(ttl_receive_buff[shouldaccept + 1] == UART_ORDER_END) + { + + } + else + { + return 0; + } + } + else + { + return 0; + } + } + else //жCRCУ + { + unsigned int CRC16 = 0; + unsigned int Get_CRC16 = 0; + CRC16 = ttl_receive_buff[shouldaccept]; + CRC16 = CRC16 << 8; + CRC16 += ttl_receive_buff[shouldaccept - 1]; + + Get_CRC16 = ModbusCRC16(ttl_receive_buff, shouldaccept - 2); + + if(CRC16 == Get_CRC16) //ݵ + { + + } + else + { + InitUart_Data(); + return 0; + } + } + + return 1; +} + + +//ݽշ(ôѭ) +void Deal_Uart_Data_For_Module(void) +{ + if(order_flag) //нյָ + { + //У + if(Check_VerfiyData() == 1) // + { + switch(order_flag) + { + //-------------------------------------------------------------------- + // + //-------------------------------------------------------------------- + case 1 : //ݽ + { + uint8_t xdata i = 0; //ʱ + uint8_t xdata len = 0; // + uint8_t xdata temp[DATA_LEN]; + + //ͱ־ + send_flag = 0; + + //ݳ + len = Get_Data_Len(); + + // + for(i = 0; i < len; i++) + { + temp[i] = ttl_receive_buff[i + FIXED_LEN - 2]; + } + + //г ֱг + Travle_Flag = temp[0]; //0 ֱ 1 + Motor_Run = temp[1]; //0 ֹͣ 1 2 еʼ 3 е + Run_Mode = temp[2]; //0 㶯 1 һ 2 + + Run_Step = temp[3]; //жȦΪһ + Run_Step <<= 8; + Run_Step += temp[4]; + + Run_Inter = temp[5]; //мʱ + Run_Inter <<= 8; + Run_Inter += temp[6]; + + Run_Stop = temp[7]; //㡱ֹͣʱ + Run_Stop <<= 8; + Run_Stop += temp[8]; + + ClrRunmotorStep();// + + } + break; + + case 2 : // + { + uint8_t i = 0; + uint8_t len = 0; + uint8_t temp[DATA_LEN]; + + send_set_resp(0xF0C1, OBJ_DEVICE_ADDR, len, temp); + + } + break; + + //-------------------------------------------------------------------- + //LED + //-------------------------------------------------------------------- + case 3 : //F111 05 00 0C 00 A1 00 C1 F1 01 05 03 50 87 1B + { + u8 addr = 0; + addr = ttl_receive_buff[FIXED_LEN - 2]; + if(addr == ((SUR_DEVICE_ADDR & 0xf0) == 0xC0)) + { + + } + } + break; + + //====================================================================== + // + //====================================================================== + case 4 : // + { + + + } + break; + + //-------------------------------------------------------------------- + //ʵʱϢ + //-------------------------------------------------------------------- + case 5 : // + { + uint8_t len = 0; + uint8_t temp[DATA_LEN]; + + + + temp[0] = (SUR_DEVICE_ADDR >> 8) & 0xff; + temp[1] = (SUR_DEVICE_ADDR >> 0) & 0xff; + +// //汾 4 + temp[2] = HD_VER >> 8; //HD_VER 0101 //Ӳ汾 + temp[3] = HD_VER & 0xff; + + temp[4] = SW_VER >> 8; //SW_VER 0101 //汾 + temp[5] = SW_VER & 0xff; + + len = 6; + send_set_resp(0xF113, OBJ_DEVICE_ADDR, len, temp); + } + break; + case 6 : // ַ + 汾 F1D3 05 00 0D 00 A1 00 00 F1 D3 00 C1 07 A9 1B + { + + uint8_t i = 0; + uint8_t len = 0; + uint8_t temp[DATA_LEN]; + + //ݳ + len = Get_Data_Len(); + + for(i = 0; i < len; i++) + { + temp[i] = ttl_receive_buff[i + FIXED_LEN - 2]; + } + + + send_set_resp(0xF1C3, OBJ_DEVICE_ADDR, len, temp); + } + break; + case 7 : //³ + { + + } + break; + + //-------------------------------------------------------------------- + //豸Ϣ + //-------------------------------------------------------------------- + case 10 : //F115 05 00 0A 00 C1 00 A1 F1 05 50 87 1B + { + + + } + break; + + + default : + { + + } + break; + } + } + + // + InitUart_Data(); + } +} + + diff --git a/Keil_C/Apps/Uart1.h b/Keil_C/Apps/Uart1.h new file mode 100644 index 0000000..e414d26 --- /dev/null +++ b/Keil_C/Apps/Uart1.h @@ -0,0 +1,66 @@ +//΢ʱ +extern void DelayUs(unsigned int delay); + +//ʱ +extern void DelayMs(unsigned int delay); + + +//жϣôڽڣ +extern void Do_Receive_Uart_For_Module(unsigned char ch); + +// +extern void UART1_SendData(uint8_t dat); + +// +extern void UART1_Send_Char(uint8_t dat); + +//һַ +//extern void send_string(uchar *p); + +//ʼ +extern void InitUart_Data(void); + +//մ1 +extern void start_ttl_receive_timer(uint32_t ms); + +extern void over_ttl_receive_timer(void); + +extern void clear_ttl_receive_timer(void); + + +//شӦǷɵĽ +//0ûʱ 1ʱ +extern uint8_t judge_ttl_receive_timer(void); + +//ڴѭеļʱ +extern void process_ttl_receive_timer(void); + +//Ŵжڣ +extern void receive_ttl_data(uint8_t rx_data); + +//CRCУ +extern unsigned int ModbusCRC16(unsigned char *data_value, unsigned char length); + +//У +extern unsigned char VerfiyRC(unsigned char data_value[], unsigned char length); + +//ʱ +extern void Uart_Send_Delay(unsigned int delay); + +// +extern void send_set_resp(unsigned int OrderNum, unsigned int addr, unsigned char Num, unsigned char sData[]); + +//ַǷΪַ +extern uint8_t Check_Resive_Addr(uint16_t addr); + +//жϣôڽڣ +extern void Do_Receive_Uart_For_Module(unsigned char ch); + +//ݳ +extern uint8_t Get_Data_Len(void); + +//У +extern unsigned char Check_VerfiyData(void); + +//ݽշ(ôѭ) +extern void Deal_Uart_Data_For_Module(void); diff --git a/Keil_C/Apps/adc.c b/Keil_C/Apps/adc.c new file mode 100644 index 0000000..9a816b3 --- /dev/null +++ b/Keil_C/Apps/adc.c @@ -0,0 +1,83 @@ +#include "SC_Init.h" //MCU Init headerInclude all IC resource headers +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" + +#include "adc.h" +#include "Uart1.h" + +unsigned int xdata ADC_Value0 = 0,ADC_Value1 = 0,ADC_Value2 = 0; + +unsigned int xdata ADC_NUM1=0; +//ȡadcתֵ +unsigned int ADC_Convert(void) +{ + unsigned int xdata Tad = 0,MinAd1 = 0x0fff,MaxAd1 = 0x0000,MinAd2 = 0x0fff,MaxAd2 = 0x0000,TempAdd = 0; + unsigned char xdata t = 0; + for(t = 0;t < 10;t++) + { + ADCCON |= 0X40; //ʼ ADC ת + while(!(ADCCON & 0x20));//ȴ ADC תɣͬͺŵתɱ־λλòͬͺ Bit5,ͺBit4,չ + //жϱ־λ + ADCCON &= ~(0X20); + Tad = ((unsigned int)ADCVH << 4) + (ADCVL >> 4); //ȡһתֵ + ADC_NUM1=Tad; + if(Tad > MaxAd1) + { + MaxAd1 = Tad;//õǰֵ + } +// else +// { +// if(Tad > MaxAd2) +// MaxAd2 = Tad; +// } + if (Tad < MinAd1) + { + MinAd1 = Tad;//õǰСֵ + } +// else +// { +// if(Tad > MinAd2) +// MinAd2 = Tad; +// } + TempAdd += Tad; + } + + //תֵۼ + TempAdd -= MinAd1;//ȥСֵ + TempAdd -= MaxAd1;//ȥֵ +// TempAdd -= MinAd2;//ȥڶСֵ +// TempAdd -= MaxAd2;//ȥڶֵ + //TempAdd = TempAdd / 16; + TempAdd >>= 3; //ƽֵ + return TempAdd; +} + +//лADC +void ADC_channel(unsigned char ADC_Channel) +{ + ADCCFG0 = 0x07; + ADCCON = 0xE0 | ADC_Channel; +} + +extern uint8_t xdata motor_data[]; +void ADC_Multichannel(void) +{ + uint8_t xdata temp_h,temp_l; //߰λ͵Ͱλ + + ADC_channel(1); //ADC л AIN1 ڣɼѹź + ADC_Value1 = ADC_Convert(); // ADC תתֵ + temp_h = (ADC_Value1 & 0xff00) >> 8;//8λֵ + temp_l = ADC_Value1 & 0x00ff; //8λֵ + motor_data[4] = temp_h; + motor_data[5] = temp_l; + + ADC_channel(2); //ADC л AIN2 ڣɼź + ADC_Value2 = ADC_Convert(); // ADC תתֵ + temp_h = (ADC_Value2 & 0xff00) >> 8;//8λֵ + temp_l = ADC_Value2 & 0x00ff; //8λֵ + motor_data[6] = temp_h; + motor_data[7] = temp_l; +} + + diff --git a/Keil_C/Apps/adc.h b/Keil_C/Apps/adc.h new file mode 100644 index 0000000..d82edfd --- /dev/null +++ b/Keil_C/Apps/adc.h @@ -0,0 +1,10 @@ + +//ȡadcתֵ +extern unsigned int ADC_Convert(void); +//лADC +extern void ADC_channel(unsigned char ADC_Channel); + +extern void ADC_Multichannel(void); + + + diff --git a/Keil_C/Apps/motor.c b/Keil_C/Apps/motor.c new file mode 100644 index 0000000..b9408f9 --- /dev/null +++ b/Keil_C/Apps/motor.c @@ -0,0 +1,1004 @@ +#include "motor.h" + +#define STEP_LIN 16 //ֱг̲λֵ +#define STEP_ROT 20 //г̲λֵ +#define DATA_LEN 10 //г̲λֵ + +bit Travle_Flag = 0; //0 ֱ 1 +char xdata Motor_Run = 0; //0 ֹͣ 1 2 еʼ 3 е +char xdata Run_Mode = 0; //0 㶯 1 һ 2 +unsigned int xdata Run_Step = 0; //в +unsigned int xdata Run_Inter = 0; //мʱ +unsigned int xdata Run_Stop = 0; //㡱ֹͣʱ +unsigned int xdata Run_mm = 0; //нȣmm/תǶȣ㣩 +unsigned int xdata Run_num = 0; //г̵תȦ +unsigned int xdata ct_num = 0; // + +bit mov_flag = 0; //־ +bit send_flag = 0; //ͱ־ +bit seat_flag = 0; //λñ־ +bit motor_dire = 1; //ת +bit flag = 0; + + +// +unsigned char xdata Runmotor_step = 0; + +// +unsigned int xdata Runmotor_Nums = 0; + +// +void motor_start(void) +{ + GPIO_Init(GPIO1, GPIO_PIN_7,GPIO_MODE_OUT_PP);//Ϊģʽյź + GPIO_WriteHigh(GPIO1,GPIO_PIN_7); + motor_data[1] = 0x01;//Ӧ01 +} + +//ֹͣ +void motor_stop(void) +{ + GPIO_WriteHigh(GPIO1,GPIO_PIN_7); + GPIO_Init(GPIO1, GPIO_PIN_7,GPIO_MODE_IN_HI);//Ϊģʽ޷յź + motor_data[1] = 0x00;//ֹͣӦ00 +} + +//ת +void FWD(void) +{ + GPIO_WriteLow(GPIO1,GPIO_PIN_6);//ŵƽõͣת +} + +//ת +void REV(void) +{ + GPIO_WriteHigh(GPIO1,GPIO_PIN_6);//ŵƽøߣת +} + + + +// +void ClrRunmotorStep(void) +{ + // + Runmotor_step = 0; + // + Runmotor_Nums = 0; + //0 + mov_flag = 0; + //ͱ0 + send_flag = 0; + //λñ0 + seat_flag = 0; +} + +// +void Deal_Motor(void) +{ + //жֱг̻ǽг + if(Travle_Flag == 0)//ֱг̡תһȦˮƽλ5mm + { + motor_data[0] = 0x00;//00 ֱг 01 г + //жϵֹͣУеʼλǽλ + if( Motor_Run == 0)//ֹͣ + { + motor_stop(); + } + else if(Motor_Run == 1)// + { + if(Motor_Run >= 1 && Runmotor_step == 0) + { + Runmotor_step = 1; + } + + //жϵзʽǵ㶯㶯ΪһͷΪ + if(Run_Mode == 0)//㶯 + { + motor_data[2] = 0x00;//ʱ + mov_step();//㶯 + } + else if(Run_Mode == 1)//һܻԽλء + { + motor_data[2] = 0x01;//ʱ + mov_loop1();//һ + } + else if(Run_Mode == 2)//ܻԽλء + { + motor_data[2] = 0x02;//ʱ + //ѭʼ--ʼ㡱һͣʼ + mov_loop2();// + } + else//ʼ + { + motor_stop(); + } + } + else if(Motor_Run == 2)//еʼλ + { + mov_begin();//صʼλ + } + else if(Motor_Run == 3)//еλ + { + mov_end();//ƶλ + } + else//ݴ + SC_Init(); + } + else //г̡תһȦת4 + { + motor_data[0] = 0x01;//00 ֱг 01 г + //жϵֹͣУеʼλǽλ + if( Motor_Run == 0)//ֹͣ + { + motor_stop(); + } + else if(Motor_Run == 1)// + { + if(Motor_Run >= 1 && Runmotor_step == 0) + { + Runmotor_step = 1; + } + + //жϵзʽǵ㶯㶯ΪһͷΪ + if(Run_Mode == 0)//㶯 + { + motor_data[2] = 0x00;//ʱ + mov_step_ang();//㶯 + } + else if(Run_Mode == 1)//һ + { + motor_data[2] = 0x01;//ʱ + mov_loop1_ang();//תһȦ + } + else if(Run_Mode == 2)// + { + motor_data[2] = 0x02;//ʱ + if(seat_flag == 0) + { + if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0) //жǷ񵽴λ + { + motor_stop(); //ֹͣ + Run_mm = 0; + seat_flag = 1;//λñ + } + else + { + REV(); //ת + motor_start(); // + motor_mov(1); //ṩź + } + } + else + { + mov_loop2_ang();//תһȦ + } + } + else//ʼ + { + motor_stop(); + } + } + else if(Motor_Run == 2 || Motor_Run == 3)//еʼλ + { + mov_begin();//صʼλ + } + else//ݴ + SC_Init(); + } +} + + +/***************************************************** +*: motor_mov +*: ٶȿ +*˵speed ٶ趨ֵ1Ϊ죬5Ϊ +*****************************************************/ +void motor_mov(unsigned int speed) +{ + switch(speed)//Ƶٶȣ趨嵵ٶ + { + //2ms + case 1: + { + if(it_1ms_flag) //1msʱ־ + { + it_1ms_flag = 0;//ʱ־ + if(mov_flag) + { + mov_flag = 0; + GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + } + else + { + mov_flag = 1; + GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + } + Runmotor_Nums++; //д + } + } + break; + //4ms + case 2: + { + if(it_2ms_flag)//2msʱ־ + { + it_2ms_flag = 0;//ʱ־ + if(mov_flag) + { + mov_flag = 0; + GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + } + else + { + mov_flag = 1; + GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + } + Runmotor_Nums++; //д + } + } + break; + //6ms + case 3: + { + if(it_3ms_flag)//3msʱ־ + { + it_3ms_flag = 0;//ʱ־ + if(mov_flag) + { + mov_flag = 0; + GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + } + else + { + mov_flag = 1; + GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + } + Runmotor_Nums++; //д + } + } + break; + //8ms + case 4: + { + if(it_4ms_flag)//4msʱ־ + { + it_4ms_flag = 0;//ʱ־ + if(mov_flag) + { + mov_flag = 0; + GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + } + else + { + mov_flag = 1; + GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + } + Runmotor_Nums++; //д + } + } + break; + //10ms + case 5: + { + if(it_5ms_flag)//5msʱ־ + { + it_5ms_flag = 0;//ʱ־ + if(mov_flag) + { + mov_flag = 0; + GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + } + else + { + mov_flag = 1; + GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + } + Runmotor_Nums++; //д + } + } + break; + default : + break; + } +} + + + +//Уһֱг̣ +void mov_loop1(void) +{ + if(Run_Step == 0) return;//Ϊ0 + + switch(Runmotor_step) + { + case 1 : //׼ + { + + FWD(); //ת + motor_dire = 1; + Run_mm = 0; + Run_num = 0; + motor_data[2] = 0x00; //ʱ + Runmotor_Nums = 0; //д + mov_flag = 0; + Runmotor_step++; + } + break; + case 2 : //й + { + if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 0) //դźж + { + if(it_1s_flag) //1msʱ־ + { + it_1s_flag = 0;//ʱ־ + Runmotor_Nums++; + } + if(Runmotor_Nums >= Run_Stop)//ʱ + { + Runmotor_step++; + motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + motor_seat(); //ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + } + else + { + if(send_flag == 0) + { + send_flag = 1; + motor_seat();//ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + motor_start(); // + motor_mov(1); //1 + Run_mm = 1; //ƶ0 + Runmotor_Nums = 0; // + Runmotor_step = 6; + } + } + break; + case 3 : //ʱ + { + if(motor_dire == 1) + { + motor_start(); // + motor_mov(1); //1 + if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + { + Runmotor_Nums = 0; // + motor_stop(); //ֹͣ + motor_data[1] = 0x01; //Ӧ01 + motor_data[3] = 0x03; //򡪡ʼ + Run_mm++; //ƶ1 + ct_num = Run_mm; // + motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + Runmotor_step++; + } + } + else + { + motor_start(); // + motor_mov(1); //1 + if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + { + Runmotor_Nums = 0; // + motor_stop(); //ֹͣ + motor_data[1] = 0x01; //Ӧ01 + motor_data[3] = 0x04; //򡪡ʼ + ct_num = ct_num - 1; // + Run_mm = ct_num; //ƶ1 + motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + Runmotor_step++; + } + } + } + break; + case 4 : //ʱ + { + if(it_1ms_flag) //1msʱ־ + { + it_1ms_flag = 0;//ʱ־ + Runmotor_Nums++; + } + if(Runmotor_Nums >= Run_Inter)//ʱ + { + + Runmotor_Nums = 0; + Runmotor_step++; + send_flag = 0; + //motor_seat(); //ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + + } + break; + case 5 : + { + if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 1 )//դźж + { + if(flag == 0) + { + Runmotor_Nums = 0; + Runmotor_step = 3; + if(motor_dire == 1) + { + REV(); + flag = 1; + motor_dire = 0; + } + else + { + Motor_Run = 2; //бǸı䣬صʼλ + } + } + else + { + Runmotor_step = 3; + } + } + else + { + Runmotor_step = 3; + flag = 0 ; + } + } + break; + case 6 : + { + if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0)//ʼλ + { + FWD();//ת + motor_dire = 1;//ת + } + if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//λ + { + REV();//ת + motor_dire = 0;//ת + } + Runmotor_step = 2; + } + break; + default : + { + + } + break; + } +} + +//Уһг̣ +void mov_loop1_ang(void) +{ + if(Run_Step == 0) return;//Ϊ0 + + switch(Runmotor_step) + { + case 1 : //׼ + { + FWD();//ת + motor_dire = 1; + motor_data[2] = 0x00;//ʱ + Runmotor_Nums = 0; //д + mov_flag = 0; + Run_mm = 0; + Run_num = 0; + Runmotor_step++; + } + break; + case 2 : //й + { + if(motor_dire == 1) + { + FWD();//ת + motor_start(); // + motor_mov(1); //1 + if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + { + Runmotor_Nums = 0; // + motor_stop(); //ֹͣ + motor_data[1] = 0x01; //Ӧ01 + motor_data[3] = 0x03; //򡪡ʼ + Run_mm++; //ƶ1 + Run_num = Run_mm * Run_Step; + motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + motor_data[9] = Run_num & 0x00ff; //ȵ8λ + Runmotor_step++; + } + } + else + { + REV();//ת + motor_start(); // + motor_mov(1); //1 + if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + { + Runmotor_Nums = 0; // + motor_stop(); //ֹͣ + motor_data[1] = 0x01; //Ӧ01 + motor_data[3] = 0x04; //򡪡ʼ + Run_mm--; //ƶ1 + Run_num = Run_mm * Run_Step; + motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + motor_data[9] = Run_num & 0x00ff; //ȵ8λ + Runmotor_step++; + } + } + } + break; + case 3 : //ʱ + { + if(it_1ms_flag) //1msʱ־ + { + it_1ms_flag = 0;//ʱ־ + Runmotor_Nums++; + } + if(Runmotor_Nums >= Run_Inter)//ʱ + { + Runmotor_Nums = 0; + Runmotor_step++; + //motor_seat(); //ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + } + break; + case 4 : + { + if(Run_num >= Run_Stop * 10&& motor_dire == 1)//жϴǷת趨ĽǶ + { + motor_dire = 0; + Runmotor_step = 2; + } + else if(Run_num <= 0 && motor_dire == 0) + { + //motor_dire = 1; + Motor_Run = 1; + } + else + { + Runmotor_step = 2; + } + } + break; + default : + { + + } + break; + } +} + + +//Уֱг̣ +void mov_loop2(void) +{ + if(Run_Step == 0) return;//Ϊ0 + + switch(Runmotor_step) + { + case 1 : //׼ + { + + FWD();//ת + motor_dire = 1; + motor_data[2] = 0x00;//ʱ + Runmotor_Nums = 0; //д + mov_flag = 0; // + Runmotor_step++; + } + break; + case 2 : //й + { + if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 0)//դźж + { + + if(it_1s_flag) //1msʱ־ + { + it_1s_flag = 0;//ʱ־ + Runmotor_Nums++; + } + if(Runmotor_Nums >= Run_Stop)//ʱ + { + Runmotor_step++; + motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + motor_seat(); //ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + }//Run_mm = 1; //ƶ1 + + } + else + { + if(send_flag == 0) + { + send_flag = 1; + motor_seat();//ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + motor_start(); // + motor_mov(1); //1 + Run_mm = 1; //ƶ0 + Runmotor_Nums = 0; // + Runmotor_step = 6; + } + } + break; + case 3 : //ʱ + { + if(motor_dire == 1) + { + motor_start(); // + motor_mov(1); //1 + if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + { + Runmotor_Nums = 0; // + motor_stop(); //ֹͣ + motor_data[1] = 0x01; //Ӧ01 + motor_data[3] = 0x03; //򡪡ʼ + Run_mm++; //ƶ1 + ct_num = Run_mm; // + motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + Runmotor_step++; + } + } + else + { + motor_start(); // + motor_mov(1); //1 + if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + { + Runmotor_Nums = 0; // + motor_stop(); //ֹͣ + motor_data[1] = 0x01; //Ӧ01 + motor_data[3] = 0x04; //򡪡ʼ + ct_num = ct_num - 1; // + Run_mm = ct_num; //ƶ1 + motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + Runmotor_step++; + } + } + } + break; + case 4 : //ʱ + { + if(it_1ms_flag) //1msʱ־ + { + it_1ms_flag = 0;//ʱ־ + Runmotor_Nums++; + } + if(Runmotor_Nums >= Run_Inter)//ʱ + { + + Runmotor_Nums = 0; + Runmotor_step++; + send_flag = 0; + //motor_seat(); //ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + + } + break; + case 5 : + { + if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 1 )//դźж + { + if(flag == 0) + { + Runmotor_Nums = 0; + Runmotor_step = 3; + if(motor_dire == 1) + { + REV(); + flag = 1; + motor_dire = 0; + } + else + { + FWD(); + flag = 1; + motor_dire = 1; + } + } + else + { + Runmotor_step = 3; + } + } + else + { + Runmotor_step = 3; + flag = 0 ; + } + } + break; + case 6 : + { + if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0)//ʼλ + { + FWD();//ת + motor_dire = 1;//ת + } + if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//λ + { + REV();//ת + motor_dire = 0;//ת + } + Runmotor_step = 2; + } + break; + + default : + { + + } + break; + } +} + +//Уг̣ +void mov_loop2_ang(void) +{ + if(Run_Step == 0) return;//Ϊ0 + + switch(Runmotor_step) + { + case 1 : //׼ + { + FWD();//ת + motor_dire = 1; + motor_data[2] = 0x00;//ʱ + Runmotor_Nums = 0; //д + mov_flag = 0; + Runmotor_step++; + } + break; + case 2 : //й + { + if(motor_dire == 1) + { + FWD();//ת + motor_start(); // + motor_mov(1); //1 + if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + { + Runmotor_Nums = 0; // + motor_stop(); //ֹͣ + motor_data[1] = 0x01; //Ӧ01 + motor_data[3] = 0x03; //򡪡ʼ + Run_mm++; //ƶ1 + Run_num = Run_mm * Run_Step; + motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + motor_data[9] = Run_num & 0x00ff; //ȵ8λ + Runmotor_step++; + } + } + else + { + REV();//ת + motor_start(); // + motor_mov(1); //1 + if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + { + Runmotor_Nums = 0; // + motor_stop(); //ֹͣ + motor_data[1] = 0x01; //Ӧ01 + motor_data[3] = 0x04; //򡪡ʼ + Run_mm--; //ƶ1 + Run_num = Run_mm * Run_Step; + motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + motor_data[9] = Run_num & 0x00ff; //ȵ8λ + Runmotor_step++; + } + } + } + break; + case 3 : //ʱ + { + if(it_1ms_flag) //1msʱ־ + { + it_1ms_flag = 0;//ʱ־ + Runmotor_Nums++; + } + if(Runmotor_Nums >= Run_Inter)//ʱ + { + Runmotor_Nums = 0; + Runmotor_step++; + //motor_seat(); //ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + } + break; + case 4 : + { + if(Run_num >= Run_Stop * 10)//жϴǷת趨ĽǶ + { + motor_dire = 0; + Runmotor_step = 2; + } + else if(Run_num <= 0) + { + motor_dire = 1; + Runmotor_step = 2; + } + else + { + Runmotor_step = 2; + } + } + break; + default : + { + + } + break; + } +} + +//㶯Уֱг̣ +void mov_step(void) +{ + if(Run_Step == 0) return;//Ϊ0 + + switch(Runmotor_step) + { + case 1 : //׼ + { + motor_start(); // + if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0)//жǷ񵽴ʼλ + FWD(); //ת + if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//жǷ񵽴λ + REV(); //ת + Runmotor_Nums = 0; //д + mov_flag = 0; + Runmotor_step++; + } + break; + case 2 : //й + { + motor_mov(1);//1 + if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + { + Runmotor_Nums = 0; + motor_stop(); //ֹͣ + Runmotor_step++; + Run_mm++; //ƶ1 + Run_num = Run_mm * Run_Step; + motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + motor_data[9] = Run_num & 0x00ff; //ȵ8λ +// motor_seat(); //ȡǰλ +// send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + } + break; + case 3 : + { + if(it_1ms_flag) //1msʱ־ + { + it_1ms_flag = 0;//ʱ־ + Runmotor_Nums++; + } + if(Runmotor_Nums >= 50)//ʱ + { + Runmotor_Nums = 0; + Runmotor_step++; + motor_seat(); //ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + } + break; + case 4 : + { + Runmotor_step = 0; + Motor_Run = 0; //б + } + break; + default : + { + + } + break; + } +} + +//㶯Уг̣ +void mov_step_ang(void) +{ + if(Run_Step == 0) return;//Ϊ0 + + switch(Runmotor_step) + { + case 1 : //׼ + { + motor_start(); // + FWD(); //ת + Runmotor_Nums = 0; //д + mov_flag = 0; + Runmotor_step++; + } + break; + case 2 : //й + { + motor_mov(1);//1 + if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + { + Runmotor_Nums = 0; + motor_stop(); //ֹͣ + Run_mm++; //ƶ1 + Run_num = Run_mm * Run_Step; + motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + motor_data[9] = Run_num & 0x00ff; //ȵ8λ + motor_seat(); //ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + Runmotor_step++; + } + } + break; + case 3 : + { + Runmotor_step = 0; + Motor_Run = 0; //б + if(Run_num >= 3600) //жϴǷתһȦ + Run_mm = 0; + } + break; + default : + { + + } + break; + } +} + +//صʼλ +void mov_begin(void) +{ + motor_data[1] = 0x02; //еʼλӦ02 + motor_data[8] = 0x00; //ȸ8λ + motor_data[9] = 0x00; //ȵ8λ + REV(); //ת + motor_start(); // + if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0) //жǷ񵽴λ + { + motor_stop(); //ֹͣ + Run_mm = 0; + Run_num = 0; + if(send_flag == 1) + { + send_flag = 0; + motor_seat(); //ȡǰλ + send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + } + } + else + motor_mov(1); //ṩ +} + +//صλ +void mov_end(void) +{ + motor_data[1] = 0x03; //еλӦ03 + FWD(); //ת + motor_start(); // + //Run_mm = 0; + if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//жǷ񵽴λ + motor_stop(); //ֹͣ + else + motor_mov(1); //ṩ +} + +//λж +void motor_seat(void) +{ + if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0) //ʼλش + motor_data[3] = 0x01; //ʱ + else if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//ڽλش + motor_data[3] = 0x02; //ʱ + else if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 0)//ͨդ + motor_data[3] = 0x03; //ʱ + else //״̬ + motor_data[3] = 0x00; //ʱ +} diff --git a/Keil_C/Apps/motor.h b/Keil_C/Apps/motor.h new file mode 100644 index 0000000..b6b711a --- /dev/null +++ b/Keil_C/Apps/motor.h @@ -0,0 +1,62 @@ +#ifndef _MOTOR_H_ +#define _MOTOR_H_ + +#include "SC_Init.h" //MCU Init headerInclude all IC resource headers +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" + +#include "sc92f_ssi.h" +#include "Uart1.h" +#include "adc.h" + +extern bit it_1ms_flag; //1msʱ־ +extern bit it_2ms_flag; //2msʱ־ +extern bit it_3ms_flag; //3msʱ־ +extern bit it_4ms_flag; //4msʱ־ +extern bit it_5ms_flag; //5msʱ־ +extern bit it_10ms_flag; //10msʱ־ +extern bit it_100ms_flag; //100msʱ־ +extern bit it_1s_flag; //1sʱ־ +extern bit it_2s_flag; //1sʱ־ +extern bit it_5s_flag; //5sʱ־ + +extern bit led_flag; //ledƿر־ +extern bit mov_flag; //־ +extern bit send_flag; //ͱ־ +extern bit seat_flag; //λñ־ +extern bit motor_dire; //ת + +extern bit Travle_Flag; //0 ֱ 1 +extern char xdata Motor_Run; //0 ֹͣ 1 2 еʼ 3 е +extern char xdata Run_Mode; //0 㶯 1 һ 2 +extern unsigned int xdata Run_Step; //в0.5mm / 㣩 +extern unsigned int xdata Run_Inter; //мʱms +extern unsigned int xdata Run_Stop; //㡱ֹͣʱ䣨s +extern unsigned int xdata Run_mm; //нȣmm +extern unsigned int xdata Run_num; //гתȦ +extern unsigned int xdata ct_num; // + +extern uint8_t xdata motor_data[]; // + +extern uint16_t xdata SUR_DEVICE_ADDR; //PC //0x00A1; //豸 +extern uint16_t xdata OBJ_DEVICE_ADDR; // //0x00B1; //PCȺ FFFF 0000 + +void motor_start(void); // +void motor_stop(void); //ֹͣ +void FWD(void); //ת +void REV(void); //ת +void ClrRunmotorStep(void); // +void Deal_Motor(void); // +void mov_loop1(void); //Уһֱг̣ +void mov_loop1_ang(void); //Уһг̣ +void mov_loop2(void); //Уֱг̣ +void mov_loop2_ang(void); //Уг̣ +void mov_step(void); //㶯Уֱг̣ +void mov_step_ang(void); //㶯Уг̣ +void motor_mov(unsigned int speed); //ٶȿ +void mov_begin(void); //صʼλ +void mov_end(void); //صλ +void motor_seat(void); //λж + +#endif diff --git a/Keil_C/Apps/test.c b/Keil_C/Apps/test.c new file mode 100644 index 0000000..e23676f --- /dev/null +++ b/Keil_C/Apps/test.c @@ -0,0 +1,80 @@ +#include "test.h" + +extern bit it_5s_flag; +extern bit it_2s_flag; +extern bit it_1s_flag; + +extern bit it_10ms_flag; +bit led_flag = 0;//ledƿر־ +bit motor_flag = 0;//־ + +/***************************************************** +*: led_test +*: IOڡʱڲú +*ڲvoid +*ڲvoid +*****************************************************/ +void led_test() +{ + //ָʾ + if(it_1s_flag == 1)//1 + { + it_1s_flag = 0; + if(led_flag) + { + led_flag = 0; + GPIO_WriteHigh(GPIO0,GPIO_PIN_0);//P0.01ledƹر + GPIO_WriteHigh(GPIO2,GPIO_PIN_6);//P2.61ledƹر + GPIO_WriteHigh(GPIO2,GPIO_PIN_7);//P2.71ledƹر + } + else + { + led_flag = 1; + GPIO_WriteLow(GPIO0,GPIO_PIN_0);//P0.00led + GPIO_WriteLow(GPIO2,GPIO_PIN_6);//P2.60led + GPIO_WriteLow(GPIO2,GPIO_PIN_7);//P2.70led + } + } +} + +/***************************************************** +*: motor_test +*: Ʋú +*ڲvoid +*ڲvoid +*****************************************************/ +void motor_test() +{ + bit t1,t2; + t1 = GPIO_ReadPin(GPIO1,GPIO_PIN_4); + t2 = GPIO_ReadPin(GPIO1,GPIO_PIN_5); + motor_start(); + motor_mov(2); + if(~t1) + { + FWD(); + } + if(~t2) + { + REV(); + } + if(it_5s_flag)//2붨ʱжϱ־ + { + it_5s_flag = 0;//־λ + if(motor_flag) + { + motor_flag = 0; + FWD();//ת + GPIO_WriteLow(GPIO0,GPIO_PIN_0);//P0.00led + } + else + { + motor_flag = 1; + REV();//ת + GPIO_WriteHigh(GPIO0,GPIO_PIN_0);//P0.01ledƹر + } + + } +} + + diff --git a/Keil_C/Apps/test.h b/Keil_C/Apps/test.h new file mode 100644 index 0000000..10725cc --- /dev/null +++ b/Keil_C/Apps/test.h @@ -0,0 +1,21 @@ +#ifndef _TEST_H_ +#define _TEST_H_ + +#include "SC_Init.h" //MCU Init headerInclude all IC resource headers +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" +#include "sc92f_ssi.h" +#include "Uart1.h" +#include "motor.h" + +extern bit it_1s_flag; //1sʱ־ +extern bit it_100ms_flag; //100msʱ־ +extern bit it_5ms_flag; //5msʱ־ + +extern bit led_flag; //ledƿر־ + +void led_test(); +void motor_test(); + +#endif \ No newline at end of file diff --git a/Keil_C/Drivers/SCDriver_List.h b/Keil_C/Drivers/SCDriver_List.h new file mode 100644 index 0000000..31ceae4 --- /dev/null +++ b/Keil_C/Drivers/SCDriver_List.h @@ -0,0 +1,13 @@ +//************************************************************ +// Copyright (c) +// ļ : SCDriver_List.H +// : Andy +// ģ鹦 : Ӧͷļб +// : 2019/1/16 +// 汾 : V0.1 +// ˵ ͷļʹõӦļ +//************************************************************* +#ifndef _SCDriver_List_H_ +#define _SCDriver_List_H_ + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F7003_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F7003_C.H new file mode 100644 index 0000000..7e09ca4 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F7003_C.H @@ -0,0 +1,206 @@ + /*-------------------------------------------------------------------------- +SC92F7003_C.H + +C Header file for SC92F7003 microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.24 +--------------------------------------------------------------------------*/ +#ifndef _SC92F7003_H_ +#define _SC92F7003_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG1 = 0xAA; //ADCüĴ0 +sfr ADCCFG0 = 0xAB; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON0 = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMCON1 = 0xDA; //PWMƼĴ +sfr PWMDTYB = 0xDB; //PWMռձüĴB +sfr PWMDTY3 = 0xDC; //PWM3üĴ +sfr PWMDTY4 = 0xDD; //PWM4üĴ +sfr PWMDTY5 = 0xDE; //PWM5üĴ +sfr PWMDTY6 = 0xDF; //PWM6üĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +sfr OTCON = 0X8F; //ƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //uartƼĴ +sfr SBUF = 0X99; //uart0ݼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSCON2 = 0X95; //SSIƼĴ2 +sfr SSDAT = 0X9F; //SSIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨 UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨 INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨 INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/* P0 */ +sbit P01 = P0^1; +sbit P00 = P0^0; + +/* P1 */ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/* P2 */ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F725X_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F725X_C.H new file mode 100644 index 0000000..8703946 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F725X_C.H @@ -0,0 +1,209 @@ + /*-------------------------------------------------------------------------- +SC92F725x_C.H + +C Header file for SC92F725x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.04.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F725x_H_ +#define _SC92F725x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON= 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD1; //PWMüĴ + +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMCFG1 = 0xD4; //PWMüĴ +sfr PWMDTY0 = 0xD5; //PWMռձüĴ +sfr PWMDTY1 = 0XD6; //PWMռձüĴ +sfr PWMDTY2 = 0XD7; //PWMռձüĴ +sfr PWMDTY3 = 0xDD; //PWMռձüĴ +sfr PWMDTY4 = 0XDE; //PWMռձüĴ +sfr PWMDTY5 = 0XDF; //PWMռձüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*option*/ +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT0жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT1жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT1ж 1:INT1ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7252װδĹܽţ +*SC92F7251װδĹܽţP04/P05 +*SC92F7250װδĹܽţP0 +******************************************/ +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7252װδĹܽţ +*SC92F7251װδĹܽţ +*SC92F7250װδĹܽţP10/P11/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7252װδĹܽţ +*SC92F7251װδĹܽţP26/P27 +*SC92F7250װδĹܽţP24/P25 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7252õú궨塣 +*****************************************************************************/ +#define SC92F7251_NIO_Init() {P0CON|=0xF0;P1CON|=0x30;P2CON|=0xCC;} //SC92F7251δIO +#define SC92F7250_NIO_Init() {P0CON|=0xFF;P1CON|=0xF3;P2CON|=0x3C;} //SC92F7250δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F730x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F730x_C.H new file mode 100644 index 0000000..5e3255f --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F730x_C.H @@ -0,0 +1,199 @@ + /*-------------------------------------------------------------------------- +SC92F730x_C.H + +C Header file for SC92F730x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.11.23 +--------------------------------------------------------------------------*/ +#ifndef _SC92F730x_H_ +#define _SC92F730x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON= 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD1; //PWMüĴ + +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMCFG1 = 0xD4; //PWMüĴ +sfr PWMDTY0 = 0xD5; //PWMռձüĴ +sfr PWMDTY1 = 0XD6; //PWMռձüĴ +sfr PWMDTY2 = 0XD7; //PWMռձüĴ +sfr PWMDTY3 = 0xDD; //PWMռձüĴ +sfr PWMDTY4 = 0XDE; //PWMռձüĴ +sfr PWMDTY5 = 0XDF; //PWMռձüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*option*/ +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT0жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT1жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7309װδĹܽţ +*SC92F7308װδĹܽţP00/P01 +******************************************/ +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7309װδĹܽţ +*SC92F7308װδĹܽţP10/P11 +******************************************/ +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7309װδĹܽţ +*SC92F7308װδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*****************************************************************************/ +#define SC92F7309_NIO_Init() {P0CON|=0xF0;P1CON|=0xF0;P2CON|=0x3C;} //SC92F7309δIO +#define SC92F7308_NIO_Init() {P0CON|=0xF3;P1CON|=0xF3;P2CON|=0x3C;} //SC92F7308δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F732x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F732x_C.H new file mode 100644 index 0000000..18f9a07 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F732x_C.H @@ -0,0 +1,232 @@ + /*-------------------------------------------------------------------------- +SC92F732x_C.H + +C Header file for SC92F732x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.04.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F732x_H_ +#define _SC92F732x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON= 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L= 0XCA; //ʱ2/׽8λ +sfr RCAP2H= 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMߵƽüĴ +sfr PWMDTY0 = 0xD5; //PWMߵƽüĴ +sfr PWMDTY1 = 0XD6; //PWMߵƽüĴ +sfr PWMDTY2 = 0XD7; //PWMߵƽüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*option*/ +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7323װδĹܽţ +*SC92F7322װδĹܽţP06/P07 +*SC92F7321װδĹܽţP04/P05/P06/P07 +*SC92F7320װδĹܽţP0 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/************************ P1 ********************* +*SC92F7323װδĹܽţ +*SC92F7322װδĹܽţP14/P15 +*SC92F7321װδĹܽţP14/P15 +*SC92F7320װδĹܽţP10/P11/P14/P15/P16/P17 +**************************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************** P2 *******%********** +*SC92F7323װδĹܽţ +*SC92F7322װδĹܽţP22/P23 +*SC92F7321װδĹܽţP24/P25/P26/P27 +*SC92F7320װδĹܽţP22/P23/P24/P25 +*********************************%*********/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************** P5 ************** +*SC92F7323װδĹܽţ +*SC92F7322װδĹܽţP50/P51 +*SC92F7321װδĹܽţP50/P51 +*SC92F7320װδĹܽţP50/P51 +***********************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7323õú궨塣 +*****************************************************************************/ +#define SC92F7322_NIO_Init() {P0CON|=0xC0;P1CON|=0x30;P2CON|=0x0C;P5CON|=0x03;} //SC92F7322δIO +#define SC92F7321_NIO_Init() {P0CON|=0xF0;P1CON|=0x30;P2CON|=0xF0;P5CON|=0x03;} //SC92F7321δIO +#define SC92F7320_NIO_Init() {P0CON|=0xFF;P1CON|=0xF3;P2CON|=0x3C;P5CON|=0x03;} //SC92F7320δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F735x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F735x_C.H new file mode 100644 index 0000000..1b062fb --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F735x_C.H @@ -0,0 +1,209 @@ + /*-------------------------------------------------------------------------- +SC92F735x_C.H + +C Header file for SC92F735x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.04.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F735x_H_ +#define _SC92F735x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON= 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD1; //PWMüĴ + +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMCFG1 = 0xD4; //PWMüĴ +sfr PWMDTY0 = 0xD5; //PWMռձüĴ +sfr PWMDTY1 = 0XD6; //PWMռձüĴ +sfr PWMDTY2 = 0XD7; //PWMռձüĴ +sfr PWMDTY3 = 0xDD; //PWMռձüĴ +sfr PWMDTY4 = 0XDE; //PWMռձüĴ +sfr PWMDTY5 = 0XDF; //PWMռձüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*option*/ +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT0жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT1жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7352װδĹܽţ +*SC92F7351װδĹܽţP04/P05 +*SC92F7350װδĹܽţP0 +******************************************/ +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7352װδĹܽţ +*SC92F7351װδĹܽţ +*SC92F7350װδĹܽţP10/P11/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7352װδĹܽţ +*SC92F7351װδĹܽţP26/P27 +*SC92F7350װδĹܽţP24/P25 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7352õú궨塣 +*****************************************************************************/ +#define SC92F7351_NIO_Init() {P0CON|=0xF0;P1CON|=0x30;P2CON|=0xCC;} //SC92F7351δIO +#define SC92F7350_NIO_Init() {P0CON|=0xFF;P1CON|=0xF3;P2CON|=0x3C;} //SC92F7350δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F736xB_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F736xB_C.H new file mode 100644 index 0000000..7ece2bf --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F736xB_C.H @@ -0,0 +1,252 @@ + /*-------------------------------------------------------------------------- +SC92F746xB_C.H + +C Header file for SC92F736xB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.06.15 +--------------------------------------------------------------------------*/ +#ifndef _SC92F736xB_H_ +#define _SC92F736xB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr16 RCAP2 = 0xCA; +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT0жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7363BװδĹܽţ +*SC92F736BװδĹܽţP06/P07 +*SC92F7361BװδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7363BװδĹܽţ +*SC92F7362BװδĹܽţP16/P17 +*SC92F7361BװδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7363BװδĹܽţ +*SC92F7362BװδĹܽţP22/P23 +*SC92F7361BװδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F7363BװδĹܽţ +*SC92F7362BװδĹܽţP50/P51 +*SC92F7361BװδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7363Bõú궨塣 +*****************************************************************************/ +#define SC92F7362B_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F7362BδIO +#define SC92F7361B_NIO_Init() {P0CON|=0xEC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F7361BδIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F740x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F740x_C.H new file mode 100644 index 0000000..76a2903 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F740x_C.H @@ -0,0 +1,222 @@ + /*-------------------------------------------------------------------------- +SC92F740x_C.H + +C Header file for SC92F740x microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.10.31 +--------------------------------------------------------------------------*/ +#ifndef _SC92F740x_H_ +#define _SC92F740x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG1 = 0xAA; //ADCüĴ0 +sfr ADCCFG0 = 0xAB; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON0 = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMCON1 = 0xDA; //PWMƼĴ +sfr PWMDTYB = 0xDB; //PWMռձüĴB +sfr PWMDTY3 = 0xDC; //PWM3üĴ +sfr PWMDTY4 = 0xDD; //PWM4üĴ +sfr PWMDTY5 = 0xDE; //PWM5üĴ +sfr PWMDTY6 = 0xDF; //PWM6üĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +sfr OTCON = 0X8F; //ƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //uartƼĴ +sfr SBUF = 0X99; //uart0ݼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSCON2 = 0X95; //SSIƼĴ2 +sfr SSDAT = 0X9F; //SSIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨 UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨 INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨 INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7402װδĹܽţ +*SC92F7401װδĹܽţ +******************************************/ +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7402װδĹܽţ +*SC92F7401װδĹܽţP12/P13 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7402װδĹܽţ +*SC92F7401װδĹܽţP24/P25 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7402õú궨塣 +*****************************************************************************/ +#define SC92F7401_NIO_Init() {P1CON|=0x0C,P2CON|=0x30;} //SC92F7401δIO +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F742x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F742x_C.H new file mode 100644 index 0000000..99ae7c6 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F742x_C.H @@ -0,0 +1,237 @@ + /*-------------------------------------------------------------------------- +SC92F742x_C.H + +C Header file for SC92F742x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.05.15 +--------------------------------------------------------------------------*/ +#ifndef _SC92F742x_H_ +#define _SC92F742x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD1; //PWMüĴ0 +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMCFG1 = 0xD4; //PWMüĴ1 +sfr PWMDTY0 = 0xD5; //PWM0ռձüĴ +sfr PWMDTY1 = 0XD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0XD7; //PWM2ռձüĴ +sfr PWMDTY3 = 0xDD; //PWM3ռձüĴ +sfr PWMDTY4 = 0XDE; //PWM4ռձüĴ +sfr PWMDTY5 = 0XDF; //PWM5ռձüĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*SSI*/ +sfr SS0CON0 = 0XA5; //SSI0ƼĴ2 +sfr SS0CON1 = 0XA6; //SSI0ƼĴ1 +sfr SS0CON2 = 0XA4; //SSI0ƼĴ0 +sfr SS0DAT = 0XA7; //SSI0ݼĴ + +sfr SS1CON2 = 0X95; //SSI1ƼĴ2 +sfr SS1CON0 = 0X9D; //SSI1ƼĴ0 +sfr SS1CON1 = 0X9E; //SSI1ƼĴ1 +sfr SS1DAT = 0X9F; //SSI1ݼĴ + +/*CHKSUM*/ +sfr OPERCON = 0xEF; //ƼĴ +sfr CHKSUML = 0xFC; //CHKSUMĴλ +sfr CHKSUMH = 0XFD; //CHKSUMĴλ + +/*option*/ +sfr OPINX = 0XFE; //Optionָ +sfr OPREG = 0XFF; //OptionĴ + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPSSI0 = IP^4; //SSI0жȿλ 0:趨SSI0жȨ ͡ 1:趨SSI0жȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit ESSI0 = IE^4; //SSI0жʹܿ 0:رSSI0ж 1:SSI0ж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/******************* P0 ****************** +*SC92F7423װδĹܽţ +*SC92F7422װδĹܽţP06/P07 +*SC92F7421װδĹܽţP04/P05/P06/P07 +*SC92F7420װδĹܽţP0 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/************************ P1 ********************* +*SC92F7423װδĹܽţ +*SC92F7422װδĹܽţP14/P15 +*SC92F7421װδĹܽţP14/P15 +*SC92F7420װδĹܽţP10/P11/P14/P15/P16/P17 +**************************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************** P2 *******%********** +*SC92F7423װδĹܽţ +*SC92F7422װδĹܽţP22/P23 +*SC92F7421װδĹܽţP24/P25/P26/P27 +*SC92F7420װδĹܽţP22/P23/P24/P25 +*********************************%*********/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************** P5 ************** +*SC92F7423װδĹܽţ +*SC92F7422װδĹܽţP50/P51 +*SC92F7421װδĹܽţP50/P51 +*SC92F7420װδĹܽţP50/P51 +***********************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7423õú궨塣 +*****************************************************************************/ +#define SC92F7422_NIO_Init() {P0CON|=0xC0;P1CON|=0x30;P2CON|=0x0C;P5CON|=0x03;} //SC92F7422δIO +#define SC92F7421_NIO_Init() {P0CON|=0xF0;P1CON|=0x30;P2CON|=0xF0;P5CON|=0x03;} //SC92F7421δIO +#define SC92F7420_NIO_Init() {P0CON|=0xFF;P1CON|=0xF3;P2CON|=0x3C;P5CON|=0x03;} //SC92F7420δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F744xB_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F744xB_C.H new file mode 100644 index 0000000..e48dd76 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F744xB_C.H @@ -0,0 +1,294 @@ +/*-------------------------------------------------------------------------- +SC92F744xB_C.H + +C Header file for SC92F744xB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.10.30 +--------------------------------------------------------------------------*/ +#ifndef _SC92F744xB_H_ +#define _SC92F744xB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMƼĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţ +*SC92F7445BװδĹܽţP00 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţ +*SC92F7445BװδĹܽţ +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţ +*SC92F7445BװδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţ +*SC92F7445BװδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţP46/P47 +*SC92F7445BװδĹܽţP40 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F7447BװδĹܽţ +*SC92F7446BװδĹܽţP54/P55 +*SC92F7445BװδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7447Bõú궨塣 +*****************************************************************************/ +#define SC92F7446B_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F7546BδIO +#define SC92F7445B_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F7545BδIO +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F746xB_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F746xB_C.H new file mode 100644 index 0000000..4cd2c72 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F746xB_C.H @@ -0,0 +1,251 @@ + /*-------------------------------------------------------------------------- +SC92F746XB_C.H + +C Header file for SC92F746XB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2018.08.24 +--------------------------------------------------------------------------*/ +#ifndef _SC92F746XB_H_ +#define _SC92F746XB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7463BװδĹܽţ +*SC92F7462BװδĹܽţP06/P07 +*SC92F7461BװδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7463BװδĹܽţ +*SC92F7462BװδĹܽţP16/P17 +*SC92F7461BװδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7463BװδĹܽţ +*SC92F7462BװδĹܽţP22/P23 +*SC92F7461BװδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F7463BװδĹܽţ +*SC92F7462BװδĹܽţP50/P51 +*SC92F7461BװδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7463Bõú궨塣 +*****************************************************************************/ +#define SC92F7462B_IO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F7462BδIO +#define SC92F7461B_IO_Init() {P0CON|=0xEC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F7461BδIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F748x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F748x_C.H new file mode 100644 index 0000000..6ac39b7 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F748x_C.H @@ -0,0 +1,254 @@ +/*-------------------------------------------------------------------------- +SC92F748x_C.H + +C Header file for SC92F748x microcontroller. +Copyright (c) 2021 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.2 +: 2021.07.14 +--------------------------------------------------------------------------*/ +#ifndef _SC92F748x_H_ +#define _SC92F748x_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr ACC = 0XE0; //ۼ +sfr B = 0XF0; //BĴ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr DPH = 0X83; //DPTRָλ +sfr DPL = 0X82; //DPTRָλ +sfr SP = 0X81; //ջָ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0XB8; //жȨƼĴ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr IOHCON = 0X97; //IOHüĴ +sfr P5PH = 0XDA; //P5ƼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P0VO = 0X9C; //P0LCDѹĴ +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0 = 0X80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr TH1 = 0X8D; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TL0 = 0X8A; //ʱ08λ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TCON = 0X88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ + +/*PWM*/ +sfr PWMCFG = 0XD1; //PWMüĴ +sfr PWMCON = 0XD2; //PWMƼĴ +sfr PWMPRD = 0XD3; //PWMüĴ +sfr PWMDTYA = 0XD4; //PWMռձüĴA +sfr PWMDTY0 = 0XD5; //PWM0üĴ +sfr PWMDTY1 = 0XD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0XD7; //PWM2ռձüĴ +sfr PWMDTYB = 0XDC; //PWMռձüĴB +sfr PWMDTY3 = 0XDD; //PWM3ռձüĴ/PWMʱüĴ +sfr PWMDTY4 = 0XDE; //PWM4ռձüĴ +sfr PWMDTY5 = 0XDF; //PWM5ռձüĴ + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0XF6; //IAPƼĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPADE = 0XF4; //IAPչַĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPKEY = 0XF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ +sfr OTCON = 0X8F; //ƼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //USCIƼĴ0 +sfr SSCON1 = 0X9E; //USCIƼĴ1 +sfr SSCON2 = 0X95; //USCIƼĴ2 +sfr SSDAT = 0X9F; //USCIݼĴ3 + +/*OPTION*/ +sfr OPINX = 0XFE; //Customer Optionָ +sfr OPREG = 0XFF; //Customer OptionĴ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ +sfr OPERCON = 0XEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; //ʱ2־λ +sbit EXF2 = T2CON^6; //T2EXⲿ¼(½)⵽ı־λ +sbit RCLK = T2CON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLK = T2CON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXEN2 = T2CON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TR2 = T2CON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit T2 = T2CON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = T2CON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + +/******************* P0 ****************** +*SC92F7483װδĹܽţ +*SC92F7482װδĹܽţP06/P07 +*SC92F7481װδĹܽţP02/P03/P04/P05/P06/P07 +*SC92F7480װδĹܽţP0 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7483װδĹܽţ +*SC92F7482װδĹܽţP16/P17 +*SC92F7481װδĹܽţP16/P17 +*SC92F7480װδĹܽţP14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7483װδĹܽţ +*SC92F7482װδĹܽţP22/P23 +*SC92F7481װδĹܽţP22/P23/P27 +*SC92F7480װδĹܽţP22/P23/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F7483װδĹܽţ +*SC92F7482װδĹܽţP50/P51 +*SC92F7481װδĹܽţP50/P51 +*SC92F7480װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7483õú궨塣 +*****************************************************************************/ +#define SC92F7482_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;}//SC92F7482δIO +#define SC92F7481_NIO_Init() {P0CON|=0xFC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;}//SC92F7481δIO +#define SC92F7480_NIO_Init() {P0CON|=0xFF,P1CON|=0xF0,P2CON|=0xEC,P5CON|=0x03;}//SC92F7480δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F7490_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F7490_C.H new file mode 100644 index 0000000..6a22ab7 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F7490_C.H @@ -0,0 +1,176 @@ + /*-------------------------------------------------------------------------- +SC92F7490_C.H + +C Header file for SC92F7490 microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.07.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F7490_H_ +#define _SC92F7490_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ + +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*SSI*/ +sfr SS0CON0 = 0XA5; //SSI0ƼĴ2 +sfr SS0CON1 = 0XA6; //SSI0ƼĴ1 +sfr SS0CON2 = 0XA4; //SSI0ƼĴ0 +sfr SS0DAT = 0XA7; //SSI0ݼĴ + +sfr SS1CON2 = 0X95; //SSI1ƼĴ2 +sfr SS1CON0 = 0X9D; //SSI1ƼĴ0 +sfr SS1CON1 = 0X9E; //SSI1ƼĴ1 +sfr SS1DAT = 0X9F; //SSI1ݼĴ + +/*CHKSUM*/ +sfr OPERCON = 0xEF; //ƼĴ +sfr CHKSUML = 0xFC; //CHKSUMĴλ +sfr CHKSUMH = 0XFD; //CHKSUMĴλ + +/*option*/ +sfr OPINX = 0XFE; //Optionָ +sfr OPREG = 0XFF; //OptionĴ + +sfr P5PH = 0xDA; +sfr P5CON = 0xD9; +sfr P5 = 0xD8; +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPSSI0 = IP^4; //SSI0жȿλ 0:趨SSI0жȨ ͡ 1:趨SSI0жȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit ESSI0 = IE^4; //SSI0жʹܿ 0:رSSI0ж 1:SSI0ж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/******************* P0 ******************/ +sbit P05 = P0^5; + +/******************* P1 ******************/ +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; + +/******************* P2 ******************/ +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺ʼIOںºꡣ +*****************************************************************************/ +#define SC92F7490_NIO_Init() {P0CON|=0xDF;P1CON|=0xF1;P2CON|=0xFC;P5CON|=0x03;} + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F74Ax_2_ASM.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F74Ax_2_ASM.H new file mode 100644 index 0000000..ffec448 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F74Ax_2_ASM.H @@ -0,0 +1,294 @@ +/*-------------------------------------------------------------------------- +SC92F74Ax_ASM.H + +ASM Header file for SC92F74Ax microcontroller. +Copyright (c) 2020 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2020.07.01 + + +--------------------------------------------------------------------------*/ +#ifndef _SC92F74Ax_ASM_H_ +#define _SC92F74Ax_ASM_H_ + +/* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +ACC EQU 0xE0; //ۼ +B EQU 0xF0; //ͨüĴB +PSW EQU 0xD0; //״̬ +DPH EQU 0x83; //ָ8λ +DPL EQU 0x82; //ָ8λ +SP EQU 0x81; //ջָ + +/*system*/ +PCON EQU 0x87; //ԴƼĴ + +/*interrupt*/ +IP EQU 0xB8; //жȨƼĴ +IE EQU 0xA8; //жϿƼĴ +IP1 EQU 0XB9; //жȼƼĴ1 +IE1 EQU 0XA9; //жϿƼĴ1 + +/*PORT*/ +P5PH EQU 0xDA; //P5ģʽƼĴ +P5CON EQU 0xD9; //P5ģʽƼĴ +P5 EQU 0xD8; //P5ݼĴ +P4PH EQU 0xC2; //P4ģʽƼĴ +P4CON EQU 0xC1; //P4ģʽƼĴ +P4 EQU 0xC0; //P4ݼĴ +P3PH EQU 0xB2; //P3ģʽƼĴ +P3CON EQU 0xB1; //P3ģʽƼĴ +P3 EQU 0xB0; //P3ݼĴ +P2PH EQU 0xA2; //P2ģʽƼĴ +P2CON EQU 0xA1; //P2ģʽƼĴ +P2 EQU 0xA0; //P2ݼĴ +P1PH EQU 0x92; //P1ģʽƼĴ +P1CON EQU 0x91; //P1ģʽƼĴ +P1 EQU 0x90; //P1ݼĴ +P0PH EQU 0x9B; //P0ģʽƼĴ +P0CON EQU 0x9A; //P0ģʽƼĴ +P0 EQU 0x80; //P0ݼĴ +IOHCON0 EQU 0x96; //IOH0üĴ +IOHCON1 EQU 0x97; //IOH1üĴ + +/*TIMER*/ +TMCON EQU 0x8E; //ʱƵʿƼĴ +TH1 EQU 0x8D; //ʱ18λ +TH0 EQU 0x8C; //ʱ08λ +TL1 EQU 0x8B; //ʱ18λ +TL0 EQU 0x8A; //ʱ08λ +TMOD EQU 0x89; //ʱģʽĴ +TCON EQU 0x88; //ʱƼĴ +T2CON EQU 0XC8; //ʱ2ƼĴ +T2MOD EQU 0XC9; //ʱ2ģʽĴ +RCAP2L EQU 0XCA; //ʱ2/׽8λ +RCAP2H EQU 0XCB; //ʱ2/׽8λ +TL2 EQU 0XCC; //ʱ28λ +TH2 EQU 0XCD; //ʱ28λ + +/*ADC*/ +ADCCFG0 EQU 0xAB; //ADCüĴ0 +ADCCFG1 EQU 0xAC; //ADCüĴ1 +ADCCFG2 EQU 0xAA; //ADCüĴ2 +ADCCON EQU 0XAD; //ADCƼĴ +ADCVL EQU 0xAE; //ADC Ĵ +ADCVH EQU 0xAF; //ADC Ĵ + +/*PWM*/ +PWMCFG EQU 0xD4; //PWMüĴ +PWMCON EQU 0xD3; //PWMƼĴ + +/*WatchDog*/ +BTMCON EQU 0XCE; //ƵʱƼĴ +WDTCON EQU 0xCF; //WDTƼĴ + +/*LCD*/ +OTCON EQU 0X8F; //LCDѹƼĴ +P0VO EQU 0X9C; //P0 LCD Bais Ĵ +P1VO EQU 0X94; //P1 LCD Bais Ĵ +P2VO EQU 0XA3; //P2 LCD Bais Ĵ +P3VO EQU 0XB3; //P3 LCD Bais Ĵ + +DDRCON EQU 0X93; //ʾüĴ + +/*INT*/ +INT0F EQU 0XBA; //INT0 ½жϿƼĴ +INT0R EQU 0XBB; //INT0 ϽжϿƼĴ +INT1F EQU 0XBC; //INT1 ½жϿƼĴ +INT1R EQU 0XBD; //INT1 ϽжϿƼĴ +INT2F EQU 0XC6; //INT2 ½жϿƼĴ +INT2R EQU 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +IAPCTL EQU 0xF6; //IAPƼĴ +IAPDAT EQU 0xF5; //IAPݼĴ +IAPADE EQU 0xF4; //IAPչַĴ +IAPADH EQU 0xF3; //IAPдַλĴ +IAPADL EQU 0xF2; //IAPдַ8λĴ +IAPKEY EQU 0xF1; //IAPĴ + +/*uart*/ +SCON EQU 0x98; //ڿƼĴ +SBUF EQU 0x99; //ݻĴ + +/*һ*/ +SSCON0 EQU 0X9D; //SSIƼĴ0 +SSCON1 EQU 0X9E; //SSIƼĴ1 +SSCON2 EQU 0X95; //SSIƼĴ2 +SSDAT EQU 0X9F; //SPIݼĴ + +OPINX EQU 0XFE; +OPREG EQU 0XFF; +EXADH EQU 0XF7; + +/*Check Sum*/ +CHKSUML EQU 0XFC; //Check SumĴλ +CHKSUMH EQU 0XFD; //Check SumĴλ + +/*˳*/ +EXA0 EQU 0xE9; //չۼ0 +EXA1 EQU 0xEA; //չۼ1 +EXA2 EQU 0xEB; //չۼ2 +EXA3 EQU 0xEC; //չۼ3 +EXBL EQU 0xED; //չBĴ0 +EXBH EQU 0xEE; //չBĴ1 +OPERCON EQU 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +CY EQU PSW .7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +AC EQU PSW .6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +F0 EQU PSW .5; //û־λ +RS1 EQU PSW .4; //Ĵѡλ +RS0 EQU PSW .3; //Ĵѡλ +OV EQU PSW .2; //־λ +F1 EQU PSW .1; //F1־ +P EQU PSW .0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +TF2 EQU T2CON .7; +EXF2 EQU T2CON .6; +RCLK EQU T2CON .5; +TCLK EQU T2CON .4; +EXEN2 EQU T2CON .3; +TR2 EQU T2CON .2; +T2 EQU T2CON .1; +CP EQU T2CON .0; + +/*IP*/ +IPADC EQU IP .6; //ADCжȿλ 0:趨ADCжȨ ͡ 1:趨ADCжȨ ߡ +IPT2 EQU IP .5; //PWMжȿλ 0:趨PWMжȨ ͡ 1:趨PWM жȨ ߡ +IPUART EQU IP .4; //Uartжȿλ 0:趨UartжȨ ͡ 1:趨UartжȨ ߡ +IPT1 EQU IP .3; //Timer1жȿλ 0:趨Timer1жȨ ͡ 1:趨Timer1жȨ ߡ +IPINT1 EQU IP .2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +IPT0 EQU IP .1; //Timer0жȿλ 0:趨Timer0жȨ ͡ 1:趨Timer0жȨ ߡ +IPINT0 EQU IP .0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +EA EQU IE .7; //жʹܵܿ 0:رеж 1:еж +EADC EQU IE .6; //ADCжʹܿ 0:رADCж 1:ADCж +ET2 EQU IE .5; //PWMжʹܿ 0:رPWMж 1:PWMж +EUART EQU IE .4; //UARTжʹܿ 0:رUARTж 1:UARTж +ET1 EQU IE .3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +EINT1 EQU IE .2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +ET0 EQU IE .1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +EINT0 EQU IE .0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +TF1 EQU TCON .7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +TR1 EQU TCON .6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +TF0 EQU TCON .5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +TR0 EQU TCON .4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +BITIE1 EQU TCON .3; //INT1ж־ +BITIE0 EQU TCON .1; //INT0ж־ + +/*SCON*/ +SM0 EQU SCON .7; +SM1 EQU SCON .6; +SM2 EQU SCON .5; +REN EQU SCON .4; +TB8 EQU SCON .3; +RB8 EQU SCON .2; +TI EQU SCON .1; +RI EQU SCON .0; + +/******************* P0 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţP00 +******************************************/ +P07 EQU P0 .7; +P06 EQU P0 .6; +P05 EQU P0 .5; +P04 EQU P0 .4; +P03 EQU P0 .3; +P02 EQU P0 .2; +P01 EQU P0 .1; +P00 EQU P0 .0; + +/******************* P1 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţ +******************************************/ +P17 EQU P1 .7; +P16 EQU P1 .6; +P15 EQU P1 .5; +P14 EQU P1 .4; +P13 EQU P1 .3; +P12 EQU P1 .2; +P11 EQU P1 .1; +P10 EQU P1 .0; + +/******************* P2 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţ +******************************************/ +P27 EQU P2 .7; +P26 EQU P2 .6; +P25 EQU P2 .5; +P24 EQU P2 .4; +P23 EQU P2 .3; +P22 EQU P2 .2; +P21 EQU P2 .1; +P20 EQU P2 .0; + +/******************* P3 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţP3 +******************************************/ +P37 EQU P3 .7; +P36 EQU P3 .6; +P35 EQU P3 .5; +P34 EQU P3 .4; +P33 EQU P3 .3; +P32 EQU P3 .2; +P31 EQU P3 .1; +P30 EQU P3 .0; + +/******************* P4 ****************** +*SC92F74A7װδĹܽţ +*SC92F84A6װδĹܽţP46/P47 +*SC92F84A5װδĹܽţP40 +******************************************/ +P47 EQU P4 .7; +P46 EQU P4 .6; +P45 EQU P4 .5; +P44 EQU P4 .4; +P43 EQU P4 .3; +P42 EQU P4 .2; +P41 EQU P4 .1; +P40 EQU P4 .0; + +/******************* P5 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP54/P55 +*SC92F84A5װδĹܽţP5 +******************************************/ +P55 EQU P5 .5; +P54 EQU P5 .4; +P53 EQU P5 .3; +P52 EQU P5 .2; +P51 EQU P5 .1; +P50 EQU P5 .0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F74A7õú궨塣 +*****************************************************************************/ +SC92F74A6_NIO_Init MACRO IO //SC92F74A6δܽŵIO + ORL P4CON,#0XC0 + ORL P5CON,#0X30 + ENDM +SC92F74A5_NIO_Init MACRO IO //SC92F74A5δܽŵIO + ORL P0CON,#0X01 + ORL P3CON,#0XFF + ORL P4CON,#0X01 + ORL P5CON,#0X3F + ENDM +#endif diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F74Ax_2_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F74Ax_2_C.H new file mode 100644 index 0000000..6356b52 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F74Ax_2_C.H @@ -0,0 +1,296 @@ +/*-------------------------------------------------------------------------- +SC92F74Ax_C.H + +C Header file for SC92F74Ax microcontroller. +Copyright (c) 2020 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2020.07.01 +--------------------------------------------------------------------------*/ +#ifndef _SC92F74Ax_H_ +#define _SC92F74Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMƼĴ + + +// +//*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ +sbit BITIE0 = TCON^1; //INT0ж־ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţP00 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţ +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţ +*SC92F74A5װδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţP46/P47 +*SC92F74A5װδĹܽţP40 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F74A7װδĹܽţ +*SC92F74A6װδĹܽţP54/P55 +*SC92F74A5װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F74A7õú궨塣 +*****************************************************************************/ +#define SC92F74A6_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F74A6δIO +#define SC92F74A5_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0x3F;} //SC92F74A5δIO +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F754x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F754x_C.H new file mode 100644 index 0000000..fe6f5d3 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F754x_C.H @@ -0,0 +1,313 @@ + /*-------------------------------------------------------------------------- +SC92F754X_C.H + +C Header file for SC92F754X microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2019.03.18 +--------------------------------------------------------------------------*/ +#ifndef _SC92F754X_H_ +#define _SC92F754X_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMüĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*TKCON*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţ +*SC92F7545װδĹܽţP00 +*SC92F7543װδĹܽţP00/P01 +*SC92F7541װδĹܽţP00/P01/P04/P05/P06 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţ +*SC92F7545װδĹܽţ +*SC92F7543װδĹܽţP10/P14/P15/P16/P17 +*SC92F7541װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţ +*SC92F7545װδĹܽţ +*SC92F7543װδĹܽţP26/P27 +*SC92F7541װδĹܽţP24/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţ +*SC92F7545װδĹܽţP3 +*SC92F7543װδĹܽţ +*SC92F7541װδĹܽţP30/P31/P32/P33/P34/P35 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţP46/P47 +*SC92F7545װδĹܽţP40 +*SC92F7543װδĹܽţP40/P44/P45/P46/P47 +*SC92F7541װδĹܽţP4 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F7547װδĹܽţ +*SC92F7546װδĹܽţP54/P55 +*SC92F7545װδĹܽţP5 +*SC92F7543װδĹܽţP5 +*SC92F7541װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F7547õú궨塣 +*****************************************************************************/ +#define SC92F7546_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F7546δIO +#define SC92F7545_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F7545δIO +#define SC92F7543_NIO_Init() {P0CON|=0x03,P1CON|=0xF1,P2CON|=0xC0,P4CON|=0xF1,P5CON|=0xFF;} //SC92F7543δIO +#define SC92F7541_NIO_Init() {P0CON|=0x73,P1CON|=0xC1,P2CON|=0xF0,P3CON|=0x3F,P4CON|=0xFF,P5CON|=0xFF;} //SC92F7541δIO +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F759x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F759x_C.H new file mode 100644 index 0000000..5ab2301 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F759x_C.H @@ -0,0 +1,297 @@ +/*-------------------------------------------------------------------------- +SC92F859x_C.H + +C Header file for SC92F859x microcontroller. +Copyright (c) 2021 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.1 +: 2021.10.22 +--------------------------------------------------------------------------*/ +#ifndef _SC92F859x_H_ +#define _SC92F859x_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr SP = 0X81; //ջָ +sfr DPL = 0X82; //DPTRָλ +sfr DPH = 0X83; //DPTRָλ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr ACC = 0XE0; //ۼ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 +sfr B = 0XF0; //BĴ + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 +sfr IP = 0XB8; //жȨƼĴ +sfr IP1 = 0XB9; //жȼƼĴ1 + +/*PORT*/ +sfr P0 = 0X80; //P0ݼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr DDRCON = 0X93; //ʾƼĴ +sfr P1VO = 0X94; //P1ʾĴ +sfr IOHCON0 = 0X96; //IOHüĴ0 +sfr IOHCON1 = 0X97; //IOHüĴ1 +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P0VO = 0X9C; //P0LCDѹĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2VO = 0XA3; //P2ʾĴ +sfr P3 = 0XB0; //P3ݼĴ +sfr P3CON = 0XB1; //P3/ƼĴ +sfr P3PH = 0XB2; //P3ƼĴ +sfr P3VO = 0XB3; //P3ʾĴ +sfr P4 = 0XC0; //P4ݼĴ +sfr P4CON = 0XC1; //P4/ƼĴ +sfr P4PH = 0XC2; //P4ƼĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5PH = 0XDA; //P5ƼĴ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*TIMER*/ +sfr TCON = 0X88; //ʱƼĴ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TL0 = 0X8A; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TH1 = 0X8D; //ʱ18λ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ + +/*PWM*/ +sfr PWMCON = 0XD3; //PWM0ƼĴ0 +sfr PWMCFG = 0XD4; //PWMüĴ + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPKEY = 0XF1; //IAPĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADE = 0XF4; //IAPչַĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPCTL = 0XF6; //IAPƼĴ + +/*uart0*/ +sfr OTCON = 0X8F; //ƼĴ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*һ*/ +sfr SSCON2 = 0X95;//SSIƼĴ2 +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSDAT = 0X9F; //SSIݼĴ + +/*OPTION*/ +sfr OPINX = 0XFE; //Customer Optionָ +sfr OPREG = 0XFF; //Customer OptionĴ + +/*CRC*/ +sfr OPERCON = 0XEF; //ƼĴ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; //ʱ2־λ +sbit EXF2 = T2CON^6; //T2EXⲿ¼(½)⵽ı־λ +sbit RCLK = T2CON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLK = T2CON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXEN2 = T2CON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TR2 = T2CON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit T2 = T2CON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = T2CON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + + +/******************* P0 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţP00 +*SC92F8593װδĹܽţP00/P01 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţ +*SC92F8593װδĹܽţP10/P14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţ +*SC92F8593װδĹܽţP26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţP3 +*SC92F8593װδĹܽţ +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţP46/P47 +*SC92F8595װδĹܽţP40 +*SC92F8593װδĹܽţP40/P44/P45/P46/P47 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţP54/P55 +*SC92F8595װδĹܽţP5 +*SC92F8593װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8597õú궨塣 +*****************************************************************************/ +#define SC92F8596_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F8596δIO +#define SC92F8595_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F8595δIO +#define SC92F8593_NIO_Init() {P0CON|=0x03,P1CON|=0xF1,P2CON|=0xC0,P4CON|=0xF1,P5CON|=0xFF;}//SC92F8593δIO + + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F8003_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F8003_C.H new file mode 100644 index 0000000..d8e44f1 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F8003_C.H @@ -0,0 +1,207 @@ + /*-------------------------------------------------------------------------- +SC92F8003_C.H + +C Header file for SC92F8003 microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.05.02 +--------------------------------------------------------------------------*/ +#ifndef _SC92F8003_H_ +#define _SC92F8003_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG1 = 0xAA; //ADCüĴ0 +sfr ADCCFG0 = 0xAB; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON0 = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMCON1 = 0xDA; //PWMƼĴ +sfr PWMDTYB = 0xDB; //PWMռձüĴB +sfr PWMDTY3 = 0xDC; //PWM3üĴ +sfr PWMDTY4 = 0xDD; //PWM4üĴ +sfr PWMDTY5 = 0xDE; //PWM5üĴ +sfr PWMDTY6 = 0xDF; //PWM6üĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +sfr OTCON = 0X8F; //ƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //uartƼĴ +sfr SBUF = 0X99; //uart0ݼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSCON2 = 0X95; //SSIƼĴ2 +sfr SSDAT = 0X9F; //SSIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //PWMжȿλ 0:趨 PWMжȨ ͡ 1:趨 PWM жȨ ߡ +sbit IPUART = IP^4; //SIFжȿλ 0:趨 SIFжȨ ͡ 1:趨 SIFжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //32K Base Timerжȿλ 0:趨 32KжȨ ͡ 1:趨 32KжȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //PWMжʹܿ 0:رPWMж 1:PWMж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //32K Base Timerжʹܿ 0:ر32Kж 1:32Kж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //TouchKeyжʹܿ 0:رTouchKeyж 1:TouchKeyж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/* P0 */ +sbit P01 = P0^1; +sbit P00 = P0^0; + +/* P1 */ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/* P2 */ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F827X_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F827X_C.H new file mode 100644 index 0000000..8f6faa5 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F827X_C.H @@ -0,0 +1,195 @@ + /*-------------------------------------------------------------------------- +SC92F827x_C.H + +C Header file for SC92F827x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.04.25 +--------------------------------------------------------------------------*/ +#ifndef _SC92F827x_H_ +#define _SC92F827x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTY3 = 0xD4; //PWM3ռձüĴ +sfr PWMDTY0 = 0xD5; //PWM0ռձüĴ +sfr PWMDTY1 = 0xD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0xD7; //PWM2ռձüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*TKCON*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/******************* P0 ****************** +*SC92F8272װδĹܽţ +*SC92F8271װδĹܽţP02/P03/P04 +*SC92F8270װδĹܽţP00/P02/P03/P04/P05 +******************************************/ +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8272װδĹܽţ +*SC92F8271װδĹܽţ +*SC92F8270װδĹܽţP11/P14/P15 +******************************************/ +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8272װδĹܽţ +*SC92F8271װδĹܽţP27 +*SC92F8270װδĹܽţP24/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8272õú궨塣 +*****************************************************************************/ +#define SC92F8271_NIO_Init() {P0CON|=0x1C,P2CON|=0x80;} //SC92F8271δIO +#define SC92F8270_NIO_Init() {P0CON|=0x3D,P1CON|=0x32,P2CON|=0xF0;} //SC92F8270δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F836xB_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F836xB_C.H new file mode 100644 index 0000000..b0dcdef --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F836xB_C.H @@ -0,0 +1,251 @@ + /*-------------------------------------------------------------------------- +SC92F836XB_C.H + +C Header file for SC92F836XB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2018.08.24 +--------------------------------------------------------------------------*/ +#ifndef _SC92F836XB_H_ +#define _SC92F836XB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F8363BװδĹܽţ +*SC92F8362BװδĹܽţP06/P07 +*SC92F8361BװδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8363BװδĹܽţ +*SC92F8362BװδĹܽţP16/P17 +*SC92F8361BװδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8363BװδĹܽţ +*SC92F8362BװδĹܽţP22/P23 +*SC92F8361BװδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F8363BװδĹܽţ +*SC92F8362BװδĹܽţP50/P51 +*SC92F8361BװδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8363Bõú궨塣 +*****************************************************************************/ +#define SC92F8362B_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F8362BδIO +#define SC92F8361B_NIO_Init() {P0CON|=0xEC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F8361BδIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F837X_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F837X_C.H new file mode 100644 index 0000000..8da7e43 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F837X_C.H @@ -0,0 +1,199 @@ + /*-------------------------------------------------------------------------- +SC92F837x_C.H + +C Header file for SC92F837x microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.03.06 +--------------------------------------------------------------------------*/ +#ifndef _SC92F837x_H_ +#define _SC92F837x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTY3 = 0xD4; //PWM3ռձüĴ +sfr PWMDTY0 = 0xD5; //PWM0ռձüĴ +sfr PWMDTY1 = 0xD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0xD7; //PWM2ռձüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*TKCON*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/******************* P0 ****************** +*SC92F8378װδĹܽţP02/P03/P04/P05 +*SC92F8372װδĹܽţ +*SC92F8371װδĹܽţP02/P03/P04 +*SC92F8370װδĹܽţP00/P02/P03/P04/P05 +******************************************/ +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8378װδĹܽţP11/P15 +*SC92F8372װδĹܽţ +*SC92F8371װδĹܽţ +*SC92F8370װδĹܽţP11/P14/P15 +******************************************/ +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8378װδĹܽţP24/P25/P26/P27 +*SC92F8372װδĹܽţ +*SC92F8371װδĹܽţP27 +*SC92F8370װδĹܽţP24/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8372õú궨塣 +*****************************************************************************/ +#define SC92F8378_NIO_Init() {P0CON|=0x3C,P1CON|=0x22,P2CON|=0xF0;} //SC92F8378δIO +#define SC92F8371_NIO_Init() {P0CON|=0x1C,P2CON|=0x80;} //SC92F8371δIO +#define SC92F8370_NIO_Init() {P0CON|=0x3D,P1CON|=0x32,P2CON|=0xF0;} //SC92F8370δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F844xB_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F844xB_C.H new file mode 100644 index 0000000..0358107 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F844xB_C.H @@ -0,0 +1,294 @@ +/*-------------------------------------------------------------------------- +SC92F844xB_C.H + +C Header file for SC92F844xB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.09.04 +--------------------------------------------------------------------------*/ +#ifndef _SC92F844xB_H_ +#define _SC92F844xB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMƼĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţ +*SC92F8445BװδĹܽţP00 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţ +*SC92F8445BװδĹܽţ +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţ +*SC92F8445BװδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţ +*SC92F8445BװδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţP46/P47 +*SC92F8445BװδĹܽţP40 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F8447BװδĹܽţ +*SC92F8446BװδĹܽţP54/P55 +*SC92F8445BװδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8447Bõú궨塣 +*****************************************************************************/ +#define SC92F8446B_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F8546BδIO +#define SC92F8445B_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F8545BδIO +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F846xB_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F846xB_C.H new file mode 100644 index 0000000..6b09632 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F846xB_C.H @@ -0,0 +1,251 @@ + /*-------------------------------------------------------------------------- +SC92F846XB_C.H + +C Header file for SC92F846XB microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2018.08.24 +--------------------------------------------------------------------------*/ +#ifndef _SC92F846XB_H_ +#define _SC92F846XB_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F8463BװδĹܽţ +*SC92F8462BװδĹܽţP06/P07 +*SC92F8461BװδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8463BװδĹܽţ +*SC92F8462BװδĹܽţP16/P17 +*SC92F8461BװδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8463BװδĹܽţ +*SC92F8462BװδĹܽţP22/P23 +*SC92F8461BװδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F8463BװδĹܽţ +*SC92F8462BװδĹܽţP50/P51 +*SC92F8461BװδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8463Bõú궨塣 +*****************************************************************************/ +#define SC92F8462B_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F8462BδIO +#define SC92F8461B_NIO_Init() {P0CON|=0xEC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F8461BδIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F848x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F848x_C.H new file mode 100644 index 0000000..df073b7 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F848x_C.H @@ -0,0 +1,254 @@ +/*-------------------------------------------------------------------------- +SC92F848x_C.H + +C Header file for SC92F848x microcontroller. +Copyright (c) 2021 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.2 +: 2021.07.14 +--------------------------------------------------------------------------*/ +#ifndef _SC92F848x_H_ +#define _SC92F848x_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr ACC = 0XE0; //ۼ +sfr B = 0XF0; //BĴ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr DPH = 0X83; //DPTRָλ +sfr DPL = 0X82; //DPTRָλ +sfr SP = 0X81; //ջָ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0XB8; //жȨƼĴ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr IOHCON = 0X97; //IOHüĴ +sfr P5PH = 0XDA; //P5ƼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P0VO = 0X9C; //P0LCDѹĴ +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0 = 0X80; //P0ݼĴ + +/*TIMER*/ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr TH1 = 0X8D; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TL0 = 0X8A; //ʱ08λ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TCON = 0X88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ + +/*PWM*/ +sfr PWMCFG = 0XD1; //PWMüĴ +sfr PWMCON = 0XD2; //PWMƼĴ +sfr PWMPRD = 0XD3; //PWMüĴ +sfr PWMDTYA = 0XD4; //PWMռձüĴA +sfr PWMDTY0 = 0XD5; //PWM0üĴ +sfr PWMDTY1 = 0XD6; //PWM1ռձüĴ +sfr PWMDTY2 = 0XD7; //PWM2ռձüĴ +sfr PWMDTYB = 0XDC; //PWMռձüĴB +sfr PWMDTY3 = 0XDD; //PWM3ռձüĴ/PWMʱüĴ +sfr PWMDTY4 = 0XDE; //PWM4ռձüĴ +sfr PWMDTY5 = 0XDF; //PWM5ռձüĴ + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0XF6; //IAPƼĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPADE = 0XF4; //IAPչַĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPKEY = 0XF1; //IAPĴ + +/*uart0*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ +sfr OTCON = 0X8F; //ƼĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //USCIƼĴ0 +sfr SSCON1 = 0X9E; //USCIƼĴ1 +sfr SSCON2 = 0X95; //USCIƼĴ2 +sfr SSDAT = 0X9F; //USCIݼĴ3 + +/*OPTION*/ +sfr OPINX = 0XFE; //Customer Optionָ +sfr OPREG = 0XFF; //Customer OptionĴ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ +sfr OPERCON = 0XEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; //ʱ2־λ +sbit EXF2 = T2CON^6; //T2EXⲿ¼(½)⵽ı־λ +sbit RCLK = T2CON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLK = T2CON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXEN2 = T2CON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TR2 = T2CON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit T2 = T2CON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = T2CON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + +/******************* P0 ****************** +*SC92F8483װδĹܽţ +*SC92F8482װδĹܽţP06/P07 +*SC92F8481װδĹܽţP02/P03/P04/P05/P06/P07 +*SC92F8480װδĹܽţP0 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8483װδĹܽţ +*SC92F8482װδĹܽţP16/P17 +*SC92F8481װδĹܽţP16/P17 +*SC92F8480װδĹܽţP14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8483װδĹܽţ +*SC92F8482װδĹܽţP22/P23 +*SC92F8481װδĹܽţP22/P23/P27 +*SC92F8480װδĹܽţP22/P23/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F8483װδĹܽţ +*SC92F8482װδĹܽţP50/P51 +*SC92F8481װδĹܽţP50/P51 +*SC92F8480װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8483õú궨塣 +*****************************************************************************/ +#define SC92F8482_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;}//SC92F8482δIO +#define SC92F8481_NIO_Init() {P0CON|=0xFC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;}//SC92F8481δIO +#define SC92F8480_NIO_Init() {P0CON|=0xFF,P1CON|=0xF0,P2CON|=0xEC,P5CON|=0x03;}//SC92F8480δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F84Ax_2_ASM.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F84Ax_2_ASM.H new file mode 100644 index 0000000..6a83914 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F84Ax_2_ASM.H @@ -0,0 +1,294 @@ +/*-------------------------------------------------------------------------- +SC92F84Ax_ASM.H + +ASM Header file for SC92F84Ax microcontroller. +Copyright (c) 2020 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2020.07.01 + + +--------------------------------------------------------------------------*/ +#ifndef _SC92F84Ax_ASM_H_ +#define _SC92F84Ax_ASM_H_ + +/* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +ACC EQU 0xE0; //ۼ +B EQU 0xF0; //ͨüĴB +PSW EQU 0xD0; //״̬ +DPH EQU 0x83; //ָ8λ +DPL EQU 0x82; //ָ8λ +SP EQU 0x81; //ջָ + +/*system*/ +PCON EQU 0x87; //ԴƼĴ + +/*interrupt*/ +IP EQU 0xB8; //жȨƼĴ +IE EQU 0xA8; //жϿƼĴ +IP1 EQU 0XB9; //жȼƼĴ1 +IE1 EQU 0XA9; //жϿƼĴ1 + +/*PORT*/ +P5PH EQU 0xDA; //P5ģʽƼĴ +P5CON EQU 0xD9; //P5ģʽƼĴ +P5 EQU 0xD8; //P5ݼĴ +P4PH EQU 0xC2; //P4ģʽƼĴ +P4CON EQU 0xC1; //P4ģʽƼĴ +P4 EQU 0xC0; //P4ݼĴ +P3PH EQU 0xB2; //P3ģʽƼĴ +P3CON EQU 0xB1; //P3ģʽƼĴ +P3 EQU 0xB0; //P3ݼĴ +P2PH EQU 0xA2; //P2ģʽƼĴ +P2CON EQU 0xA1; //P2ģʽƼĴ +P2 EQU 0xA0; //P2ݼĴ +P1PH EQU 0x92; //P1ģʽƼĴ +P1CON EQU 0x91; //P1ģʽƼĴ +P1 EQU 0x90; //P1ݼĴ +P0PH EQU 0x9B; //P0ģʽƼĴ +P0CON EQU 0x9A; //P0ģʽƼĴ +P0 EQU 0x80; //P0ݼĴ +IOHCON0 EQU 0x96; //IOH0üĴ +IOHCON1 EQU 0x97; //IOH1üĴ + +/*TIMER*/ +TMCON EQU 0x8E; //ʱƵʿƼĴ +TH1 EQU 0x8D; //ʱ18λ +TH0 EQU 0x8C; //ʱ08λ +TL1 EQU 0x8B; //ʱ18λ +TL0 EQU 0x8A; //ʱ08λ +TMOD EQU 0x89; //ʱģʽĴ +TCON EQU 0x88; //ʱƼĴ +T2CON EQU 0XC8; //ʱ2ƼĴ +T2MOD EQU 0XC9; //ʱ2ģʽĴ +RCAP2L EQU 0XCA; //ʱ2/׽8λ +RCAP2H EQU 0XCB; //ʱ2/׽8λ +TL2 EQU 0XCC; //ʱ28λ +TH2 EQU 0XCD; //ʱ28λ + +/*ADC*/ +ADCCFG0 EQU 0xAB; //ADCüĴ0 +ADCCFG1 EQU 0xAC; //ADCüĴ1 +ADCCFG2 EQU 0xAA; //ADCüĴ2 +ADCCON EQU 0XAD; //ADCƼĴ +ADCVL EQU 0xAE; //ADC Ĵ +ADCVH EQU 0xAF; //ADC Ĵ + +/*PWM*/ +PWMCFG EQU 0xD4; //PWMüĴ +PWMCON EQU 0xD3; //PWMƼĴ + +/*WatchDog*/ +BTMCON EQU 0XCE; //ƵʱƼĴ +WDTCON EQU 0xCF; //WDTƼĴ + +/*LCD*/ +OTCON EQU 0X8F; //LCDѹƼĴ +P0VO EQU 0X9C; //P0 LCD Bais Ĵ +P1VO EQU 0X94; //P1 LCD Bais Ĵ +P2VO EQU 0XA3; //P2 LCD Bais Ĵ +P3VO EQU 0XB3; //P3 LCD Bais Ĵ + +DDRCON EQU 0X93; //ʾüĴ + +/*INT*/ +INT0F EQU 0XBA; //INT0 ½жϿƼĴ +INT0R EQU 0XBB; //INT0 ϽжϿƼĴ +INT1F EQU 0XBC; //INT1 ½жϿƼĴ +INT1R EQU 0XBD; //INT1 ϽжϿƼĴ +INT2F EQU 0XC6; //INT2 ½жϿƼĴ +INT2R EQU 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +IAPCTL EQU 0xF6; //IAPƼĴ +IAPDAT EQU 0xF5; //IAPݼĴ +IAPADE EQU 0xF4; //IAPչַĴ +IAPADH EQU 0xF3; //IAPдַλĴ +IAPADL EQU 0xF2; //IAPдַ8λĴ +IAPKEY EQU 0xF1; //IAPĴ + +/*uart*/ +SCON EQU 0x98; //ڿƼĴ +SBUF EQU 0x99; //ݻĴ + +/*һ*/ +SSCON0 EQU 0X9D; //SSIƼĴ0 +SSCON1 EQU 0X9E; //SSIƼĴ1 +SSCON2 EQU 0X95; //SSIƼĴ2 +SSDAT EQU 0X9F; //SPIݼĴ + +OPINX EQU 0XFE; +OPREG EQU 0XFF; +EXADH EQU 0XF7; + +/*Check Sum*/ +CHKSUML EQU 0XFC; //Check SumĴλ +CHKSUMH EQU 0XFD; //Check SumĴλ + +/*˳*/ +EXA0 EQU 0xE9; //չۼ0 +EXA1 EQU 0xEA; //չۼ1 +EXA2 EQU 0xEB; //չۼ2 +EXA3 EQU 0xEC; //չۼ3 +EXBL EQU 0xED; //չBĴ0 +EXBH EQU 0xEE; //չBĴ1 +OPERCON EQU 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +CY EQU PSW .7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +AC EQU PSW .6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +F0 EQU PSW .5; //û־λ +RS1 EQU PSW .4; //Ĵѡλ +RS0 EQU PSW .3; //Ĵѡλ +OV EQU PSW .2; //־λ +F1 EQU PSW .1; //F1־ +P EQU PSW .0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +TF2 EQU T2CON .7; +EXF2 EQU T2CON .6; +RCLK EQU T2CON .5; +TCLK EQU T2CON .4; +EXEN2 EQU T2CON .3; +TR2 EQU T2CON .2; +T2 EQU T2CON .1; +CP EQU T2CON .0; + +/*IP*/ +IPADC EQU IP .6; //ADCжȿλ 0:趨ADCжȨ ͡ 1:趨ADCжȨ ߡ +IPT2 EQU IP .5; //PWMжȿλ 0:趨PWMжȨ ͡ 1:趨PWM жȨ ߡ +IPUART EQU IP .4; //Uartжȿλ 0:趨UartжȨ ͡ 1:趨UartжȨ ߡ +IPT1 EQU IP .3; //Timer1жȿλ 0:趨Timer1жȨ ͡ 1:趨Timer1жȨ ߡ +IPINT1 EQU IP .2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +IPT0 EQU IP .1; //Timer0жȿλ 0:趨Timer0жȨ ͡ 1:趨Timer0жȨ ߡ +IPINT0 EQU IP .0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +EA EQU IE .7; //жʹܵܿ 0:رеж 1:еж +EADC EQU IE .6; //ADCжʹܿ 0:رADCж 1:ADCж +ET2 EQU IE .5; //PWMжʹܿ 0:رPWMж 1:PWMж +EUART EQU IE .4; //UARTжʹܿ 0:رUARTж 1:UARTж +ET1 EQU IE .3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +EINT1 EQU IE .2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +ET0 EQU IE .1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +EINT0 EQU IE .0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +TF1 EQU TCON .7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +TR1 EQU TCON .6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +TF0 EQU TCON .5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +TR0 EQU TCON .4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +BITIE1 EQU TCON .3; //INT1ж־ +BITIE0 EQU TCON .1; //INT0ж־ + +/*SCON*/ +SM0 EQU SCON .7; +SM1 EQU SCON .6; +SM2 EQU SCON .5; +REN EQU SCON .4; +TB8 EQU SCON .3; +RB8 EQU SCON .2; +TI EQU SCON .1; +RI EQU SCON .0; + +/******************* P0 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţP00 +******************************************/ +P07 EQU P0 .7; +P06 EQU P0 .6; +P05 EQU P0 .5; +P04 EQU P0 .4; +P03 EQU P0 .3; +P02 EQU P0 .2; +P01 EQU P0 .1; +P00 EQU P0 .0; + +/******************* P1 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţ +******************************************/ +P17 EQU P1 .7; +P16 EQU P1 .6; +P15 EQU P1 .5; +P14 EQU P1 .4; +P13 EQU P1 .3; +P12 EQU P1 .2; +P11 EQU P1 .1; +P10 EQU P1 .0; + +/******************* P2 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţ +******************************************/ +P27 EQU P2 .7; +P26 EQU P2 .6; +P25 EQU P2 .5; +P24 EQU P2 .4; +P23 EQU P2 .3; +P22 EQU P2 .2; +P21 EQU P2 .1; +P20 EQU P2 .0; + +/******************* P3 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţP3 +******************************************/ +P37 EQU P3 .7; +P36 EQU P3 .6; +P35 EQU P3 .5; +P34 EQU P3 .4; +P33 EQU P3 .3; +P32 EQU P3 .2; +P31 EQU P3 .1; +P30 EQU P3 .0; + +/******************* P4 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP46/P47 +*SC92F84A5װδĹܽţP40 +******************************************/ +P47 EQU P4 .7; +P46 EQU P4 .6; +P45 EQU P4 .5; +P44 EQU P4 .4; +P43 EQU P4 .3; +P42 EQU P4 .2; +P41 EQU P4 .1; +P40 EQU P4 .0; + +/******************* P5 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP54/P55 +*SC92F84A5װδĹܽţP5 +******************************************/ +P55 EQU P5 .5; +P54 EQU P5 .4; +P53 EQU P5 .3; +P52 EQU P5 .2; +P51 EQU P5 .1; +P50 EQU P5 .0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F84A7õú궨塣 +*****************************************************************************/ +SC92F84A6_NIO_Init MACRO IO //SC92F84A6δܽŵIO + ORL P4CON,#0XC0 + ORL P5CON,#0X30 + ENDM +SC92F84A5_NIO_Init MACRO IO //SC92F84A5δܽŵIO + ORL P0CON,#0X01 + ORL P3CON,#0XFF + ORL P4CON,#0X01 + ORL P5CON,#0X3F + ENDM +#endif diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F84Ax_2_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F84Ax_2_C.H new file mode 100644 index 0000000..ade8ddb --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F84Ax_2_C.H @@ -0,0 +1,296 @@ +/*-------------------------------------------------------------------------- +SC92F84Ax_C.H + +C Header file for SC92F84Ax microcontroller. +Copyright (c) 2020 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2020.07.01 +--------------------------------------------------------------------------*/ +#ifndef _SC92F84Ax_H_ +#define _SC92F84Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMƼĴ + + +// +//*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ +sbit BITIE0 = TCON^1; //INT0ж־ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţP00 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţ +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţ +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţ +*SC92F84A5װδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP46/P47 +*SC92F84A5װδĹܽţP40 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F84A7װδĹܽţ +*SC92F84A6װδĹܽţP54/P55 +*SC92F84A5װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F84A7õú궨塣 +*****************************************************************************/ +#define SC92F84A6_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F84A6δIO +#define SC92F84A5_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0x3F;} //SC92F84A5δIO +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F854x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F854x_C.H new file mode 100644 index 0000000..1ca0703 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F854x_C.H @@ -0,0 +1,320 @@ + /*-------------------------------------------------------------------------- +SC92F854X_C.H + +C Header file for SC92F854X microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.10.09 +--------------------------------------------------------------------------*/ +#ifndef _SC92F854X_H_ +#define _SC92F854X_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD4; //PWMüĴ +sfr PWMCON = 0xD3; //PWMüĴ + + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ +sfr P1VO = 0X94; //P1 LCD Bais Ĵ +sfr P2VO = 0XA3; //P2 LCD Bais Ĵ +sfr P3VO = 0XB3; //P3 LCD Bais Ĵ + +sfr DDRCON = 0X93; //ʾüĴ + + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ + + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*TKCON*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţ +*SC92F8545װδĹܽţP00 +*SC92F8543װδĹܽţP00/P01 +*SC92F8542װδĹܽţP00/P01/P04/P05 +*SC92F8541װδĹܽţP00/P01/P04/P05/P06 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţ +*SC92F8545װδĹܽţ +*SC92F8543װδĹܽţP10/P14/P15/P16/P17 +*SC92F8542װδĹܽţP14/P15/P16/P17 +*SC92F8541װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţ +*SC92F8545װδĹܽţ +*SC92F8543װδĹܽţP26/P27 +*SC92F8542װδĹܽţP26/P27 +*SC92F8541װδĹܽţP24/P25/P26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţ +*SC92F8545װδĹܽţP3 +*SC92F8543װδĹܽţ +*SC92F8542װδĹܽţP3 +*SC92F8541װδĹܽţP30/P31/P32/P33/P34/P35 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţP46/P47 +*SC92F8545װδĹܽţP40 +*SC92F8543װδĹܽţP40/P44/P45/P46/P47 +*SC92F8542װδĹܽţP44/P45/P46/P47 +*SC92F8541װδĹܽţP4 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F8547װδĹܽţ +*SC92F8546װδĹܽţP54/P55 +*SC92F8545װδĹܽţP5 +*SC92F8543װδĹܽţP5 +*SC92F8542װδĹܽţP5 +*SC92F8541װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8547õú궨塣 +*****************************************************************************/ +#define SC92F8546_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F8546δIO +#define SC92F8545_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F8545δIO +#define SC92F8543_NIO_Init() {P0CON|=0x03,P1CON|=0xF1,P2CON|=0xC0,P4CON|=0xF1,P5CON|=0xFF;} //SC92F8543δIO +#define SC92F8542_NIO_Init() {P0CON|=0x33,P1CON|=0xF0,P2CON|=0xC0,P3CON|=0xFF,P4CON|=0xF0,P5CON|=0xFF;} //SC92F8542δIO +#define SC92F8541_NIO_Init() {P0CON|=0x73,P1CON|=0xC1,P2CON|=0xF0,P3CON|=0x3F,P4CON|=0xFF,P5CON|=0xFF;} //SC92F8541δIO +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92F859x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92F859x_C.H new file mode 100644 index 0000000..5ab2301 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92F859x_C.H @@ -0,0 +1,297 @@ +/*-------------------------------------------------------------------------- +SC92F859x_C.H + +C Header file for SC92F859x microcontroller. +Copyright (c) 2021 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.1 +: 2021.10.22 +--------------------------------------------------------------------------*/ +#ifndef _SC92F859x_H_ +#define _SC92F859x_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr SP = 0X81; //ջָ +sfr DPL = 0X82; //DPTRָλ +sfr DPH = 0X83; //DPTRָλ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr ACC = 0XE0; //ۼ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 +sfr B = 0XF0; //BĴ + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 +sfr IP = 0XB8; //жȨƼĴ +sfr IP1 = 0XB9; //жȼƼĴ1 + +/*PORT*/ +sfr P0 = 0X80; //P0ݼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr DDRCON = 0X93; //ʾƼĴ +sfr P1VO = 0X94; //P1ʾĴ +sfr IOHCON0 = 0X96; //IOHüĴ0 +sfr IOHCON1 = 0X97; //IOHüĴ1 +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P0VO = 0X9C; //P0LCDѹĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2VO = 0XA3; //P2ʾĴ +sfr P3 = 0XB0; //P3ݼĴ +sfr P3CON = 0XB1; //P3/ƼĴ +sfr P3PH = 0XB2; //P3ƼĴ +sfr P3VO = 0XB3; //P3ʾĴ +sfr P4 = 0XC0; //P4ݼĴ +sfr P4CON = 0XC1; //P4/ƼĴ +sfr P4PH = 0XC2; //P4ƼĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5PH = 0XDA; //P5ƼĴ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*TIMER*/ +sfr TCON = 0X88; //ʱƼĴ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TL0 = 0X8A; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TH1 = 0X8D; //ʱ18λ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ + +/*PWM*/ +sfr PWMCON = 0XD3; //PWM0ƼĴ0 +sfr PWMCFG = 0XD4; //PWMüĴ + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPKEY = 0XF1; //IAPĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADE = 0XF4; //IAPչַĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPCTL = 0XF6; //IAPƼĴ + +/*uart0*/ +sfr OTCON = 0X8F; //ƼĴ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*һ*/ +sfr SSCON2 = 0X95;//SSIƼĴ2 +sfr SSCON0 = 0X9D; //SSIƼĴ0 +sfr SSCON1 = 0X9E; //SSIƼĴ1 +sfr SSDAT = 0X9F; //SSIݼĴ + +/*OPTION*/ +sfr OPINX = 0XFE; //Customer Optionָ +sfr OPREG = 0XFF; //Customer OptionĴ + +/*CRC*/ +sfr OPERCON = 0XEF; //ƼĴ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; //ʱ2־λ +sbit EXF2 = T2CON^6; //T2EXⲿ¼(½)⵽ı־λ +sbit RCLK = T2CON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLK = T2CON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXEN2 = T2CON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TR2 = T2CON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit T2 = T2CON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = T2CON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + + +/******************* P0 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţP00 +*SC92F8593װδĹܽţP00/P01 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţ +*SC92F8593װδĹܽţP10/P14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţ +*SC92F8593װδĹܽţP26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţ +*SC92F8595װδĹܽţP3 +*SC92F8593װδĹܽţ +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţP46/P47 +*SC92F8595װδĹܽţP40 +*SC92F8593װδĹܽţP40/P44/P45/P46/P47 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92F8597װδĹܽţ +*SC92F8596װδĹܽţP54/P55 +*SC92F8595װδĹܽţP5 +*SC92F8593װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F8597õú궨塣 +*****************************************************************************/ +#define SC92F8596_NIO_Init() {P4CON|=0xC0,P5CON|=0x30;} //SC92F8596δIO +#define SC92F8595_NIO_Init() {P0CON|=0x01,P3CON|=0xFF,P4CON|=0x01,P5CON|=0xFF;} //SC92F8595δIO +#define SC92F8593_NIO_Init() {P0CON|=0x03,P1CON|=0xF1,P2CON|=0xC0,P4CON|=0xF1,P5CON|=0xFF;}//SC92F8593δIO + + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92FWxx_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92FWxx_C.H new file mode 100644 index 0000000..815b979 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92FWxx_C.H @@ -0,0 +1,286 @@ + /*-------------------------------------------------------------------------- +SC92FWxx_C.H + +C Header file for SC92FWxx microcontroller. +Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2018.10.09 +--------------------------------------------------------------------------*/ +#ifndef _SC92FWxx_H_ +#define _SC92FWxx_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P4PH = 0xC2; //P4ģʽƼĴ +sfr P4CON = 0xC1; //P4ģʽƼĴ +sfr P4 = 0xC0; //P4ݼĴ +sfr P3PH = 0xB2; //P3ģʽƼĴ +sfr P3CON = 0xB1; //P3ģʽƼĴ +sfr P3 = 0xB0; //P3ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON0 = 0x96; //IOH0üĴ +sfr IOHCON1 = 0x97; //IOH1üĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG0 = 0xD2; //PWM0üĴ +sfr PWMCON0 = 0xD1; //PWM0ƼĴ +sfr PWMCFG1 = 0xD4; //PWM1üĴ +sfr PWMCON1 = 0xD3; //PWM1üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +sfr OTCON = 0X8F; //ƼĴ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*ģȽ*/ +sfr CMPCFG = 0XB6; //ģȽüĴ +sfr CMPCON = 0XB7; //ģȽƼĴ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +///* ------------------- λĴ-------------------- */ +/*B*/ +/*ACC*/ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit CLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP04/P05/P06/P07 +*SC92FW16װδĹܽţP00/P01/P04/P05 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP10/P12/P14/P15/P16/P17 +*SC92FW16װδĹܽţP14/P15/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP26/P27 +*SC92FW16װδĹܽţP26/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P3 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP34/P35/P36/P37 +*SC92FW16װδĹܽţP3 +******************************************/ +sbit P37 = P3^7; +sbit P36 = P3^6; +sbit P35 = P3^5; +sbit P34 = P3^4; +sbit P33 = P3^3; +sbit P32 = P3^2; +sbit P31 = P3^1; +sbit P30 = P3^0; + +/******************* P4 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP46/P47 +*SC92FW16װδĹܽţP44/P45/P46/P47 +******************************************/ +sbit P47 = P4^7; +sbit P46 = P4^6; +sbit P45 = P4^5; +sbit P44 = P4^4; +sbit P43 = P4^3; +sbit P42 = P4^2; +sbit P41 = P4^1; +sbit P40 = P4^0; + +/******************* P5 ****************** +*SC92FW40װδĹܽţ +*SC92FW24װδĹܽţP54/P55 +*SC92FW16װδĹܽţP5 +******************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92FW40õú궨塣 +*****************************************************************************/ +#define SC92FW24_NIO_Init() {P0CON|=0xF0,P1CON|=0xF5,P2CON|=0xC0,P3CON|=0xF0,P4CON|=0xC0,P5CON|=0xF0;} //SC92FW24δIO +#define SC92FW16_NIO_Init() {P0CON|=0x33,P1CON|=0xF0,P2CON|=0xC0,P3CON|=0xFF,P4CON|=0xF0,P5CON|=0xFF;} //SC92FW16δIO +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92L753x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92L753x_C.H new file mode 100644 index 0000000..15aba03 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92L753x_C.H @@ -0,0 +1,277 @@ +/*-------------------------------------------------------------------------- +SC92L753x_C.H + +C Header file for SC92L853x microcontroller. +Copyright (c) 2022 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V0.1 +: 2022.01.18 +--------------------------------------------------------------------------*/ +#ifndef _SC92L753x_C_H_ +#define _SC92L753x_C_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr SP = 0X81; //ջָ +sfr DPL = 0X82; //DPTRָλ +sfr DPH = 0X83; //DPTRָλ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr ACC = 0XE0; //ۼ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 +sfr B = 0XF0; //BĴ + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 +sfr IE2 = 0XAA; //жʹܼĴ2 +sfr IP = 0XB8; //жȨƼĴ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP2 = 0XBA; //жȼƼĴ2 + +/*PORT*/ +sfr P0 = 0X80; //P0ݼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr P1VO = 0X93; //P1ʾĴ +sfr P0VO = 0X94; //P0LCDѹĴ +sfr DDRCON = 0X95; //ʾƼĴ +sfr IOHCON0 = 0X96; //IOHüĴ0 +sfr IOHCON1 = 0X97; //IOHüĴ1 +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2VO = 0XA3; //P2ʾĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5PH = 0XDA; //P5ƼĴ +sfr P5VO = 0XDB; //P5ʾĴ + + +/*TIMER*/ +sfr TCON = 0X88; //ʱƼĴ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TL0 = 0X8A; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TH1 = 0X8D; //ʱ18λ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr TXCON = 0XC8; //ʱ2/3/4ƼĴ +sfr TXMOD = 0XC9; //ʱ2/3/4ģʽĴ +sfr RCAPXL = 0XCA; //ʱ2/3/4/׽8λ +sfr RCAPXH = 0XCB; //ʱ2/3/4/׽8λ +sfr TLX = 0XCC; //ʱ2/3/48λ +sfr THX = 0XCD; //ʱ2/3/48λ +sfr TXINX = 0XCE; //ʱƼĴָ + +/*ADC*/ +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ +sfr ADCCFG2 = 0XB5; //ADCüĴ2 + +/*PWM*/ +sfr PWMCFG = 0XD1; //PWMüĴ +sfr PWMCON0 = 0XD2; //PWMƼĴ0 +sfr PWMCON1 = 0XD3; //PWMƼĴ1 +sfr PWMPDL = 0XD4; //PWMڼĴ8λ +sfr PWMPDH = 0XD5; //PWMڼĴ8λ +sfr PWMDFR = 0XD6; //PWMüĴ +sfr PWMFLT = 0XD7; //PWMϼüĴ + +/*LPD*/ +sfr LPDCFG = 0XB7; //LPD + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XFB; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XB4; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XBE; //INT2 ½жϿƼĴ +sfr INT2R = 0XBF; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPKEY = 0XF1; //IAPĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADE = 0XF4; //IAPдչַĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPCTL = 0XF6; //IAPƼĴ + +/*uart0*/ +sfr OTCON = 0X8F; //ƼĴ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*һ*/ +sfr US0CON0 = 0X9C; //USCI0ƼĴ0 +sfr US0CON1 = 0X9D; //USCI0ƼĴ1 +sfr US0CON2 = 0X9E; //USCI0ƼĴ2 +sfr US0CON3 = 0X9F; //USCI0ƼĴ3 +sfr US1CON0 = 0XA4; //USCI1ƼĴ0 +sfr US1CON1 = 0XA5; //USCI1ƼĴ1 +sfr US1CON2 = 0XA6; //USCI1ƼĴ2 +sfr US1CON3 = 0XA7; //USCI1ƼĴ3 +sfr US2CON0 = 0XC4; //USCI2ƼĴ0 +sfr US2CON1 = 0XC5; //USCI2ƼĴ1 +sfr US2CON2 = 0XC6; //USCI2ƼĴ2 +sfr US2CON3 = 0XC7; //USCI2ƼĴ3 + +/*OPTION*/ +sfr OPINX = 0XFE; //Optionָ +sfr OPREG = 0XFF; //OptionĴ + +/*CRC*/ +sfr OPERCON = 0XEF; //ƼĴ +sfr CRCINX = 0XFC; //CRCָ +sfr CRCREG = 0XFD; //CRCĴ + + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*TXCON*/ +sbit TFX = TXCON^7; //ʱ2/3/4־λ +sbit EXFX = TXCON^6; //TnEXn=2/3/4ⲿ¼(½)⵽ı־λ +sbit RCLKX = TXCON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLKX = TXCON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXENX = TXCON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TRX = TXCON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit TX = TXCON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = TXCON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + + +/******************* P0 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţP06/P07 +*SC92L8531װδĹܽţP02/P03/P04/P06/P07 +***********************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţ +*SC92L8531װδĹܽţ +***********************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţ +*SC92L8531װδĹܽţP22/P23/P27 +***********************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + + +/******************* P5 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţP52/P53/P54/P55 +*SC92L8532װδĹܽţP5 +*SC92L8531װδĹܽţP5 +***********************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92L7535õú궨塣 +*****************************************************************************/ +#define SC92L7533_NIO_Init() {P5CON|=0x3C;} //SC92L8533δIO +#define SC92L7532_NIO_Init() {P0CON|=0xC0,P5CON|=0x3F;} //SC92L8532δIO +#define SC92L7531_NIO_Init() {P0CON|=0xDC,P2CON|=0X8C,P5CON|=0x3F;} //SC92L8531δIO +#endif diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92L853x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92L853x_C.H new file mode 100644 index 0000000..857cfa5 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92L853x_C.H @@ -0,0 +1,277 @@ +/*-------------------------------------------------------------------------- +SC92L853x_C.H + +C Header file for SC92L853x microcontroller. +Copyright (c) 2022 Shenzhen SinOne Microelectronics Co., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V0.1 +: 2022.01.18 +--------------------------------------------------------------------------*/ +#ifndef _SC92L853x_C_H_ +#define _SC92L853x_C_H_ + +///* ------------------- ֽڼĴ-------------------- */ +/*CPU*/ +sfr SP = 0X81; //ջָ +sfr DPL = 0X82; //DPTRָλ +sfr DPH = 0X83; //DPTRָλ +sfr PSW = 0XD0; //״ּ̬Ĵ +sfr ACC = 0XE0; //ۼ +sfr EXA0 = 0XE9; //չۼ0 +sfr EXA1 = 0XEA; //չۼ1 +sfr EXA2 = 0XEB; //չۼ2 +sfr EXA3 = 0XEC; //չۼ3 +sfr EXBL = 0XED; //չBĴ0 +sfr EXBH = 0XEE; //չBĴ1 +sfr B = 0XF0; //BĴ + +/*SRAM*/ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*system*/ +sfr PCON = 0X87; //ԴƼĴ + +/*Interrupt*/ +sfr IE = 0XA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 +sfr IE2 = 0XAA; //жʹܼĴ2 +sfr IP = 0XB8; //жȨƼĴ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP2 = 0XBA; //жȼƼĴ2 + +/*PORT*/ +sfr P0 = 0X80; //P0ݼĴ +sfr P1 = 0X90; //P1ݼĴ +sfr P1CON = 0X91; //P1/ƼĴ +sfr P1PH = 0X92; //P1ƼĴ +sfr P1VO = 0X93; //P1ʾĴ +sfr P0VO = 0X94; //P0LCDѹĴ +sfr DDRCON = 0X95; //ʾƼĴ +sfr IOHCON0 = 0X96; //IOHüĴ0 +sfr IOHCON1 = 0X97; //IOHüĴ1 +sfr P0CON = 0X9A; //P0/ƼĴ +sfr P0PH = 0X9B; //P0ƼĴ +sfr P2 = 0XA0; //P2ݼĴ +sfr P2CON = 0XA1; //P2/ƼĴ +sfr P2PH = 0XA2; //P2ƼĴ +sfr P2VO = 0XA3; //P2ʾĴ +sfr P5 = 0XD8; //P5ݼĴ +sfr P5CON = 0XD9; //P5/ƼĴ +sfr P5PH = 0XDA; //P5ƼĴ +sfr P5VO = 0XDB; //P5ʾĴ + + +/*TIMER*/ +sfr TCON = 0X88; //ʱƼĴ +sfr TMOD = 0X89; //ʱģʽĴ +sfr TL0 = 0X8A; //ʱ08λ +sfr TL1 = 0X8B; //ʱ18λ +sfr TH0 = 0X8C; //ʱ08λ +sfr TH1 = 0X8D; //ʱ18λ +sfr TMCON = 0X8E; //ʱƵʿƼĴ +sfr TXCON = 0XC8; //ʱ2/3/4ƼĴ +sfr TXMOD = 0XC9; //ʱ2/3/4ģʽĴ +sfr RCAPXL = 0XCA; //ʱ2/3/4/׽8λ +sfr RCAPXH = 0XCB; //ʱ2/3/4/׽8λ +sfr TLX = 0XCC; //ʱ2/3/48λ +sfr THX = 0XCD; //ʱ2/3/48λ +sfr TXINX = 0XCE; //ʱƼĴָ + +/*ADC*/ +sfr ADCCFG0 = 0XAB; //ADCüĴ0 +sfr ADCCFG1 = 0XAC; //ADCüĴ1 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0XAE; //ADCĴ +sfr ADCVH = 0XAF; //ADCĴ +sfr ADCCFG2 = 0XB5; //ADCüĴ2 + +/*PWM*/ +sfr PWMCFG = 0XD1; //PWMüĴ +sfr PWMCON0 = 0XD2; //PWMƼĴ0 +sfr PWMCON1 = 0XD3; //PWMƼĴ1 +sfr PWMPDL = 0XD4; //PWMڼĴ8λ +sfr PWMPDH = 0XD5; //PWMڼĴ8λ +sfr PWMDFR = 0XD6; //PWMüĴ +sfr PWMFLT = 0XD7; //PWMϼüĴ + +/*LPD*/ +sfr LPDCFG = 0XB7; //LPD + +/*WatchDog*/ +sfr WDTCON = 0XCF; //WDTƼĴ + +/*BTM*/ +sfr BTMCON = 0XFB; //ƵʱƼĴ + +/*INT*/ +sfr INT0F = 0XB4; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XBE; //INT2 ½жϿƼĴ +sfr INT2R = 0XBF; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPKEY = 0XF1; //IAPĴ +sfr IAPADL = 0XF2; //IAPдַλĴ +sfr IAPADH = 0XF3; //IAPдַλĴ +sfr IAPADE = 0XF4; //IAPдչַĴ +sfr IAPDAT = 0XF5; //IAPݼĴ +sfr IAPCTL = 0XF6; //IAPƼĴ + +/*uart0*/ +sfr OTCON = 0X8F; //ƼĴ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*һ*/ +sfr US0CON0 = 0X9C; //USCI0ƼĴ0 +sfr US0CON1 = 0X9D; //USCI0ƼĴ1 +sfr US0CON2 = 0X9E; //USCI0ƼĴ2 +sfr US0CON3 = 0X9F; //USCI0ƼĴ3 +sfr US1CON0 = 0XA4; //USCI1ƼĴ0 +sfr US1CON1 = 0XA5; //USCI1ƼĴ1 +sfr US1CON2 = 0XA6; //USCI1ƼĴ2 +sfr US1CON3 = 0XA7; //USCI1ƼĴ3 +sfr US2CON0 = 0XC4; //USCI2ƼĴ0 +sfr US2CON1 = 0XC5; //USCI2ƼĴ1 +sfr US2CON2 = 0XC6; //USCI2ƼĴ2 +sfr US2CON3 = 0XC7; //USCI2ƼĴ3 + +/*OPTION*/ +sfr OPINX = 0XFE; //Optionָ +sfr OPREG = 0XFF; //OptionĴ + +/*CRC*/ +sfr OPERCON = 0XEF; //ƼĴ +sfr CRCINX = 0XFC; //CRCָ +sfr CRCREG = 0XFD; //CRCĴ + + +///* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*TXCON*/ +sbit TFX = TXCON^7; //ʱ2/3/4־λ +sbit EXFX = TXCON^6; //TnEXn=2/3/4ⲿ¼(½)⵽ı־λ +sbit RCLKX = TXCON^5; //UART0ʱӿλ 0: ʱ1ղ 1: ʱ2ղ +sbit TCLKX = TXCON^4; //UART0ʱӿλ 0: ʱ1Ͳ 1: ʱ2Ͳ +sbit EXENX = TXCON^3; //T2EXϵⲿ¼(½)/񴥷/ֹ +sbit TRX = TXCON^2; //ʱ2ʼ/ֹͣλ 0: ֹͣʱ2 1: ʼʱ2 +sbit TX = TXCON^1; //ʱ2ʱ/ʽѡλ2 +sbit CP = TXCON^0; ///طʽѡλ + +/*IP*/ +sbit IPADC = IP^6; //ADCжȨѡ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȨѡ 0:趨 Timer 2жȨ ͡ 1:趨 Timer 2жȨ ߡ +sbit IPUART = IP^4; //UARTжȨѡ 0:趨 UARTжȨ ͡ 1:趨 UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȨѡ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȨѡ 0:趨 INT1жȨ ͡ 1:趨 INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȨѡ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȨѡ 0:趨 INT0жȨΪ ͡ 1: INT0жȨΪ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTIMER2ж 1:TIMER2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رSIFж 1:SIFж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //ⲿж1жʹܿ 0:رⲿж1ж 1:ⲿж1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //ⲿж0жʹܿ 0:رⲿж0ж 1:ⲿж0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + + +/*SCON*/ +sbit SM0 = SCON^7; //ͨģʽλ:SM1ʹ 00: ģʽ08λ˫ͬͨģʽ 01: ģʽ110λȫ˫첽ͨ 11: ģʽ311λȫ˫첽ͨ +sbit SM1 = SCON^6; //ͨģʽλ +sbit SM2 = SCON^5; //ͨģʽλ2˿λֻģʽ3Ч 0ÿյһ֡λRIж 1յһ֡ʱֻеRB8=1ʱŻλRIж +sbit REN = SCON^4; //λ 0: 1 +sbit TB8 = SCON^3; //ֻģʽ3ЧΪݵĵ9λ +sbit RB8 = SCON^2; //ֻģʽ3ЧΪݵĵ9λ +sbit TI = SCON^1; //жϱ־λ +sbit RI = SCON^0; //жϱ־λ + + +/******************* P0 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţP06/P07 +*SC92L8531װδĹܽţP02/P03/P04/P06/P07 +***********************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţ +*SC92L8531װδĹܽţ +***********************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţ +*SC92L8532װδĹܽţ +*SC92L8531װδĹܽţP22/P23/P27 +***********************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + + +/******************* P5 *********************** +*SC92L8535װδĹܽţ +*SC92L8533װδĹܽţP52/P53/P54/P55 +*SC92L8532װδĹܽţP5 +*SC92L8531װδĹܽţP5 +***********************************************/ +sbit P55 = P5^5; +sbit P54 = P5^4; +sbit P53 = P5^3; +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92L8535õú궨塣 +*****************************************************************************/ +#define SC92L8533_NIO_Init() {P5CON|=0x3C;} //SC92L8533δIO +#define SC92L8532_NIO_Init() {P0CON|=0xC0,P5CON|=0x3F;} //SC92L8532δIO +#define SC92L8531_NIO_Init() {P0CON|=0xDC,P2CON|=0X8C,P5CON|=0x3F;} //SC92L8531δIO +#endif diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92f73Ax_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92f73Ax_C.H new file mode 100644 index 0000000..724dc4a --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92f73Ax_C.H @@ -0,0 +1,252 @@ + /*-------------------------------------------------------------------------- +SC92F73Ax_C.H + +C Header file for SC92F73Ax microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.17 +--------------------------------------------------------------------------*/ +#ifndef _SC92F73Ax_H_ +#define _SC92F73Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //ƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; //Option ָ +sfr OPREG = 0XFF; //OptionĴ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ 0:CPUӦӲ 1:жϲ +sbit BITIE0 = TCON^1; //INT0ж־ 0:CPUӦӲ 1:жϲ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F73A3װδĹܽţ +*SC92F73A2װδĹܽţP06/P07 +*SC92F73A1װδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F73A3װδĹܽţ +*SC92F73A2װδĹܽţP16/P17 +*SC92F73A1װδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F73A3װδĹܽţ +*SC92F73A2װδĹܽţP22/P23 +*SC92F73A1װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F73A3װδĹܽţ +*SC92F73A2װδĹܽţP50/P51 +*SC92F73A1װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F73A3õú궨塣 +*****************************************************************************/ +#define SC92F73A2_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F73A2δIO +#define SC92F73A1_NIO_Init() {P0CON|=0xDC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F73A1δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92f74Ax_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92f74Ax_C.H new file mode 100644 index 0000000..03a091e --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92f74Ax_C.H @@ -0,0 +1,253 @@ + /*-------------------------------------------------------------------------- +SC92F74Ax_C.H + +C Header file for SC92F74Ax microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.17 +--------------------------------------------------------------------------*/ +#ifndef _SC92F74Ax_H_ +#define _SC92F74Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //ƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; //Option ָ +sfr OPREG = 0XFF; //OptionĴ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ 0:CPUӦӲ 1:жϲ +sbit BITIE0 = TCON^1; //INT0ж־ 0:CPUӦӲ 1:жϲ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F74A3װδĹܽţ +*SC92F74A2װδĹܽţP06/P07 +*SC92F74A1װδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F74A3װδĹܽţ +*SC92F74A2װδĹܽţP16/P17 +*SC92F74A1װδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F74A3װδĹܽţ +*SC92F74A2װδĹܽţP22/P23 +*SC92F74A1װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F74A3װδĹܽţ +*SC92F74A2װδĹܽţP50/P51 +*SC92F74A1װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F74A3õú궨塣 +*****************************************************************************/ +#define SC92F74A2_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F74A2δIO +#define SC92F74A1_NIO_Init() {P0CON|=0xDC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F74A1δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92f83Ax_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92f83Ax_C.H new file mode 100644 index 0000000..04c9bc5 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92f83Ax_C.H @@ -0,0 +1,253 @@ + /*-------------------------------------------------------------------------- +SC92F83Ax_C.H + +C Header file for SC92F83Ax microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.17 +--------------------------------------------------------------------------*/ +#ifndef _SC92F83Ax_H_ +#define _SC92F83Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //ƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; //Option ָ +sfr OPREG = 0XFF; //OptionĴ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ 0:CPUӦӲ 1:жϲ +sbit BITIE0 = TCON^1; //INT0ж־ 0:CPUӦӲ 1:жϲ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F83A3װδĹܽţ +*SC92F83A2װδĹܽţP06/P07 +*SC92F83A1װδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F83A3װδĹܽţ +*SC92F83A2װδĹܽţP16/P17 +*SC92F83A1װδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F83A3װδĹܽţ +*SC92F83A2װδĹܽţP22/P23 +*SC92F83A1װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F83A3װδĹܽţ +*SC92F83A2װδĹܽţP50/P51 +*SC92F83A1װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F83A3õú궨塣 +*****************************************************************************/ +#define SC92F83A2_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F83A2δIO +#define SC92F83A1_NIO_Init() {P0CON|=0xDC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F83A1δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC92f84Ax_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC92f84Ax_C.H new file mode 100644 index 0000000..06d7a8e --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC92f84Ax_C.H @@ -0,0 +1,253 @@ + /*-------------------------------------------------------------------------- +SC92F84Ax_C.H + +C Header file for SC92F84Ax microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V1.0 +: 2019.06.17 +--------------------------------------------------------------------------*/ +#ifndef _SC92F84Ax_H_ +#define _SC92F84Ax_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ + + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ +sfr P5CON = 0xD9; //P5ģʽƼĴ +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ +sfr P2CON = 0xA1; //P2ģʽƼĴ +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ +sfr P1CON = 0x91; //P1ģʽƼĴ +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ +sfr P0CON = 0x9A; //P0ģʽƼĴ +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0xC8; //ʱ2ƼĴ +sfr T2MOD = 0xC9; //ʱ2ģʽĴ +sfr RCAP2L = 0xCA; //ʱ2/׽8λ +sfr RCAP2H = 0xCB; //ʱ2/׽8λ +sfr TL2 = 0xCC; //ʱ28λ +sfr TH2 = 0xCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //ADCüĴ0 +sfr ADCCFG1 = 0xAC; //ADCüĴ1 +sfr ADCCFG2 = 0XAA; //ADCüĴ2 +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMռձüĴA +sfr PWMDTY0 = 0xD5; //PWM0üĴ +sfr PWMDTY1 = 0xD6; //PWM1üĴ +sfr PWMDTY2 = 0xD7; //PWM2üĴ +sfr PWMDTYB = 0xDC; //PWMռձüĴB +sfr PWMDTY3 = 0xDD; //PWM3üĴ +sfr PWMDTY4 = 0xDE; //PWM4üĴ +sfr PWMDTY5 = 0xDF; //PWM5üĴ + +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + +/*LCD*/ +sfr OTCON = 0X8F; //ƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*uart*/ +sfr SCON = 0x98; //ڿƼĴ +sfr SBUF = 0x99; //ݻĴ + +/*һ*/ +sfr SSCON0 = 0X9D; //SPIƼĴ0 +sfr SSCON1 = 0X9E; //SPIƼĴ1 +sfr SSCON2 = 0X95; //SPIƼĴ2 +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr OPINX = 0XFE; //Option ָ +sfr OPREG = 0XFF; //OptionĴ +sfr EXADH = 0XF7; //ⲿSRAMַλ + +/*Check Sum*/ +sfr CHKSUML = 0XFC; //Check SumĴλ +sfr CHKSUMH = 0XFD; //Check SumĴλ + +/*˳*/ +sfr EXA0 = 0xE9; //չۼ0 +sfr EXA1 = 0xEA; //չۼ1 +sfr EXA2 = 0xEB; //չۼ2 +sfr EXA3 = 0xEC; //չۼ3 +sfr EXBL = 0xED; //չBĴ0 +sfr EXBH = 0xEE; //չBĴ1 +sfr OPERCON = 0xEF; //ƼĴ + +/* ------------------- λĴ-------------------- */ +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit F1 = PSW^1; //F1־ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ +sbit BITIE1 = TCON^3; //INT1ж־ 0:CPUӦӲ 1:жϲ +sbit BITIE0 = TCON^1; //INT0ж־ 0:CPUӦӲ 1:жϲ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC92F84A3װδĹܽţ +*SC92F84A2װδĹܽţP06/P07 +*SC92F84A1װδĹܽţP02/P03/P04/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC92F84A3װδĹܽţ +*SC92F84A2װδĹܽţP16/P17 +*SC92F84A1װδĹܽţP16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; +sbit P10 = P1^0; + +/******************* P2 ****************** +*SC92F84A3װδĹܽţ +*SC92F84A2װδĹܽţP22/P23 +*SC92F84A1װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC92F84A3װδĹܽţ +*SC92F84A2װδĹܽţP50/P51 +*SC92F84A1װδĹܽţP50/P51 +******************************************/ +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +*ѡSC92F84A3õú궨塣 +*****************************************************************************/ +#define SC92F84A2_NIO_Init() {P0CON|=0xC0,P1CON|=0xC0,P2CON|=0x0C,P5CON|=0x03;} //SC92F84A2δIO +#define SC92F84A1_NIO_Init() {P0CON|=0xDC,P1CON|=0xC0,P2CON|=0x8C,P5CON|=0x03;} //SC92F84A1δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC93F743x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC93F743x_C.H new file mode 100644 index 0000000..5726c5b --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC93F743x_C.H @@ -0,0 +1,242 @@ + /*-------------------------------------------------------------------------- +SC93F743x_C.H + +C Header file for SC93F743x microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2019.06.24 +--------------------------------------------------------------------------*/ +#ifndef _SC93F743x_H_ +#define _SC93F743x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ +sfr DPL1 = 0x84; //DPTR1ָ1λ +sfr DPH1 = 0x85; //DPTR1ָ1λ +sfr DPS = 0x86; //DPTRѡĴ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMߵƽüĴ +sfr PWMDTY0 = 0xD5; //PWMߵƽüĴ +sfr PWMDTY1 = 0XD6; //PWMߵƽüĴ +sfr PWMDTY2 = 0XD7; //PWMߵƽüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ +sfr PGACFG = 0XBE; //PGAüĴ +sfr PGACON = 0XBF; //PGAƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ +sfr SSCON1 = 0X9E; //SPI״̬Ĵ +sfr SSCON2 = 0X95; //SPI״̬Ĵ +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr MXAX = 0XEA; +sfr TA = 0XEB; +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*temperature sensor*/ +sfr TSCFG = 0XAA; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC93F7433װδĹܽţ +*SC93F7432װδĹܽţP06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC93F7433װδĹܽţP10 +*SC93F7432װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; + +/******************* P2 ****************** +*SC93F7433װδĹܽţ +*SC93F7432װδĹܽţP22/P23 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC93F7433װδĹܽţ +*SC93F7432װδĹܽţP50/P51 +******************************************/ +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +* +*****************************************************************************/ +#define SC93F7433_NIO_Init() {P1CON|=0x01;} //SC93F7433δIO +#define SC93F7432_NIO_Init() {P0CON|=0xC0,P1CON|=0xC1,P2CON|=0x0C,P5CON|=0x03;} //SC93F7432δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC93F833x_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC93F833x_C.H new file mode 100644 index 0000000..02a0741 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC93F833x_C.H @@ -0,0 +1,247 @@ + /*-------------------------------------------------------------------------- +SC93F833x_C.H + +C Header file for SC93F833x microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2019.06.24 +--------------------------------------------------------------------------*/ +#ifndef _SC93F833x_H_ +#define _SC93F833x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ +sfr DPL1 = 0x84; //DPTR1ָ1λ +sfr DPH1 = 0x85; //DPTR1ָ1λ +sfr DPS = 0x86; //DPTRѡĴ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMߵƽüĴ +sfr PWMDTY0 = 0xD5; //PWMߵƽüĴ +sfr PWMDTY1 = 0XD6; //PWMߵƽüĴ +sfr PWMDTY2 = 0XD7; //PWMߵƽüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ +sfr PGACFG = 0XBE; //PGAüĴ +sfr PGACON = 0XBF; //PGAƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ +sfr SSCON1 = 0X9E; //SPI״̬Ĵ +sfr SSCON2 = 0X95; //SPI״̬Ĵ +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr MXAX = 0XEA; +sfr TA = 0XEB; +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*temperature sensor*/ +sfr TSCFG = 0XAA; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC93F8333װδĹܽţ +*SC93F8332װδĹܽţP06/P07 +*SC93F8331װδĹܽţP02/P03/P05/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC93F8333װδĹܽţP10 +*SC93F8332װδĹܽţP10/P16/P17 +*SC93F8331װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; + +/******************* P2 ****************** +*SC93F8333װδĹܽţ +*SC93F8332װδĹܽţP22/P23 +*SC93F8331װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC93F8333װδĹܽţ +*SC93F8332װδĹܽţP50/P51 +*SC93F8331װδĹܽţP50/P51 +******************************************/ +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +* +*****************************************************************************/ +#define SC93F8333_NIO_Init() {P1CON|=0x01;} //SC93F8333δIO +#define SC93F8332_NIO_Init() {P0CON|=0xC0,P1CON|=0xC1,P2CON|=0x0C,P5CON|=0x03;} //SC93F8332δIO +#define SC93F8331_NIO_Init() {P0CON|=0xEC,P1CON|=0xC1,P2CON|=0x8C,P5CON|=0x03;} //SC93F8331δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/SC93F843X_C.H b/Keil_C/FWLib/SC92F_Lib/inc/SC93F843X_C.H new file mode 100644 index 0000000..1ac6a17 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/SC93F843X_C.H @@ -0,0 +1,247 @@ + /*-------------------------------------------------------------------------- +SC93F843x_C.H + +C Header file for SC93F843x microcontroller. +Copyright (c) 2019 Shenzhen SinOne Chip Electronic CO., Ltd. +All rights reserved. +Ԫ΢޹˾ +汾: V2.0 +: 2019.06.24 +--------------------------------------------------------------------------*/ +#ifndef _SC93F843x_H_ +#define _SC93F843x_H_ + +/* ------------------- ֽڼĴ-------------------- */ +///*CPU*/ +sfr ACC = 0xE0; //ۼ +sfr B = 0xF0; //ͨüĴB +sfr PSW = 0xD0; //״̬ +sfr DPH = 0x83; //ָ8λ +sfr DPL = 0x82; //ָ8λ +sfr SP = 0x81; //ջָ +sfr DPL1 = 0x84; //DPTR1ָ1λ +sfr DPH1 = 0x85; //DPTR1ָ1λ +sfr DPS = 0x86; //DPTRѡĴ + +/*system*/ +sfr PCON = 0x87; //ԴƼĴ + +/*interrupt*/ +sfr IP1 = 0XB9; //жȼƼĴ1 +sfr IP = 0xB8; //жȨƼĴ +sfr IE = 0xA8; //жϿƼĴ +sfr IE1 = 0XA9; //жϿƼĴ1 + +/*PORT*/ +sfr P5PH = 0xDA; //P5ģʽƼĴ0 +sfr P5CON = 0xD9; //P5ģʽƼĴ1 +sfr P5 = 0xD8; //P5ݼĴ +sfr P2PH = 0xA2; //P2ģʽƼĴ0 +sfr P2CON = 0xA1; //P2ģʽƼĴ1 +sfr P2 = 0xA0; //P2ݼĴ +sfr P1PH = 0x92; //P1ģʽƼĴ0 +sfr P1CON = 0x91; //P1ģʽƼĴ1 +sfr P1 = 0x90; //P1ݼĴ +sfr P0PH = 0x9B; //P0ģʽƼĴ1 +sfr P0CON = 0x9A; //P0ģʽƼĴ1 +sfr P0 = 0x80; //P0ݼĴ +sfr IOHCON = 0x97; //IOHüĴ + +/*TIMER*/ +sfr TMCON = 0x8E; //ʱƵʿƼĴ +sfr TH1 = 0x8D; //ʱ18λ +sfr TH0 = 0x8C; //ʱ08λ +sfr TL1 = 0x8B; //ʱ18λ +sfr TL0 = 0x8A; //ʱ08λ +sfr TMOD = 0x89; //ʱģʽĴ +sfr TCON = 0x88; //ʱƼĴ +sfr T2CON = 0XC8; //ʱ2ƼĴ +sfr T2MOD = 0XC9; //ʱ2ģʽĴ +sfr RCAP2L = 0XCA; //ʱ2/׽8λ +sfr RCAP2H = 0XCB; //ʱ2/׽8λ +sfr TL2 = 0XCC; //ʱ28λ +sfr TH2 = 0XCD; //ʱ28λ + + +/*ADC*/ +sfr ADCCFG0 = 0xAB; //P1ADCüĴ/οѹ +sfr ADCCFG1 = 0xAC; //P1ADCüĴ/οѹ +sfr ADCCON = 0XAD; //ADCƼĴ +sfr ADCVL = 0xAE; //ADC Ĵ +sfr ADCVH = 0xAF; //ADC Ĵ + +/*PWM*/ +sfr PWMCFG = 0xD1; //PWMüĴ +sfr PWMCON = 0xD2; //PWMƼĴ +sfr PWMPRD = 0xD3; //PWMüĴ +sfr PWMDTYA = 0xD4; //PWMߵƽüĴ +sfr PWMDTY0 = 0xD5; //PWMߵƽüĴ +sfr PWMDTY1 = 0XD6; //PWMߵƽüĴ +sfr PWMDTY2 = 0XD7; //PWMߵƽüĴ + +// +///*WatchDog*/ +sfr BTMCON = 0XCE; //ƵʱƼĴ +sfr WDTCON = 0xCF; //WDTƼĴ + + +/*LCD*/ +sfr OTCON = 0X8F; //LCDѹƼĴ +sfr P0VO = 0X9C; //P0 LCD Bais Ĵ + +/*INT*/ +sfr INT0F = 0XBA; //INT0 ½жϿƼĴ +sfr INT0R = 0XBB; //INT0 ϽжϿƼĴ +sfr INT1F = 0XBC; //INT1 ½жϿƼĴ +sfr INT1R = 0XBD; //INT1 ϽжϿƼĴ +sfr INT2F = 0XC6; //INT2 ½жϿƼĴ +sfr INT2R = 0XC7; //INT2 ϽжϿƼĴ + +/*PGA*/ +sfr PGACFG = 0XBE; //PGAüĴ +sfr PGACON = 0XBF; //PGAƼĴ + +/*IAP */ +sfr IAPCTL = 0xF6; //IAPƼĴ +sfr IAPDAT = 0xF5; //IAPݼĴ +sfr IAPADE = 0xF4; //IAPչַĴ +sfr IAPADH = 0xF3; //IAPдַλĴ +sfr IAPADL = 0xF2; //IAPдַ8λĴ +sfr IAPKEY = 0xF1; //IAPĴ + +/*UART*/ +sfr SCON = 0X98; //ڿƼĴ +sfr SBUF = 0X99; //ݻĴ + +/*SPI*/ +sfr SSCON0 = 0X9D; //SPIƼĴ +sfr SSCON1 = 0X9E; //SPI״̬Ĵ +sfr SSCON2 = 0X95; //SPI״̬Ĵ +sfr SSDAT = 0X9F; //SPIݼĴ + +sfr MXAX = 0XEA; +sfr TA = 0XEB; +sfr OPINX = 0XFE; +sfr OPREG = 0XFF; +sfr EXADH = 0XF7; + +/*temperature sensor*/ +sfr TSCFG = 0XAA; + +///* ------------------- λĴ-------------------- */ + +/*PSW*/ +sbit CY = PSW^7; //־λ 0:ӷλ޽λ߼λ޽λʱ 1:ӷλнλ߼λнλʱ +sbit AC = PSW^6; //λ־λ 0:޽λλ 1:ӷʱbit3λнλbit3λнλʱ +sbit F0 = PSW^5; //û־λ +sbit RS1 = PSW^4; //Ĵѡλ +sbit RS0 = PSW^3; //Ĵѡλ +sbit OV = PSW^2; //־λ +sbit P = PSW^0; //ż־λ 0:ACC1ĸΪż0 1:ACC1ĸΪ + +/*T2CON*/ +sbit TF2 = T2CON^7; +sbit EXF2 = T2CON^6; +sbit RCLK = T2CON^5; +sbit TCLK = T2CON^4; +sbit EXEN2 = T2CON^3; +sbit TR2 = T2CON^2; +sbit T2 = T2CON^1; +sbit CP = T2CON^0; + + +/*IP*/ +sbit IPADC = IP^6; //ADCжȿλ 0:趨 ADCжȨ ͡ 1:趨 ADCжȨ ߡ +sbit IPT2 = IP^5; //Timer2жȿλ 0:趨 Timer2жȨ ͡ 1:趨Timer2жȨ ߡ +sbit IPUART = IP^4; //UARTжȿλ 0:趨UARTжȨ ͡ 1:趨UARTжȨ ߡ +sbit IPT1 = IP^3; //Timer1жȿλ 0:趨 Timer 1жȨ ͡ 1:趨 Timer 1жȨ ߡ +sbit IPINT1 = IP^2; //INT1жȿλ 0:趨INT1жȨ ͡ 1:趨INT1жȨ ߡ +sbit IPT0 = IP^1; //Timer0жȿλ 0:趨 Timer 0жȨ ͡ 1:趨 Timer 0жȨ ߡ +sbit IPINT0 = IP^0; //INT0жȿλ 0:趨INT0жȨ ͡ 1:趨INT0жȨ ߡ + +/*IE*/ +sbit EA = IE^7; //жʹܵܿ 0:رеж 1:еж +sbit EADC = IE^6; //ADCжʹܿ 0:رADCж 1:ADCж +sbit ET2 = IE^5; //Timer2жʹܿ 0:رTimer2ж 1:Timer2ж +sbit EUART = IE^4; //UARTжʹܿ 0:رUARTж 1:UARTж +sbit ET1 = IE^3; //Timer1жʹܿ 0:رTIMER1ж 1:TIMER1ж +sbit EINT1 = IE^2; //INT1жʹܿ 0:رINT1ж 1:INT1ж +sbit ET0 = IE^1; //Timer0жʹܿ 0:رTIMER0ж 1:TIMER0ж +sbit EINT0 = IE^0; //INT0жʹܿ 0:رINT0ж 1:INT0ж + +/*TCON*/ +sbit TF1 = TCON^7; //T1ж־λ T1жʱӲTF1Ϊ1жϣCPUӦʱӲ塰0 +sbit TR1 = TCON^6; //ʱT1пλ 0:Timer1ֹ 1:Timer1ʼ +sbit TF0 = TCON^5; //T0ж־λ T0жʱӲTF0Ϊ1жϣCPUӦʱӲ塰0 +sbit TR0 = TCON^4; //ʱT0пλ 0:Timer0ֹ 1:Timer0ʼ + +/*SCON*/ +sbit SM0 = SCON^7; +sbit SM1 = SCON^6; +sbit SM2 = SCON^5; +sbit REN = SCON^4; +sbit TB8 = SCON^3; +sbit RB8 = SCON^2; +sbit TI = SCON^1; +sbit RI = SCON^0; + +/******************* P0 ****************** +*SC93F8433װδĹܽţ +*SC93F8432װδĹܽţP06/P07 +*SC93F8431װδĹܽţP02/P03/P05/P06/P07 +******************************************/ +sbit P07 = P0^7; +sbit P06 = P0^6; +sbit P05 = P0^5; +sbit P04 = P0^4; +sbit P03 = P0^3; +sbit P02 = P0^2; +sbit P01 = P0^1; +sbit P00 = P0^0; + +/******************* P1 ****************** +*SC93F8433װδĹܽţP10 +*SC93F8432װδĹܽţP10/P16/P17 +*SC93F8431װδĹܽţP10/P16/P17 +******************************************/ +sbit P17 = P1^7; +sbit P16 = P1^6; +sbit P15 = P1^5; +sbit P14 = P1^4; +sbit P13 = P1^3; +sbit P12 = P1^2; +sbit P11 = P1^1; + +/******************* P2 ****************** +*SC93F8433װδĹܽţ +*SC93F8432װδĹܽţP22/P23 +*SC93F8431װδĹܽţP22/P23/P27 +******************************************/ +sbit P27 = P2^7; +sbit P26 = P2^6; +sbit P25 = P2^5; +sbit P24 = P2^4; +sbit P23 = P2^3; +sbit P22 = P2^2; +sbit P21 = P2^1; +sbit P20 = P2^0; + +/******************* P5 ****************** +*SC93F8433װδĹܽţ +*SC93F8432װδĹܽţP50/P51 +*SC93F8431װδĹܽţP50/P51 +******************************************/ +sbit P52 = P5^2; +sbit P51 = P5^1; +sbit P50 = P5^0; + +/**************************************************************************** +*ע⣺װδĹܽţΪǿģʽ +*ICѡͣʹõICͺ,ڳʼIOں󣬵ӦδܽŵIO; +* +*****************************************************************************/ +#define SC93F8433_NIO_Init() {P1CON|=0x01;} //SC93F8433δIO +#define SC93F8432_NIO_Init() {P0CON|=0xC0;P1CON|=0xC1;P2CON|=0x0C;P5CON|=0x03;} //SC93F8432δIO +#define SC93F8431_NIO_Init() {P0CON|=0xEC;P1CON|=0xC1;P2CON|=0x8C;P5CON|=0x03;} //SC93F8431δIO + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f.h new file mode 100644 index 0000000..7b393f5 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f.h @@ -0,0 +1,201 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f.h +// : +// ģ鹦 : ԪSC92ϵϵͳͷļ +// ֲб: +// : 202276 +// 汾 : V1.10030 +// ˵ ļԪ92FϵеƬ +//************************************************************* + +#ifndef _sc92f_H +#define _sc92f_H + +#ifdef SC92F854x + #include "SC92F854x_C.H" +#endif + +#ifdef SC92F754x + #include "SC92F754x_C.H" +#endif + +#ifdef SC92F844xB + #include "SC92F844xB_C.H" +#endif + +#ifdef SC92F744xB + #include "SC92F744xB_C.H" +#endif + +#ifdef SC92F846xB + #include "SC92F846xB_C.H" +#endif + +#ifdef SC92F746xB + #include "SC92F746xB_C.H" +#endif + +#ifdef SC92F836xB + #include "SC92F836xB_C.H" +#endif + +#ifdef SC92F736xB + #include "SC92F736xB_C.H" +#endif + +#ifdef SC92F742x + #include "SC92F742x_C.H" +#endif + +#ifdef SC92F7003 + #include "SC92F7003_C.H" +#endif + +#ifdef SC92F8003 + #include "SC92F8003_C.H" +#endif + +#ifdef SC92F740x + #include "SC92F740x_C.H" +#endif + +#ifdef SC92F74Ax + #include "SC92F74Ax_C.H" +#endif + +#ifdef SC92F84Ax + #include "SC92F84Ax_C.H" +#endif + +#ifdef SC92F73Ax + #include "SC92F73Ax_C.H" +#endif + +#ifdef SC92F83Ax + #include "SC92F83Ax_C.H" +#endif + +#ifdef SC92F74Ax_2 + #include "SC92F74Ax_2_C.H" +#endif + +#ifdef SC92F84Ax_2 + #include "SC92F84Ax_2_C.H" +#endif + +#ifdef SC92F730x + #include "SC92F730x_C.h" +#endif + +#ifdef SC92F827X + #include "SC92F827X_C.h" +#endif + +#ifdef SC92F837X + #include "SC92F837X_C.H" +#endif + +#ifdef SC92F7490 + #include "SC92F7490_C.H" +#endif + +#ifdef SC92F725X + #include "SC92F725X_C.h" +#endif + +#ifdef SC92F735X + #include "SC92F735X_C.h" +#endif + +#ifdef SC92F732X + #include "SC92F732X_C.H" +#endif + +#ifdef SC92FWxx + #include "SC92FWxx_C.H" +#endif + +#ifdef SC93F833x + #include "SC93F833x_C.H" +#endif + +#ifdef SC93F843x + #include "SC93F843x_C.H" +#endif + +#ifdef SC93F743x + #include "SC93F743x_C.H" +#endif + +#ifdef SC92F848x + #include "SC92F848x_C.H" +#endif + +#ifdef SC92F748x + #include "SC92F748x_C.H" +#endif + +#ifdef SC92F859x + #include "SC92F859x_C.H" +#endif + +#ifdef SC92F759x + #include "SC92F759x_C.H" +#endif + +#ifdef SC92L853x + #include "SC92L853x_C.H" +#endif + +#ifdef SC92L753x + #include "SC92L753x_C.H" +#endif + +#define enableInterrupts() EA=1 /** ж **/ +#define disableInterrupts() EA=0 /** رж **/ + +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*!< Signed integer types */ +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed long int32_t; + +/*!< Unsigned integer types */ +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned long uint32_t; + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, +ITStatus, BitStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +typedef enum {LOW = 0, HIGH = !LOW} PriorityStatus; + +#define SET_BIT(SFR,BIT) ((SFR) |= (BIT)) + +#define CLEAR_BIT(SFR,BIT) ((SFR) &= ~(BIT)) + +#define READ_BIT(SFR, BIT) ((SFR) & (BIT)) + +#define CLEAR_REG(SFR) ((SFR) = (0x0)) + +#define WRITE_REG(SFR, VAL) ((SFR) = (VAL)) + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_acmp.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_acmp.h new file mode 100644 index 0000000..6844837 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_acmp.h @@ -0,0 +1,78 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_acmp.h +// : +// ģ鹦 : ACMP̼⺯ͷļ +// : 2020/8/20 +// 汾 : V1.0001 +// ˵ : +//************************************************************* + +#ifndef _sc92f_ACMP_H_ +#define _sc92f_ACMP_H_ + +#include "sc92f.h" +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + ACMP_VREF_EXTERNAL = (uint8_t)0X00, //ѡCMPRΪACMPıȽϵѹ + ACMP_VREF_1D16VDD = (uint8_t)0X01, //ѡ1/16VDDΪACMPıȽϵѹ + ACMP_VREF_2D16VDD = (uint8_t)0X02, //ѡ2/16VDDΪACMPıȽϵѹ + ACMP_VREF_3D16VDD = (uint8_t)0X03, //ѡ3/16VDDΪACMPıȽϵѹ + ACMP_VREF_4D16VDD = (uint8_t)0X04, //ѡ4/16VDDΪACMPıȽϵѹ + ACMP_VREF_5D16VDD = (uint8_t)0X05, //ѡ5/16VDDΪACMPıȽϵѹ + ACMP_VREF_6D16VDD = (uint8_t)0X06, //ѡ6/16VDDΪACMPıȽϵѹ + ACMP_VREF_7D16VDD = (uint8_t)0X07, //ѡ7/16VDDΪACMPıȽϵѹ + ACMP_VREF_8D16VDD = (uint8_t)0X08, //ѡ8/16VDDΪACMPıȽϵѹ + ACMP_VREF_9D16VDD = (uint8_t)0X09, //ѡ9/16VDDΪACMPıȽϵѹ + ACMP_VREF_10D16VDD = (uint8_t)0X0A, //ѡ10/16VDDΪACMPıȽϵѹ + ACMP_VREF_11D16VDD = (uint8_t)0X0B, //ѡ11/16VDDΪACMPıȽϵѹ + ACMP_VREF_12D16VDD = (uint8_t)0X0C, //ѡ12/16VDDΪACMPıȽϵѹ + ACMP_VREF_13D16VDD = (uint8_t)0X0D, //ѡ13/16VDDΪACMPıȽϵѹ + ACMP_VREF_14D16VDD = (uint8_t)0X0E, //ѡ14/16VDDΪACMPıȽϵѹ + ACMP_VREF_15D16VDD = (uint8_t)0X0F //ѡ15/16VDDΪACMPıȽϵѹ +} ACMP_Vref_Typedef; + +typedef enum +{ + ACMP_CHANNEL_0 = (uint8_t)0x00, //ѡCMP0ACMP + ACMP_CHANNEL_1 = (uint8_t)0x01, //ѡCMP1ACMP + ACMP_CHANNEL_2 = (uint8_t)0x02, //ѡCMP2ACMP + ACMP_CHANNEL_3 = (uint8_t)0x03, //ѡCMP3ACMP + #if defined(SC92F859x) || defined (SC92F759x) + ACMP_CHANNEL_P = (uint8_t)0x10, //ѡCMPPACMPڣCMPPΪ׼ѹ1.5V + #endif +} ACMP_Channel_TypeDef; + +typedef enum +{ + ACMP_TRIGGER_NO = (uint8_t)0x00, //ж + ACMP_TRIGGER_RISE_ONLY = (uint8_t)0x04, //ģȽʽΪ + ACMP_TRIGGER_FALL_ONLY = (uint8_t)0x08, //ģȽʽΪ½ + ACMP_TRIGGER_RISE_FALL = (uint8_t)0x0C //ģȽʽΪ½ +} ACMP_TriggerMode_Typedef; + +typedef enum +{ + ACMP_FLAG_CMPIF = (uint8_t)0x40, //ACMPжϱ־λ + ACMP_FLAG_CMPSTA = (uint8_t)0x20 //ACMP״̬ +} ACMP_Flag_TypeDef; + +void ACMP_DeInit(void); +void ACMP_Init(ACMP_Vref_Typedef ACMP_Vref, + ACMP_Channel_TypeDef ACMP_Channel); +void ACMP_SetTriggerMode(ACMP_TriggerMode_Typedef + ACMP_TriggerMode); +void ACMP_Cmd(FunctionalState NewState); +void ACMP_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +FlagStatus ACMP_GetFlagStatus(ACMP_Flag_TypeDef + ACMP_Flag); +void ACMP_ClearFlag(void); + +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_adc.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_adc.h new file mode 100644 index 0000000..d0a2d7d --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_adc.h @@ -0,0 +1,326 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_adc.h +// : ԪӦŶ +// ģ鹦: ADC̼⺯ͷļ +// : 2022323 +// 汾: V1.100014 +// ˵: ļԪ92F/93F/92LϵеƬ +//************************************************************* +#ifndef _sc92f_ADC_H_ +#define _sc92f_ADC_H_ + +/* ͷļ */ +#include "sc92f.h" +/* ˵:ADCοԴöٶsc92f_option.hʹADCע⽫ļ */ +#include "sc92f_option.h" + +#if !defined(SC92F827X) && !defined(SC92F837X) +/* ADCʱӷƵת */ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2) || defined(SC92FWxx) +typedef enum +{ + ADC_PRESSEL_FOSC_D6 = (uint8_t)0x02, //ԤƵ fADC = fHRC/6 + ADC_PRESSEL_FOSC_D12 = (uint8_t)0x01 //ԤƵ fADC = fHRC/12 +} ADC_PresSel_TypeDef; +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + ADC_PRESSEL_FHRC_D32 = (uint8_t)0x00, //ԤƵ fADC = fHRC/32 + ADC_PRESSEL_FHRC_D24 = (uint8_t)0x01, //ԤƵ fADC = fHRC/24 + ADC_PRESSEL_FHRC_D16 = (uint8_t)0x02, //ԤƵ fADC = fHRC/16 + ADC_PRESSEL_FHRC_D12 = (uint8_t)0x03, //ԤƵ fADC = fHRC/12 + ADC_PRESSEL_FHRC_D8 = (uint8_t)0x04, //ԤƵ fADC = fHRC/8 + ADC_PRESSEL_FHRC_D6 = (uint8_t)0x05, //ԤƵ fADC = fHRC/6 + ADC_PRESSEL_FHRC_D4 = (uint8_t)0x06, //ԤƵ fADC = fHRC/4 + ADC_PRESSEL_FHRC_D3 = (uint8_t)0x07 //ԤƵ fADC = fHRC/3 +} ADC_PresSel_TypeDef; +#elif defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) || defined (SC92F7490)\ + || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + ADC_PRESSEL_2_MHz = (uint8_t)0x00, //ԤƵ fADC = 2MHz + ADC_PRESSEL_333_kHz = (uint8_t)0x20 //ԤƵ fADC = 333kHz +} ADC_PresSel_TypeDef; +#elif defined(SC92F848x) || defined(SC92F748x) +typedef enum +{ + ADC_PRESSEL_FSYS_D16 = (uint8_t)0x00, //ԤƵ fADC = fSYS/16 + ADC_PRESSEL_FSYS_D12 = (uint8_t)0x01, //ԤƵ fADC = fSYS/12 + ADC_PRESSEL_FSYS_D8 = (uint8_t)0x02, //ԤƵ fADC = fSYS/8 + ADC_PRESSEL_FSYS_D6 = (uint8_t)0x03, //ԤƵ fADC = fSYS/6 + ADC_PRESSEL_FSYS_D4 = (uint8_t)0x04, //ԤƵ fADC = fSYS/4 + ADC_PRESSEL_FSYS_D3 = (uint8_t)0x05, //ԤƵ fADC = fSYS/3 + ADC_PRESSEL_FSYS_D2 = (uint8_t)0x06, //ԤƵ fADC = fSYS/2 + ADC_PRESSEL_FSYS_D1 = (uint8_t)0x07 //ԤƵ fADC = fSYS/1 +} ADC_PresSel_TypeDef; +#elif defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + ADC_PRESSEL_FSYS_D16 = (uint8_t)0x00, //ԤƵ fADC = fSYS/16 + ADC_PRESSEL_FSYS_D12 = (uint8_t)0x01, //ԤƵ fADC = fSYS/12 + ADC_PRESSEL_FSYS_D6 = (uint8_t)0x02, //ԤƵ fADC = fSYS/6 + ADC_PRESSEL_FSYS_D4 = (uint8_t)0x03, //ԤƵ fADC = fSYS/4 +} ADC_PresSel_TypeDef; +#elif defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_PRESSEL_3CLOCK = (uint8_t)0x10, //ʱΪ3ϵͳʱ + ADC_PRESSEL_6CLOCK = (uint8_t)0x14, //ʱΪ6ϵͳʱ + ADC_PRESSEL_16CLOCK = (uint8_t)0x18, //ʱΪ16ϵͳʱ + ADC_PRESSEL_32CLOCK = (uint8_t)0x1c //ʱΪ32ϵͳʱ +} ADC_PresSel_TypeDef; +#endif + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ +|| defined(SC92FWxx) || defined(SC92F859x) || defined (SC92F759x) +typedef enum +{ + ADC_Cycle_6Cycle = (uint8_t)0x00, //ADCʱΪ6ADCʱ + ADC_Cycle_36Cycle = (uint8_t)0x04 //ADCʱΪ36ADCʱ +} ADC_Cycle_TypeDef; +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F7003) || defined(SC92F8003) || defined (SC92F740x) || defined (SC92F848x) || defined (SC92F748x) +typedef enum +{ + ADC_Cycle_6Cycle = (uint8_t)0x00, //ADCʱΪ6ADCʱ + ADC_Cycle_36Cycle = (uint8_t)0x08 //ADCʱΪ36ADCʱ +} ADC_Cycle_TypeDef; +#elif defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X)\ +|| defined (SC92F7490) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_Cycle_Null = (uint8_t)0x00, +} ADC_Cycle_TypeDef; +#endif + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_2 = (uint8_t)0x02, //ѡAIN2AD + ADC_CHANNEL_3 = (uint8_t)0x03, //ѡAIN3AD + ADC_CHANNEL_4 = (uint8_t)0x04, //ѡAIN4AD + ADC_CHANNEL_5 = (uint8_t)0x05, //ѡAIN5AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_7 = (uint8_t)0x07, //ѡAIN7AD + ADC_CHANNEL_8 = (uint8_t)0x08, //ѡAIN8AD + ADC_CHANNEL_9 = (uint8_t)0x09, //ѡAIN9AD + ADC_CHANNEL_10 = (uint8_t)0x0A, //ѡAIN10AD + ADC_CHANNEL_11 = (uint8_t)0x0B, //ѡAIN11AD + ADC_CHANNEL_12 = (uint8_t)0x0C, //ѡAIN12AD + ADC_CHANNEL_13 = (uint8_t)0x0D, //ѡAIN13AD + ADC_CHANNEL_14 = (uint8_t)0x0E, //ѡAIN14AD + ADC_CHANNEL_15 = (uint8_t)0x0F, //ѡAIN15AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_2 = (uint8_t)0x02, //ѡAIN2AD + ADC_CHANNEL_3 = (uint8_t)0x03, //ѡAIN3AD + ADC_CHANNEL_4 = (uint8_t)0x04, //ѡAIN4AD + ADC_CHANNEL_5 = (uint8_t)0x05, //ѡAIN5AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F83Ax)\ +|| defined(SC92F73Ax) || defined(SC92F84Ax) || defined(SC92F74Ax) || defined(SC92F742x) || defined(SC92F725X)\ +|| defined(SC92F735X) || defined(SC92F732X) || defined(SC92F848x) || defined(SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_2 = (uint8_t)0x02, //ѡAIN2AD + ADC_CHANNEL_3 = (uint8_t)0x03, //ѡAIN3AD + ADC_CHANNEL_4 = (uint8_t)0x04, //ѡAIN4AD + ADC_CHANNEL_5 = (uint8_t)0x05, //ѡAIN5AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_7 = (uint8_t)0x07, //ѡAIN7AD + ADC_CHANNEL_8 = (uint8_t)0x08, //ѡAIN8AD + ADC_CHANNEL_9 = (uint8_t)0x09, //ѡAIN9AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC92F730x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_7 = (uint8_t)0x07, //ѡAIN7AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC92F7490) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x1f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#elif defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +typedef enum +{ + ADC_CHANNEL_0 = (uint8_t)0x00, //ѡAIN0AD + ADC_CHANNEL_1 = (uint8_t)0x01, //ѡAIN1AD + ADC_CHANNEL_2 = (uint8_t)0x02, //ѡAIN2AD + ADC_CHANNEL_3 = (uint8_t)0x03, //ѡAIN3AD + ADC_CHANNEL_4 = (uint8_t)0x04, //ѡAIN4AD + ADC_CHANNEL_5 = (uint8_t)0x05, //ѡAIN5AD + ADC_CHANNEL_6 = (uint8_t)0x06, //ѡAIN6AD + ADC_CHANNEL_7 = (uint8_t)0x07, //ѡAIN7AD + ADC_CHANNEL_8 = (uint8_t)0x08, //ѡAIN8AD + ADC_CHANNEL_9 = (uint8_t)0x09, //ѡAIN9AD + ADC_CHANNEL_9_PGA = (uint8_t)0x19, //ѡAIN9PGA + ADC_CHANNEL_Temp = (uint8_t)0x0e, //ѡڲ¶ȴΪAD + ADC_CHANNEL_VDD_D4 = (uint8_t)0x0f //ѡڲ1/4VDDAD +} ADC_Channel_TypeDef; +#endif + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 + ADC_EAIN_2 = (uint16_t)0x0004, //ѡAIN2 + ADC_EAIN_3 = (uint16_t)0x0008, //ѡAIN3 + ADC_EAIN_4 = (uint16_t)0x0010, //ѡAIN4 + ADC_EAIN_5 = (uint16_t)0x0020, //ѡAIN5 + ADC_EAIN_6 = (uint16_t)0x0040, //ѡAIN6 + ADC_EAIN_7 = (uint16_t)0x0080, //ѡAIN7 + ADC_EAIN_8 = (uint16_t)0x0100, //ѡAIN8 + ADC_EAIN_9 = (uint16_t)0x0200, //ѡAIN9 + ADC_EAIN_10 = (uint16_t)0x0400, //ѡAIN10 + ADC_EAIN_11 = (uint16_t)0x0800, //ѡAIN11 + ADC_EAIN_12 = (uint16_t)0x1000, //ѡAIN12 + ADC_EAIN_13 = (uint16_t)0x2000, //ѡAIN13 + ADC_EAIN_14 = (uint16_t)0x4000, //ѡAIN14 + ADC_EAIN_15 = (uint16_t)0x8000 //ѡAIN15 +} ADC_EAIN_TypeDef; +#elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 + ADC_EAIN_2 = (uint16_t)0x0004, //ѡAIN2 + ADC_EAIN_3 = (uint16_t)0x0008, //ѡAIN3 + ADC_EAIN_4 = (uint16_t)0x0010, //ѡAIN4 + ADC_EAIN_5 = (uint16_t)0x0020, //ѡAIN5 + ADC_EAIN_6 = (uint16_t)0x0040 //ѡAIN6 +} ADC_EAIN_TypeDef; +#elif defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F83Ax)\ +|| defined(SC92F73Ax) || defined(SC92F84Ax) || defined(SC92F74Ax) || defined(SC92F742x) || defined(SC92F725X)\ +|| defined(SC92F735X) || defined(SC92F732X) || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x)\ +|| defined(SC92F848x) || defined(SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 + ADC_EAIN_2 = (uint16_t)0x0004, //ѡAIN2 + ADC_EAIN_3 = (uint16_t)0x0008, //ѡAIN3 + ADC_EAIN_4 = (uint16_t)0x0010, //ѡAIN4 + ADC_EAIN_5 = (uint16_t)0x0020, //ѡAIN5 + ADC_EAIN_6 = (uint16_t)0x0040, //ѡAIN6 + ADC_EAIN_7 = (uint16_t)0x0080, //ѡAIN7 + ADC_EAIN_8 = (uint16_t)0x0100, //ѡAIN8 + ADC_EAIN_9 = (uint16_t)0x0200, //ѡAIN9 +} ADC_EAIN_TypeDef; +#elif defined(SC92F730x) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 + ADC_EAIN_6 = (uint16_t)0x0040, //ѡAIN6 + ADC_EAIN_7 = (uint16_t)0x0080, //ѡAIN7 +} ADC_EAIN_TypeDef; +#elif defined(SC92F7490) +typedef enum +{ + ADC_EAIN_0 = (uint16_t)0x0001, //ѡAIN0 + ADC_EAIN_1 = (uint16_t)0x0002, //ѡAIN1 +} ADC_EAIN_TypeDef; +#endif + +/* ڲ¶ȲɼͿɵŴPGAö*/ +#if defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +/* PGAģѹö */ +typedef enum +{ + ADC_PGACOM_0V = 0x00, //ģѹΪ0V + ADC_PGACOM_1_2V = 0x40, //ģѹΪ1.2V +} ADC_PGACOM_TypeDef; + +/* PGAͬö */ +typedef enum +{ + ADC_PGAGAN_NonInvert20 = 0x00, //ͬΪ20Ϊ19 + ADC_PGAGAN_NonInvert100 = 0x20, //ͬΪ100Ϊ99 +} ADC_PGAGAN_TypeDef; + +/* PGAλö */ +typedef enum +{ + ADC_PGAIPT_NonInvert = 0x00, //ͬ + ADC_PGAIPT_Invert = 0x10, // +} ADC_PGAIPT_TypeDef; +#endif + +/*******************************꺯*******************************/ +/***************************************************** +*:void ADC_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:ADCжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +#define ADC_ITConfig(NewState,Priority) \ + do{ \ + EADC = (bit)NewState; \ + IPADC = (bit)Priority; \ + }while(0) + +/***************************************************** +*:void ADC_StartConversion(void) +*:ʼһADת +*ڲ:void +*ڲ:void +*****************************************************/ +#define ADC_StartConversion() SET_BIT(ADCCON,0X40) + +/* ڲ¶ȲɼͿɵŴ */ +#if defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +/* ڲ¶Ȳɼغ */ +void ADC_TSCmd(FunctionalState NewState); +void ADC_CHOPConfig(PriorityStatus NewState); +uint16_t ADC_Get_TS_StandardData(void); +float ADC_GetTSValue(void); +/* PGAغ */ +void ADC_PGAConfig(ADC_PGACOM_TypeDef ADC_PGACOM, ADC_PGAGAN_TypeDef ADC_PGAGAN, ADC_PGAIPT_TypeDef ADC_PGAIPT); +void ADC_PGACmd(PriorityStatus NewState); +#endif + +/* ADCͨú */ +void ADC_DeInit(void); +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, ADC_Cycle_TypeDef ADC_Cycle); +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, + FunctionalState NewState); +void ADC_Cmd(FunctionalState NewState); +unsigned int ADC_GetConversionValue(void); +FlagStatus ADC_GetFlagStatus(void); +void ADC_ClearFlag(void); +void ADC_EAINConfig(uint16_t ADC_EAIN_Select, + FunctionalState NewState); +void ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref); + + +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_btm.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_btm.h new file mode 100644 index 0000000..5eb4f1b --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_btm.h @@ -0,0 +1,89 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_btm.h +// : ԪӦŶ +// ģ鹦: BTM̼⺯Hļ +// : 202242 +// 汾: V1.10002 +// ˵: +//************************************************************* +#ifndef _sc92f_BTM_H_ +#define _sc92f_BTM_H_ + +#include "sc92f.h" + +#if defined(SC92F748x) || defined(SC92F848x) || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + BTM_TIMEBASE_15_625MS = (uint8_t)0x00, //BTMÿ15.625MSһж + BTM_TIMEBASE_31_25MS = (uint8_t)0x01, //BTMÿ31.25MSһж + BTM_TIMEBASE_62_5MS = (uint8_t)0x02, //BTMÿ62.5MSһж + BTM_TIMEBASE_125MS = (uint8_t)0x03, //BTMÿ125MSһж + BTM_TIMEBASE_250MS = (uint8_t)0x04, //BTMÿ0.25Sһж + BTM_TIMEBASE_500MS = (uint8_t)0x05, //BTMÿ0.5Sһж + BTM_TIMEBASE_1S = (uint8_t)0x06, //BTMÿ1Sһж + BTM_TIMEBASE_2S = (uint8_t)0x07, //BTMÿ2Sһж + BTM_TIMEBASE_8S = (uint8_t)0x09, //BTMÿ8Sһж + BTM_TIMEBASE_16S = (uint8_t)0x0A, //BTMÿ16Sһж + BTM_TIMEBASE_32S = (uint8_t)0x0B, //BTMÿ32һж +} BTM_Timebase_TypeDef; +#elif defined (SC92F732X) +typedef enum +{ + BTM_TIMEBASE_15_625MS = (uint8_t)0x00, //BTMÿ15.625MSһж + BTM_TIMEBASE_31_25MS = (uint8_t)0x01, //BTMÿ31.25MSһж + BTM_TIMEBASE_62_5MS = (uint8_t)0x02, //BTMÿ62.5MSһж + BTM_TIMEBASE_125MS = (uint8_t)0x03, //BTMÿ125MSһж + BTM_TIMEBASE_250MS = (uint8_t)0x04, //BTMÿ0.25Sһж + BTM_TIMEBASE_500MS = (uint8_t)0x05, //BTMÿ0.5Sһж + BTM_TIMEBASE_1S = (uint8_t)0x06, //BTMÿ1Sһж + BTM_TIMEBASE_2S = (uint8_t)0x07, //BTMÿ2Sһж +} BTM_Timebase_TypeDef; +#else +typedef enum +{ + BTM_TIMEBASE_15_625MS = (uint8_t)0x00, //BTMÿ15.625MSһж + BTM_TIMEBASE_31_25MS = (uint8_t)0x01, //BTMÿ31.25MSһж + BTM_TIMEBASE_62_5MS = (uint8_t)0x02, //BTMÿ62.5MSһж + BTM_TIMEBASE_125MS = (uint8_t)0x03, //BTMÿ125MSһж + BTM_TIMEBASE_250MS = (uint8_t)0x04, //BTMÿ0.25Sһж + BTM_TIMEBASE_500MS = (uint8_t)0x05, //BTMÿ0.5Sһж + BTM_TIMEBASE_1S = (uint8_t)0x06, //BTMÿ1Sһж + BTM_TIMEBASE_2S = (uint8_t)0x07, //BTMÿ2Sһж + BTM_TIMEBASE_4S = (uint8_t)0x08, //BTMÿ4Sһж +} BTM_Timebase_TypeDef; +#endif + +/*******************************꺯*******************************/ +/************************************************** +*:void BTM_DeInit(void) +*:BTMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +#define BTM_DeInit() CLEAR_REG(BTMCON) + +/***************************************************** +*:void BTM_GetFlagStatus(void) +*:ȡBTMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:BTMжϱ־״̬ +*****************************************************/ +#define BTM_GetFlagStatus() ((READ_BIT(BTMCON,0x40)) ? (SET):(RESET)) + +/***************************************************** +*:void BTM_ClearFlag(void) +*:BTMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +#define BTM_ClearFlag() CLEAR_BIT(BTMCON,0x40) + +void BTM_Init(BTM_Timebase_TypeDef BTM_Timebase); +void BTM_Cmd(FunctionalState NewState); +void BTM_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_chksum.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_chksum.h new file mode 100644 index 0000000..b75a7b1 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_chksum.h @@ -0,0 +1,28 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_chksum.h +// : +// ģ鹦 : CHKSUM̼⺯ͷļ +// : 2021/8/20 +// 汾 : V1.10000 +// ˵ : +//************************************************************* + +#ifndef _sc92f_CHKSUM_H_ +#define _sc92f_CHKSUM_H_ + +#include "sc92f.h" + +#if defined(SC92F7003) || defined(SC92F8003) || defined(SC92F736xB) || defined(SC92F836xB) || defined(SC92F740x) || defined(SC92F742x)\ + || defined(SC92F73Ax) || defined(SC92F83Ax) || defined(SC92F744xB) || defined(SC92F844xB) || defined(SC92F746xB) || defined(SC92F846xB)\ + || defined(SC92F748x) || defined(SC92F848x) || defined(SC92F74Ax) || defined(SC92F84Ax) || defined(SC92F74Ax_2) || defined(SC92F84Ax_2)\ + || defined(SC92F754x) || defined (SC92F854x) || defined (SC92F759x) || defined(SC92F859x) || defined (SC92F7490) || defined(SC92FWxx)\ + || defined(SC92F827X) || defined(SC92F847X) + void CHKSUM_DeInit(void); + void CHKSUM_StartOperation(void); + uint16_t CHKSUM_GetCheckValue(void); +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_conf.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_conf.h new file mode 100644 index 0000000..ad2c889 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_conf.h @@ -0,0 +1,40 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_conf.h +// : +// ģ鹦 : sc92fͷļ +// : 2022/01/24 +// 汾 : V1.10002 +// ˵ ļԪ92FϵеƬ +//************************************************************* + +#ifndef _sc92f_CONF_H_ +#define _sc92f_CONF_H_ + +#include "sc92f_gpio.h" +#include "sc92f_timer0.h" +#include "sc92f_timer1.h" +#include "sc92f_timer2.h" +#include "sc92f_timer3.h" +#include "sc92f_timer4.h" +#include "sc92f_adc.h" +#include "sc92f_btm.h" +#include "sc92f_pwm.h" +#include "sc92f_int.h" +#include "sc92f_uart0.h" +#include "sc92f_ssi.h" +#include "sc92f_chksum.h" +#include "sc92f_iap.h" +#include "sc92f_option.h" +#include "sc92f_wdt.h" +#include "sc92f_pwr.h" +#include "sc92f_ddic.h" +#include "sc92f_acmp.h" +#include "sc92f_mdu.h" +#include "sc92f_CRC.h" +#include "sc92f_usci0.h" +#include "sc92f_usci1.h" +#include "sc92f_usci2.h" +#include "sc92f_lpd.h" + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_crc.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_crc.h new file mode 100644 index 0000000..bafba09 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_crc.h @@ -0,0 +1,24 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_CRC.h +// : +// ģ鹦 : CRC̼⺯ͷļ +// : 2020/8/14 +// 汾 : V1.0 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_CRC_H_ +#define _sc92f_CRC_H_ + +#include "sc92f.h" + +#if defined (SC92L853x) || defined (SC92L753x) +uint32_t CRC_All(void); //IAP RangeѡӲCRCCODEݣCRC +uint32_t CRC_Frame(uint8_t *buff, + uint8_t Length); //CRCbuffָCRC㣬CRC +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_ddic.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_ddic.h new file mode 100644 index 0000000..3933fe3 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_ddic.h @@ -0,0 +1,195 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ddic.c +// : +// ģ鹦 : DDIC̼⺯Cļ +// ֲб: +// : 2022/01/20 +// 汾 : V1.10002 +// ˵ : +//************************************************************* +#ifndef _sc92f_DDIC_H_ +#define _sc92f_DDIC_H_ + +#include "sc92f.h" + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + DDIC_PIN_X0 = ((uint8_t)0x01), //Px0ڴʾ + DDIC_PIN_X1 = ((uint8_t)0x02), //Px1ڴʾ + DDIC_PIN_X2 = ((uint8_t)0x04), //Px2ڴʾ + DDIC_PIN_X3 = ((uint8_t)0x08), //Px3ڴʾ + DDIC_PIN_X4 = ((uint8_t)0x10), //Px4ڴʾ + DDIC_PIN_X5 = ((uint8_t)0x20), //Px5ڴʾ + DDIC_PIN_X6 = ((uint8_t)0x40), //Px6ڴʾ + DDIC_PIN_X7 = ((uint8_t)0x80), //Px7ڴʾ +} DDIC_Pin_TypeDef; + +typedef enum +{ + DDIC_DUTYCYCLE_D8 = (uint8_t)0x00, //1/8 ռձ + DDIC_DUTYCYCLE_D6 = (uint8_t)0x10, //1/6 ռձ + DDIC_DUTYCYCLE_D5 = (uint8_t)0x20, //1/5 ռձ + DDIC_DUTYCYCLE_D4 = (uint8_t)0x30 //1/4 ռձ +} DDIC_DutyCycle_TypeDef; + +typedef enum +{ + DDIC_ResSel_100K = (uint8_t)0X00, //趨ڲѹΪ100k + DDIC_ResSel_200K = (uint8_t)0X04, //趨ڲѹΪ200k + DDIC_ResSel_400K = (uint8_t)0X08, //趨ڲѹΪ400k + DDIC_ResSel_800K = (uint8_t)0X0C //趨ڲѹΪ800k +} DDIC_ResSel_Typedef; + +typedef enum +{ + DDIC_BIAS_D3 = 0X01, //LCDƫõѹΪ1/3 + DDIC_BIAS_D4 = 0X00 //LCDƫõѹΪ1/4 +} DDIC_BiasVoltage_Typedef; + +#if defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + SEG0_27COM4_7 = (uint8_t)0x01, // 1/4ռձʱS0-S27ΪsegmentC4-C7Ϊcommon + SEG4_27COM0_3 = (uint8_t)0x00 // 1/4ռձʱS4-S27ΪsegmentC0-C3Ϊcommon +} DDIC_OutputPin_TypeDef; + +#else + +typedef enum +{ + SEG0_27COM4_7 = (uint8_t)0x00, // 1/4ռձʱS0-S27ΪsegmentC4-C7Ϊcommon + SEG4_27COM0_3 = (uint8_t)0x01 // 1/4ռձʱS4-S27ΪsegmentC0-C3Ϊcommon +} DDIC_OutputPin_TypeDef; + +#endif + +typedef enum +{ + DMOD_LCD = (uint8_t)0x00, // LCDģʽ + DMOD_LED = (uint8_t)0x01 // LEDģʽ +} DDIC_DMOD_TypeDef; + +typedef enum +{ + DDIC_SEG0 = (uint8_t)0, //SEG0 + DDIC_SEG1 = (uint8_t)1, //SEG1 + DDIC_SEG2 = (uint8_t)2, //SEG2 + DDIC_SEG3 = (uint8_t)3, //SEG3 + DDIC_SEG4 = (uint8_t)4, //SEG4 + DDIC_SEG5 = (uint8_t)5, //SEG5 + DDIC_SEG6 = (uint8_t)6, //SEG6 + DDIC_SEG7 = (uint8_t)7, //SEG7 + DDIC_SEG8 = (uint8_t)8, //SEG8 + DDIC_SEG9 = (uint8_t)9, //SEG9 + DDIC_SEG10 = (uint8_t)10, //SEG10 + DDIC_SEG11 = (uint8_t)11, //SEG11 + DDIC_SEG12 = (uint8_t)12, //SEG12 + DDIC_SEG13 = (uint8_t)13, //SEG13 + DDIC_SEG14 = (uint8_t)14, //SEG14 + DDIC_SEG15 = (uint8_t)15, //SEG15 + DDIC_SEG16 = (uint8_t)16, //SEG16 + DDIC_SEG17 = (uint8_t)17, //SEG17 + DDIC_SEG18 = (uint8_t)18, //SEG18 + DDIC_SEG19 = (uint8_t)19, //SEG19 + DDIC_SEG20 = (uint8_t)20, //SEG20 + DDIC_SEG21 = (uint8_t)21, //SEG21 + DDIC_SEG22 = (uint8_t)22, //SEG22 + DDIC_SEG23 = (uint8_t)23, //SEG23 + DDIC_SEG24 = (uint8_t)24, //SEG24 + DDIC_SEG25 = (uint8_t)25, //SEG25 + DDIC_SEG26 = (uint8_t)26, //SEG26 + DDIC_SEG27 = (uint8_t)27, //SEG27 +} DDIC_Control_SEG_TypeDef; + +typedef enum +{ + DDIC_COM0 = (uint8_t)0x01, //COM0 + DDIC_COM1 = (uint8_t)0x02, //COM1 + DDIC_COM2 = (uint8_t)0x04, //COM2 + DDIC_COM3 = (uint8_t)0x08, //COM3 + DDIC_COM4 = (uint8_t)0x10, //COM4 + DDIC_COM5 = (uint8_t)0x20, //COM5 + DDIC_COM6 = (uint8_t)0x40, //COM6 + DDIC_COM7 = (uint8_t)0x80 //COM7 +} DDIC_Control_COM_TypeDef; +typedef enum +{ + DDIC_Control_ON = (uint8_t)0x01, // + DDIC_Control_OFF = (uint8_t)0x00 //Ϩ +} DDIC_Control_Status; + + +extern uint8_t xdata LCDRAM[30]; + +void DDIC_DeInit(void); +void DDIC_Init(DDIC_DutyCycle_TypeDef + DDIC_DutyCylce, uint8_t P0OutputPin, + uint8_t P1OutputPin, uint8_t P2OutputPin, + uint8_t P3OutputPin); +void DDIC_LEDConfig(void); +void DDIC_LCDConfig(uint8_t LCDVoltage, + DDIC_ResSel_Typedef DDIC_ResSel, + DDIC_BiasVoltage_Typedef DDIC_BiasVoltage); +void DDIC_Cmd(FunctionalState NewState); +void DDIC_OutputPinOfDutycycleD4( + DDIC_OutputPin_TypeDef DDIC_OutputPin); +void DDIC_DMOD_Selcet(DDIC_DMOD_TypeDef + DDIC_DMOD); +void DDIC_Control(DDIC_Control_SEG_TypeDef DDIC_Seg, + uint8_t DDIC_Com, + DDIC_Control_Status DDIC_Contr); +#endif + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax)|| defined (SC92F74Ax)|| defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92F848x) || defined (SC92F748x) +#if defined (SC92F730x) +typedef enum +{ + DDIC_PIN_00 = ((uint8_t)0x01), //P0x0LCD + DDIC_PIN_01 = ((uint8_t)0x02), //P0x1LCD + DDIC_PIN_02 = ((uint8_t)0x04), //P0x2LCD + DDIC_PIN_03 = ((uint8_t)0x08), //P0x3LCD +} DDIC_Pin_TypeDef; +#else +typedef enum +{ + DDIC_PIN_00 = ((uint8_t)0x01), //P0x0LCD + DDIC_PIN_01 = ((uint8_t)0x02), //P0x1LCD + DDIC_PIN_02 = ((uint8_t)0x04), //P0x2LCD + DDIC_PIN_03 = ((uint8_t)0x08), //P0x3LCD + DDIC_PIN_04 = ((uint8_t)0x10), //P0x4LCD +} DDIC_Pin_TypeDef; +#endif + +#if defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + DDIC_ResSel_0K = (uint8_t)0X00, //رڲѹ + DDIC_ResSel_25K = (uint8_t)0X04, //趨ڲѹΪ12.5k + DDIC_ResSel_50K = (uint8_t)0X08, //趨ڲѹΪ37.5k + DDIC_ResSel_100K = (uint8_t)0X0c //趨ڲѹΪ87.5k +} DDIC_ResSel_Typedef; +#else +typedef enum +{ + DDIC_ResSel_0K = (uint8_t)0X00, //رڲѹ + DDIC_ResSel_12_5K = (uint8_t)0X04, //趨ڲѹΪ12.5k + DDIC_ResSel_37_5K = (uint8_t)0X08, //趨ڲѹΪ37.5k + DDIC_ResSel_87_5K = (uint8_t)0X0c //趨ڲѹΪ87.5k +} DDIC_ResSel_Typedef; + +#endif + +void DDIC_DeInit(); +void DDIC_Init(uint8_t P0OutputPin); +void DDIC_LCDConfig(DDIC_ResSel_Typedef + DDIC_ResSel); +void DDIC_Config_Init(uint8_t P0OutputPin, + DDIC_ResSel_Typedef DDIC_ResSel); +#endif + +#endif + +/******************* (C) COPYRIGHT 2022 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_gpio.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_gpio.h new file mode 100644 index 0000000..c5d7396 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_gpio.h @@ -0,0 +1,94 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_gpio.h +// : +// ģ鹦 : GPIO̼⺯ͷļ +// ֲб: +// : 2021/08/20 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#ifndef _sc92f_GPIO_H_ +#define _sc92f_GPIO_H_ + +#include "sc92f.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined(SC92FWxx)|| defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + + GPIO0 = (uint8_t)0x00, //P0 + GPIO1 = (uint8_t)0x01, //P1 + GPIO2 = (uint8_t)0x02, //P2 + GPIO3 = (uint8_t)0x03, //P3 + GPIO4 = (uint8_t)0x04, //P4 + GPIO5 = (uint8_t)0x05 //P5 +}GPIO_TypeDef; +#elif defined (SC92F730x ) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F8003) || defined (SC92F740x) || defined (SC92F827X) || defined (SC92F837X) || defined (SC92F7003) +typedef enum +{ + GPIO0 = (uint8_t)0x00, //P0 + GPIO1 = (uint8_t)0x01, //P1 + GPIO2 = (uint8_t)0x02, //P2 +}GPIO_TypeDef; +#else +typedef enum +{ + GPIO0 = (uint8_t)0x00, //P0 + GPIO1 = (uint8_t)0x01, //P1 + GPIO2 = (uint8_t)0x02, //P2 + GPIO5 = (uint8_t)0x05 //P5 +}GPIO_TypeDef; +#endif + + +typedef enum +{ + GPIO_MODE_IN_HI = (uint8_t)0x00, //ģʽ + GPIO_MODE_IN_PU = (uint8_t)0x01, //ģʽ + GPIO_MODE_OUT_PP = (uint8_t)0x02 //ǿģʽ +} GPIO_Mode_TypeDef; + +typedef enum +{ + GPIO_PIN_0 = ((uint8_t)0x01), //IOܽPx0 + GPIO_PIN_1 = ((uint8_t)0x02), //IOܽPx1 + GPIO_PIN_2 = ((uint8_t)0x04), //IOܽPx2 + GPIO_PIN_3 = ((uint8_t)0x08), //IOܽPx3 + GPIO_PIN_4 = ((uint8_t)0x10), //IOܽPx4 + GPIO_PIN_5 = ((uint8_t)0x20), //IOܽPx5 + GPIO_PIN_6 = ((uint8_t)0x40), //IOܽPx6 + GPIO_PIN_7 = ((uint8_t)0x80), //IOܽPx7 + GPIO_PIN_LNIB = ((uint8_t)0x0F), //IOܽPx0~3 + GPIO_PIN_HNIB = ((uint8_t)0xF0), //IOܽPx4~7 + GPIO_PIN_ALL = ((uint8_t)0xFF) //IOܽPx0~7 +} GPIO_Pin_TypeDef; + +typedef enum +{ + IOH_Grade_0 = ((uint8_t)0x00), //IOHȼ0 + IOH_Grade_1 = ((uint8_t)0x01), //IOHȼ1 + IOH_Grade_2 = ((uint8_t)0x02), //IOHȼ2 + IOH_Grade_3 = ((uint8_t)0x03), //IOHȼ3 +} GPIO_IOH_Grade_TypeDef; + +void GPIO_IOH_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef PortPins,GPIO_IOH_Grade_TypeDef GPIO_IOH_Grade); + +void GPIO_DeInit(void); +void GPIO_Init(GPIO_TypeDef GPIOx, + uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode); +void GPIO_Write(GPIO_TypeDef GPIOx, + uint8_t PortVal); +void GPIO_WriteHigh(GPIO_TypeDef GPIOx, + uint8_t PortPins); +void GPIO_WriteLow(GPIO_TypeDef GPIOx, + uint8_t PortPins); +uint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx); +BitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, + uint8_t PortPins); + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_iap.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_iap.h new file mode 100644 index 0000000..9f8ccf9 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_iap.h @@ -0,0 +1,82 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_iap.h +// : ԪӦŶ +// ģ鹦: IAP̼⺯ͷļ +// : 2022323 +// 汾: V1.100005 +// ˵: ļԪ92F/93F/92LϵеƬ +//************************************************************* + +#ifndef _sc92f_IAP_H_ +#define _sc92f_IAP_H_ + +#include "sc92f.h" +#include "intrins.h" + +typedef enum +{ + IAP_MEMTYPE_ROM = (uint8_t)0x00, //IAPΪROM + IAP_MEMTYPE_UID = (uint8_t)0x01, //IAPΪUIDֻ!!! + IAP_MEMTYPE_EEPROM = (uint8_t)0x02 //IAPΪEEPROM +} IAP_MemType_TypeDef; + + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ +|| defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) +typedef enum +{ + IAP_HOLDTIME_1500US = (uint8_t)0x08, //趨CPU Hold TimeΪ1.5MS + IAP_HOLDTIME_3000US = (uint8_t)0x04, //趨CPU Hold TimeΪ3MS + IAP_HOLDTIME_6000US = (uint8_t)0x00 //趨CPU Hold TimeΪ6MS +}IAP_HoldTime_TypeDef; +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax)|| defined (SC92F742x) || defined (SC92F730x) || defined (SC92F827X) || defined (SC92F837X) \ + || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) || defined (SC92F7490) || defined (SC93F833x) || defined (SC93F843x)\ + || defined (SC93F733x) || defined (SC93F743x) +typedef enum +{ + IAP_HOLDTIME_4MS = (uint8_t)0x00, //趨CPU Hold TimeΪ4MS + IAP_HOLDTIME_2MS = (uint8_t)0x04, //趨CPU Hold TimeΪ2MS + IAP_HOLDTIME_1MS = (uint8_t)0x08 //趨CPU Hold TimeΪ1MS +}IAP_HoldTime_TypeDef; +#elif defined (SC92FWxx) +typedef enum +{ + IAP_HOLDTIME_3000US = (uint8_t)0x00, //趨CPU Hold TimeΪ4MS + IAP_HOLDTIME_1500US = (uint8_t)0x04, //趨CPU Hold TimeΪ2MS + IAP_HOLDTIME_1000US = (uint8_t)0x08 //趨CPU Hold TimeΪ1MS +}IAP_HoldTime_TypeDef; +#elif defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + IAP_HOLDTIME_Null = (uint8_t)0x00 //FlashҪHold Time +}IAP_HoldTime_TypeDef; + +typedef enum +{ + IAP_BTLDType_APPROM = (uint8_t)0x00, //MCUλAPROMλ + IAP_BTLDType_LDROM = (uint8_t)0x01, //MCUλLDROMλ +} IAP_BTLDType_TypeDef; + + +#endif + + +void IAP_DeInit(void); +void IAP_SetHoldTime(IAP_HoldTime_TypeDef IAP_HoldTime); +void IAP_ProgramByte(uint16_t Address, + uint8_t Data, IAP_MemType_TypeDef IAP_MemType, + uint8_t WriteTimeLimit); +uint8_t IAP_ReadByte(uint16_t Address, + IAP_MemType_TypeDef IAP_MemType); + +#if defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +void IAP_SectorErase(IAP_MemType_TypeDef IAP_MemType, uint32_t IAP_SectorEraseAddress, + uint8_t WriteTimeLimit); +void IAP_BootLoaderControl(IAP_BTLDType_TypeDef IAP_BTLDType); +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_int.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_int.h new file mode 100644 index 0000000..ccc3d04 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_int.h @@ -0,0 +1,220 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_INT.h +// : +// ģ鹦 : INT̼⺯ͷļ +// ֲб: +// : 2022/01/05 +// 汾 : V1.10003 +// ˵ : +//************************************************************* + +#ifndef _sc92f_INT_H_ +#define _sc92f_INT_H_ + +#include "sc92f.h" + +typedef enum +{ + INT_TRIGGER_RISE_ONLY = (uint8_t)0x01, //ⲿжϴʽΪ + INT_TRIGGER_FALL_ONLY = (uint8_t)0x02, //ⲿжϴʽΪ½ + INT_TRIGGER_RISE_FALL = (uint8_t)0x03, //ⲿжϴʽΪ½ + INT_TRIGGER_DISABLE = (uint8_t)0x04 //رⲿжϴ +} INT_TriggerMode_Typedef; + +typedef enum +{ + INT0 = (uint8_t)0x00, //ⲿж0 + INT1 = (uint8_t)0x01, //ⲿж1 + INT2 = (uint8_t)0x02 //ⲿж2 +} INTx_Typedef; + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) +typedef enum +{ + INT01 = (uint8_t)0x02, //P11ΪINT0 + INT02 = (uint8_t)0x04, //P12ΪINT0 + INT03 = (uint8_t)0x08 //P13ΪINT0 + +} INT0x_Typedef; + +#elif defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ +|| defined (SC92FWxx) || defined (SC92F859x) || defined (SC92F759x) +typedef enum +{ + INT04 = (uint8_t)0x10, //P04ΪⲿжϽ + INT05 = (uint8_t)0x20, //P05ΪⲿжϽ + INT06 = (uint8_t)0x40, //P06ΪⲿжϽ + INT07 = (uint8_t)0x80 //P07ΪⲿжϽ +} INT0x_Typedef; + +#elif defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + INT00 = (uint8_t)0x01, //P00ΪINT0 + INT01 = (uint8_t)0x02 //P01ΪINT0 +} INT0x_Typedef; + +#elif defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) +typedef enum +{ + INT00 = (uint8_t)0x01, //P10ΪINT0 + INT01 = (uint8_t)0x02, //P11ΪINT0 + INT02 = (uint8_t)0x04, //P12ΪINT0 + INT03 = (uint8_t)0x08 //P13ΪINT0 +} INT0x_Typedef; + +#elif defined (SC92F827X) || defined (SC92F837X) || defined (SC92F7490) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + INT01 = (uint8_t)0x02, //P11ΪINT0 + INT02 = (uint8_t)0x04, //P12ΪINT0 + INT03 = (uint8_t)0x08 //P13ΪINT0 +} INT0x_Typedef; + +#endif + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ +|| defined (SC92FWxx) || defined (SC92F859x) || defined (SC92F759x) +typedef enum +{ + INT10 = (uint8_t)0x01, //P40ΪⲿжϽ + INT11 = (uint8_t)0x02, //P41ΪⲿжϽ + INT12 = (uint8_t)0x04, //P42ΪⲿжϽ + INT13 = (uint8_t)0x08, //P43ΪⲿжϽ + INT14 = (uint8_t)0x10, //P14ΪⲿжϽ + INT15 = (uint8_t)0x20, //P15ΪⲿжϽ + INT16 = (uint8_t)0x40, //P16ΪⲿжϽ + INT17 = (uint8_t)0x80 //P17ΪⲿжϽ +} INT1x_Typedef; + +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + INT10 = (uint8_t)0x01, //P14ΪINT1 + INT11 = (uint8_t)0x02, //P15ΪINT1 + INT12 = (uint8_t)0x04, //P16ΪINT1 + INT13 = (uint8_t)0x08 //P17ΪINT1 +} INT1x_Typedef; + +#elif defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + INT10 = (uint8_t)0x01, //P10ΪINT1 + INT11 = (uint8_t)0x02, //P11ΪINT1 + INT12 = (uint8_t)0x04, //P12ΪINT1 + INT13 = (uint8_t)0x08, //P13ΪINT1 + INT14 = (uint8_t)0x10, //P14ΪINT1 + INT15 = (uint8_t)0x20, //P15ΪINT1 + INT16 = (uint8_t)0x40 //P16ΪINT1 +} INT1x_Typedef; + +#elif defined (SC92F742x) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + INT10 = (uint8_t)0x01, //P14ΪINT1 + INT11 = (uint8_t)0x02, //P15ΪINT1 + INT12 = (uint8_t)0x04, //P16ΪINT1 + INT13 = (uint8_t)0x08 //P17ΪINT1 +} INT1x_Typedef; + +#elif defined (SC92F730x) || defined (SC92F827X) || defined (SC92F837X) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F7490) +typedef enum +{ + INT_Null = (uint8_t)0x00, //ûINT1 +} INT1x_Typedef; + +#endif + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ +|| defined (SC92FWxx) || defined (SC92F859x) || defined (SC92F759x) +typedef enum +{ + INT20 = (uint8_t)0x01, //P20ΪⲿжϽ + INT21 = (uint8_t)0x02, //P21ΪⲿжϽ + INT22 = (uint8_t)0x04, //P22ΪⲿжϽ + INT23 = (uint8_t)0x08 //P23ΪⲿжϽ +} INT2x_Typedef; + +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + INT20 = (uint8_t)0x01, //P04ΪINT2 + INT21 = (uint8_t)0x02, //P05ΪINT2 + INT22 = (uint8_t)0x04, //P06ΪINT2 + INT23 = (uint8_t)0x08, //P07ΪINT2 + INT24 = (uint8_t)0x10, //P20ΪINT2 + INT25 = (uint8_t)0x20 //P21ΪINT2 +} INT2x_Typedef; + +#elif defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + INT21 = (uint8_t)0x02, //P21ΪINT2 + INT22 = (uint8_t)0x04, //P22ΪINT2 + INT23 = (uint8_t)0x08, //P23ΪINT2 + INT24 = (uint8_t)0x10, //P24ΪINT2 + INT25 = (uint8_t)0x20, //P25ΪINT2 + INT26 = (uint8_t)0x40, //P26ΪINT2 + INT27 = (uint8_t)0x80 //P27ΪINT2 +} INT2x_Typedef; + +#elif defined (SC92F742x) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + INT20 = (uint8_t)0x01, //P04ΪINT2 + INT21 = (uint8_t)0x02, //P05ΪINT2 + INT22 = (uint8_t)0x04, //P06ΪINT2 + INT23 = (uint8_t)0x08, //P07ΪINT2 + INT24 = (uint8_t)0x10, //P20ΪINT2 + INT25 = (uint8_t)0x20 //P21ΪINT2 +} INT2x_Typedef; + +#elif defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) +typedef enum +{ + INT24 = (uint8_t)0x10, //P20ΪⲿжϽ + INT25 = (uint8_t)0x20 //P21ΪⲿжϽ +} INT2x_Typedef; + +#elif defined (SC92F837X) +typedef enum +{ + INT20 = (uint8_t)0x01, //P04ΪINT2 + INT21 = (uint8_t)0x02, //P05ΪINT2 + INT24 = (uint8_t)0x10, //P20ΪINT2 + INT25 = (uint8_t)0x20 //P21ΪINT2 +} INT2x_Typedef; + +#elif defined (SC92F7490) || defined (SC92F827X) +typedef enum +{ + INT21 = (uint8_t)0x02, //P05ΪINT2 + INT24 = (uint8_t)0x10, //P20ΪINT2 + INT25 = (uint8_t)0x20 //P21ΪINT2 +} INT2x_Typedef; + +#endif + + +void INT_DeInit(INTx_Typedef INTx); +void INT0_SetTriggerMode(uint8_t INT0x, + INT_TriggerMode_Typedef TriggerMode); +void INT0_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) || defined (SC92F735X) +void INT1_SetTriggerMode(uint8_t INT1x, + INT_TriggerMode_Typedef TriggerMode); +void INT1_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#endif +void INT2_SetTriggerMode(uint8_t INT2x, + INT_TriggerMode_Typedef TriggerMode); +void INT2_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_lpd.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_lpd.h new file mode 100644 index 0000000..fdc7da1 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_lpd.h @@ -0,0 +1,59 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92F_LPD.h +// : ԪӦŶ +// ģ鹦: LPD̼⺯ͷļ +// : 2022323 +// 汾: V1.100001 +// ˵: ļSC92LϵоƬ +//************************************************************* + +#ifndef _sc92f_LPD_H_ +#define _sc92f_LPD_H_ + +#include "sc92f.h" + +typedef enum +{ + LPD_VTRIP_1_85V = (uint8_t)0x00, //LPD޵ѹֵΪ1.85V + LPD_VTRIP_2_05V = (uint8_t)0x01, //LPD޵ѹֵΪ2.05V + LPD_VTRIP_2_25V = (uint8_t)0x02, //LPD޵ѹֵΪ2.25V + LPD_VTRIP_2_45V = (uint8_t)0x03, //LPD޵ѹֵΪ2.45V + LPD_VTRIP_2_85V = (uint8_t)0x04, //LPD޵ѹֵΪ2.85V + LPD_VTRIP_3_45V = (uint8_t)0x05, //LPD޵ѹֵΪ3.45V + LPD_VTRIP_3_85V = (uint8_t)0x06, //LPD޵ѹֵΪ3.85V + LPD_VTRIP_4_45V = (uint8_t)0x07, //LPD޵ѹֵΪ4.45V +} LPD_Vtrip_TypeDef; + +typedef enum +{ + LPD_FLAG_LPDIF = (uint8_t)0x40, //LPDж־ + LPD_FLAG_LPDOF = (uint8_t)0x80, //LPD״̬־λ +} LPD_Flag_TypeDef; + +/*******************************꺯*******************************/ +/***************************************************** +*:FlagStatus LPD_GetFlagStatus(LPD_Flag_Typedef LPD_Flag) +*:LPDжϱ־״̬ +*ڲ: +LPD_GetFlagStatus:LPD_Flag:жϱ־λѡ +*ڲ: +FlagStatus:LPDжϱ־λ״̬ +*****************************************************/ +#define LPD_GetFlagStatus(LPD_Flag) ((READ_BIT(SCON,LPD_Flag)) ? (SET):(RESET)) + +/***************************************************** +*:void LPD_ClearFlag(LPD_Flag_Typedef LPD_Flag) +*:LPDжϱ־״̬ +*ڲ: +LPD_Flag_Typedef;LPD_Flag:жϱ־λѡ +*ڲ:void +*****************************************************/ +#define LPD_ClearFlag() CLEAR_BIT(SCON,LPD_Flag) + +void LPD_DeInit(void); +void LPD_VtripConfig(LPD_Vtrip_TypeDef LPD_Vtrip); +void LPD_ITConfig(FunctionalState NewState, PriorityStatus Priority); +void LPD_Cmd(FunctionalState NewState); + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_mdu.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_mdu.h new file mode 100644 index 0000000..250de4d --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_mdu.h @@ -0,0 +1,48 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_mdu.h +// : +// ģ鹦 : MDU̼⺯ͷļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#ifndef _sc92f_MDU_H_ +#define _sc92f_MDU_H_ + +#include "sc92f.h" + +#if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F848x) || defined (SC92F748x)\ + || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +typedef struct +{ + uint8_t MDU_EXA3Reg; //EXA3Ĵ + uint8_t MDU_EXA2Reg; //EXA2Ĵ + uint8_t MDU_EXA1Reg; //EXA1Ĵ + uint8_t MDU_EXA0Reg; //EXA0Ĵ +} MDU_EXAxReg_Typedef; + +typedef union +{ + MDU_EXAxReg_Typedef MDU_EXAxReg; + uint32_t MDU_Temp; +} MDU_Temp_Union; + +void MDU_DeInit(void); +void MDU_MultiplicationConfig(uint16_t + Multiplicand, uint16_t Multiplier); +void MDU_DivisionConfig(uint32_t Dividend, + uint16_t Divisor); +void MDU_StartOperation(void); +uint32_t MDU_GetProduct(void); +uint32_t MDU_GetQuotient(void); +uint16_t MDU_GetRemainder(void); + +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_option.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_option.h new file mode 100644 index 0000000..d7bc40b --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_option.h @@ -0,0 +1,141 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_option.h +// : +// ģ鹦 : Customer OptionĴͷļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.0007 +// ˵ : +//************************************************************* + +#ifndef _sc92f_OPTION_H_ +#define _sc92f_OPTION_H_ + +#include "sc92f.h" + +#if defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + SYSCLK_PRESSEL_FOSC_D1 = (uint8_t)0x00, //ԤƵ Fsys = Fosc/1 + SYSCLK_PRESSEL_FOSC_D2 = (uint8_t)0x10, //ԤƵ Fsys = Fosc/2 + SYSCLK_PRESSEL_FOSC_D4 = (uint8_t)0x20, //ԤƵ Fsys = Fosc/4 + SYSCLK_PRESSEL_FOSC_D8 = (uint8_t)0x30 //ԤƵ Fsys = Fosc/8 +} SYSCLK_PresSel_TypeDef; +#else +typedef enum +{ + SYSCLK_PRESSEL_FOSC_D1 = (uint8_t)0x00, //ԤƵ Fsys = Fosc/1 + SYSCLK_PRESSEL_FOSC_D2 = (uint8_t)0x10, //ԤƵ Fsys = Fosc/2 + SYSCLK_PRESSEL_FOSC_D4 = (uint8_t)0x20, //ԤƵ Fsys = Fosc/4 + SYSCLK_PRESSEL_FOSC_D12 = (uint8_t)0x30 //ԤƵ Fsys = Fosc/12 +} SYSCLK_PresSel_TypeDef; +#endif + +#if defined (SC92F859x) || defined (SC92F759x)||defined (SC92F848x) || defined (SC92F748x) +typedef enum +{ + LVR_INVALID = (uint8_t)0x04, //LVRЧ + LVR_1_9V = (uint8_t)0x00, //LVR 1.9Vλ + LVR_2_9V = (uint8_t)0x01, //LVR 2.9Vλ + LVR_3_7V = (uint8_t)0x02, //LVR 3.7Vλ + LVR_4_3V = (uint8_t)0x03 //LVR 4.3Vλ +} LVR_Config_TypeDef; +#elif defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + LVR_INVALID = (uint8_t)0x04, //LVRЧ + LVR_1_7V = (uint8_t)0x00, //LVR 1.7Vλ + LVR_2_7V = (uint8_t)0x01, //LVR 2.7Vλ + LVR_3_7V = (uint8_t)0x02, //LVR 3.7Vλ + LVR_4_3V = (uint8_t)0x03 //LVR 4.3Vλ +} LVR_Config_TypeDef; +#else +typedef enum +{ + LVR_INVALID = (uint8_t)0x04, //LVRЧ + LVR_2_3V = (uint8_t)0x00, //LVR 2.3Vλ + LVR_2_9V = (uint8_t)0x01, //LVR 2.9Vλ + LVR_3_7V = (uint8_t)0x02, //LVR 3.7Vλ + LVR_4_3V = (uint8_t)0x03 //LVR 4.3Vλ +} LVR_Config_TypeDef; +#endif + +#if defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + IAP_OPERATERANGE_ONLY_EEPROM = (uint8_t)0x00, //ֻEEPROMIAP + IAP_OPERATERANGE__LAST_1K_CODEREGION = (uint8_t)0x04, //ROM1kEEPROMIAP + IAP_OPERATERANGE__LAST_2K_CODEREGION = (uint8_t)0x08, //ROM2kEEPROMIAP + IAP_OPERATERANGE__ALL_CODEREGION = (uint8_t)0x0c //ROMEEPROMIAP +} IAP_OperateRange_TypeDef; +#else +typedef enum +{ + IAP_OPERATERANGE_ONLY_EEPROM = (uint8_t)0x00, //ֻEEPROMIAP + IAP_OPERATERANGE__LAST_0_5K_CODEREGION = (uint8_t)0x04, //ROM0.5kEEPROMIAP + IAP_OPERATERANGE__LAST_1K_CODEREGION = (uint8_t)0x08, //ROM1kEEPROMIAP + IAP_OPERATERANGE__ALL_CODEREGION = (uint8_t)0x0c //ROMEEPROMIAP +} IAP_OperateRange_TypeDef; +#endif + + +#if defined (SC92F859x) || defined (SC92F759x) || defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +typedef enum +{ + ADC_VREF_VDD = 0x00, //ѡVDDADCοѹ + ADC_VREF_1_024V = 0x40, //ѡڲ1.024VADCοѹ + ADC_VREF_2_4V = 0x80, //ѡڲ2.4VADCοѹ + ADC_VREF_2_048V = 0xC0, //ѡڲ2.048VADCοѹ +} ADC_Vref_TypeDef; +#else + +typedef enum +{ + ADC_VREF_VDD = 0x00, //ѡVDDADCοѹ + ADC_VREF_2_4V = 0x80, //ѡڲ2.4VADCοѹ +} ADC_Vref_TypeDef; +#endif + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax)\ + || defined (SC92F73Ax) || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F740x)\ + || defined (SC92F848x) || defined (SC92F748x) || defined (SC92F8003) || defined (SC92F7003) +typedef enum +{ + XTIPLL_HIGHER_THAN_12M = (uint8_t)0x40, //ӾƵʴڵ12M + XTIPLL_UNDER_12M = (uint8_t)0x00 //ӾƵС12M +} XTIPLL_Range_TypeDef; +#endif + +void OPTION_WDT_Cmd(FunctionalState NewState); + +void OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef + SYSCLK_PresSel); +#if !defined(SC92F848x) && !defined(SC92F748x) && !defined(SC92F859x) && !defined (SC92F759x) && !defined(SC92L853x) && !defined (SC92L753x) +void OPTION_RST_PIN_Cmd(FunctionalState NewState); +#endif +void OPTION_LVR_Init(LVR_Config_TypeDef + LVR_Config); +void OPTION_ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref); +void OPTION_IAP_SetOperateRange( + IAP_OperateRange_TypeDef IAP_OperateRange); + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax)\ + || defined (SC92F73Ax) || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F740x)\ + || defined (SC92F8003) || defined (SC92F7003) +void OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef + XTIPLL_Range); +#endif + +#if !defined(SC92F848x) && !defined(SC92F748x) +void OPTION_XTIPLL_Cmd(FunctionalState NewState); +#endif + +#if defined (SC92F742x)||defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) \ + ||defined (SC92F74Ax_2)||defined (SC92F84Ax_2)||defined (SC92F844xB)||defined (SC92F744xB) \ + ||defined (SC92F859x) || defined (SC92F759x) ||defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +void OPTION_JTG_Cmd(FunctionalState NewState); +#endif + + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_pwm.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_pwm.h new file mode 100644 index 0000000..2309a85 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_pwm.h @@ -0,0 +1,406 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_pwm.h +// : +// ģ鹦 : PWM̼⺯ͷļ +// ֲб: +// : 202276 +// 汾 : V1.10005 +// ˵ : +//************************************************************* + +#ifndef _sc92f_PWM_H_ +#define _sc92f_PWM_H_ + +#include "sc92f.h" +#if !defined (SC92F7490) +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F859x) || defined(SC92F759x) +typedef enum +{ + PWM_PRESSEL_FHRC_D1 = (uint8_t)0x00, //PWMԤƵΪFhrc/1 + PWM_PRESSEL_FHRC_D2 = (uint8_t)0x10, //PWMԤƵΪFhrc/2 + PWM_PRESSEL_FHRC_D4 = (uint8_t)0x20, //PWMԤƵΪFhrc/4 + PWM_PRESSEL_FHRC_D8 = (uint8_t)0x30 //PWMԤƵΪFhrc/8 +} PWM_PresSel_TypeDef; + +typedef enum +{ + PWM40 = (uint8_t)0x01, //PWMͨѡ:PWM40 + PWM41 = (uint8_t)0x02, //PWMͨѡ:PWM41 + PWM42 = (uint8_t)0x04, //PWMͨѡ:PWM42 + PWM43 = (uint8_t)0x08, //PWMͨѡ:PWM43 + PWM50 = (uint8_t)0x10, //PWMͨѡ:PWM50 + PWM51 = (uint8_t)0x20, //PWMͨѡ:PWM51 + PWM52 = (uint8_t)0x40, //PWMͨѡ:PWM52 + PWM53 = (uint8_t)0x80 //PWMͨѡ:PWM53 +} PWM_OutputPin_TypeDef; +#elif defined (SC92F742x) || defined (SC92F730x) || defined (SC92F827X) || defined (SC92F837X) || defined (SC92F725X) || defined(SC92F735X) +typedef enum +{ + PWM_PRESSEL_FSYS_D1 = (uint8_t)0x00, //PWMԤƵΪFsys/1 + PWM_PRESSEL_FSYS_D2 = (uint8_t)0x01, //PWMԤƵΪFsys/2 + PWM_PRESSEL_FSYS_D4 = (uint8_t)0x02, //PWMԤƵΪFsys/4 + PWM_PRESSEL_FSYS_D8 = (uint8_t)0x03, //PWMԤƵΪFsys/8 + PWM_PRESSEL_FSYS_D32 = (uint8_t)0x04, //PWMԤƵΪFsys/32 + PWM_PRESSEL_FSYS_D64 = (uint8_t)0x05, //PWMԤƵΪFsys/64 + PWM_PRESSEL_FSYS_D128 = (uint8_t)0x06, //PWMԤƵΪFsys/128 + PWM_PRESSEL_FSYS_D256 = (uint8_t)0x07 //PWMԤƵΪFsys/256 +} PWM_PresSel_TypeDef; + +#if defined (SC92F827X) +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 +} PWM_OutputPin_TypeDef; +#elif defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 +} PWM_OutputPin_TypeDef; +#elif defined (SC92F837X) +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM3 = (uint8_t)0x08, //PWMͨѡ:PWM3 +} PWM_OutputPin_TypeDef; +#elif defined (SC92F730x) +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM4 = (uint8_t)0x10, //PWMͨѡ:PWM4 + PWM5 = (uint8_t)0x20 //PWMͨѡ:PWM5 +} PWM_OutputPin_TypeDef; +#else +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM3 = (uint8_t)0x08, //PWMͨѡ:PWM3 + PWM4 = (uint8_t)0x10, //PWMͨѡ:PWM4 + PWM5 = (uint8_t)0x20 //PWMͨѡ:PWM5 +} PWM_OutputPin_TypeDef; +#endif + +#elif defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) +typedef enum +{ + PWM_PRESSEL_FOSC_D1 = (uint8_t)0x00, //PWMԤƵΪFosc/1 + PWM_PRESSEL_FOSC_D2 = (uint8_t)0x01, //PWMԤƵΪFosc/2 + PWM_PRESSEL_FOSC_D8 = (uint8_t)0x02, //PWMԤƵΪFosc/8 + PWM_PRESSEL_FOSC_D32 = (uint8_t)0x03 //PWMԤƵΪFosc/32 +} PWM_PresSel_TypeDef; +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM3 = (uint8_t)0x08, //PWMͨѡ:PWM3 + PWM4 = (uint8_t)0x10, //PWMͨѡ:PWM4 + PWM5 = (uint8_t)0x20, //PWMͨѡ:PWM5 +} PWM_OutputPin_TypeDef; + +typedef enum +{ + PWM0PWM3 = (uint8_t)0x00, //PWMģʽͨѡ:PWM0PWM3 + PWM1PWM4 = (uint8_t)0x01, //PWMģʽͨѡ:PWM1PWM4 + PWM2PWM5 = (uint8_t)0x02 //PWMģʽͨѡ:PWM2PWM5 +} PWM_ComplementaryOutputPin_TypeDef; +#elif defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + PWM_PRESSEL_FOSC_D1 = (uint8_t)0x00, //PWMԤƵΪFosc/1 + PWM_PRESSEL_FOSC_D2 = (uint8_t)0x01, //PWMԤƵΪFosc/2 + PWM_PRESSEL_FOSC_D8 = (uint8_t)0x02, //PWMԤƵΪFosc/8 + PWM_PRESSEL_FOSC_D32 = (uint8_t)0x03 //PWMԤƵΪFosc/32 +} PWM_PresSel_TypeDef; +typedef enum +{ + PWM2_OutputPin_P26 = ((uint8_t)0x00), //PWM2ѡP26 + PWM2_OutputPin_P14 = ((uint8_t)0x04) //PWM2ѡP14 +} PWM2_OutputPin_TypeDef; + +typedef enum +{ + PWM5_OutputPin_P12 = ((uint8_t)0x00), //PWM5ѡP12 + PWM5_OutputPin_P21 = ((uint8_t)0x08) //PWM5ѡP21 +} PWM5_OutputPin_TypeDef; + +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 + PWM3 = (uint8_t)0x08, //PWMͨѡ:PWM3 + PWM4 = (uint8_t)0x10, //PWMͨѡ:PWM4 + PWM5 = (uint8_t)0x20, //PWMͨѡ:PWM5 + PWM6 = (uint8_t)0x40, //PWMͨѡ:PWM6 +} PWM_OutputPin_TypeDef; + +typedef enum +{ + PWM0PWM3 = (uint8_t)0x00, //PWMģʽͨѡ:PWM0PWM3 + PWM1PWM4 = (uint8_t)0x01, //PWMģʽͨѡ:PWM1PWM4 + PWM2PWM5 = (uint8_t)0x02 //PWMģʽͨѡ:PWM2PWM5 +} PWM_ComplementaryOutputPin_TypeDef; +#elif defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + PWM_PRESSEL_FSYS_D1 = (uint8_t)0x00, //PWMԤƵΪFsys/1 + PWM_PRESSEL_FSYS_D2 = (uint8_t)0x01, //PWMԤƵΪFsys/2 + PWM_PRESSEL_FSYS_D4 = (uint8_t)0x02, //PWMԤƵΪFsys/4 + PWM_PRESSEL_FSYS_D8 = (uint8_t)0x03, //PWMԤƵΪFsys/8 + PWM_PRESSEL_FSYS_D32 = (uint8_t)0x04, //PWMԤƵΪFsys/32 + PWM_PRESSEL_FSYS_D64 = (uint8_t)0x05, //PWMԤƵΪFsys/64 + PWM_PRESSEL_FSYS_D128 = (uint8_t)0x06, //PWMԤƵΪFsys/128 + PWM_PRESSEL_FSYS_D256 = (uint8_t)0x07 //PWMԤƵΪFsys/256 +} PWM_PresSel_TypeDef; + +typedef enum +{ + PWM0 = (uint8_t)0x01, //PWMͨѡ:PWM0 + PWM1 = (uint8_t)0x02, //PWMͨѡ:PWM1 + PWM2 = (uint8_t)0x04, //PWMͨѡ:PWM2 +} PWM_OutputPin_TypeDef; + +typedef enum +{ + PWM0_OutputPin_P00 = ((uint8_t)0x00), //PWM2ѡP26 + PWM0_OutputPin_P25 = ((uint8_t)0x01) //PWM2ѡP14 +} PWM0_OutputPin_TypeDef; + +typedef enum +{ + PWM1_OutputPin_P01 = ((uint8_t)0x00), //PWM5ѡP12 + PWM1_OutputPin_P26 = ((uint8_t)0x02) //PWM5ѡP21 +} PWM1_OutputPin_TypeDef; + +typedef enum +{ + PWM2_OutputPin_P02 = ((uint8_t)0x00), //PWM2ѡP26 + PWM2_OutputPin_P27 = ((uint8_t)0x04) //PWM2ѡP14 +} PWM2_OutputPin_TypeDef; + +//duty΢ƣĸPWM2Ϊһѭ: +typedef enum +{ + PWM_DutyMode0 = ((uint8_t)0x00), //00:ĸPWM2dutyΪPDT2趨ֵ(DDDD) + PWM_DutyMode1 = ((uint8_t)0x01), //01:һPWM2dutyΪPDT2趨ֵ1PWM2dutyΪPDT2趨ֵ(D+1DDD) + PWM_DutyMode2 = ((uint8_t)0x02), //10:һ͵ڶPWM2dutyΪPDT2趨ֵ1PWM2dutyΪPDT2趨ֵ(D+1D+1DD) + PWM_DutyMode3 = ((uint8_t)0x03), //11:һڶ͵PWM2dutyΪPDT2趨ֵ1ĸPWM2DutyΪPDT2趨ֵ (D+1D+1D+1D) +} PWM_DutyMode_TypeDef; +#elif defined (SC92FWxx) +typedef enum +{ + PWM0_PRESSEL_FHRC_D1 = (uint8_t)0x00, //PWM0ԤƵΪFhrc/1 + PWM0_PRESSEL_FHRC_D2 = (uint8_t)0x10, //PWM0ԤƵΪFhrc/2 + PWM0_PRESSEL_FHRC_D4 = (uint8_t)0x20, //PWM0ԤƵΪFhrc/4 + PWM0_PRESSEL_FHRC_D8 = (uint8_t)0x30, //PWM0ԤƵΪFhrc/8 + PWM1_PRESSEL_FHRC_D1 = (uint8_t)0x01, //PWM1ԤƵΪFhrc/1 + PWM1_PRESSEL_FHRC_D2 = (uint8_t)0x11, //PWM1ԤƵΪFhrc/2 + PWM1_PRESSEL_FHRC_D4 = (uint8_t)0x21, //PWM1ԤƵΪFhrc/4 + PWM1_PRESSEL_FHRC_D8 = (uint8_t)0x31, //PWM1ԤƵΪFhrc/8 +} PWM_PresSel_TypeDef; + +typedef enum +{ + PWM000 = (uint8_t)0x00, //PWMͨѡ: PWM000 + PWM001 = (uint8_t)0x02, //PWMͨѡ: PWM001 + PWM002 = (uint8_t)0x04, //PWMͨѡ: PWM002 + PWM003 = (uint8_t)0x06, //PWMͨѡ: PWM003 + PWM004 = (uint8_t)0x08, //PWMͨѡ: PWM004 + PWM005 = (uint8_t)0x0A, //PWMͨѡ: PWM005 + PWM006 = (uint8_t)0x0C, //PWMͨѡ: PWM006 + PWM007 = (uint8_t)0x0E, //PWMͨѡ: PWM007 + PWM010 = (uint8_t)0x10, //PWMͨѡ: PWM010 + PWM011 = (uint8_t)0x12, //PWMͨѡ: PWM011 + PWM012 = (uint8_t)0x14, //PWMͨѡ: PWM012 + PWM013 = (uint8_t)0x16, //PWMͨѡ: PWM013 + PWM014 = (uint8_t)0x18, //PWMͨѡ: PWM014 + PWM015 = (uint8_t)0x1A, //PWMͨѡ: PWM015 + PWM016 = (uint8_t)0x1C, //PWMͨѡ: PWM016 + PWM017 = (uint8_t)0x1E, //PWMͨѡ: PWM017 + PWM020 = (uint8_t)0x20, //PWMͨѡ: PWM020 + PWM021 = (uint8_t)0x22, //PWMͨѡ: PWM021 + PWM022 = (uint8_t)0x24, //PWMͨѡ: PWM022 + PWM023 = (uint8_t)0x26, //PWMͨѡ: PWM023 + PWM024 = (uint8_t)0x28, //PWMͨѡ: PWM024 + PWM025 = (uint8_t)0x2A, //PWMͨѡ: PWM025 + PWM026 = (uint8_t)0x2C, //PWMͨѡ: PWM026 + PWM027 = (uint8_t)0x2E, //PWMͨѡ: PWM027 + PWM030 = (uint8_t)0x30, //PWMͨѡ: PWM030 + PWM031 = (uint8_t)0x32, //PWMͨѡ: PWM031 + PWM032 = (uint8_t)0x34, //PWMͨѡ: PWM032 + PWM033 = (uint8_t)0x36, //PWMͨѡ: PWM033 + PWM034 = (uint8_t)0x38, //PWMͨѡ: PWM034 + PWM035 = (uint8_t)0x3A, //PWMͨѡ: PWM025 + PWM036 = (uint8_t)0x3C, //PWMͨѡ: PWM026 + PWM037 = (uint8_t)0x3E, //PWMͨѡ: PWM027 + PWM140 = (uint8_t)0x40, //PWMͨѡ: PWM140 + PWM141 = (uint8_t)0x42, //PWMͨѡ: PWM141 + PWM142 = (uint8_t)0x44, //PWMͨѡ: PWM142 + PWM143 = (uint8_t)0x46, //PWMͨѡ: PWM153 + PWM150 = (uint8_t)0x48, //PWMͨѡ: PWM150 + PWM151 = (uint8_t)0x4A, //PWMͨѡ: PWM151 + PWM152 = (uint8_t)0x4C, //PWMͨѡ: PWM152 + PWM153 = (uint8_t)0x4E, //PWMͨѡ: PWM153 +} PWM_OutputPin_TypeDef; + +typedef enum +{ + PWM0_Type = (uint8_t)0x00, //PWMԤƵΪFhrc/1 + PWM1_Type = (uint8_t)0x01, //PWMԤƵΪFhrc/2 +} PWM_Type_TypeDef; + +#elif defined (SC92L853x) || defined (SC92L753x) +//PWMԤƵѡ +typedef enum +{ + PWM_PRESSEL_FHRC_D1 = (uint8_t)0x00, //PWM0ԤƵΪFhrc/1 + PWM_PRESSEL_FHRC_D2 = (uint8_t)0x10, //PWM0ԤƵΪFhrc/2 + PWM_PRESSEL_FHRC_D4 = (uint8_t)0x20, //PWM0ԤƵΪFhrc/4 + PWM_PRESSEL_FHRC_D8 = (uint8_t)0x30, //PWM0ԤƵΪFhrc/8 +} PWM_PresSel_TypeDef; + +//PWMͨѡ +typedef enum +{ + PWM0 = (uint8_t)0x00, //PWMͨѡ: PWM00 + PWM1 = (uint8_t)0x02, //PWMͨѡ: PWM01 + PWM2 = (uint8_t)0x04, //PWMͨѡ: PWM02 + PWM3 = (uint8_t)0x06, //PWMͨѡ: PWM03 + PWM4 = (uint8_t)0x08, //PWMͨѡ: PWM04 + PWM5 = (uint8_t)0x0A, //PWMͨѡ: PWM05 + PWM6 = (uint8_t)0x0C, //PWMͨѡ: PWM06 + PWM7 = (uint8_t)0x0E, //PWMͨѡ: PWM07 +} PWM_OutputPin_TypeDef; + +//PWMģʽ +typedef enum +{ + PWM0_Edge_Aligned_Mode = (uint8_t)0x00, //PWMضģʽ + PWM0_Center_Alignment_Mode = (uint8_t)0x01, //PWMмģʽ +} PWM_Aligned_Mode_TypeDef; + +//PWMϼģʽ +typedef enum +{ + PWM0_Latch_Mode = ((uint8_t)0x00), //PWMϼģʽ:ģʽ + PWM0_Immediate_Mode = ((uint8_t)0x20) //PWMϼģʽ:ģʽ +} PWM_FaultDetectionMode_TypeDef; + +//PWMϼƽѡ +typedef enum +{ + PWM0_FaultDetectionVoltage_Low = ((uint8_t)0x00), //PWMϼ͵ƽѡ + PWM0_FaultDetectionVoltage_high = ((uint8_t)0x10) //PWMϼߵƽѡ +} PWM_FaultDetectionVoltageSelect_TypeDef; + +//PWMϼź˲ʱ +typedef enum +{ + PWM0_WaveFilteringTime_0us = ((uint8_t)0x00), //PWMϼź˲ʱ0us + PWM0_WaveFilteringTime_1us = ((uint8_t)0x01), //PWMϼź˲ʱ1us + PWM0_WaveFilteringTime_4us = ((uint8_t)0x02), //PWMϼź˲ʱ4us + PWM0_WaveFilteringTime_16us = ((uint8_t)0x03) //PWMϼź˲ʱ16us +} PWM_FaultDetectionWaveFilteringTime_TypeDef; + +//PWMģʽͨѡ +typedef enum +{ + PWM0PWM1 = (uint8_t)0x00, //PWMģʽͨѡ:PWM00PWM01 + PWM2PWM3 = (uint8_t)0x04, //PWMģʽͨѡ:PWM02PWM03 + PWM4PWM5 = (uint8_t)0x08, //PWMģʽͨѡ:PWM04PWM05 + PWM6PWM7 = (uint8_t)0x0C //PWMģʽͨѡ:PWM06PWM07 +} PWM_ComplementaryOutputPin_TypeDef; + +//PWMԴѡ +typedef enum +{ + PWM0_Type = (uint8_t)0x00, //PWM0 +} PWM_Type_TypeDef; +#endif + +typedef enum +{ + PWM_OUTPUTSTATE_DISABLE = ((uint8_t)0x00), //PINΪGPIO + PWM_OUTPUTSTATE_ENABLE = ((uint8_t)0x01) //PINΪPWM +} PWM_OutputState_TypeDef; + +typedef enum +{ + PWM_POLARITY_NON_INVERT = ((uint8_t)0x00), //PWM` + PWM_POLARITY_INVERT = ((uint8_t)0x01) //PWM +} PWM_Polarity_TypeDef; + +void PWM_DeInit(void); +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period); +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState); +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity); +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle); +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority); + +#if defined (SC92FWxx) || defined (SC92L853x) || defined (SC92L753x) +#if !defined (SC92FWxx) +void PWM_Aligned_Mode_Select(PWM_Aligned_Mode_TypeDef PWM_Aligned_Mode); +void PWM_FaultDetectionModeConfigEX(PWM_Type_TypeDef PWM_Type, + PWM_FaultDetectionMode_TypeDef FaultDetectionMode, + PWM_FaultDetectionVoltageSelect_TypeDef FaultDetectionVoltageSelect, + PWM_FaultDetectionWaveFilteringTime_TypeDef FaultDetectionWaveFilteringTime); +#endif +void PWM_CmdEX(PWM_Type_TypeDef PWM_Type, + FunctionalState NewState); +FlagStatus PWM_GetFlagStatusEX(PWM_Type_TypeDef PWM_Type); +void PWM_ClearFlagEX(PWM_Type_TypeDef PWM_Type); +void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle, + PWM_OutputState_TypeDef PWM_OutputState); + +void PWM_ITConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState, PriorityStatus Priority); +FlagStatus PWM_GetFaultDetectionFlagStatusEX(PWM_Type_TypeDef PWM_Type); +void PWM_ClearFaultDetectionFlagEX(PWM_Type_TypeDef PWM_Type); +void PWM_FaultDetectionConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState); +#else +void PWM_Cmd(FunctionalState NewState); +FlagStatus PWM_GetFlagStatus(void); +void PWM_ClearFlag(void); +#endif + +/* ͨԼú */ +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax)|| defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) || defined (SC92F848x) || defined (SC92F748x) || defined (SC92F848x) || defined (SC92F748x) +void PWM_ComplementaryModeConfig( PWM_ComplementaryOutputPin_TypeDef + PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle); +void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime); +#endif +#if defined (SC92L853x) || defined (SC92L753x) +void PWM_DeadTimeConfigEX(PWM_Type_TypeDef PWM_Type, uint8_t PWM_RisingDeadTime, uint8_t PWM_FallingDeadTime); +#endif +/* PWMͨѡ */ +#if defined (SC92F8003) || defined (SC92F740x) || defined (SC92F7003) + void PWM_PWM2Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin); + void PWM_PWM5Selection(PWM5_OutputPin_TypeDef PWM5_OutputPin); +#endif +#if defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) + void PWM_PWM0Selection(PWM0_OutputPin_TypeDef PWM0_OutputPin); + void PWM_PWM1Selection(PWM1_OutputPin_TypeDef PWM1_OutputPin); + void PWM_PWM2Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin); + void PMM_DutyModeSelection(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_DutyMode_TypeDef PWM_DutyMode); +#endif + +#endif + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_pwr.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_pwr.h new file mode 100644 index 0000000..ddb4f72 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_pwr.h @@ -0,0 +1,24 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_pwr.h +// : +// ģ鹦 : PWR̼⺯ͷļ +// ֲб: +// : 2020/8/18 +// 汾 : V1.0 +// ˵ : +//************************************************************* + +#ifndef _sc92f_PWR_H_ +#define _sc92f_PWR_H_ + +#include "sc92f.h" +#include + +void PWR_DeInit(void); +void PWR_EnterSTOPMode(void); +void PWR_EnterIDLEMode(void); + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_ssi.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_ssi.h new file mode 100644 index 0000000..3159e3a --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_ssi.h @@ -0,0 +1,282 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ssi.h +// : +// ģ鹦 : SSI̼⺯ͷļ +// ֲб: +// : 2020/08/20 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#ifndef _sc92f_SSI_H_ +#define _sc92f_SSI_H_ + +#include "sc92f.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)||defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined (SC92F83Ax) || defined (SC92F73Ax) || defined (SC92F7003) || defined(SC92F8003) || defined (SC92F740x) || defined (SC92F827X)\ + || defined (SC92F837X) || defined (SC92FWxx) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92F848x) || defined (SC92F748x)\ + || defined (SC92F859x) || defined (SC92F859x) +typedef enum +{ + SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} SPI_FirstBit_TypeDef; + +typedef enum +{ + SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x00, //SPIʱΪϵͳʱӳ4 + SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x01, //SPIʱΪϵͳʱӳ8 + SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x02, //SPIʱΪϵͳʱӳ16 + SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x03, //SPIʱΪϵͳʱӳ32 + SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x04, //SPIʱΪϵͳʱӳ64 + SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x05, //SPIʱΪϵͳʱӳ128 + SPI_BAUDRATEPRESCALER_256 = (uint8_t)0x06, //SPIʱΪϵͳʱӳ256 + SPI_BAUDRATEPRESCALER_512 = (uint8_t)0x07 //SPIʱΪϵͳʱӳ512 +} SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} SPI_Mode_TypeDef; + +typedef enum +{ + SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} SPI_ClockPolarity_TypeDef; + +typedef enum +{ + SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} SPI_ClockPhase_TypeDef; + +typedef enum +{ + //Ϊӻ + TWI_SlaveBusy = 0x00, + TWI_SlaveReceivedaAddress = 0x01, + TWI_SlaveReceivedaData = 0x02, + TWI_SlaveSendData = 0x03, + TWI_SlaveReceivedaUACK = 0x04, + TWI_SlaveDisableACK = 0x05, + TWI_SlaveAddressError = 0x06, + +}SSI_TWIState_TypeDef; + +typedef enum +{ + SPI_TXE_DISINT = (uint8_t)0x00, //TXEΪ1ʱж + SPI_TXE_ENINT = (uint8_t)0x01 //TXEΪ1ʱж +} SPI_TXE_INT_TypeDef; + +typedef enum +{ + UART1_Mode_10B = 0X00,//UART1Ϊ10λģʽ + UART1_Mode_11B = 0X80 //UART1Ϊ11λģʽ +} UART1_Mode_TypeDef; + +typedef enum +{ + UART1_RX_ENABLE = 0X10,//UART1 + UART1_RX_DISABLE = 0X00 //UART1ֹ +} UART1_RX_TypeDef; + +typedef enum +{ + SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + UART1_FLAG_TI = (uint8_t)0x02, //UART1жϱ־λTI + UART1_FLAG_RI = (uint8_t)0x01 //UART1жϱ־λRI +} SSI_Flag_TypeDef; + +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + SSI_PinSelection_P10P27P26 = (uint8_t)0x00, //SSIΪP10P27P26 + SSI_PinSelection_P21P22P23 = (uint8_t)0x20, //SSIΪP21P22P23 + SSI_PinSelection_URATP27 = (uint8_t)0x00, //SSIUARTΪP27,RX + SSI_PinSelection_URATP22 = (uint8_t)0x20 //SSIUARTΪP22,RX +} SSI_PinSelection_TypeDef; +void SSI_PinSelection(SSI_PinSelection_TypeDef + PinSeletion); +#endif + +void SSI_DeInit(void); +void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT); +void SSI_SPI_Cmd(FunctionalState NewState); +void SSI_SPI_SendData(uint8_t Data); +uint8_t SSI_SPI_ReceiveData(void); +void SSI_TWI_Init(uint8_t TWI_Address); +void SSI_TWI_AcknowledgeConfig(FunctionalState NewState); +void SSI_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus SSI_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState); +FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG); +void SSI_TWI_Cmd(FunctionalState NewState); +void SSI_TWI_SendData(uint8_t Data); +uint8_t SSI_TWI_ReceiveData(void); +void SSI_UART1_Init(uint32_t UART1Fsys, + uint32_t BaudRate, UART1_Mode_TypeDef Mode, + UART1_RX_TypeDef RxMode); +void SSI_UART1_SendData8(uint8_t Data); +uint8_t SSI_UART1_ReceiveData8(void); +void SSI_UART1_SendData9(uint16_t Data); +uint16_t SSI_UART1_ReceiveData9(void); +void SSI_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG); +#endif + +#if defined (SC92F742x) || defined (SC92F7490) +typedef enum +{ + SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} SPI_FirstBit_TypeDef; + +typedef enum +{ + SPI_BAUDRATEPRESCALER_1 = (uint8_t)0x00, //SPIʱΪFsys/1 + SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x01, //SPIʱΪFsys/2 + SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x02, //SPIʱΪFsys/4 + SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x03, //SPIʱΪFsys/8 + SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x04, //SPIʱΪFsys/16 + SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x05, //SPIʱΪFsys/32 + SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x06, //SPIʱΪFsys/64 + SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x07 //SPIʱΪFsys/128 +} SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} SPI_Mode_TypeDef; + +typedef enum +{ + SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} SPI_ClockPolarity_TypeDef; + +typedef enum +{ + SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} SPI_ClockPhase_TypeDef; + +typedef enum +{ + SPI_TXE_DISINT = (uint8_t)0x00, //TXEΪ0ʱж + SPI_TXE_ENINT = (uint8_t)0x01 //TXEΪ1ʱж +} SPI_TXE_INT_TypeDef; + +typedef enum +{ + UART_Mode_10B = 0X00, //UARTΪ10λģʽ + UART_Mode_11B = 0X80 //UARTΪ11λģʽ +} UART_Mode_TypeDef; + +typedef enum +{ + UART_RX_ENABLE = 0X10, //UART + UART_RX_DISABLE = 0X00 //UARTֹ +} UART_RX_TypeDef; + +typedef enum{ + //Ϊӻ + TWI_SlaveBusy = 0x00, + TWI_SlaveReceivedaAddress = 0x01, + TWI_SlaveReceivedaData = 0x02, + TWI_SlaveSendData = 0x03, + TWI_SlaveReceivedaUACK = 0x04, + TWI_SlaveDisableACK = 0x05, + TWI_SlaveAddressError = 0x06, + +}SSI_TWIState_TypeDef; + +typedef enum +{ + SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + UART_FLAG_TI = (uint8_t)0x02, //UARTжϱ־λTI + UART_FLAG_RI = (uint8_t)0x01 //UARTжϱ־λRI +} SSI_Flag_TypeDef; + +void SSI0_DeInit(void); +void SSI0_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT); +void SSI0_SPI_Cmd(FunctionalState NewState); +void SSI0_SPI_SendData(uint8_t Data); +uint8_t SSI0_SPI_ReceiveData(void); +void SSI0_TWI_Init(uint8_t TWI_Address); +void SSI0_TWI_AcknowledgeConfig(FunctionalState NewState); +void SSI0_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus SSI0_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState); +void SSI0_TWI_Cmd(FunctionalState NewState); +void SSI0_TWI_SendData(uint8_t Data); +uint8_t SSI0_TWI_ReceiveData(void); +void SSI0_UART_Init(uint32_t UARTFsys, + uint32_t BaudRate, UART_Mode_TypeDef Mode, + UART_RX_TypeDef RxMode); +void SSI0_UART_SendData8(uint8_t Data); +uint8_t SSI0_UART_ReceiveData8(void); +void SSI0_UART_SendData9(uint16_t Data); +uint16_t SSI0_UART_ReceiveData9(void); +void SSI0_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +FlagStatus SSI0_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG); +void SSI0_ClearFlag(SSI_Flag_TypeDef SSI_FLAG); + +void SSI1_DeInit(void); +void SSI1_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT); +void SSI1_SPI_Cmd(FunctionalState NewState); +void SSI1_SPI_SendData(uint8_t Data); +uint8_t SSI1_SPI_ReceiveData(void); +void SSI1_TWI_Init(uint8_t TWI_Address); +void SSI1_TWI_AcknowledgeConfig(FunctionalState NewState); +void SSI1_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus SSI1_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState); +void SSI1_TWI_Cmd(FunctionalState NewState); +void SSI1_TWI_SendData(uint8_t Data); +uint8_t SSI1_TWI_ReceiveData(void); +void SSI1_UART_Init(uint32_t UARTFsys, + uint32_t BaudRate, UART_Mode_TypeDef Mode, + UART_RX_TypeDef RxMode); +void SSI1_UART_SendData8(uint8_t Data); +uint8_t SSI1_UART_ReceiveData8(void); +void SSI1_UART_SendData9(uint16_t Data); +uint16_t SSI1_UART_ReceiveData9(void); +void SSI1_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +FlagStatus SSI1_GetFlagStatus(SSI_Flag_TypeDef + SSI_FLAG); +void SSI1_ClearFlag(SSI_Flag_TypeDef SSI_FLAG); +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer0.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer0.h new file mode 100644 index 0000000..5dcd8bc --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer0.h @@ -0,0 +1,139 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_tiemr0.h +// : ԪӦŶ +// ģ鹦: TIMER0̼⺯Cļ +// : 2022323 +// 汾: V1.10001 +// ˵: +//************************************************************* + +#ifndef _sc92f_TIMER0_H_ +#define _sc92f_TIMER0_H_ + +#include "sc92f.h" + +typedef enum +{ + TIM0_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER0Դϵͳʱ12Ƶ + TIM0_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER0Դϵͳʱ +} TIM0_PresSel_TypeDef; + +typedef enum +{ + TIM0_MODE_TIMER = ((uint8_t)0x01), //TIMER0ʱ + TIM0_MODE_COUNTER = ((uint8_t)0x02) //TIMER0 +} TIM0_CountMode_TypeDef; + +typedef enum +{ + TIM0_WORK_MODE0 = ((uint8_t)0x00), //TIMER0ѡģʽ0 + TIM0_WORK_MODE1 = ((uint8_t)0x01), //TIMER0ѡģʽ1 + TIM0_WORK_MODE2 = ((uint8_t)0x02), //TIMER0ѡģʽ2 + TIM0_WORK_MODE3 = ((uint8_t)0x03) //TIMER0ѡģʽ3 +} TIM0_WorkMode_TypeDef; + +/************************꺯************************/ +/************************************************** +*:void TIM0_Mode0SetReloadCounter(uint16_t TIM0_SetCounter) +*:TIMER0ģʽ0ֵغ +*ڲ: +uint16_t:TIM0_SetCounter:TIMER0ֵ +*ڲ:void +**************************************************/ +#define TIM0_Mode0SetReloadCounter(TIM0_SetCounter) \ + do{ \ + TL0 = (uint8_t)TIM0_SetCounter; \ + TH0 = (TIM0_SetCounter >> 5); \ + }while(0) + +/************************************************** +*:void TIM0_Mode1SetReloadCounter(uint16_t TIM0_SetCounter) +*:TIMER0ģʽ1ֵغ +*ڲ: +uint16_t:TIM0_SetCounter:TIMER0ֵ +*ڲ:void +**************************************************/ +#define TIM0_Mode1SetReloadCounter(TIM0_SetCounter) \ + do{ \ + TL0 = (uint8_t)TIM0_SetCounter; \ + TH0 = (TIM0_SetCounter >> 8); \ + }while(0) + +/************************************************** +*:void TIM0_SetTH0Counter(uint8_t TIM0_SetCounter) +*:TIMER0 TH0ֵ +*ڲ: +uint8_t:TIM0_SetCounter:TH0 +*ڲ:void +**************************************************/ +#define TIM0_SetTH0Counter(TIM0_SetCounter) (TH0 = TIM0_SetCounter) + +/************************************************** +*:void TIM0_SetTL0Counter(uint8_t TIM0_SetCounter) +*:TIMER0 TL0ֵ +*ڲ: +uint8_t:TIM0_SetCounter:TL0 +*ڲ:void +**************************************************/ +#define TIM0_SetTL0Counter(TIM0_SetCounter) (TL0 = TIM0_SetCounter) + +/***************************************************** +*:void TIM0_Cmd(FunctionalState NewState) +*:TIMER0ܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +#define TIM0_Cmd(NewState) (TR0 = (bit)NewState) + +/***************************************************** +*:FlagStatus TIM0_GetFlagStatus(void) +*:TIMER0жϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:TIMER0жϱ־״̬ +*****************************************************/ +#define TIM0_GetFlagStatus() (TF0) + +/***************************************************** +*:void TIM0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:TIMER1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +#define TIM0_ITConfig(NewState,Priority) \ + do{ \ + ET0 = (bit)NewState; \ + IPT0 = (bit)Priority; \ + }while(0) + +/***************************************************** +*:void TIM0_ClearFlag(void) +*:TIMER0жϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +#define TIM0_ClearFlag() (TF0 = 0) + +void TIM0_DeInit(void); +void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef + TIM0_PrescalerSelection, + TIM0_CountMode_TypeDef TIM0_CountMode); +void TIM0_WorkMode0Config(uint16_t + TIM0_SetCounter); +void TIM0_WorkMode1Config(uint16_t + TIM0_SetCounter); +void TIM0_WorkMode2Config(uint8_t + TIM0_SetCounter); +void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, + uint8_t TIM1_SetCounter); +void TIM0_WorkModeConfig(TIM0_WorkMode_TypeDef + TIM0_WorkMode, uint16_t TIM0_SetCounter1, + uint16_t TIM0_SetCounter2); + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer1.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer1.h new file mode 100644 index 0000000..bdf392f --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer1.h @@ -0,0 +1,116 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timer1.h +// : +// ģ鹦 : TIMER1̼⺯ͷļ +// ֲб: +// : 2020/8/18 +// 汾 : V1.0 +// ˵ : +//************************************************************* + +#ifndef _sc92f_TIMER1_H_ +#define _sc92f_TIMER1_H_ + +#include "sc92f.h" + +typedef enum +{ + TIM1_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER1Դϵͳʱ12Ƶ + TIM1_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER1Դϵͳʱ +} TIM1_PresSel_TypeDef; + +typedef enum +{ + TIM1_MODE_TIMER = ((uint8_t)0x01), //TIMER1ʱ + TIM1_MODE_COUNTER = ((uint8_t)0x02) //TIMER1 +} TIM1_CountMode_TypeDef; + +typedef enum +{ + TIM1_WORK_MODE0 = ((uint8_t)0x00), //TIMER1ѡģʽ0 + TIM1_WORK_MODE1 = ((uint8_t)0x01), //TIMER1ѡģʽ1 + TIM1_WORK_MODE2 = ((uint8_t)0x02), //TIMER1ѡģʽ2 +} TIM1_WorkMode_TypeDef; + +/************************꺯************************/ +/************************************************** +*:void TIM1_Mode0SetReloadCounter(uint16_t TIM1_SetCounter) +*:TIMER1ģʽ0ֵغ +*ڲ: +uint16_t:TIM1_SetCounter:TIMER0ֵ +*ڲ:void +**************************************************/ +#define TIM1_Mode0SetReloadCounter(TIM1_SetCounter) \ + do{ \ + TL1 = (uint8_t)TIM1_SetCounter; \ + TH1 = (TIM1_SetCounter >> 5); \ + }while(0) + +/************************************************** +*:void TIM1_Mode1SetReloadCounter(uint16_t TIM1_SetCounter) +*:TIMER0ģʽ1ֵغ +*ڲ: +uint16_t:TIM1_SetCounter:TIMER0ֵ +*ڲ:void +**************************************************/ +#define TIM1_Mode1SetReloadCounter(TIM1_SetCounter) \ + do{ \ + TL1 = (uint8_t)TIM1_SetCounter; \ + TH1 = (TIM1_SetCounter >> 8); \ + }while(0) + +/***************************************************** +*:void TIM1_Cmd(FunctionalState NewState) +*:TIMER1ܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +#define TIM1_Cmd(NewState) (TR1 = (bit)NewState) + +/***************************************************** +*:void TIM1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:TIMER1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +#define TIM1_ITConfig(NewState,Priority) \ + do{ \ + ET1 = (bit)NewState; \ + IPT1 = (bit)Priority; \ + }while(0) + +/***************************************************** +*:FlagStatus TIM1_GetFlagStatus(void) +*:TIMER1жϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:TIMER1жϱ־״̬ +*****************************************************/ +#define TIM1_GetFlagStatus() (TF1) + +/***************************************************** +*:void TIM1_ClearFlag(void) +*:TIMER1жϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +#define TIM1_ClearFlag() (TF1 = 0) + +void TIM1_DeInit(void); +void TIM1_TimeBaseInit(TIM1_PresSel_TypeDef + TIM1_PrescalerSelection, + TIM1_CountMode_TypeDef TIM1_CountMode); +void TIM1_WorkMode0Config(uint16_t TIM1_SetCounter); +void TIM1_WorkMode1Config(uint16_t TIM1_SetCounter); +void TIM1_WorkMode2Config(uint8_t TIM1_SetCounter); +void TIM1_WorkModeConfig(TIM1_WorkMode_TypeDef TIM1_WorkMode, + uint16_t TIM1_SetCounter); + + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer2.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer2.h new file mode 100644 index 0000000..883933b --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer2.h @@ -0,0 +1,98 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_timer2.h +// : ԪӦŶ +// ģ鹦: TIMER2̼⺯ͷļ +// : 2022323 +// 汾: V1.10003 +// ˵: ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_TIMER2_H_ +#define _sc92f_TIMER2_H_ + +#include "sc92f.h" + +typedef enum +{ + TIM2_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER2Դϵͳʱ12Ƶ + TIM2_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER2Դϵͳʱ +} TIM2_PresSel_TypeDef; + +#if defined (SC92F730x) || defined (SC92F827X) || defined (SC92F837X) || defined (SC92F725X) || defined (SC92F735X) + +typedef enum +{ + TIM2_MODE_TIMER = ((uint8_t)0x01), //TIMER2ʱ +} TIM2_CountMode_TypeDef; + +typedef enum +{ + TIM2_COUNTDIRECTION_UP = ((uint8_t)0x00), //ϼģʽ +} TIM2_CountDirection_TypeDef; + +typedef enum +{ + TIM2_FLAG_TF2 = (uint8_t)0x80, //жϱ־λTF2 +} TIM2_Flag_TypeDef; + +typedef enum +{ + TIM2_WORK_MODE1 = ((uint8_t)0x00), //TIMER2ѡģʽ1 +} TIM2_WorkMode_TypeDef; + +#else + +typedef enum +{ + TIM2_MODE_TIMER = ((uint8_t)0x01), //TIMER2ʱ + TIM2_MODE_COUNTER = ((uint8_t)0x02) //TIMER2 +} TIM2_CountMode_TypeDef; + +typedef enum +{ + TIM2_COUNTDIRECTION_UP = ((uint8_t)0x00), //ϼģʽ + TIM2_COUNTDIRECTION_DOWN_UP = ((uint8_t)0x10) ///¼ģʽ +} TIM2_CountDirection_TypeDef; + +typedef enum +{ + TIM2_FLAG_TF2 = (uint8_t)0x80, //жϱ־λTF2 + TIM2_FLAG_EXF2 = (uint8_t)0x40 //жϱ־λEXF2ⲿ +} TIM2_Flag_TypeDef; + +typedef enum +{ + TIM2_WORK_MODE0 = ((uint8_t)0x00), //TIMER2ѡģʽ0 + TIM2_WORK_MODE1 = ((uint8_t)0x01), //TIMER2ѡģʽ1 + TIM2_WORK_MODE3 = ((uint8_t)0x03), //TIMER2ѡģʽ3 +} TIM2_WorkMode_TypeDef; + +#endif + +/***************************************************** +*:void BTM_ClearFlag(void) +*:BTMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +#define BTM_ClearFlag() CLEAR_BIT(BTMCON,0x40) + +void TIM2_DeInit(); +void TIM2_PrescalerSelection(TIM2_PresSel_TypeDef TIM2_PrescalerSelection); +void TIM2_TimeBaseInit(TIM2_PresSel_TypeDef TIM2_PrescalerSelection, + TIM2_CountMode_TypeDef TIM2_CountMode, + TIM2_CountDirection_TypeDef TIM2_CountDirection); +void TIM2_WorkMode0Config(uint16_t TIM2_SetCounter); +void TIM2_WorkMode1Config(uint16_t TIM2_SetCounter); +void TIM2_WorkMode3Config(uint16_t TIM2_SetCounter); +void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef TIM2_WorkMode, uint16_t TIM2_SetCounter); +void TIM2_SetEXEN2(FunctionalState NewState); +void TIM2_Cmd(FunctionalState NewState); +void TIM2_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus TIM2_GetFlagStatus(TIM2_Flag_TypeDef TIM2_Flag); +void TIM2_ClearFlag(TIM2_Flag_TypeDef TIM2_Flag); + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer3.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer3.h new file mode 100644 index 0000000..9521c8c --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer3.h @@ -0,0 +1,63 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timer3.h +// : +// ģ鹦 : TIMER3̼⺯ͷļ +// : 2022/01/18 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_TIMER3_H_ +#define _sc92f_TIMER3_H_ + +#include "sc92f.H" + +typedef enum +{ + TIM3_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER3Դϵͳʱ12Ƶ + TIM3_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER3Դϵͳʱ +} TIM3_PresSel_TypeDef; + +typedef enum +{ + TIM3_MODE_TIMER = ((uint8_t)0x01), //TIMER3ʱ + TIM3_MODE_COUNTER = ((uint8_t)0x02) //TIMER3 +} TIM3_CountMode_TypeDef; + +typedef enum +{ + TIM3_COUNTDIRECTION_UP = ((uint8_t)0x00), //ϼģʽ + TIM3_COUNTDIRECTION_DOWN_UP = ((uint8_t)0x10) ///¼ģʽ +} TIM3_CountDirection_TypeDef; + +typedef enum +{ + TIM3_FLAG_TF3 = (uint8_t)0x80, //жϱ־λTF3 + TIM3_FLAG_EXF3 = (uint8_t)0x40 //жϱ־λEXF3 +} TIM3_Flag_TypeDef; + +typedef enum +{ + TIM3_WORK_MODE0 = ((uint8_t)0x00), //TIMER3ѡģʽ0 + TIM3_WORK_MODE1 = ((uint8_t)0x01), //TIMER3ѡģʽ1 + TIM3_WORK_MODE3 = ((uint8_t)0x03), //TIMER3ѡģʽ3 +} TIM3_WorkMode_TypeDef; + +void TIM3_DeInit(); +void TIM3_PrescalerSelection(TIM3_PresSel_TypeDef TIM3_PrescalerSelection); +void TIM3_WorkMode1Config(uint16_t TIM3_SetCounter); +void TIM3_Cmd(FunctionalState NewState); +void TIM3_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus TIM3_GetFlagStatus(TIM3_Flag_TypeDef TIM3_Flag); +void TIM3_ClearFlag(TIM3_Flag_TypeDef TIM3_Flag); + +void TIM3_TimeBaseInit(TIM3_CountMode_TypeDef TIM3_CountMode, + TIM3_CountDirection_TypeDef TIM3_CountDirection); +void TIM3_WorkMode0Config(uint16_t TIM3_SetCounter); +void TIM3_WorkMode3Config(uint16_t TIM3_SetCounter); +void TIM3_WorkModeConfig(TIM3_WorkMode_TypeDef TIM3_WorkMode, uint16_t TIM3_SetCounter); +void TIM3_SetEXEN3(FunctionalState NewState); + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer4.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer4.h new file mode 100644 index 0000000..b454786 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_timer4.h @@ -0,0 +1,62 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timerx.h +// : +// ģ鹦 : TIMER4̼⺯ͷļ +// : 2021/01/18 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_TIMER4_H_ +#define _sc92f_TIMER4_H_ + +#include "sc92f.H" + +typedef enum +{ + TIM4_PRESSEL_FSYS_D12 = ((uint8_t)0x00), //TIMER4Դϵͳʱ12Ƶ + TIM4_PRESSEL_FSYS_D1 = ((uint8_t)0x01) //TIMER4Դϵͳʱ +} TIM4_PresSel_TypeDef; + +typedef enum +{ + TIM4_MODE_TIMER = ((uint8_t)0x01), //TIMER2ʱ + TIM4_MODE_COUNTER = ((uint8_t)0x02) //TIMER2 +} TIM4_CountMode_TypeDef; + +typedef enum +{ + TIM4_COUNTDIRECTION_UP = ((uint8_t)0x00), //ϼģʽ + TIM4_COUNTDIRECTION_DOWN_UP = ((uint8_t)0x10) ///¼ģʽ +} TIM4_CountDirection_TypeDef; + +typedef enum +{ + TIM4_FLAG_TF4 = (uint8_t)0x80, //жϱ־λTF4 + TIM4_FLAG_EXF4 = (uint8_t)0x40 //жϱ־λEXF4 +} TIM4_Flag_TypeDef; + +typedef enum +{ + TIM4_WORK_MODE0 = ((uint8_t)0x00), //TIMER4ѡģʽ0 + TIM4_WORK_MODE1 = ((uint8_t)0x01), //TIMER4ѡģʽ1 + TIM4_WORK_MODE3 = ((uint8_t)0x03), //TIMER4ѡģʽ3 +} TIM4_WorkMode_TypeDef; + +void TIM4_DeInit(); +void TIM4_PrescalerSelection(TIM4_PresSel_TypeDef TIM4_PrescalerSelection); +void TIM4_WorkMode1Config(uint16_t TIM4_SetCounter); +void TIM4_Cmd(FunctionalState NewState); +void TIM4_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus TIM4_GetFlagStatus(TIM4_Flag_TypeDef TIM4_Flag); +void TIM4_ClearFlag(TIM4_Flag_TypeDef TIM4_Flag); + +void TIM4_TimeBaseInit(TIM4_CountMode_TypeDef TIM4_CountMode, + TIM4_CountDirection_TypeDef TIM4_CountDirection); +void TIM4_WorkMode0Config(uint16_t TIM4_SetCounter); +void TIM4_WorkMode3Config(uint16_t TIM4_SetCounter); +void TIM4_WorkModeConfig(TIM4_WorkMode_TypeDef TIM4_WorkMode, uint16_t TIM4_SetCounter); +void TIM4_SetEXEN4(FunctionalState NewState); + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_uart0.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_uart0.h new file mode 100644 index 0000000..a236e3e --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_uart0.h @@ -0,0 +1,127 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_uart0.h +// : +// ģ鹦 : UART0̼⺯ͷļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.10002 +// ˵ :ļԪ92F/93F/92LϵеƬ +//************************************************************* +#ifndef _sc92f_UART0_H_ +#define _sc92f_UART0_H_ + +#include "sc92f.h" +#if !defined (SC92F742x) && !defined (SC92F827X) && !defined (SC92F837X) + +#define UART0_BaudRate_FsysDIV12 0X00 //ģʽ0ãж˿ϵͳʱӵ1/12 +#define UART0_BaudRate_FsysDIV4 0X01 //ģʽ0ãж˿ϵͳʱӵ1/4 +#define UART0_BaudRate_FsysDIV64 0X00 //ģʽ1ãж˿ϵͳʱӵ1/64 +#define UART0_BaudRate_FsysDIV32 0X01 //ģʽ1ãж˿ϵͳʱӵ1/32 +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +typedef enum +{ + UART0_PinSelection_P15P16 = (uint8_t)0x00, //UART0ΪP15P16 + UART0_PinSelection_P15 = (uint8_t)0x00, //UART0ΪP15P16RX + UART0_PinSelection_P11P20 = (uint8_t)0x10, //UART0ΪP11P20 + UART0_PinSelection_P20 = (uint8_t)0x10, //UART0ΪP20RX +} UART0_PinSelection_TypeDef; +#endif + +#if defined(SC92F725X) || defined(SC92F735X)|| defined (SC92F730x ) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + UART0_CLOCK_TIMER1 = (uint8_t)0X02, //TIMER1ʷ + UART0_CLOCK_TIMER1_FreqMcl2 = (uint8_t)0X82, //TIMER1ʷ,ҶƵ + UART0_CLOCK_TIMER1_DIV6 = (uint8_t)0X80, //TIMER1ʷ,6Ƶ + UART0_CLOCK_TIMER1_DIV12 = (uint8_t)0X00, //TIMER1ʷ,12Ƶ + UART0_CLOCK_TIMER2 = (uint8_t)0X34, //TIMER2ʷ + UART0_CLOCK_TIMER2_DIV12 = (uint8_t)0X30, //ʱ2 12Ƶģʽ13ͨ +}UART0_Clock_Typedef; +#elif defined (SC92F848x) || defined (SC92F748x) || defined(SC92F859x) || defined(SC92F759x) || defined(SC92L853x) || defined(SC92L753x) +typedef enum +{ + UART0_CLOCK_TIMER1 = (uint8_t)0X00, //TIMER1ʷ + UART0_CLOCK_TIMER2 = (uint8_t)0X30, //TIMER2ʷ + UART0_CLOCK_TIMER1_DIV16 = (uint8_t)0X80, //TIMER1ʷ + UART0_CLOCK_TIMER2_DIV16 = (uint8_t)0XB0, //TIMER2ʷ +}UART0_Clock_Typedef; +#else +typedef enum +{ + //ģʽ03Ķʱѡ + UART0_CLOCK_TIMER1 = (uint8_t)0X00, //TIMER1ʷ + UART0_CLOCK_TIMER2 = (uint8_t)0X30, //TIMER2ʷ +}UART0_Clock_Typedef; +#endif + +#if defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +typedef enum +{ + UART0_Mode_8B = 0X00, //UARTģʽ:8λ˫ + UART0_Mode_10B = 0X40, //UARTģʽ:10λȫ˫ + UART0_Mode_11B = 0XC0, //UARTģʽ:11λȫ˫ + UART0_Mode_11B_BaudRateFix = 80//UARTģʽ:11λȫ˫,ʹ̶ +}UART0_Mode_Typedef; +#else +typedef enum +{ + UART0_Mode_8B = 0X00, //UARTģʽ:8λ˫ + UART0_Mode_10B = 0X40, //UARTģʽ:10λȫ˫ + UART0_Mode_11B = 0XC0, //UARTģʽ:11λȫ˫ +}UART0_Mode_Typedef; +#endif + +typedef enum +{ + UART0_RX_ENABLE = 0x10, // + UART0_RX_DISABLE = 0x00 // +} UART0_RX_Typedef; + +typedef enum +{ + UART0_FLAG_RI = 0X01, //жϱ־λRI + UART0_FLAG_TI = 0X02 //жϱ־λTI +} UART0_Flag_Typedef; + +/*******************************꺯*******************************/ +/***************************************************** +*:FlagStatus UART0_GetFlagStatus(UART0_Flag_Typedef UART0_Flag) +*:UART0жϱ־״̬ +*ڲ: +UART0_GetFlagStatus:UART0_Flag:жϱ־λѡ +*ڲ: +FlagStatus:UART0жϱ־λ״̬ +*****************************************************/ +#define UART0_GetFlagStatus(UART0_Flag) ((UART0_Flag == UART0_FLAG_TI) ? (TI):(RI)) + +/***************************************************** +*:void UART0_ClearFlag(UART0_Flag_Typedef UART0_Flag) +*:UART0жϱ־״̬ +*ڲ: +UART0_Flag_Typedef;UART0_Flag:жϱ־λѡ +*ڲ:void +*****************************************************/ +#define UART0_ClearFlag(UART0_Flag) CLEAR_BIT(SCON,UART0_Flag) + +void UART0_DeInit(void); +void UART0_Init(uint32_t Uart0Fsys, + uint32_t BaudRate, UART0_Mode_Typedef Mode, + UART0_Clock_Typedef ClockMode, + UART0_RX_Typedef RxMode); +void UART0_SendData8(uint8_t Data); +uint8_t UART0_ReceiveData8(void); +void UART0_SendData9(uint16_t Data); +uint16_t UART0_ReceiveData9(void); +void UART0_ITConfig(FunctionalState NewState, + PriorityStatus Priority); +#if defined (SC92F8003) || defined (SC92F740x) || defined (SC92F7003) +void UART0_PinSelection(UART0_PinSelection_TypeDef + PinSeletion); +#endif + +#endif + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci0.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci0.h new file mode 100644 index 0000000..32b97b4 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci0.h @@ -0,0 +1,171 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_usci0.h +// : +// ģ鹦 : USCI0̼⺯ͷļ +// : 2022/01/05 +// 汾 : V1.1000 +// ˵ : ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_USCI0_H_ +#define _sc92f_USCI0_H_ + +#include "sc92f.h" + +#define USCI0_UART_BaudRate_FsysDIV12 0X00 //ģʽ0ãж˿ϵͳʱӵ1/12 +#define USCI0_UART_BaudRate_FsysDIV4 0X01 //ģʽ0ãж˿ϵͳʱӵ1/4 + +#if defined(SC92L853x) || defined(SC92L753x) +typedef enum +{ + USCI0_Mode_SPI = (uint8_t)0x01, //SPI + USCI0_Mode_TWI = (uint8_t)0x02, //TWI + USCI0_Mode_UART = (uint8_t)0x03 //UART +} USCI0_CommunicationMode_TypeDef; +#endif + +typedef enum +{ + USCI0_SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + USCI0_SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} USCI0_SPI_FirstBit_TypeDef; + +typedef enum +{ + USCI0_SPI_BAUDRATEPRESCALER_1 = (uint8_t)0x00, //SPIʱΪϵͳʱӳ1 + USCI0_SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x01, //SPIʱΪϵͳʱӳ2 + USCI0_SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x02, //SPIʱΪϵͳʱӳ4 + USCI0_SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x03, //SPIʱΪϵͳʱӳ8 + USCI0_SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x04, //SPIʱΪϵͳʱӳ16 + USCI0_SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x05, //SPIʱΪϵͳʱӳ32 + USCI0_SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x06, //SPIʱΪϵͳʱӳ64 + USCI0_SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x07 //SPIʱΪϵͳʱӳ128 +} USCI0_SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + USCI0_SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + USCI0_SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} USCI0_SPI_Mode_TypeDef; + +typedef enum +{ + USCI0_SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + USCI0_SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} USCI0_SPI_ClockPolarity_TypeDef; + +typedef enum +{ + USCI0_SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + USCI0_SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} USCI0_SPI_ClockPhase_TypeDef; + +typedef enum +{ + USCI0_SPI_TXE_DISINT = (uint8_t)0x00, //TBIEΪ0ʱж + USCI0_SPI_TXE_ENINT = (uint8_t)0x01 //TBIEΪ1ʱж +} USCI0_SPI_TXE_INT_TypeDef; + +typedef enum +{ + USCI0_SPI_DATA8 = (uint8_t)0x00, //SPI 8λģʽ + USCI0_SPI_DATA16 = (uint8_t)0x02 //SPI 16λģʽ +} USCI0_TransmissionMode_TypeDef; + +typedef enum +{ + USCI0_TWI_1024 = (uint8_t)0x00, //TWIͨ Fhrc/1024 + USCI0_TWI_512 = (uint8_t)0x01, //TWIͨ Fhrc/512 + USCI0_TWI_256 = (uint8_t)0x02, //TWIͨ Fhrc/256 + USCI0_TWI_128 = (uint8_t)0x03, //TWIͨ Fhrc/128 + USCI0_TWI_64 = (uint8_t)0x04, //TWIͨ Fhrc/64 + USCI0_TWI_32 = (uint8_t)0x05, //TWIͨ Fhrc/32 + USCI0_TWI_16 = (uint8_t)0x06, //TWIͨ Fhrc/16 +} USCI0_TWI_MasterCommunicationRate_TypeDef; + +typedef enum +{ + USCI0_TWI_SlaveBusy = 0x00, //Ϊӻ + USCI0_TWI_SlaveReceivedaAddress = 0x01, + USCI0_TWI_SlaveReceivedaData = 0x02, + USCI0_TWI_SlaveSendData = 0x03, + USCI0_TWI_SlaveReceivedaUACK = 0x04, + USCI0_TWI_SlaveDisableACK = 0x05, + USCI0_TWI_SlaveAddressError = 0x06, + USCI0_TWI_MasterBusy = 0x00, //Ϊ + USCI0_TWI_MasterSendAddress = 0x01, + USCI0_TWI_MasterSendData = 0x02, + USCI0_TWI_MasterReceivedaData = 0x03, + USCI0_TWI_MasterReceivedaUACK = 0x04, +} USCI0_TWIState_TypeDef; + +typedef enum +{ + USCI0_UART_Mode_8B = 0X00, //UARTΪ8λģʽ + USCI0_UART_Mode_10B = 0X40, //UARTΪ10λģʽ + USCI0_UART_Mode_11B = 0X80 //UARTΪ11λģʽ +} USCI0_UART_Mode_TypeDef; + +typedef enum +{ + USCI0_UART_RX_ENABLE = 0X10, //UART + USCI0_UART_RX_DISABLE = 0X00 //UARTֹ +} USCI0_UART_RX_TypeDef; + +typedef enum +{ + USCI0_SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + USCI0_SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + USCI0_SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + USCI0_TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + USCI0_TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + USCI0_TWI_FLAG_MSTR = (uint8_t)0x20, //TWIӱ־λMSTR + USCI0_TWI_FLAG_TXRXnE = (uint8_t)0x80, + USCI0_UART_FLAG_RI = (uint8_t)0x01, //UARTжϱ־λRI + USCI0_UART_FLAG_TI = (uint8_t)0x02, //UARTжϱ־λTI +} USCI0_Flag_TypeDef; + +typedef enum +{ + USCI0_TWI_Write = 0x00, //д + USCI0_TWI_Read = 0x01, // +} USCI0_TWI_RWType; + +void USCI0_DeInit(void); +void USCI0_SPI_Init(USCI0_SPI_FirstBit_TypeDef FirstBit, + USCI0_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI0_SPI_Mode_TypeDef Mode, + USCI0_SPI_ClockPolarity_TypeDef ClockPolarity, USCI0_SPI_ClockPhase_TypeDef ClockPhase, + USCI0_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI0_TransmissionMode_TypeDef TransmissionMode); +void USCI0_TransmissionMode(USCI0_TransmissionMode_TypeDef TransmissionMode); +void USCI0_SPI_Cmd(FunctionalState NewState); +void USCI0_SPI_SendData_8(uint8_t Data); +uint8_t USCI0_SPI_ReceiveData_8(void); +void USCI0_SPI_SendData_16(uint16_t Data); +uint16_t USCI0_SPI_ReceiveData_16(void); +void USCI0_TWI_Slave_Init(uint8_t TWI_Address); +void USCI0_TWI_MasterCommunicationRate(USCI0_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate); +void USCI0_TWI_Start(void); +void USCI0_TWI_MasterModeStop(void); +void USCI0_TWI_SendAddr(uint8_t Addr, USCI0_TWI_RWType RW); +void USCI0_TWI_SlaveClockExtension(FunctionalState NewState); +void USCI0_TWI_AcknowledgeConfig(FunctionalState NewState); +void USCI0_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus USCI0_GetTWIStatus(USCI0_TWIState_TypeDef USCI0_TWIState); +void USCI0_TWI_Cmd(FunctionalState NewState); +void USCI0_TWI_SendData(uint8_t Data); +uint8_t USCI0_TWI_ReceiveData(void); +void USCI0_UART_Init(uint32_t UART1Fsys, uint32_t BaudRate, USCI0_UART_Mode_TypeDef Mode, + USCI0_UART_RX_TypeDef RxMode); +void USCI0_UART_SendData8(uint8_t Data); +uint8_t USCI0_UART_ReceiveData8(void); +void USCI0_UART_SendData9(uint16_t Data); +uint16_t USCI0_UART_ReceiveData9(void); +void USCI0_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus USCI0_GetFlagStatus(USCI0_Flag_TypeDef USCI0_FLAG); +void USCI0_ClearFlag(USCI0_Flag_TypeDef USCI0_FLAG); + +#endif + +/******************* (C) COPYRIGHT 2019 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci1.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci1.h new file mode 100644 index 0000000..df5ff09 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci1.h @@ -0,0 +1,168 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_usci1.h +// : +// ģ鹦 : USCI1̼⺯ͷļ +// : 2022/01/05 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_USCI1_H_ +#define _sc92f_USCI1_H_ + +#include "sc92f.h" + +#define USCI1_UART_BaudRate_FsysDIV12 0X00 //ģʽ0ãж˿ϵͳʱӵ1/12 +#define USCI1_UART_BaudRate_FsysDIV4 0X01 //ģʽ0ãж˿ϵͳʱӵ1/4 + +typedef enum +{ + USCI1_Mode_SPI = (uint8_t)0x01, //SPI + USCI1_Mode_TWI = (uint8_t)0x02, //TWI + USCI1_Mode_UART = (uint8_t)0x03 //UART +} USCI1_CommunicationMode_TypeDef; + +typedef enum +{ + USCI1_SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + USCI1_SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} USCI1_SPI_FirstBit_TypeDef; + +typedef enum +{ + USCI1_SPI_BAUDRATEPRESCALER_1 = (uint8_t)0x00, //SPIʱΪϵͳʱӳ1 + USCI1_SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x01, //SPIʱΪϵͳʱӳ2 + USCI1_SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x02, //SPIʱΪϵͳʱӳ4 + USCI1_SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x03, //SPIʱΪϵͳʱӳ8 + USCI1_SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x04, //SPIʱΪϵͳʱӳ16 + USCI1_SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x05, //SPIʱΪϵͳʱӳ32 + USCI1_SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x06, //SPIʱΪϵͳʱӳ64 + USCI1_SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x07 //SPIʱΪϵͳʱӳ128 +} USCI1_SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + USCI1_SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + USCI1_SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} USCI1_SPI_Mode_TypeDef; + +typedef enum +{ + USCI1_SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + USCI1_SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} USCI1_SPI_ClockPolarity_TypeDef; + +typedef enum +{ + USCI1_SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + USCI1_SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} USCI1_SPI_ClockPhase_TypeDef; + +typedef enum +{ + USCI1_SPI_TXE_DISINT = (uint8_t)0x00, //TBIEΪ0ʱж + USCI1_SPI_TXE_ENINT = (uint8_t)0x01 //TBIEΪ1ʱж +} USCI1_SPI_TXE_INT_TypeDef; + +typedef enum +{ + USCI1_SPI_DATA8 = (uint8_t)0x00, //SPI 8λģʽ + USCI1_SPI_DATA16 = (uint8_t)0x02 //SPI 16λģʽ +} USCI1_TransmissionMode_TypeDef; + +typedef enum +{ + USCI1_TWI_1024 = (uint8_t)0x00, //TWIͨ Fhrc/1024 + USCI1_TWI_512 = (uint8_t)0x01, //TWIͨ Fhrc/512 + USCI1_TWI_256 = (uint8_t)0x02, //TWIͨ Fhrc/256 + USCI1_TWI_128 = (uint8_t)0x03, //TWIͨ Fhrc/128 + USCI1_TWI_64 = (uint8_t)0x04, //TWIͨ Fhrc/64 + USCI1_TWI_32 = (uint8_t)0x05, //TWIͨ Fhrc/32 + USCI1_TWI_16 = (uint8_t)0x06, //TWIͨ Fhrc/16 +} USCI1_TWI_MasterCommunicationRate_TypeDef; + +typedef enum +{ + USCI1_TWI_SlaveBusy = 0x00, + USCI1_TWI_SlaveReceivedaAddress = 0x01, + USCI1_TWI_SlaveReceivedaData = 0x02, + USCI1_TWI_SlaveSendData = 0x03, + USCI1_TWI_SlaveReceivedaUACK = 0x04, + USCI1_TWI_SlaveDisableACK = 0x05, + USCI1_TWI_SlaveAddressError = 0x06, + USCI1_TWI_MasterBusy = 0x00, + USCI1_TWI_MasterSendAddress = 0x01, + USCI1_TWI_MasterSendData = 0x02, + USCI1_TWI_MasterReceivedaData = 0x03, + USCI1_TWI_MasterReceivedaUACK = 0x04, +} USCI1_TWIState_TypeDef; + +typedef enum +{ + USCI1_UART_Mode_8B = 0X00, //UARTΪ8λģʽ + USCI1_UART_Mode_10B = 0X40, //UARTΪ10λģʽ + USCI1_UART_Mode_11B = 0X80 //UARTΪ11λģʽ +} USCI1_UART_Mode_TypeDef; + +typedef enum +{ + USCI1_UART_RX_ENABLE = 0X10, //UART + USCI1_UART_RX_DISABLE = 0X00 //UARTֹ +} USCI1_UART_RX_TypeDef; + +typedef enum +{ + USCI1_SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + USCI1_SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + USCI1_SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + USCI1_TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + USCI1_TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + USCI1_TWI_FLAG_MSTR = (uint8_t)0x20, //TWIӱ־λMSTR + USCI1_TWI_FLAG_TXRXnE = (uint8_t)0x80, + USCI1_UART_FLAG_RI = (uint8_t)0x01, //UARTжϱ־λRI + USCI1_UART_FLAG_TI = (uint8_t)0x02, //UARTжϱ־λTI +} USCI1_Flag_TypeDef; + +typedef enum +{ + USCI1_TWI_Write = 0x00, //д + USCI1_TWI_Read = 0x01, // +} USCI1_TWI_RWType; + +void USCI1_DeInit(void); +void USCI1_SPI_Init(USCI1_SPI_FirstBit_TypeDef FirstBit, + USCI1_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI1_SPI_Mode_TypeDef Mode, + USCI1_SPI_ClockPolarity_TypeDef ClockPolarity, USCI1_SPI_ClockPhase_TypeDef ClockPhase, + USCI1_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI1_TransmissionMode_TypeDef TransmissionMode); +void USCI1_TransmissionMode(USCI1_TransmissionMode_TypeDef TransmissionMode); +void USCI1_SPI_Cmd(FunctionalState NewState); +void USCI1_SPI_SendData_8(uint8_t Data); +uint8_t USCI1_SPI_ReceiveData_8(void); +void USCI1_SPI_SendData_16(uint16_t Data); +uint16_t USCI1_SPI_ReceiveData_16(void); +void USCI1_TWI_Slave_Init(uint8_t TWI_Address); +void USCI1_TWI_MasterCommunicationRate(USCI1_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate); +void USCI1_TWI_Start(void); +void USCI1_TWI_MasterModeStop(void); +void USCI1_TWI_SlaveClockExtension(FunctionalState NewState); +void USCI1_TWI_AcknowledgeConfig(FunctionalState NewState); +void USCI1_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus USCI1_GetTWIStatus(USCI1_TWIState_TypeDef USCI1_TWIState); +void USCI1_TWI_Cmd(FunctionalState NewState); +void USCI1_TWI_SendData(uint8_t Data); +uint8_t USCI1_TWI_ReceiveData(void); +void USCI1_UART_Init(uint32_t UART1Fsys, uint32_t BaudRate, USCI1_UART_Mode_TypeDef Mode, + USCI1_UART_RX_TypeDef RxMode); +void USCI1_UART_SendData8(uint8_t Data); +uint8_t USCI1_UART_ReceiveData8(void); +void USCI1_UART_SendData9(uint16_t Data); +uint16_t USCI1_UART_ReceiveData9(void); +void USCI1_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus USCI1_GetFlagStatus(USCI1_Flag_TypeDef USCI1_FLAG); +void USCI1_ClearFlag(USCI1_Flag_TypeDef USCI1_FLAG); +void USCI1_TWI_SendAddr(uint8_t Addr, USCI1_TWI_RWType RW); +#endif + +/******************* (C) COPYRIGHT 2019 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci2.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci2.h new file mode 100644 index 0000000..9b82bf0 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_usci2.h @@ -0,0 +1,168 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_usci2.h +// : +// ģ鹦 : USCI2̼⺯ͷļ +// : 2022/01/05 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#ifndef _sc92f_USCI2_H_ +#define _sc92f_USCI2_H_ + +#include "sc92f.h" + +#define USCI2_UART_BaudRate_FsysDIV12 0X00 //ģʽ0ãж˿ϵͳʱӵ1/12 +#define USCI2_UART_BaudRate_FsysDIV4 0X01 //ģʽ0ãж˿ϵͳʱӵ1/4 + +typedef enum +{ + USCI2_Mode_SPI = (uint8_t)0x01, //SPI + USCI2_Mode_TWI = (uint8_t)0x02, //TWI + USCI2_Mode_UART = (uint8_t)0x03 //UART +} USCI2_CommunicationMode_TypeDef; + +typedef enum +{ + USCI2_SPI_FIRSTBIT_MSB = (uint8_t)0x00, //MSBȷ + USCI2_SPI_FIRSTBIT_LSB = (uint8_t)0x04 //LSBȷ +} USCI2_SPI_FirstBit_TypeDef; + +typedef enum +{ + USCI2_SPI_BAUDRATEPRESCALER_1 = (uint8_t)0x00, //SPIʱΪϵͳʱӳ1 + USCI2_SPI_BAUDRATEPRESCALER_2 = (uint8_t)0x01, //SPIʱΪϵͳʱӳ2 + USCI2_SPI_BAUDRATEPRESCALER_4 = (uint8_t)0x02, //SPIʱΪϵͳʱӳ4 + USCI2_SPI_BAUDRATEPRESCALER_8 = (uint8_t)0x03, //SPIʱΪϵͳʱӳ8 + USCI2_SPI_BAUDRATEPRESCALER_16 = (uint8_t)0x04, //SPIʱΪϵͳʱӳ16 + USCI2_SPI_BAUDRATEPRESCALER_32 = (uint8_t)0x05, //SPIʱΪϵͳʱӳ32 + USCI2_SPI_BAUDRATEPRESCALER_64 = (uint8_t)0x06, //SPIʱΪϵͳʱӳ64 + USCI2_SPI_BAUDRATEPRESCALER_128 = (uint8_t)0x07 //SPIʱΪϵͳʱӳ128 +} USCI2_SPI_BaudRatePrescaler_TypeDef; + +typedef enum +{ + USCI2_SPI_MODE_MASTER = (uint8_t)0x20, //SPIΪ豸 + USCI2_SPI_MODE_SLAVE = (uint8_t)0x00 //SPIΪ豸 +} USCI2_SPI_Mode_TypeDef; + +typedef enum +{ + USCI2_SPI_CLOCKPOLARITY_LOW = (uint8_t)0x00, //SCKڿ״̬Ϊ͵ƽ + USCI2_SPI_CLOCKPOLARITY_HIGH = (uint8_t)0x10 //SCKڿ״̬Ϊߵƽ +} USCI2_SPI_ClockPolarity_TypeDef; + +typedef enum +{ + USCI2_SPI_CLOCKPHASE_1EDGE = (uint8_t)0x00, //SCKĵһزɼ + USCI2_SPI_CLOCKPHASE_2EDGE = (uint8_t)0x08 //SCKĵڶزɼ +} USCI2_SPI_ClockPhase_TypeDef; + +typedef enum +{ + USCI2_SPI_TXE_DISINT = (uint8_t)0x00, //TBIEΪ0ʱж + USCI2_SPI_TXE_ENINT = (uint8_t)0x01 //TBIEΪ1ʱж +} USCI2_SPI_TXE_INT_TypeDef; + +typedef enum +{ + USCI2_SPI_DATA8 = (uint8_t)0x00, //SPI 8λģʽ + USCI2_SPI_DATA16 = (uint8_t)0x01 //SPI 16λģʽ +} USCI2_TransmissionMode_TypeDef; + +typedef enum +{ + USCI2_TWI_1024 = (uint8_t)0x00, //TWIͨ Fhrc/1024 + USCI2_TWI_512 = (uint8_t)0x01, //TWIͨ Fhrc/512 + USCI2_TWI_256 = (uint8_t)0x02, //TWIͨ Fhrc/256 + USCI2_TWI_128 = (uint8_t)0x03, //TWIͨ Fhrc/128 + USCI2_TWI_64 = (uint8_t)0x04, //TWIͨ Fhrc/64 + USCI2_TWI_32 = (uint8_t)0x05, //TWIͨ Fhrc/32 + USCI2_TWI_16 = (uint8_t)0x06, //TWIͨ Fhrc/16 +} USCI2_TWI_MasterCommunicationRate_TypeDef; + +typedef enum +{ + USCI2_TWI_SlaveBusy = 0x00, + USCI2_TWI_SlaveReceivedaAddress = 0x01, + USCI2_TWI_SlaveReceivedaData = 0x02, + USCI2_TWI_SlaveSendData = 0x03, + USCI2_TWI_SlaveReceivedaUACK = 0x04, + USCI2_TWI_SlaveDisableACK = 0x05, + USCI2_TWI_SlaveAddressError = 0x06, + USCI2_TWI_MasterBusy = 0x00, + USCI2_TWI_MasterSendAddress = 0x01, + USCI2_TWI_MasterSendData = 0x02, + USCI2_TWI_MasterReceivedaData = 0x03, + USCI2_TWI_MasterReceivedaUACK = 0x04, +} USCI2_TWIState_TypeDef; + +typedef enum +{ + USCI2_UART_Mode_8B = 0X00, //UARTΪ8λģʽ + USCI2_UART_Mode_10B = 0X40, //UARTΪ10λģʽ + USCI2_UART_Mode_11B = 0X80 //UARTΪ11λģʽ +} USCI2_UART_Mode_TypeDef; + +typedef enum +{ + USCI2_UART_RX_ENABLE = 0X10, //UART + USCI2_UART_RX_DISABLE = 0X00 //UARTֹ +} USCI2_UART_RX_TypeDef; + +typedef enum +{ + USCI2_SPI_FLAG_SPIF = (uint8_t)0x80, //SPIݴͱ־λSPIF + USCI2_SPI_FLAG_WCOL = (uint8_t)0x50, //SPIдͻ־λWCOL + USCI2_SPI_FLAG_TXE = (uint8_t)0x08, //SPIͻձ־TXE + USCI2_TWI_FLAG_TWIF = (uint8_t)0x40, //TWIжϱ־λTWIF + USCI2_TWI_FLAG_GCA = (uint8_t)0x10, //TWIͨõַӦ־λGCA + USCI2_TWI_FLAG_MSTR = (uint8_t)0x20, //TWIӱ־λMSTR + USCI2_TWI_FLAG_TXRXnE = (uint8_t)0x80, + USCI2_UART_FLAG_RI = (uint8_t)0x01, //UARTжϱ־λRI + USCI2_UART_FLAG_TI = (uint8_t)0x02, //UARTжϱ־λTI +} USCI2_Flag_TypeDef; + +typedef enum +{ + USCI2_TWI_Write = 0x00, //д + USCI2_TWI_Read = 0x01, // +} USCI2_TWI_RWType; + +void USCI2_DeInit(void); +void USCI2_SPI_Init(USCI2_SPI_FirstBit_TypeDef FirstBit, + USCI2_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI2_SPI_Mode_TypeDef Mode, + USCI2_SPI_ClockPolarity_TypeDef ClockPolarity, USCI2_SPI_ClockPhase_TypeDef ClockPhase, + USCI2_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI2_TransmissionMode_TypeDef TransmissionMode); +void USCI2_TransmissionMode(USCI2_TransmissionMode_TypeDef TransmissionMode); +void USCI2_SPI_Cmd(FunctionalState NewState); +void USCI2_SPI_SendData_8(uint8_t Data); +uint8_t USCI2_SPI_ReceiveData_8(void); +void USCI2_SPI_SendData_16(uint16_t Data); +uint16_t USCI2_SPI_ReceiveData_16(void); +void USCI2_TWI_Slave_Init(uint8_t TWI_Address); +void USCI2_TWI_MasterCommunicationRate(USCI2_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate); +void USCI2_TWI_Start(void); +void USCI2_TWI_MasterModeStop(void); +void USCI2_TWI_SlaveClockExtension(FunctionalState NewState); +void USCI2_TWI_AcknowledgeConfig(FunctionalState NewState); +void USCI2_TWI_GeneralCallCmd(FunctionalState NewState); +FlagStatus USCI2_GetTWIStatus(USCI2_TWIState_TypeDef USCI2_TWIState); +void USCI2_TWI_Cmd(FunctionalState NewState); +void USCI2_TWI_SendData(uint8_t Data); +uint8_t USCI2_TWI_ReceiveData(void); +void USCI2_UART_Init(uint32_t UART1Fsys, uint32_t BaudRate, USCI2_UART_Mode_TypeDef Mode, + USCI2_UART_RX_TypeDef RxMode); +void USCI2_UART_SendData8(uint8_t Data); +uint8_t USCI2_UART_ReceiveData8(void); +void USCI2_UART_SendData9(uint16_t Data); +uint16_t USCI2_UART_ReceiveData9(void); +void USCI2_ITConfig(FunctionalState NewState, PriorityStatus Priority); +FlagStatus USCI2_GetFlagStatus(USCI2_Flag_TypeDef USCI2_FLAG); +void USCI2_ClearFlag(USCI2_Flag_TypeDef USCI2_FLAG); +void USCI2_TWI_SendAddr(uint8_t Addr, USCI2_TWI_RWType RW); +#endif + +/******************* (C) COPYRIGHT 2019 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/inc/sc92f_wdt.h b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_wdt.h new file mode 100644 index 0000000..e0bdf38 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/inc/sc92f_wdt.h @@ -0,0 +1,43 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_wdt.h +// : +// ģ鹦: WDT̼⺯ͷļ +// : 2022323 +// 汾: V1.10002 +// ˵: +//************************************************************* + +#ifndef _sc92f_WDT_H_ +#define _sc92f_WDT_H_ + +#include "sc92f.h" + +typedef enum +{ + WDT_OverflowTime_500MS = (uint8_t)0x00, //ŹʱΪ500MS + WDT_OverflowTime_250MS = (uint8_t)0x01, //ŹʱΪ250MS + WDT_OverflowTime_125MS = (uint8_t)0x02, //ŹʱΪ125MS + WDT_OverflowTime_62_5MS = (uint8_t)0x03, //ŹʱΪ62.5MS + WDT_OverflowTime_31_5MS = (uint8_t)0x04, //ŹʱΪ31.5MS + WDT_OverflowTime_15_75MS = (uint8_t)0x05, //ŹʱΪ15.75MS + WDT_OverflowTime_7_88MS = (uint8_t)0x06, //ŹʱΪ7.88MS + WDT_OverflowTime_3_94MS = (uint8_t)0x07 //ŹʱΪ3.94MS +} WDT_OverflowTime_TypeDef; + +/************************꺯************************/ +/***************************************************** +*:void WDT_SetReload(void) +*:WDTι +*ڲ:void +*ڲ:void +*****************************************************/ +#define WDT_SetReload() SET_BIT(WDTCON,0x10) + +void WDT_DeInit(void); +void WDT_Init(WDT_OverflowTime_TypeDef + OverflowTime); +void WDT_Cmd(FunctionalState NewState); +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_acmp.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_acmp.c new file mode 100644 index 0000000..039b3b4 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_acmp.c @@ -0,0 +1,129 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_acmp.c +// : +// ģ鹦 : ACMP̼⺯Cļ +// ֲб: +// : 2020/8/18 +// 汾 : V1.00000 +// ˵ : +//************************************************************* + +#include "sc92f_acmp.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) +/************************************************** +*:void ACMP_DeInit(void) +*:MDUؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void ACMP_DeInit(void) +{ + CMPCON = 0X00; + CMPCFG = 0X00; +} + +/************************************************** +*:void ACMP_Init(ACMP_Vref_Typedef ACMP_Vref, ACMP_Channel_TypeDef ACMP_Channel) +*:ģȽʼú +*ڲ: +ACMP_Vref_Typedef:ACMP_Vref:ACMPοѹѡ +ACMP_Channel_TypeDef:ACMP_Channel:ACMPͨѡ +*ڲ:void +**************************************************/ +void ACMP_Init(ACMP_Vref_Typedef ACMP_Vref, + ACMP_Channel_TypeDef ACMP_Channel) +{ + CMPCON = CMPCON & 0XF0 | ACMP_Vref; + CMPCFG = CMPCFG & 0XEC | ACMP_Channel; +} + +/************************************************** +*:void ACMP_SetTriggerMode(ACMP_TriggerMode_Typedef ACMP_TriggerMode) +*:ACMPжϴʽú +*ڲ: +ACMP_TriggerMode_Typedef:ACMP_TriggerMode:жϴʽѡ +*ڲ:void +**************************************************/ +void ACMP_SetTriggerMode(ACMP_TriggerMode_Typedef + ACMP_TriggerMode) +{ + CMPCFG = CMPCFG & 0XF3 | ACMP_TriggerMode; +} + +/***************************************************** +*:void ACMP_Cmd(FunctionalState NewState) +*:ACMPܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void ACMP_Cmd(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + CMPCON &= 0X7F; + } + else + { + CMPCON |= 0x80; + } +} + +/***************************************************** +*:void ACMP_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:ACMPжϳʼ +*ڲ:FunctionalState:NewState:жʹ/رѡ + PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void ACMP_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState == DISABLE) + { + IE1 &= 0XBF; + } + else + { + IE1 |= 0X20; + } + + /************************************************************/ + if(Priority == LOW) + { + IP1 &= 0XBF; + } + else + { + IP1 |= 0X20; + } +} + +/***************************************************** +*:FlagStatus ACMP_GetFlagStatus(ACMP_Flag_TypeDef ACMP_Flag) +*:ACMP־״̬ +*ڲ:ACMP_Flag ־λѡ +*ڲ: +ACMP_Flag_TypeDef:FlagStatus:ACMP־״̬ +*****************************************************/ +FlagStatus ACMP_GetFlagStatus(ACMP_Flag_TypeDef + ACMP_Flag) +{ + return (bool)(CMPCON & ACMP_Flag); +} + +/***************************************************** +*:void ACMP_ClearFlag(void) +*:־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void ACMP_ClearFlag(void) +{ + CMPCON &= (~ACMP_FLAG_CMPIF); +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_adc.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_adc.c new file mode 100644 index 0000000..37c01a6 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_adc.c @@ -0,0 +1,462 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_adc.c +// : ԪӦŶ +// ģ鹦: ADC̼⺯Cļ +// : 2022323 +// 汾: V1.10005 +// ˵: +//************************************************************* + +/* ͷļ */ +#include "sc92f_adc.h" + +#if !defined(SC92F827X) && !defined(SC92F837X) +/************************************************** +*:void ADC_DeInit(void) +*:ADCؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void ADC_DeInit(void) +{ + ADCCON = 0x00; + ADCCFG0 = 0X00; + ADCCFG1 = 0X00; +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F84Ax) || defined(SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F848x) || defined(SC92F748x) || defined (SC92F859x) || defined (SC92F759x)\ + || defined (SC92L853x) || defined (SC92L753x) + ADCCFG2 = 0X00; +#endif + ADCVL = 0X00; + ADCVH = 0X00; + EADC = 0; + IPADC = 0; +} + +/************************************************** +*:void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, ADC_Cycle_TypeDef ADC_Cycle) +*:ADCʼú +*ڲ: +ADC_PresSel_TypeDef:ADC_PrescalerSelection:ԤƵѡ +ADC_Cycle_TypeDef:ADC_Cycle:ʱѡ +*ڲ:void +**************************************************/ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F84Ax) || defined(SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92FWxx) || defined(SC92F848x) || defined(SC92F748x)\ + || defined (SC92F859x) || defined (SC92F759x) +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, + ADC_Cycle_TypeDef ADC_Cycle) +{ + /* ADCʱӷƵͲ */ + ADCCFG2 = ADC_PrescalerSelection | ADC_Cycle; +} +#elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, + ADC_Cycle_TypeDef ADC_Cycle) +{ + /* ADCʱӷƵͲ */ + ADCCFG1 = ADC_PrescalerSelection | ADC_Cycle; +} +#elif defined(SC92F742x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F730x) || defined(SC92F732X) || defined(SC92F7490)\ + || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, + ADC_Cycle_TypeDef ADC_Cycle) +{ + ADC_Cycle = 0; //SC92F742x޴˹ + /* ADCʱӷƵ */ + ADCCON = (ADCCON & 0xDF) | ADC_PrescalerSelection; +} +#elif defined (SC92L853x) || defined (SC92L753x) +void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, ADC_Cycle_TypeDef ADC_Cycle) +{ + ADC_Cycle = 0x00; //92LϵЧ + /* ADCʱӷƵ */ + ADCCFG2 = ADC_PrescalerSelection; +} +#endif + +/************************************************** +*:void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +*:ADCúʹع +*ڲ: +ADC_Channel_TypeDef:ADC_Channel:ADCѡ +FunctionalState:NewState:ADCxʹ/رѡ +*ڲ:void +**************************************************/ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F84Ax) || defined(SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92FWxx) || defined(SC92F848x) || defined(SC92F748x)\ + || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +{ + uint16_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0XE0) | ADC_Channel; + + /* ADCⲿͨ */ + if (ADC_Channel < ADC_CHANNEL_VDD_D4) //ڲͨ + { + TempReg = (0x0001 << ADC_Channel); + if (NewState == DISABLE)// ʹADCͨ + { + ADCCFG0 &= (~(uint8_t)TempReg); + ADCCFG1 &= (~(uint8_t)(TempReg >> 8)); + } + else // ʧADCͨ + { + ADCCFG0 |= ((uint8_t)TempReg); + ADCCFG1 |= ((uint8_t)(TempReg >> 8)); + } + } +} +#elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) || defined(SC92F7490) +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +{ + uint8_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0xE0) | ADC_Channel; + + /* ADCͨ */ + if (ADC_Channel < ADC_CHANNEL_VDD_D4) //ڲͨ + { + TempReg = (0x01 << ADC_Channel); + if (ADC_Channel < ADC_CHANNEL_VDD_D4) + { + if (NewState == DISABLE) //ʧADCͨ + { + ADCCFG0 &= (~TempReg); + } + else //ʹADCͨ + { + ADCCFG0 |= TempReg; + } + } + } +} +#elif defined(SC92F742x) || defined(SC92F730x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F732X) +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +{ + uint16_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0xF0) | ADC_Channel; + + /* ADCͨ */ + if (ADC_Channel < ADC_CHANNEL_VDD_D4) //ڲͨ + { + TempReg = (0x0001 << ADC_Channel); + if (NewState == DISABLE) + { + ADCCFG0 &= (~(uint8_t)TempReg); + ADCCFG1 &= (~(uint8_t)(TempReg >> 8)); + } + else + { + ADCCFG0 |= ((uint8_t)TempReg); + ADCCFG1 |= ((uint8_t)(TempReg >> 8)); + } + } +} +#elif defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) +{ + uint16_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0xF0) | ADC_Channel; + + /* ADCͨ */ + if (ADC_Channel < ADC_CHANNEL_Temp) //ⲿͨ + { + TempReg = (0x0001 << ADC_Channel); + if (NewState == DISABLE) + { + ADCCFG0 &= (~(uint8_t)TempReg); + ADCCFG1 &= (~(uint8_t)(TempReg >> 8)); + } + else + { + ADCCFG0 |= ((uint8_t)TempReg); + ADCCFG1 |= ((uint8_t)(TempReg >> 8)); + } + } + else if (ADC_Channel == ADC_CHANNEL_Temp) //ڲ¶Ȳͨ + { + if (NewState == DISABLE) + { + TSCFG &= 0X7F; + } + else + { + /* ADCοѹѡڲ2.4VΪο */ + OPINX = 0xC2; + OPREG = OPREG & 0X7F | 0x80; + + TSCFG |= 0x80; + } + } + else if (ADC_Channel == ADC_CHANNEL_9_PGA) //ɱŴͨ + { + unsigned char code *IFBAddr = 0x3D; + if (NewState == DISABLE) + { + ADCCFG1 &= (~(uint8_t)0x02); //رͨ9 + PGACON &= 0x7F; //ʹPGA + } + /* ȡPGAڲУ׼ֵ */ + else + { + ADCCFG1 |= ((uint8_t)0x02); //PGAͨͨ9ãʹͨ9 + + IAPADE = 0x01; //ָָ IFB + PGACFG = *(IFBAddr); //ȡУ׼ֵ + IAPADE = 0x00; //ָָ ROM + + PGACON |= 0x80; //ʹPGA + } + } +} +#endif + +/************************************************** +*:void ADC_EAINConfig(uint16_t ADC_Channel, FunctionalState NewState) +*:ӦADCΪģģʽ +*ڲ: +ADC_EAIN_TypeDef:ADC_EAIN_Select:ѡҪõADC +FunctionalState:NewState:ADCͨʹ/رѡ +*ڲ:void +**************************************************/ +void ADC_EAINConfig(uint16_t ADC_EAIN_Select, + FunctionalState NewState) +{ + if (NewState == DISABLE) + { + ADCCFG0 &= (~(uint8_t)ADC_EAIN_Select); +#if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)||defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined (SC92F759x)\ + || defined (SC92L853x) || defined (SC92L753x) + ADCCFG1 &= (~(uint8_t)(ADC_EAIN_Select >> 8)); +#endif + } + else + { + ADCCFG0 |= ((uint8_t)ADC_EAIN_Select); +#if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined (SC92F759x)\ + || defined (SC92L853x) || defined (SC92L753x) + ADCCFG1 |= ((uint8_t)(ADC_EAIN_Select >> 8)); +#endif + } +} +/***************************************************** +*:void ADC_Cmd(FunctionalState NewState) +*:ADCܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void ADC_Cmd(FunctionalState NewState) +{ + if (NewState == DISABLE) + { + ADCCON &= 0X7F; + } + else + { + ADCCON |= 0x80; + } +} + +/***************************************************** +*:uint16_t ADC_GetConversionValue(void) +*:һADת +*ڲ:void +*ڲ:uint16_t +*****************************************************/ +unsigned int ADC_GetConversionValue(void) +{ + return ((ADCVH << 4) + (ADCVL >> 4)); +} + +/***************************************************** +*:FlagStatus ADC_GetFlagStatus(void) +*:ADCжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:ADCжϱ־״̬ +*****************************************************/ +FlagStatus ADC_GetFlagStatus(void) +{ +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)||defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined (SC92F83Ax) || defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) || defined (SC92FWxx)\ + || defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + return (bool)(ADCCON & 0x20); +#elif defined(SC92F742x) || defined(SC92F730x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F732X) || defined(SC92F7490) || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) + return (bool)(ADCCON & 0x10); +#endif +} + +/***************************************************** +*:void ADC_ClearFlag(void) +*:ADCжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void ADC_ClearFlag(void) +{ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC92F84Ax) || defined(SC92F74Ax)\ + || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F8003) || defined(SC92F740x) || defined(SC92F848x) || defined(SC92F748x)\ + || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + ADCCON &= 0xdf; +#endif +#if defined(SC92F742x) || defined(SC92F730x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F732X) || defined(SC92F7490) || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) + ADCCON &= 0xef; +#endif +} + +#if defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) +unsigned int ADC_TS_StandardData = 0x8000; + +/***************************************************** +*:void ADC_TSCmd(PriorityStatus NewState) +*:ADC ¶ȴܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void ADC_TSCmd(FunctionalState NewState) +{ + if (NewState == DISABLE) + { + TSCFG &= 0X7F; + } + else + { + TSCFG |= 0X80; + } +} + +/***************************************************** +*:void ADC_CHOPConfig(PriorityStatus NewState) +*:߻͵offsetӦÿλ +*ڲ: +PriorityStatus:NewState:¶ȴ/ѡ +*ڲ:void +*****************************************************/ +void ADC_CHOPConfig(PriorityStatus NewState) +{ + if (NewState == LOW) + { + TSCFG &= 0XFE; + } + else + { + TSCFG |= 0x01; + } +} + +/***************************************************** +*:void ADC_CHOPConfig(PriorityStatus NewState) +*:ȡʱADC 25ʱתֵ +*ڲ:void +*ڲ:void +*****************************************************/ +uint16_t ADC_Get_TS_StandardData(void) +{ + unsigned int code *IFBAddr = 0x3E; + IAPADE = 0x01; //ָָ IFB + ADC_TS_StandardData = *(IFBAddr); + IAPADE = 0x00; //ָָ ROM + return ADC_TS_StandardData; +} + +/***************************************************** +*:void ADC_GetTSValue(void) +*:ֱӻȡfloat¶ֵȡ¶ʱرж +*ڲ:void +*ڲ: +float:¶ֵ +*****************************************************/ +float ADC_GetTSValue(void) +{ + unsigned char EADC_Flag = EADC; //ȡEA־λ״̬ + unsigned int ADC_Value1 = 0, ADC_Value2 = 0, ADC_Value = 0; + unsigned int code *IFBAddr = 0x3E; + + ADC_Get_TS_StandardData(); + disableInterrupts(); //رж + ADC_CHOPConfig(LOW); //͵offsetӦÿλ + ADC_StartConversion(); //ʼADת + while(!ADC_GetFlagStatus()); //ȴת + ADC_ClearFlag(); //ת־λ + ADC_Value1 = ADC_GetConversionValue(); //ȡһADתֵ + ADC_CHOPConfig(HIGH); //ߵoffsetӦÿλ + ADC_StartConversion(); //ʼADת + while(!ADC_GetFlagStatus()); //ȴת + ADC_ClearFlag(); //ת־λ + ADC_Value2 = ADC_GetConversionValue(); //ȡڶADתֵ + ADC_Value = (ADC_Value1 + ADC_Value2) / 2; //ȡADƽֵ + + if (EADC_Flag) //ԭǰEA־λ + { + enableInterrupts(); + } + return (25 + ((float)ADC_Value - (float)ADC_TS_StandardData) / 8); +} + +/***************************************************** +*:ADC_PGAConfig(ADC_PGACOM_TypeDef ADC_PGACOM,ADC_PGAGAN_TypeDef ADC_PGAGAN,ADC_PGAIPT_TypeDef ADC_PGAIPT) +*:PGA +*ڲ: +ADC_PGACOM_TypeDef:ADC_PGACOM:PGAģѹѡ +ADC_PGAGAN_TypeDef:ADC_PGAGAN:PGAŴ +ADC_PGAIPT_TypeDef:ADC_PGAIPT:PGAͬ/ѡ +*ڲ:void +*****************************************************/ +void ADC_PGAConfig(ADC_PGACOM_TypeDef ADC_PGACOM, ADC_PGAGAN_TypeDef ADC_PGAGAN, ADC_PGAIPT_TypeDef ADC_PGAIPT) +{ + PGACON &= 0x8F; + PGACON |= (ADC_PGACOM | ADC_PGAGAN | ADC_PGAIPT); +} + +/***************************************************** +*:void ADC_PGACmd(PriorityStatus NewState) +*:ADC PGAܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void ADC_PGACmd(PriorityStatus NewState) +{ + if (NewState == LOW) + { + PGACON &= 0XFE; + } + else + { + PGACON |= 0x01; + } +} +#endif + + +/***************************************************** +*:void ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) +*:ADC οѹѡ +*ڲ: +ADC_Vref_TypeDef:ADC_Vref:ѡADCοѹ +*ڲ:void +*****************************************************/ +void ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) +{ + OPINX = 0xC2; + OPREG = OPREG & 0X7F | ADC_Vref; +} +#endif + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_btm.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_btm.c new file mode 100644 index 0000000..e14a5ad --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_btm.c @@ -0,0 +1,78 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_btm.c +// : ԪӦŶ +// ģ鹦: BTM̼⺯Cļ +// ֲб: +// : 202242 +// 汾: V1.10002 +// ˵: +//************************************************************* + +#include "sc92f_btm.h" + + +/************************************************** +*:void BTM_Init(BTM_Timebase_TypeDef BTM_Timebase) +*:BTMʼú +*ڲ: +BTM_Timebase_TypeDef:BTM_Timebase:BTMʱѡ +*ڲ:void +**************************************************/ +void BTM_Init(BTM_Timebase_TypeDef BTM_Timebase) +{ + BTMCON = (BTMCON & 0xF0) | BTM_Timebase; //ʱ +} + +/***************************************************** +*:void BTM_Cmd(FunctionalState NewState) +*:BTMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void BTM_Cmd(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + BTMCON &= 0x7f; //ʧBTM + } + else + { + BTMCON |= 0x80; //ʹBTM + } +} + +/***************************************************** +*:void BTM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:BTMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void BTM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + //жʹ + if(NewState == DISABLE) + { + IE1 &= 0xfb; + } + else + { + IE1 |= 0x04; + } + + //жȼ + if(Priority == LOW) + { + IP1 &= 0xfb; + } + else + { + IP1 |= 0x04; + } +} + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_chksum.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_chksum.c new file mode 100644 index 0000000..24412e7 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_chksum.c @@ -0,0 +1,59 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_chksum.c +// : +// ģ鹦 : CHKSUM̼⺯Cļ +// : 2021/08/20 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#include "sc92f_chksum.h" + +#if defined(SC92F7003) || defined(SC92F8003) || defined(SC92F736xB) || defined(SC92F836xB) || defined(SC92F740x) || defined(SC92F742x)\ + || defined(SC92F73Ax) || defined(SC92F83Ax) || defined(SC92F744xB) || defined(SC92F844xB) || defined(SC92F746xB) || defined(SC92F846xB)\ + || defined(SC92F748x) || defined(SC92F848x) || defined(SC92F74Ax) || defined(SC92F84Ax) || defined(SC92F74Ax_2) || defined(SC92F84Ax_2)\ + || defined(SC92F754x) || defined (SC92F854x) || defined (SC92F759x) || defined(SC92F859x) || defined (SC92F7490) || defined(SC92FWxx)\ + || defined(SC92F827X) || defined(SC92F847X) +/************************************************** +*:void CHKSUM_DeInit(void) +*:CHKSUMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void CHKSUM_DeInit(void) +{ + OPERCON &= 0XFE; + CHKSUML = 0X00; + CHKSUMH = 0X00; +} + +/************************************************** +*:void CHKSUM_StartOperation(void) +*:һcheck sum +*ڲ:void +*ڲ:void +**************************************************/ +void CHKSUM_StartOperation(void) +{ + OPERCON |= 0X01; + + while(OPERCON & 0x01); +} + +/************************************************** +*:uint16_t CHKSUM_GetCheckValue(void) +*:ȡһcheck sumֵ +*ڲ:void +*ڲ: +uint16_t:check sumֵ +**************************************************/ +uint16_t CHKSUM_GetCheckValue(void) +{ + uint16_t checktemp; + checktemp = (uint16_t)(CHKSUMH << 8) + + (uint16_t)CHKSUML; + return checktemp; +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_crc.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_crc.c new file mode 100644 index 0000000..73fac1d --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_crc.c @@ -0,0 +1,97 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_CRC.c +// : +// ģ鹦 : CRC̼⺯Cļ +// : 2020/8/13 +// 汾 : V1.0000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_CRC.h" +#include "intrins.H" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:unsigned long CRC_All() +*:󱾹HEXCRC32УֵüOPTIONIAR Rangeͬ仯 +*ڲ:void +*ڲ: +uint32_t:CRC +**************************************************/ +uint32_t CRC_All() +{ + uint32_t CRC_Result; + OPERCON |= 0x01; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + CRCINX = 0x00; + CRC_Result = CRCREG; + CRC_Result = CRCREG * 256 + CRC_Result; + CRC_Result = CRCREG * 65536 + CRC_Result; + CRC_Result = CRCREG * 16777216 + CRC_Result; + return CRC_Result; +} + +/************************************************** +*:uint32_t CRC_Frame(uint8_t* buff,uint8_t Length) +*:֡CRCУֵ +*ڲ: +uint8_t*:buff:ҪCRC +uint8_t:Length:Ҫ鳤 +*ڲ: +uint32_t:CRC +**************************************************/ +uint32_t CRC_Frame(uint8_t *buff, uint8_t Length) +{ + uint8_t i; + uint32_t CRC_Result = 0; + + EA = 0; + OPERCON |= 0x02; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + + for (i = 0; i < Length; i++) + { + CRC_Result = *(buff + i); + CRCREG = CRC_Result; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + } + + CRCINX = 0x00; + CRC_Result = CRCREG; + CRC_Result = CRCREG * 256 + CRC_Result; + CRC_Result = CRCREG * 65536 + CRC_Result; + CRC_Result = CRCREG * 16777216 + CRC_Result; + EA = 1; + + return CRC_Result; +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_ddic.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_ddic.c new file mode 100644 index 0000000..eaf69f8 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_ddic.c @@ -0,0 +1,228 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ddic.c +// : +// ģ鹦 : DDIC̼⺯Cļ +// ֲб: +// : 2022/01/20 +// 汾 : V1.10002 +// ˵ : +//************************************************************* + +#include "sc92f_ddic.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + +#if defined (SC92L853x) || defined (SC92L753x) +uint8_t xdata LCDRAM[30] _at_ 0xF00; +#else +uint8_t xdata LCDRAM[30] _at_ 0x700; +#endif + +/************************************************** +*:void DDIC_DeInit(void) +*:DDICؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void DDIC_DeInit(void) +{ + DDRCON = 0X00; + P0VO = 0X00; + P1VO = 0X00; + P2VO = 0X00; +#if defined (SC92L853x) || defined (SC92L753x) + P5VO = 0X00; +#else + P3VO = 0X00; +#endif + OTCON &= 0XF0; +} + +/************************************************** +*:void DDIC_Init(uint8_t P0OutputPin) +*:DDICʼú +*ڲ: +DDIC_DutyCycle_TypeDef:DDIC_DutyCylce:LCD/LEDʾռձȿ +DDIC_Pin_TypeDef:P0OutputPin:P0ΪLCDѹ,ʹûöٵĶԱ +DDIC_Pin_TypeDef:P1OutputPin:P1ΪLCDѹ,ʹûöٵĶԱ +DDIC_Pin_TypeDef:P2OutputPin:P2ΪLCDѹ,ʹûöٵĶԱ +DDIC_Pin_TypeDef:P3OutputPin:P3ΪLCDѹ,ʹûöٵĶԱ + ע:ͺΪSC92L853xSC92L753xʱʵΪP5 +*ڲ:void +**************************************************/ +void DDIC_Init(DDIC_DutyCycle_TypeDef DDIC_DutyCylce, + uint8_t P0OutputPin, uint8_t P1OutputPin, + uint8_t P2OutputPin, uint8_t P3OutputPin) +{ + DDRCON = DDRCON & 0XCF | DDIC_DutyCylce; + P0VO = P0OutputPin; + P1VO = P1OutputPin; + P2VO = P2OutputPin; +#if defined (SC92L853x) || defined (SC92L753x) + P5VO = P3OutputPin; +#else + P3VO = P3OutputPin; +#endif +} + +/************************************************** +*:void DDIC_LEDConfig(void) +*:LEDú +*ڲ:void +*ڲ:void +**************************************************/ +void DDIC_LEDConfig(void) +{ + DDRCON |= 0X40; +} + +/************************************************** +*:void DDIC_LCDConfig(uint8_t LCDVoltage, + DDIC_ResSel_Typedef DDIC_ResSel, + DDIC_BiasVoltage_Typedef DDIC_BiasVoltage) +*:LCDú +*ڲ: +uint8_t:LCDVoltage:LCDѹ +DDIC_ResSel_Typedef:DDIC_ResSel:LCDѹڵѡ +DDIC_BiasVoltage_Typedef:DDIC_BiasVoltage:LCDʾƫõѹ +*ڲ:void +**************************************************/ +void DDIC_LCDConfig(uint8_t LCDVoltage, + DDIC_ResSel_Typedef DDIC_ResSel, + DDIC_BiasVoltage_Typedef DDIC_BiasVoltage) +{ + DDRCON = DDRCON & 0XB0 | LCDVoltage; + OTCON = OTCON & 0XF2 | DDIC_ResSel | DDIC_BiasVoltage; +} +/************************************************** +*:void DDIC_DMOD_Selcet(DDIC_DMOD_TypeDef DDIC_DMOD) +*:ʾģʽѡ +*ڲ: +DDIC_DMOD_TypeDef:DDIC_DMOD:ѡʾģʽ +*ڲ:void +**************************************************/ +void DDIC_DMOD_Selcet(DDIC_DMOD_TypeDef DDIC_DMOD) +{ + if(DDIC_DMOD == DMOD_LED) + { + DDRCON |= 0X40; + } + else + { + DDRCON &= 0XBF; + } +} +/***************************************************** +*:void DDIC_OutputPinOfDutycycleD4(DDIC_OutputPin_TypeDef DDIC_OutputPin) +*:1/4ռձʱsegmentcommonùܽѡ +*ڲ: +DDIC_OutputPin_TypeDef:DDIC_OutputPin:ܽѡ +*ڲ:void +*****************************************************/ +void DDIC_OutputPinOfDutycycleD4( + DDIC_OutputPin_TypeDef DDIC_OutputPin) +{ + OTCON &= ~0X02; + OTCON = DDIC_OutputPin<<1; +} + +/***************************************************** +*:void DDIC_Cmd(FunctionalState NewState) +*:ʾܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void DDIC_Cmd(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + DDRCON &= 0X7F; + } + else + { + DDRCON |= 0x80; + } +} + +/***************************************************** +*:void DDIC_Control(DDIC_Control_SEG_TypeDef DDIC_Seg,DDIC_Control_COM_TypeDef DDIC_Com,DDIC_Control_Status DDIC_Contr) +*:SEGCOMŶӦLCD/LED +*ڲ:DDIC_Control_SEG_TypeDef DDIC_Seg ѡƵSEG + DDIC_Control_COM_TypeDef DDIC_Com ѡƵCOM + DDIC_Control_Status DDIC_Contr ״̬ +*ڲ:void +*****************************************************/ +void DDIC_Control(DDIC_Control_SEG_TypeDef DDIC_Seg, + uint8_t DDIC_Com, + DDIC_Control_Status DDIC_Contr) +{ + if(DDIC_Contr) + { + LCDRAM[DDIC_Seg] |= DDIC_Com; + } + else + { + LCDRAM[DDIC_Seg] &= (~DDIC_Com); + } +} +#endif + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F83Ax) || defined (SC92F73Ax)\ + || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined (SC92F735X)\ + || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92F848x) || defined (SC92F748x) +/************************************************** +*:void DDIC_DeInit(void) +*:DDICؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void DDIC_DeInit(void) +{ + P0VO = 0X00; + OTCON &= 0XF3; +} + +/************************************************** +*:void DDIC_Init(uint8_t P0OutputPin) +*:DDICʼú +*ڲ: +DDIC_Pin_TypeDef:P0OutputPin:P0ΪLCDѹڣʹûöٵĶԱ +*ڲ:void +**************************************************/ +void DDIC_Init(uint8_t P0OutputPin) +{ + P0VO = P0OutputPin; +} + +/************************************************** +*:void DDIC_LCDConfig(DDIC_ResSel_Typedef DDIC_ResSel) +*:LCDú +*ڲ: +DDIC_ResSel_Typedef:DDIC_ResSel:LCDѹڵѡ +*ڲ:void +**************************************************/ +void DDIC_LCDConfig(DDIC_ResSel_Typedef DDIC_ResSel) +{ + OTCON = (OTCON & 0XF3) | DDIC_ResSel; +} + +/************************************************** +*:void DDIC_Config_Init(uint8_t P0OutputPin,DDIC_ResSel_Typedef DDIC_ResSel) +*:LCDʼú +*ڲ: +DDIC_Pin_TypeDef:P0OutputPin:P0ΪLCDѹڣʹûöٵĶԱ +DDIC_ResSel_Typedef:DDIC_ResSel:LCDѹڵѡ +*ڲ:void +**************************************************/ +void DDIC_Config_Init(uint8_t P0OutputPin, + DDIC_ResSel_Typedef DDIC_ResSel) +{ + P0VO = P0OutputPin; + OTCON = (OTCON & 0XF3) | DDIC_ResSel; +} + +#endif +/******************* (C) COPYRIGHT 2019 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_gpio.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_gpio.c new file mode 100644 index 0000000..d18e543 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_gpio.c @@ -0,0 +1,539 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_gpio.c +// : +// ģ鹦 : GPIO̼⺯Cļ +// ֲб : +// : 2022/01/11 +// 汾 : V1.10004 +// ˵ : ļԪ92F/93F/92LϵеƬ +//************************************************************* + + +#include "sc92f_gpio.h" + +/************************************************** +*:void GPIO_DeInit(void) +*:GPIOؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void GPIO_DeInit(void) +{ + P0CON = 0x00; + P0PH = 0x00; + P0 = 0; + P1CON = 0x00; + P1PH = 0x00; + P1 = 0; + P2CON = 0x00; + P2PH = 0x00; + P2 = 0; +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + P3CON = 0x00; + P3PH = 0x00; + P3 = 0; + P4CON = 0x00; + P4PH = 0x00; + P4 = 0; +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F7003) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) + P5CON = 0x00; + P5PH = 0x00; + P5 = 0; +#endif +} + +/************************************************** +*:void GPIO_Init(GPIO_TypeDef GPIOx, uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode) +*:GPIOģʽóʼ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOܽPxy +GPIO_Mode_TypeDef:GPIO_Mode:ѡGPIOģʽ롢롢 +*ڲ:void +**************************************************/ +void GPIO_Init(GPIO_TypeDef GPIOx, + uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode) +{ + if (GPIOx == GPIO0) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P0CON &= ~PortPins; + P0PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P0CON &= ~PortPins; + P0PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P0CON |= PortPins; + } + } + else if (GPIOx == GPIO1) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P1CON &= ~PortPins; + P1PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P1CON &= ~PortPins; + P1PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P1CON |= PortPins; + } + } + else if (GPIOx == GPIO2) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P2CON &= ~PortPins; + P2PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P2CON &= ~PortPins; + P2PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P2CON |= PortPins; + } + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + else if (GPIOx == GPIO3) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P3CON &= ~PortPins; + P3PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P3CON &= ~PortPins; + P3PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P3CON |= PortPins; + } + } + else if (GPIOx == GPIO4) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P4CON &= ~PortPins; + P4PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P4CON &= ~PortPins; + P4PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P4CON |= PortPins; + } + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F7003) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) + else if (GPIOx == GPIO5) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P5CON &= ~PortPins; + P5PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P5CON &= ~PortPins; + P5PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P5CON |= PortPins; + } + } + +#endif +} + +/************************************************** +*:void GPIO_Write(GPIO_TypeDef GPIOx, uint8_t PortVal) +*:GPIOڸֵ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +uint8_t:PortVal:GPIOڵֵ +*ڲ:void +**************************************************/ +void GPIO_Write(GPIO_TypeDef GPIOx, + uint8_t PortVal) +{ + if (GPIOx == GPIO0) + { + P0 = PortVal; + } + + if (GPIOx == GPIO1) + { + P1 = PortVal; + } + + if (GPIOx == GPIO2) + { + P2 = PortVal; + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + + if (GPIOx == GPIO3) + { + P3 = PortVal; + } + + if (GPIOx == GPIO4) + { + P4 = PortVal; + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + + if (GPIOx == GPIO5) + { + P5 = PortVal; + } + +#endif +} + +/************************************************** +*:void GPIO_WriteHigh(GPIO_TypeDef GPIOx, uint8_t PortPins) +*:GPIOڹܽPxyλ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy +*ڲ:void +**************************************************/ +void GPIO_WriteHigh(GPIO_TypeDef GPIOx, + uint8_t PortPins) +{ + if (GPIOx == GPIO0) + { + P0 |= PortPins; + } + + if (GPIOx == GPIO1) + { + P1 |= PortPins; + } + + if (GPIOx == GPIO2) + { + P2 |= PortPins; + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + + if (GPIOx == GPIO3) + { + P3 |= PortPins; + } + + if (GPIOx == GPIO4) + { + P4 |= PortPins; + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + + if (GPIOx == GPIO5) + { + P5 |= PortPins; + } + +#endif +} + +/************************************************** +*:void GPIO_WriteLow(GPIO_TypeDef GPIOx, uint8_t PortPins) +*:GPIOڹܽPxyλ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy +*ڲ:void +**************************************************/ +void GPIO_WriteLow(GPIO_TypeDef GPIOx, + uint8_t PortPins) +{ + if (GPIOx == GPIO0) + { + P0 &= ~PortPins; + } + + if (GPIOx == GPIO1) + { + P1 &= ~PortPins; + } + + if (GPIOx == GPIO2) + { + P2 &= ~PortPins; + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + + if (GPIOx == GPIO3) + { + P3 &= ~PortPins; + } + + if (GPIOx == GPIO4) + { + P4 &= ~PortPins; + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + + if (GPIOx == GPIO5) + { + P5 &= ~PortPins; + } + +#endif +} + +/************************************************** +*:uint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx) +*:GPIOPxֵ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +*ڲ:uint8_t Pxֵ +**************************************************/ +uint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx) +{ + if (GPIOx == GPIO0) + { + return P0; + } + else if (GPIOx == GPIO1) + { + return P1; + } + else if (GPIOx == GPIO2) + { + return P2; + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + else if (GPIOx == GPIO3) + { + return P3; + } + else if (GPIOx == GPIO4) + { + return P4; + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + else if (GPIOx == GPIO5) + { + return P5; + } + +#endif + else + { + return 0; + } +} + +/************************************************** +*:BitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, uint8_t PortPins) +*:GPIOڹܽPxyֵ +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy +*ڲ:BitStatus Pxyֵ +**************************************************/ +BitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, + uint8_t PortPins) +{ + if (GPIOx == GPIO0) + { + return ((bit)(P0 & PortPins)); + } + else if (GPIOx == GPIO1) + { + return ((bit)(P1 & PortPins)); + } + else if (GPIOx == GPIO2) + { + return ((bit)(P2 & PortPins)); + } + +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + else if (GPIOx == GPIO3) + { + return ((bit)(P3 & PortPins)); + } + else if (GPIOx == GPIO4) + { + return ((bit)(P4 & PortPins)); + } + +#endif +#if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + else if (GPIOx == GPIO5) + { + return ((bit)(P5 & PortPins)); + } + +#endif + return 0; +} + + +/************************************************** +*:void GPIO_IOH_Config(GPIO_TypeDef GPIOx, uint8_t PortPins,GPIO_IOH_Grade_TypeDef GPIO_IOH_Grade) +*:GPIOڹܽIOH +*ڲ: +GPIO_TypeDef:GPIOx:ѡGPIO +GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy +GPIO_IOH_Grade_TypeDef:GPIO_IOH_Grade:IOȼ +*ڲ:BitStatus Pxyֵ +**************************************************/ +#if !defined(SC92F7003) && !defined(SC92F8003) && !defined(SC92F740x) +void GPIO_IOH_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef PortPins, GPIO_IOH_Grade_TypeDef GPIO_IOH_Grade) +{ +#if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92F84Ax_2) || defined(SC92F74Ax_2)\ + || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + switch (GPIOx) + { + case GPIO0: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON0 &= 0xFC; + IOHCON0 |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON0 &= 0xF3; + IOHCON0 |= GPIO_IOH_Grade << 2; + } + break; + case GPIO1: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON0 &= 0xCF; + IOHCON0 |= GPIO_IOH_Grade << 4; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON0 &= 0x3F; + IOHCON0 |= GPIO_IOH_Grade << 6; + } + break; + case GPIO2: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON1 &= 0xFC; + IOHCON1 |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON1 &= 0xF3; + IOHCON1 |= GPIO_IOH_Grade << 2; + } + break; +#if defined (SC92L853x) || defined (SC92L753x) + case GPIO5: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON1 &= 0xCF; + IOHCON1 |= GPIO_IOH_Grade << 4; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON1 &= 0x3f; + IOHCON1 |= GPIO_IOH_Grade << 6; + } + break; +#else + case GPIO3: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON1 &= 0xCF; + IOHCON1 |= GPIO_IOH_Grade << 4; + } + break; +#endif + default: + break; + } +#else + switch (GPIOx) + { + case GPIO0: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON &= 0xFC; + IOHCON |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON &= 0xF3; + IOHCON |= GPIO_IOH_Grade << 2; + } + break; + case GPIO2: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON &= 0xFC; + IOHCON |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON &= 0xF3; + IOHCON |= GPIO_IOH_Grade << 2; + } + break; + default: + break; + } +#endif +} +#endif + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_iap.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_iap.c new file mode 100644 index 0000000..71d92fa --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_iap.c @@ -0,0 +1,172 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_iap.c +// : +// ģ鹦 : IAP̼⺯Cļ +// : 2022/01/24 +// 汾 : V1.10002 +// ˵ :ļԪ92F/93F/92LϵеƬ +//************************************************************* + +#include "sc92f_iap.h" + +/************************************************** +*:void IAP_DeInit(void) +*:IAPؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void IAP_DeInit(void) +{ + IAPKEY = 0X00; + IAPADL = 0X00; + IAPADH = 0X00; + IAPADE = 0X00; + IAPDAT = 0X00; + IAPCTL = 0X00; +} + +/************************************************** +*:void IAP_SetHoldTime(IAP_HoldTime_TypeDef IAP_HoldTime) +*:IAPCPU Hold Timeú +*ڲ: +IAP_HoldTime_TypeDef:IAP_HoldTimed:Hold TimeTimeѡ +*ڲ:void +**************************************************/ +void IAP_SetHoldTime(IAP_HoldTime_TypeDef + IAP_HoldTime) +{ + IAPCTL = IAPCTL & 0XF3 | IAP_HoldTime; +} + +/************************************************** +*:void IAP_ProgramByte(uint16_t Address, uint8_t Data, IAP_MemType_TypeDef IAP_MemType, uint8_t WriteTimeLimit) +*:IAPдһֽ +*ڲ: +uint16_t:Address:IAPַ +uint8_t:Data:д +IAP_MemType_TypeDef:IAP_MemType:IAPROMEEPROM +עIAP_MEMTYPE_UIDдUIDдЧ +uint8_t:WriteTimeLimit:IAPʱ (ֵ) +*ڲ:void +**************************************************/ +void IAP_ProgramByte(uint16_t Address, + uint8_t Data, IAP_MemType_TypeDef IAP_MemType, + uint8_t WriteTimeLimit) +{ + BitStatus tmpbit; + + /* UIDд */ + if(IAP_MemType == IAP_MEMTYPE_UID) + return; + + tmpbit = (BitStatus)EA; + if(tmpbit != RESET) + { + disableInterrupts(); + } + + IAPADE = IAP_MemType; + IAPDAT = Data; + IAPADH = (uint8_t)(Address >> 8); + IAPADL = (uint8_t)Address; + IAPKEY = WriteTimeLimit; +#if defined (SC92F848x) || defined (SC92F748x) || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + IAPCTL |= 0x10; +#endif + IAPCTL |= 0x02; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + IAPADE = IAP_MEMTYPE_ROM; + + if(tmpbit != RESET) + { + enableInterrupts(); + } +} + +/************************************************** +*:uint8_t IAP_ReadByte(uint16_t Address, IAP_MemType_TypeDef IAP_MemType) +*:IAPһֽ +*ڲ: +uint16_t:Address:IAPַ +IAP_MemType_TypeDef:FLASH_MemType:IAPROMUIDEEPROM +*ڲ:uint8_t ֽ +**************************************************/ +uint8_t IAP_ReadByte(uint16_t Address, + IAP_MemType_TypeDef IAP_MemType) +{ + uint8_t tmpbyte; + BitStatus tmpbit; + tmpbit = (BitStatus)EA; + + if(tmpbit != RESET) + { + disableInterrupts(); + } + + IAPADE = IAP_MemType; + tmpbyte = *((uint8_t code*)Address); + IAPADE = IAP_MEMTYPE_ROM; + + if(tmpbit != RESET) + { + enableInterrupts(); + } + + return tmpbyte; +} + +#if defined (SC92F848x) || defined (SC92F748x) || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void IAP_SectorErase(IAP_MemType_TypeDef IAP_MemType, uint16_t IAP_SectorEraseAddress) +*:IAP +*ڲ: +IAP_MemType_TypeDef:IAP_MemType:IAPROM +uint32_t:IAP_SectorEraseAddress:IAPĿַ +uint8_t:WriteTimeLimit:IAPʱ(ֵڵ0x40) +*ڲ:void +**************************************************/ +void IAP_SectorErase(IAP_MemType_TypeDef IAP_MemType, uint32_t IAP_SectorEraseAddress, + uint8_t WriteTimeLimit) +{ + /* UID */ + if((IAP_MemType == IAP_MEMTYPE_UID) || (IAP_MemType == IAP_MEMTYPE_EEPROM)) + return; + + IAPADE = IAP_MemType; + IAPADH = (uint8_t)(IAP_SectorEraseAddress >> 8); //IAPĿַλֵ + IAPADL = (uint8_t)IAP_SectorEraseAddress; //IAPĿַλֵ + IAPKEY = WriteTimeLimit; + IAPCTL = 0x20; + IAPCTL |= 0x02; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + IAPADE = IAP_MEMTYPE_ROM; +} + +/************************************************** +*:void IAP_BootLoaderControl(IAP_BTLDType_TypeDef IAP_BTLDType) +*:MCUλǸ +*ڲ: +IAP_BTLDType_TypeDef:IAP_BTLDType:ѡ +*ڲ:void +**************************************************/ +void IAP_BootLoaderControl(IAP_BTLDType_TypeDef IAP_BTLDType) +{ + IAPCTL = (IAPCTL & ~IAP_BTLDType_LDROM) | IAP_BTLDType; +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_int.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_int.c new file mode 100644 index 0000000..e0e08ae --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_int.c @@ -0,0 +1,284 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_int.c +// : +// ģ鹦 : INT̼⺯Cļ +// ֲб: +// : 2022/01/05 +// 汾 : V1.10003 +// ˵ : +//************************************************************* + +#include "sc92f_int.h" + +/************************************************** +*:void INT_DeInit(INTx_Typedef INTx) +*:INTxؼĴλȱʡֵ +*ڲ: +INTx_Typedef:INTx:INTxѡ +*ڲ:void +**************************************************/ +#if !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F730x) && !defined (SC92F725X) && !defined (SC92F735X) && !defined (SC92F7490) +void INT_DeInit(INTx_Typedef INTx) +{ + switch(INTx) + { + case INT0: + INT0R = 0x00; + INT0F = 0x00; + IE &= (~0X01); + IP &= ~0X01; + TCON &= (~0X02); + break; + + case INT1: + INT1R = 0x00; + INT1F = 0x00; + IE &= (~0X04); + IP &= ~0X04; + TCON &= (~0X08); + break; + + case INT2: + INT2R = 0x00; + INT2F = 0x00; + IE1 &= (~0X08); + IP1 &= ~0X08; + break; + + default: + break; + } +} +#else +void INT_DeInit(INTx_Typedef INTx) +{ + switch(INTx) + { + case INT0: + INT0R = 0x00; + INT0F = 0x00; + IE &= (~0X01); + IP &= ~0X01; + TCON &= (~0X02); + break; + + case INT2: + INT2R = 0x00; + INT2F = 0x00; + IE1 &= (~0X08); + IP1 &= ~0X08; + break; + + default: + break; + } +} +#endif + +/************************************************** +*:void INT0_SetTriggerMode(uint8_t INT0x, INT_TriggerMode_Typedef TriggerMode) +*:INT0xжϴʽú +*ڲ: +INT0x_Typedef:INT0x:INT0xѡ +INT_TriggerMode_Typedef:TriggerMode:жϴʽѡ +*ڲ:void +**************************************************/ +void INT0_SetTriggerMode(uint8_t INT0x, + INT_TriggerMode_Typedef TriggerMode) +{ + switch(TriggerMode) + { + case INT_TRIGGER_RISE_ONLY: + INT0R |= INT0x; + INT0F &= (~INT0x); + break; + + case INT_TRIGGER_FALL_ONLY: + INT0R &= (~INT0x); + INT0F |= INT0x; + break; + + case INT_TRIGGER_RISE_FALL: + INT0R |= INT0x; + INT0F |= INT0x; + break; + + case INT_TRIGGER_DISABLE: + INT0R &= (~INT0x); + INT0F &= (~INT0x); + + default: + break; + } +} + + +/************************************************** +*:void INT1_SetTriggerMode(uint8_t INT1x, INT_TriggerMode_Typedef TriggerMode) +*:INT1xжϴʽú +*ڲ: +INT1x_Typedef:INT1x:INT1xѡ +INT_TriggerMode_Typedef:TriggerMode:жϴʽѡ +*ڲ:void +**************************************************/ +#if !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F730x) && !defined (SC92F725X) && !defined (SC92F735X) && !defined (SC92F7490) +void INT1_SetTriggerMode(uint8_t INT1x, + INT_TriggerMode_Typedef TriggerMode) +{ + switch(TriggerMode) + { + case INT_TRIGGER_RISE_ONLY: + INT1R |= INT1x; + INT1F &= (~INT1x); + break; + + case INT_TRIGGER_FALL_ONLY: + INT1R &= (~INT1x); + INT1F |= INT1x; + break; + + case INT_TRIGGER_RISE_FALL: + INT1R |= INT1x; + INT1F |= INT1x; + break; + + case INT_TRIGGER_DISABLE: + INT1R &= (~INT1x); + INT1F &= (~INT1x); + + default: + break; + } +} +#endif + +/************************************************** +*:void INT2_SetTriggerMode(uint8_t INT2x, INT_TriggerMode_Typedef TriggerMode) +*:INT2xжϴʽú +*ڲ: +INT2x_Typedef:INT2x:INT2xѡ +INT_TriggerMode_Typedef:TriggerMode:жϴʽѡ +*ڲ:void +**************************************************/ +void INT2_SetTriggerMode(uint8_t INT2x, + INT_TriggerMode_Typedef TriggerMode) +{ + switch(TriggerMode) + { + case INT_TRIGGER_RISE_ONLY: + INT2R |= INT2x; + INT2F &= (~INT2x); + break; + + case INT_TRIGGER_FALL_ONLY: + INT2R &= (~INT2x); + INT2F |= INT2x; + break; + + case INT_TRIGGER_RISE_FALL: + INT2R |= INT2x; + INT2F |= INT2x; + break; + + case INT_TRIGGER_DISABLE: + INT2R &= (~INT2x); + INT2F &= (~INT2x); + + default: + break; + } +} + +/***************************************************** +*:void INT0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:INT0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void INT0_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState != DISABLE) + { + IE |= 0X01; + } + else + { + IE &= (~0X01); + } + + if(Priority == LOW) + { + IP &= ~0X01; + } + else + { + IP |= 0X01; + } +} + +/***************************************************** +*:void INT1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:INT1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void INT1_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState != DISABLE) + { + IE |= 0X04; + } + else + { + IE &= (~0X04); + } + + if(Priority == LOW) + { + IP &= ~0X04; + } + else + { + IP |= 0X04; + } +} + +/***************************************************** +*:void INT2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:INT0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void INT2_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState != DISABLE) + { + IE1 |= 0X08; + } + else + { + IE1 &= (~0X08); + } + + if(Priority == LOW) + { + IP1 &= ~0X08; + } + else + { + IP1 |= 0X08; + } +} + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ + diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_lpd.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_lpd.c new file mode 100644 index 0000000..c562f5c --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_lpd.c @@ -0,0 +1,94 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92F_LPD.c +// : ԪӦŶ +// ģ鹦: LPD̼⺯Cļ +// : 2022323 +// 汾: V1.100002 +// ˵: ļSC92LϵоƬ +//************************************************************* + +#include "sc92f_lpd.h" + +#if defined (SC92L853x) || defined (SC92L753x) + +/************************************************** +*:void USCI1_DeInit(void) +*:USCI1ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void LPD_DeInit(void) +{ + /* ؼĴλ */ + LPDCFG = 0x00; + /* жؼĴλ */ + IE2 &= 0x7F; + IP2 &= 0x7F; +} + +/************************************************** +*:void LPD_VtripConfig(LPD_Vtrip_TypeDef LPD_Vtrip) +*:LPD޵ѹֵ +*ڲ: +LPD_Vtrip_TypeDef:LPD_Vtrip:LPD޵ѹֵ +*ڲ:void +**************************************************/ +void LPD_VtripConfig(LPD_Vtrip_TypeDef LPD_Vtrip) +{ + LPDCFG &= 0xF1; //λ޵ѹֵĴ + LPDCFG = LPD_Vtrip << 1; //޵ѹֵĴ +} + +/************************************************** +*:void LPD_Cmd(FunctionalState NewState) +*:ʹLPD +*ڲ: +FunctionalState:NewState:ʹ/ʧ +*ڲ:void +**************************************************/ +void LPD_Cmd(FunctionalState NewState) +{ + if(NewState == ENABLE) + { + LPDCFG &= 0xFE; + } + else + { + LPDCFG |= 0x01; + } +} + +/***************************************************** +*:void LPD_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:LPDжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void LPD_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + /* жϿ */ + if (NewState != DISABLE) + { + IE2 |= 0x01; + } + else + { + IE2 &= 0xFE; + } + + /* жȼ */ + if (Priority != LOW) + { + IP2 |= 0x01; + } + else + { + IP2 &= 0xFE; + } +} + + +#endif \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_mdu.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_mdu.c new file mode 100644 index 0000000..0301ee8 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_mdu.c @@ -0,0 +1,132 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_mdu.c +// : +// ģ鹦 : MDU̼⺯Cļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#include "sc92f_mdu.h" + +#if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB) || defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F848x) || defined (SC92F748x)\ + || defined (SC92F859x) || defined (SC92F759x) || defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void MDU_DeInit(void) +*:MDUؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void MDU_DeInit(void) +{ + OPERCON &= 0X3F; + EXA0 = 0X00; + EXA1 = 0X00; + EXA2 = 0X00; + EXA3 = 0X00; + EXBL = 0X00; + EXBH = 0X00; +} + +/************************************************** +*:void MDU_MultiplicationConfig(uint16_t Multiplicand, uint16_t Multiplier) +*:MDU˷ú +*ڲ: +uint32_t:Multiplicand: +uint32_t:Multiplier: +*ڲ:void +**************************************************/ +void MDU_MultiplicationConfig(uint16_t + Multiplicand, uint16_t Multiplier) +{ + OPERCON &= 0XBF; + EXBL = Multiplier ; + EXBH = Multiplier >> 8; + EXA0 = Multiplicand ; + EXA1 = Multiplicand >> 8; +} + +/************************************************** +*:void MDU_DivisionConfig(uint32_t Dividend, uint16_t Divisor) +*:MDUú +*ڲ: +uint32_t:Dividend: +uint32_t:Divisor: +*ڲ:void +**************************************************/ +void MDU_DivisionConfig(uint32_t Dividend, + uint16_t Divisor) +{ + MDU_Temp_Union MDU_DivisionTemp; + MDU_DivisionTemp.MDU_Temp = Dividend; + OPERCON |= 0X40; + EXA0 = MDU_DivisionTemp.MDU_EXAxReg.MDU_EXA0Reg; + EXA1 = MDU_DivisionTemp.MDU_EXAxReg.MDU_EXA1Reg; + EXA2 = MDU_DivisionTemp.MDU_EXAxReg.MDU_EXA2Reg; + EXA3 = MDU_DivisionTemp.MDU_EXAxReg.MDU_EXA3Reg; + EXBL = Divisor; + EXBH = Divisor >> 8; +} + +/************************************************** +*:void MDU_StartOperation(void) +*:MDUһ +*ڲ:void +*ڲ:void +**************************************************/ +void MDU_StartOperation(void) +{ + OPERCON |= 0x80; + + while(OPERCON & 0x80); +} + +/************************************************** +*:uint32_t MDU_GetProduct(void) +*:ȡ˻ +*ڲ:void +*ڲ:uint32_t:˻ +**************************************************/ +uint32_t MDU_GetProduct(void) +{ + MDU_Temp_Union MDU_ProductTemp; + MDU_ProductTemp.MDU_EXAxReg.MDU_EXA0Reg = EXA0; + MDU_ProductTemp.MDU_EXAxReg.MDU_EXA1Reg = EXA1; + MDU_ProductTemp.MDU_EXAxReg.MDU_EXA2Reg = EXA2; + MDU_ProductTemp.MDU_EXAxReg.MDU_EXA3Reg = EXA3; + return MDU_ProductTemp.MDU_Temp; +} + +/************************************************** +*:uint32_t MDU_GetQuotient(void) +*:ȡ +*ڲ:void +*ڲ:uint32_t: +**************************************************/ +uint32_t MDU_GetQuotient(void) +{ + MDU_Temp_Union MDU_QuotientTemp; + MDU_QuotientTemp.MDU_EXAxReg.MDU_EXA0Reg = EXA0; + MDU_QuotientTemp.MDU_EXAxReg.MDU_EXA1Reg = EXA1; + MDU_QuotientTemp.MDU_EXAxReg.MDU_EXA2Reg = EXA2; + MDU_QuotientTemp.MDU_EXAxReg.MDU_EXA3Reg = EXA3; + return MDU_QuotientTemp.MDU_Temp; +} + +/************************************************** +*:uint16_t MDU_GetRemainder(void) +*:ȡ +*ڲ:void +*ڲ:uint16_t: +**************************************************/ +uint16_t MDU_GetRemainder(void) +{ + uint16_t MDU_RemainderTemp; + MDU_RemainderTemp = EXBH * 256 + EXBL; + return MDU_RemainderTemp; +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_option.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_option.c new file mode 100644 index 0000000..f93b338 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_option.c @@ -0,0 +1,178 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_option.c +// : +// ģ鹦 : Customer OptionĴCļ +// ֲб: +// : 2022/01/24 +// 汾 : V1.0005 +// ˵ : +//************************************************************* + +#include "sc92f_option.h" + +/***************************************************** +*:void OPTION_WDT_Cmd(FunctionalState NewState) +*:WDTܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void OPTION_WDT_Cmd(FunctionalState NewState) +{ + OPINX = 0XC1; + + if(NewState == DISABLE) + { + OPREG &= 0X7F; + } + else + { + OPREG |= 0X80; + } +} + +/***************************************************** +*:void OPTION_XTIPLL_Cmd(FunctionalState NewState) +*:Ӿʹ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +#if !defined(SC92F848x) && !defined(SC92F748x) +void OPTION_XTIPLL_Cmd(FunctionalState NewState) +{ + OPINX = 0XC1; + + if(NewState == DISABLE) + { + OPREG &= 0XBF; + } + else + { + OPREG |= 0X40; + } +} +#endif +/***************************************************** +*:void OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef SYSCLK_PresSel) +*:ϵͳʱӷƵʼ +*ڲ: +SYSCLK_PresSel_TypeDef:SYSCLK_PresSel:ѡϵͳʱӷƵ +*ڲ:void +*****************************************************/ +void OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef + SYSCLK_PresSel) +{ + OPINX = 0XC1; + OPREG = OPREG & 0XCF | SYSCLK_PresSel; +} + +/***************************************************** +*:void OPTION_RST_PIN_Cmd(FunctionalState NewState) +*:ⲿλܽţP17ʹ +*ڲ: +FunctionalState:NewState:ʹ/رѡ +*ڲ:void +*****************************************************/ +#if !defined(SC92F848x) && !defined(SC92F748x) && !defined(SC92F859x) && !defined (SC92F759x) && !defined(SC92L853x) && !defined (SC92L753x) +void OPTION_RST_PIN_Cmd(FunctionalState NewState) +{ + OPINX = 0XC1; + + if(NewState == DISABLE) + { + OPREG |= 0X08; + } + else + { + OPREG &= 0XF7; + } +} +#endif + +/***************************************************** +*:void OPTION_LVR_Init(LVR_Config_TypeDef LVR_Config) +*:LVR ѹѡ +*ڲ: +LVR_Config_TypeDef:LVR_Config:ѡLVRѹ +*ڲ:void +*****************************************************/ +void OPTION_LVR_Init(LVR_Config_TypeDef + LVR_Config) +{ + OPINX = 0XC1; + OPREG = OPREG & 0XF8 | LVR_Config; +} + +/***************************************************** +*:void OPTION_ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) +*:ADC οѹѡ +*ڲ: +ADC_Vref_TypeDef:ADC_Vref:ѡADCοѹ +*ڲ:void +*****************************************************/ +void OPTION_ADC_VrefConfig(ADC_Vref_TypeDef + ADC_Vref) +{ + OPINX = 0xC2; + OPREG = OPREG & 0X7F | ADC_Vref; +} + +/************************************************** +*:void OPTION_IAP_SetOperateRange(IAP_OperateRange_TypeDef IAP_OperateRange) +*:IAPķΧ +*ڲ: +IAP_OperateRange_TypeDef:IAP_OperateRange:IAPΧ +*ڲ:void +**************************************************/ +void OPTION_IAP_SetOperateRange( + IAP_OperateRange_TypeDef IAP_OperateRange) +{ + OPINX = 0xC2; + OPREG = (OPREG & 0xF3) | IAP_OperateRange; +} + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax)\ + || defined (SC92F73Ax) || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F740x)\ + || defined (SC92F8003) || defined (SC92F7003) +/***************************************************** +*:void OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef XTIPLL_Range) +*:ⲿƵƵʷΧ +*ڲ: +XTIPLL_Range_TypeDef:XTIPLL_Range:ⲿƵѡ +*ڲ:void +*****************************************************/ +void OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef + XTIPLL_Range) +{ + OPINX = 0XC2; + OPREG = OPREG & 0XBF | XTIPLL_Range; +} +#endif + +#if defined (SC92F742x)||defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) \ + ||defined (SC92F74Ax_2)||defined (SC92F84Ax_2)||defined (SC92F844xB)||defined (SC92F744xB) \ + ||defined (SC92F859x) || defined (SC92F759x) ||defined (SC92F848x) || defined (SC92F748x) || defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void OPTION_JTG_Cmd(FunctionalState NewState) +*:JTAGģʽʹܿ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +**************************************************/ +void OPTION_JTG_Cmd(FunctionalState NewState) +{ + OPINX = 0xC2; + + if(NewState == DISABLE) + { + OPREG |= 0X10; //1 JTAGЧ + } + else + { + OPREG &= 0XEF; //0 JTAGЧ + } +} +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_pwm.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_pwm.c new file mode 100644 index 0000000..8d2e174 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_pwm.c @@ -0,0 +1,2086 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_pwm.c +// : +// ģ鹦 : PWM̼⺯Cļ +// ֲб: +// : 202262 +// 汾 : V1.10004 +// ˵ :ļԪ92F/93F/92LϵеƬ +//************************************************************* + +#include "sc92f_pwm.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ +||defined (SC92F859x) || defined (SC92F759x) +uint16_t xdata PWMREG[8] _at_ +0x740; //PWMռձȵڼĴ +uint16_t pwm_tmpreg[8] = {0, 0, 0, 0, 0, 0, 0, 0}; //PWMռձȵڼĴ + +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + static uint8_t i; + PWMCFG = 0X00; + PWMCON = 0X00; + IE1 &= 0XFD; + IP1 &= 0XFD; + + for(i = 0; i < 8; i++) + { + PWMREG[i] = 0; + } +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCFG = (PWMCFG & 0XCF) | + PWM_PresSel; //ԤƵ + PWMCFG = (PWMCFG & 0XF0) | (uint8_t)( + PWM_Period / 256); //ڸ4λ + PWMCON = (uint8_t)(PWM_Period & + 0X00FF); //ڵ8λ +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +uint8_t:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + uint8_t i; + + for(i = 0; i < 8; i++) + { + if(PWM_OutputPin & (0x01 << i)) + { + if(PWM_OutputState == PWM_OUTPUTSTATE_DISABLE) + { + pwm_tmpreg[i] &= 0X7FFF; + } + else + { + pwm_tmpreg[i] |= 0X8000; + } + + PWMREG[i] = pwm_tmpreg[i]; + } + } +} + + +/************************************************** +*:void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +uint8_t:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + uint8_t i; + + for(i = 0; i < 8; i++) + { + if(PWM_OutputPin & (0x01 << i)) + { + if(PWM_Polarity == PWM_POLARITY_NON_INVERT) + { + pwm_tmpreg[i] &= 0XBFFF; + } + else + { + pwm_tmpreg[i] |= 0X4000; + } + + PWMREG[i] = pwm_tmpreg[i]; + } + } +} +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + uint8_t i; + + for(i = 0; i < 8; i++) + { + if(PWM_OutputPin & (0x01 << i)) + { + pwm_tmpreg[i] = pwm_tmpreg[i] & 0XF000 | + PWM_DutyCycle; + PWMREG[i] = pwm_tmpreg[i]; + } + } +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCFG |= 0X80; + } + else + { + PWMCFG &= 0X7F; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCFG & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCFG &= 0XBF; +} +#endif + +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F848x) || defined (SC92F748x) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMDTYA = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; + PWMDTYB = 0X00; + PWMDTY3 = 0X00; + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; + IE1 &= ~0X02; + IP1 &= ~0X02; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCFG = (PWMCFG & 0X3F) | (PWM_PresSel << 6); //ԤƵ + PWMDTYA = (PWMDTYA & 0X3F) | ((uint8_t)( PWM_Period % 4) << 6); //ڵλ + PWMPRD = (uint8_t)(PWM_Period >> 2); //ڸ߰λ +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON |= PWM_OutputPin; + } + else + { + PWMCON &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= PWM_OutputPin; + } + else + { + PWMCFG &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + PWMDTYB &= 0X7F; //PWMΪģʽ + + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTYA = PWMDTYA & 0xfc | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM1: + PWMDTYA = PWMDTYA & 0xf3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM2: + PWMDTYA = PWMDTYA & 0xcf | ((PWM_DutyCycle % 4) << + 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM3: + PWMDTYB = PWMDTYB & 0xfc | (PWM_DutyCycle % 4); + PWMDTY3 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM4: + PWMDTYB = PWMDTYB & 0xf3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY4 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM5: + PWMDTYB = PWMDTYB & 0xcf | ((PWM_DutyCycle % 4) << + 4); + PWMDTY5 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + default: + break; + } +} + +/************************************************** +*:void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t PWM_DutyCycle) +*:PWMxPWMyģʽú +*ڲ: +PWM_ComplementaryOutputPin_TypeDef:PWM_ComplementaryOutputPin:PWMxPWMyͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle) +{ + PWMDTYB |= 0X80; //PWMΪģʽ + + switch(PWM_ComplementaryOutputPin) //ռձ + { + case PWM0PWM3: + PWMDTYA = PWMDTYA & 0xfc | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM1PWM4: + PWMDTYA = PWMDTYA & 0xf3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM2PWM5: + PWMDTYA = PWMDTYA & 0xcf | ((PWM_DutyCycle % 4) << + 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + default: + break; + } +} + +/************************************************** +*:void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) +*:PWMģʽʱú +*ڲ: +uint8_t:PWM012_RisingDeadTime:PWMʱ +uint8_t:PWM345_fallingDeadTime:PWM½ʱ +*ڲ:void +**************************************************/ +void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, + uint8_t PWM345_fallingDeadTime) +{ + PWMDTY3 = (PWM012_RisingDeadTime | + (PWM345_fallingDeadTime << 4)); +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= 0XFD; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON &= 0XBF; +} +#endif + +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG = 0X00; + PWMCON0 = 0X00; + PWMPRD = 0X00; + PWMDTYA = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; + PWMCON1 = 0X00; + PWMDTYB = 0X00; + PWMDTY3 = 0X00; + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; + PWMDTY6 = 0X00; + IE1 &= 0XFD; + IP1 &= 0XFD; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCON0 = (PWMCON0 & 0XCC) | PWM_PresSel | + (uint8_t)(PWM_Period & + 0X0003); //ԤƵڵĵ2λ + PWMPRD = (uint8_t)(PWM_Period >> + 2); //ڸ߰λ +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON1 |= PWM_OutputPin; + } + else + { + PWMCON1 &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_PWM2Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin) +*:PWM2ܽѡ +*ڲ: +PWM2_OutputPin_TypeDef:PWM2_OutputPin:PWM2ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM2Selection(PWM2_OutputPin_TypeDef + PWM2_OutputPin) +{ + PWMCON0 = PWMCON0 & 0XFB | PWM2_OutputPin; +} + +/************************************************** +*:void PWM_PWM5Selection(PWM5_OutputPin_TypeDef PWM5_OutputPin) +*:PWM5ܽѡ +*ڲ: +PWM5_OutputPin_TypeDef:PWM5_OutputPin:PWM5ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM5Selection(PWM5_OutputPin_TypeDef + PWM5_OutputPin) +{ + PWMCON0 = PWMCON0 & 0XF7 | PWM5_OutputPin; +} + +/************************************************** +*:void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= PWM_OutputPin; + } + else + { + PWMCFG &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + if(PWM_OutputPin != PWM6) + { + PWMCON1 &= 0X7F; //PWMΪģʽ + } + + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTYA = PWMDTYA & 0XFC | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM1: + PWMDTYA = PWMDTYA & 0XF3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM2: + PWMDTYA = PWMDTYA & 0XCF | ((PWM_DutyCycle % 4) << + 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM3: + PWMDTYA = PWMDTYA & 0X3F | ((PWM_DutyCycle % 4) << + 6); + PWMDTY3 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM4: + PWMDTYB = PWMDTYB & 0XFC | (PWM_DutyCycle % 4); + PWMDTY4 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM5: + PWMDTYB = PWMDTYB & 0XF3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY5 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM6: + PWMDTYB = PWMDTYB & 0XCF | ((PWM_DutyCycle % 4) << + 4); + PWMDTY6 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + default: + break; + } +} + +/************************************************** +*:void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t PWM_DutyCycle) +*:PWMxPWMyģʽú +*ڲ: +PWM_ComplementaryOutputPin_TypeDef:PWM_ComplementaryOutputPin:PWMxPWMyͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle) +{ + PWMCON1 |= 0X80; //PWMΪģʽ + + switch(PWM_ComplementaryOutputPin) //ռձ + { + case PWM0PWM3: + PWMDTYA = PWMDTYA & 0XFC | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM1PWM4: + PWMDTYA = PWMDTYA & 0XF3 | ((PWM_DutyCycle % 4) << + 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + case PWM2PWM5: + PWMDTYA = PWMDTYA & 0XCF | ((PWM_DutyCycle % 4) << + 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + + default: + break; + } +} + +/************************************************** +*:void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) +*:PWMģʽʱú +*ڲ: +uint8_t:PWM012_RisingDeadTime:PWMʱ +uint8_t:PWM345_fallingDeadTime:PWM½ʱ +*ڲ:void +**************************************************/ +void PWM_DeadTimeConfig(uint8_t + PWM012_RisingDeadTime, + uint8_t PWM345_fallingDeadTime) +{ + PWMDTY3 = (PWM012_RisingDeadTime | + (PWM345_fallingDeadTime << 4)); +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON0 |= 0X80; + } + else + { + PWMCON0 &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= 0XFD; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON0 & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON0 &= 0XBF; +} +#endif + +#if defined (SC92F742x) || defined (SC92F730x) || defined (SC92F725X) || defined(SC92F735X) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG0 = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMCFG1 = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; +#if !defined (SC92F730x) + PWMDTY3 = 0X00; +#endif + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; + IE1 &= ~0X02; + IP1 &= ~0X02; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCON = (PWMCON & 0XF8) | PWM_PresSel; //ԤƵ + PWMPRD = PWM_Period; // +} + +/************************************************** +*:void PWM_OutputStateConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +uint8_t:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_DISABLE) + { + PWMCON = PWMCON & (~((PWM_OutputPin & 0x07) << 3)); + PWMCON = PWMCON | (PWM_OutputPin & 0x07) << 3; + } + else + { + PWMCON = PWMCON | (PWM_OutputPin & 0x07) << 3; + PWMCFG0 = PWMCFG0 | (PWM_OutputPin & 0x38) >> 3; + } +} + +/************************************************** +*:void PWM_PolarityConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_PolarityConfig:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_NON_INVERT) + { + PWMCFG0 = PWMCFG0 & ~((PWM_OutputPin & 0x07) << 3); + PWMCFG1 = PWMCFG1 & ~((PWM_OutputPin & 0x38)); + } + else + { + PWMCFG0 = PWMCFG0 | (PWM_OutputPin & 0x07) << 3; + PWMCFG1 = PWMCFG1 | (PWM_OutputPin & 0x38); + } + +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig( + PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTY0 = PWM_DutyCycle; + break; + + case PWM1: + PWMDTY1 = PWM_DutyCycle; + break; + + case PWM2: + PWMDTY2 = PWM_DutyCycle; + break; +#if !defined (SC92F730x) + + case PWM3: + PWMDTY3 = PWM_DutyCycle; + break; +#endif + + case PWM4: + PWMDTY4 = PWM_DutyCycle; + break; + + case PWM5: + PWMDTY5 = PWM_DutyCycle; + break; + + default: + break; + } +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= ~0X02; + } + + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON &= 0XBF; +} +#endif + +#if defined (SC92F827X) || defined (SC92F837X) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; +#if !defined (SC92F827X) + PWMDTY2 = 0X00; + PWMDTY3 = 0X00; +#if !defined (SC92F837X) + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; +#endif +#endif + IE1 &= ~0X02; + IP1 &= ~0X02; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCON = (PWMCON & 0XF8) | PWM_PresSel; //ԤƵ + PWMPRD = PWM_Period; // +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON |= PWM_OutputPin; + } + else + { + PWMCON &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= PWM_OutputPin; + } + else + { + PWMCFG &= (~PWM_OutputPin); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig( + PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTY0 = PWM_DutyCycle; + break; + + case PWM1: + PWMDTY1 = PWM_DutyCycle; + break; +#if !defined (SC92F827X) + + case PWM2: + PWMDTY2 = PWM_DutyCycle; + break; + + case PWM3: + PWMDTY3 = PWM_DutyCycle; + break; +#if !defined (SC92F837X) + + case PWM4: + PWMDTY4 = PWM_DutyCycle; + break; + + case PWM5: + PWMDTY5 = PWM_DutyCycle; + break; +#endif +#endif + + default: + break; + } +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= 0XFD; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:FlagStatus PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON &= 0XBF; +} +#endif + +#if defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + PWMCFG = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMDTYA = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; + IE1 &= ~0X02; + IP1 &= ~0X02; +} + +/************************************************** +*:void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + PWM_Period -= 1; + PWMCON = (PWMCON & 0XF8) | PWM_PresSel; //ԤƵ + PWMPRD = PWM_Period; // +} + +/************************************************** +*:void PWM_OutputStateConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == PWM_OUTPUTSTATE_DISABLE) + { + PWMCON = PWMCON & (~(PWM_OutputPin << 3)); + } + else + { + PWMCON = PWMCON | (PWM_OutputPin << 3); + } +} + +/************************************************** +*:void PWM_PolarityConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:WM_OutputPin:PWMxѡ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_NON_INVERT) + { + PWMCFG = PWMCFG & (~PWM_OutputPin<<3); + } + else + { + PWMCFG = PWMCFG | (PWM_OutputPin<<3); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig( + PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + switch(PWM_OutputPin) //ռձ + { + case PWM0: + PWMDTY0 = PWM_DutyCycle; + break; + + case PWM1: + PWMDTY1 = PWM_DutyCycle; + break; + + case PWM2: + PWMDTY2 = PWM_DutyCycle; + break; + + default: + break; + } +} + +/***************************************************** +*:void PWM_Cmd(FunctionalState NewState) +*:PWMܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_Cmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= ~0X02; + } + + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ: +FlagStatus:PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatus(void) +{ + return (bool)(PWMCON & 0X40); +} + +/***************************************************** +*:void PWM_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ:void +*ڲ:void +*****************************************************/ +void PWM_ClearFlag(void) +{ + PWMCON &= 0XBF; +} + +/************************************************** +*:void PWM_PWM0Selection(PWM0_OutputPin_TypeDef PWM0_OutputPin) +*:PWM0ܽѡ +*ڲ: +PWM0_OutputPin_TypeDef:PWM0_OutputPin:PWM0ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM0Selection(PWM0_OutputPin_TypeDef + PWM0_OutputPin) +{ + PWMCFG = PWMCFG & 0XFE | PWM0_OutputPin; +} + +/************************************************** +*:void PWM_PWM1Selection(PWM1_OutputPin_TypeDef PWM1_OutputPin) +*:PWM1ܽѡ +*ڲ: +PWM1_OutputPin_TypeDef:PWM1_OutputPin:PWM1ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM1Selection(PWM1_OutputPin_TypeDef + PWM1_OutputPin) +{ + PWMCFG = PWMCFG & 0XFD | PWM1_OutputPin; +} + +/************************************************** +*:void PWM_PWM1Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin) +*:PWM2ܽѡ +*ڲ: +PWM2_OutputPin_TypeDef:PWM2_OutputPin:PWM1ܽѡ +*ڲ:void +**************************************************/ +void PWM_PWM2Selection(PWM2_OutputPin_TypeDef + PWM2_OutputPin) +{ + PWMCFG = PWMCFG & 0XFB | PWM2_OutputPin; +} + +/************************************************** +*:void PMM_DutyModeSelection(PWM_DutyMode_TypeDef PWM_DutyMode) +*:PWMռձ΢ģʽѡ +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMͨ +PWM_DutyMode_TypeDef:PWM_DutyMode:PWM΢ģʽ +*ڲ:void +**************************************************/ +void PMM_DutyModeSelection(PWM_OutputPin_TypeDef + PWM_OutputPin, PWM_DutyMode_TypeDef PWM_DutyMode) +{ + PWMDTYA = PWMDTYA & (~(0x03 << (PWM_OutputPin - + 1))) | (PWM_DutyMode << (PWM_OutputPin - 1)); +} +#endif + +#if defined (SC92FWxx) + +uint8_t xdata PWMREG[80] _at_ +0x700; //PWMռձȵڼĴ +uint8_t PWMREG_Status[10]; +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + static uint8_t i; + PWMCFG0 = 0X00; + PWMCON0 = 0X00; + PWMCFG1 = 0X00; + PWMCON1 = 0X00; + IE1 &= 0XFD; + IP1 &= 0XFD; + + for(i = 0; i < 80; i++) + { + PWMREG[i] = 0; + } +} + +/************************************************** +*:PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, + uint16_t PWM_Period) +{ + if((PWM_PresSel & 0X0F) == PWM0_Type) + { + PWM_Period -= 1; + PWMCFG0 = (PWMCFG0 & 0XCF) | (PWM_PresSel & + 0XF0); //ԤƵ + PWMCFG0 = (PWMCFG0 & 0XF0) | (uint8_t)( + PWM_Period / 256); //ڸ4λ + PWMCON0 = (uint8_t)(PWM_Period & + 0X00FF); //ڵ8λ + } + else + if ((PWM_PresSel & 0X0F) == PWM1_Type) + { + PWM_Period -= 1; + PWMCFG1 = (PWMCFG1 & 0XCF) | (PWM_PresSel & + 0XF0); //ԤƵ + PWMCFG1 = (PWMCFG1 & 0XF0) | (uint8_t)( + PWM_Period / 256); //ڸ4λ + PWMCON1 = (uint8_t)(PWM_Period & + 0X00FF); //ڵ8λ + } +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ(ͺβ֧Χδ) +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == ENABLE) + { + PWMREG[PWM_OutputPin] |= 0x80; + } + else + { + PWMREG[PWM_OutputPin] &= 0x7F; + } +} + +/************************************************** +*:void PWM_PolarityConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ(ͺβ֧Χδ) +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMREG[PWM_OutputPin] |= 0x40; + } + else + { + PWMREG[PWM_OutputPin] &= 0xBF; + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡ(ͺβ֧Χδ) +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle) +{ + PWMREG[PWM_OutputPin + 1] = PWM_DutyCycle; + PWMREG[PWM_OutputPin] = (PWMREG[PWM_OutputPin] * 0xF0) |(PWM_DutyCycle / 256); +} + +/***************************************************** +*:void PWM_Cmd(PWM_Type_TypeDef PWM_Type,FunctionalState NewState) +*:PWMܿغ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_CmdEX(PWM_Type_TypeDef PWM_Type, + FunctionalState NewState) +{ + if(PWM_Type == PWM0_Type) + { + if (NewState != DISABLE) + { + PWMCFG0 |= 0X80; + } + else + { + PWMCFG0 &= 0X7F; + } + } + else + { + if (NewState != DISABLE) + { + PWMCFG1 |= 0X80; + } + else + { + PWMCFG1 &= 0X7F; + } + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:FlagStatus PWM1_Type_GetFlagStatus(void) +*:PWMжϱ־״̬ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +*ڲ:FlagStatus PWMжϱ־״̬ +*****************************************************/ +FlagStatus PWM_GetFlagStatusEX(PWM_Type_TypeDef + PWM_Type) +{ + if(PWM_Type == PWM0_Type) + { + return (bool)(PWMCFG0 & 0X40); + } + else + { + return (bool)(PWMCFG1 & 0X40); + } +} + +/***************************************************** +*:void PWM1_ClearFlag(void) +*:PWMжϱ־״̬ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +*ڲ:void +*****************************************************/ +void PWM_ClearFlagEX(PWM_Type_TypeDef PWM_Type) +{ + if(PWM_Type == PWM0_Type) + { + PWMCFG0 &= 0XBF; + } + else + { + PWMCFG1 &= 0XBF; + } +} + +/***************************************************** +*:void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMжϱ־״̬ +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle, + PWM_OutputState_TypeDef PWM_OutputState) +{ + if(PWM_OutputState == ENABLE) + { + PWMREG[PWM_OutputPin] = (PWMREG[PWM_OutputPin] * 0xF0) | (0x80 | (PWM_DutyCycle / + 256)); + PWMREG[PWM_OutputPin + 1] = PWM_DutyCycle; + } + else + { + PWMREG[PWM_OutputPin] &= 0x7F; + } +} + +#endif + +#if defined (SC92L853x) || defined (SC92L753x) +uint8_t xdata PWMREG[28] _at_ 0x0F40; //PWMռձȵڼĴ +/************************************************** +*:void PWM_DeInit(void) +*:PWMؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWM_DeInit(void) +{ + static uint8_t i; + + //PWM0ؼĴ + PWMCON0 = 0X00; + PWMCFG = 0X00; + PWMCON1 = 0X00; + PWMPDL = 0x00; + PWMPDH = 0x00; + IE1 &= 0XFD; + IP1 &= 0XFD; + + //ռձȼĴ + for (i = 0; i < 14; i++) + { + PWMREG[i] = 0; + } +} + +/************************************************** +*:PWM_Init(PWM_Type_TypeDef PWM_Type,PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +*:PWMʼú +*ڲ: +PWM_PresSel_TypeDef:PWM_PresSel:ԤƵѡ +uint16_t:PWM_Period:PWM +*ڲ:void +**************************************************/ +void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) +{ + /* PWM0ʱʼ */ + PWM_Period -= 1; + PWMCON0 = ((PWMCON0 & 0XCF) | PWM_PresSel); //ԤƵ + PWMPDH = (uint8_t)(PWM_Period >> 8); //ڸ8λ + PWMPDL = (uint8_t)(PWM_Period & 0X00FF); //ڵ8λ +} + +/***************************************************** +*:void PWM_Aligned_Mode_Select(void) +*:ѡPWMĶģʽ +*ڲ: +PWM_Aligned_Mode_TypeDef:PWM_Aligned_Mode:ѡģʽ +*ڲ:void +*****************************************************/ +void PWM_Aligned_Mode_Select(PWM_Aligned_Mode_TypeDef PWM_Aligned_Mode) +{ + PWMCON0 &= ~0x01; //PWMģʽ + PWMCON0 |= (PWM_Aligned_Mode<<1); //PWMģʽ +} + +/************************************************** +*:void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMxʹ/ʧú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡuint8_tΪΣλ +PWM_OutputState_TypeDef:PWM_OutputState:PWM״̬ +*ڲ:void +**************************************************/ +void PWM_OutputStateConfig(uint8_t PWM_OutputPin, + PWM_OutputState_TypeDef PWM_OutputState) +{ + /* PWM0ͨʹ */ + if (PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON1 |= 1 << ((PWM_OutputPin >> 1) & 0x0F); + } + else + { + PWMCON1 &= ~(1 << ((PWM_OutputPin >> 1) & 0x0F)); + } +} + +/************************************************** +*:void PWM_PolarityConfig(PWM_OutputPin_TypeDef PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) +*:PWMx/ú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxѡuint8_tΪΣλ +PWM_Polarity_TypeDef:PWM_Polarity:PWM/ +*ڲ:void +**************************************************/ +void PWM_PolarityConfig(uint8_t PWM_OutputPin, + PWM_Polarity_TypeDef PWM_Polarity) +{ + if (PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= 1 << ((PWM_OutputPin >> 1) & 0x0F); + } + else + { + PWMCFG &= ~(1 << ((PWM_OutputPin >> 1) & 0x0F)); + } +} + +/************************************************** +*:void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +*:PWMxģʽú +*ڲ: +PWM_OutputPin_TypeDef:PWM_OutputPin:PWMxͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) +{ + PWMCON0 &= ~0x02; //PWMΪģʽ + /* PWM */ + PWMREG[ PWM_ComplementaryOutputPin] = PWM_DutyCycle; + PWMREG[ PWM_ComplementaryOutputPin+1] = PWM_DutyCycle >> 8; +} + +/************************************************** +*:void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t PWM_DutyCycle) +*:PWMxPWMyģʽú +*ڲ: +PWM_ComplementaryOutputPin_TypeDef:PWM_ComplementaryOutputPin:PWMxPWMyͨѡ +uint16_t:PWM_DutyCycle:PWMռձ +*ڲ:void +**************************************************/ +void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle) +{ + PWMCON0 |= 0x02; + PWMREG[ PWM_ComplementaryOutputPin] = PWM_DutyCycle; + PWMREG[ PWM_ComplementaryOutputPin+1] = PWM_DutyCycle >> 8; +} + +/************************************************** +*:PWM_DeadTimeConfigEX(PWM_Type_TypeDef PWM_Type,uint8_t PWM_RisingDeadTime, uint8_t PWM_FallingDeadTime) +*:PWMģʽʱú +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMԴѡ +uint8_t:PWM_RisingDeadTime:PWMʱ 00-FF +uint8_t:PWM_FallingDeadTime:PWM½ʱ 00-FF +*ڲ:void +**************************************************/ +void PWM_DeadTimeConfigEX(PWM_Type_TypeDef PWM_Type, uint8_t PWM_RisingDeadTime, uint8_t PWM_FallingDeadTime) +{ + if (PWM_Type == PWM0_Type) + { + PWMDFR = (PWM_RisingDeadTime | (PWM_FallingDeadTime << 4)); + } +} + +/***************************************************** +*:void PWM_Cmd(PWM_Type_TypeDef PWM_Type,FunctionalState NewState) +*:PWMܿغ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_CmdEX(PWM_Type_TypeDef PWM_Type, + FunctionalState NewState) +{ + if (PWM_Type == PWM0_Type) + { + if (NewState != DISABLE) + { + PWMCON0 |= 0X80; + } + else + { + PWMCON0 &= 0X7F; + } + } + else + { + TXINX = PWM_Type; + if (NewState != DISABLE) + { + TXCON |= 0X04; + } + else + { + TXCON &= ~0X04; + } + } +} + +/***************************************************** +*:void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:PWMжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + + if (Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } +} + +/***************************************************** +*:void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle, PWM_OutputState_TypeDef PWM_OutputState) +*:PWMģʽ +*ڲ: +PWM_OutputPin_TypeDef:PWM_ComplementaryOutputPin:PWMͨ +uint16_t:PWM_DutyCycle:PWMռձ +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_IndependentModeConfigEX(PWM_OutputPin_TypeDef PWM_ComplementaryOutputPin, + uint16_t PWM_DutyCycle, + PWM_OutputState_TypeDef PWM_OutputState) +{ + PWM_IndependentModeConfig(PWM_ComplementaryOutputPin, PWM_DutyCycle); //ռձ + PWM_OutputStateConfig(PWM_ComplementaryOutputPin, PWM_OutputState); //IOPWMú + if (PWM_OutputState == ENABLE) + { + PWM_CmdEX(PWM_ComplementaryOutputPin >> 4, ENABLE); //PWM + } +} + +/***************************************************** +*:void PWM_ComplementaryModeConfigEX(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle, PWM_OutputState_TypeDef PWM_OutputState) +*:PWM +*ڲ: +PWM_ComplementaryOutputPin_TypeDef:PWM_OutputPin:PWMͨ +uint16_t:PWM_DutyCycle:PWMռձ +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void PWM_ComplementaryModeConfigEX(PWM_ComplementaryOutputPin_TypeDef PWM_OutputPin, + uint16_t PWM_DutyCycle, + PWM_OutputState_TypeDef PWM_OutputState) +{ + PWM_ComplementaryModeConfig(PWM_OutputPin, PWM_DutyCycle); //ռձ + PWM_OutputStateConfig(PWM_OutputPin, PWM_OutputState); //IOPWMú + PWM_OutputStateConfig(PWM_OutputPin + 2, PWM_OutputState); //IOPWMú + if (PWM_OutputState == ENABLE) + { + PWM_CmdEX(PWM_OutputPin >> 4, ENABLE); //PWM + } +} + +/***************************************************** +*:PWM_GetFlagStatusEX(PWM_Type_TypeDef PWM_Type) +*:ȡPWMжϱ־λ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMԴѡ +*ڲ:void +*****************************************************/ +FlagStatus PWM_GetFlagStatusEX(PWM_Type_TypeDef PWM_Type) +{ + if ((PWM_Type == PWM0_Type)) + { + return (bool)(PWMCON0 & 0X40); + } + + return RESET; +} + +/***************************************************** +*:void PWM_ClearFlagEX(PWM_Type_TypeDef PWM_Type) +*:PWMж +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMԴѡ +*ڲ:void +*****************************************************/ +void PWM_ClearFlagEX(PWM_Type_TypeDef PWM_Type) +{ + if ((PWM_Type == PWM0_Type)) + { + PWMCON0 &= ~0X40; + } +} + +/***************************************************** +*:FlagStatus PWM_GetFaultDetectionFlagStatus(void) +*:PWMϼ־λ״̬ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +*ڲ: +FlagStatus:PWMϼ־λ״̬ +*****************************************************/ +FlagStatus PWM_GetFaultDetectionFlagStatusEX(PWM_Type_TypeDef PWM_Type) +{ + if (PWM_Type == PWM0_Type) + { + return (bool)(PWMFLT & 0X40); + } + return RESET; +} + +/***************************************************** +*:void PWM_ClearFaultDetectionFlag(void) +*:PWMϼ־λ״̬ // ע,ģʽ£λ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWM +*ڲ:void +*****************************************************/ +void PWM_ClearFaultDetectionFlagEX(PWM_Type_TypeDef PWM_Type) +{ + if (PWM_Type == PWM0_Type) + { + PWMFLT &= 0XBF; + } +} + +/***************************************************** +*:void PWM_FaultDetectionFunctionConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState) +*:PWMϼ⹦ܿ/ر-չ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMѡ +FunctionalState:NewState:ϼ⹦ܿ/ر +*ڲ:void +*****************************************************/ +void PWM_FaultDetectionConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState) +{ + if (PWM_Type == PWM0_Type) + { + if (NewState != DISABLE) + { + PWMFLT |= 0X80; + } + else + { + PWMFLT &= 0X7F; + } + } +} + +/***************************************************** +*:void PWM_FaultDetectionModeConfigEX(PWM_Type_TypeDef PWM_Type, PWM_FaultDetectionMode_TypeDef FaultDetectionMode, PWM_FaultDetectionVoltageSelect_TypeDef FaultDetectionVoltageSelect, PWM_FaultDetectionWaveFilteringTime_TypeDef FaultDetectionWaveFilteringTime) +*:PWMϼģʽ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMѡ +PWM_FaultDetectionMode_TypeDef:FaultDetectionMode:ϼ⹦ģʽ: ģʽ/ģʽ +PWM_FaultDetectionVoltageSelect_TypeDef:FaultDetectionVoltageSelect:ϼƽѡ +PWM_FaultDetectionWaveFilteringTime_TypeDef:FaultDetectionWaveFilteringTime:ϼź˲ʱѡ +*ڲ:void +*****************************************************/ +void PWM_FaultDetectionModeConfigEX(PWM_Type_TypeDef PWM_Type, + PWM_FaultDetectionMode_TypeDef FaultDetectionMode, + PWM_FaultDetectionVoltageSelect_TypeDef FaultDetectionVoltageSelect, + PWM_FaultDetectionWaveFilteringTime_TypeDef FaultDetectionWaveFilteringTime) +{ + if (PWM_Type == PWM0_Type) + { + PWMFLT = (PWMFLT & 0XC0) | FaultDetectionMode | FaultDetectionVoltageSelect | + FaultDetectionWaveFilteringTime; + } +} + +/***************************************************** +*:void PWM_ITConfigEX(PWM_Type_TypeDef PWM_Type,FunctionalState NewState, PriorityStatus Priority) +*:PWMжú-չ +*ڲ: +PWM_Type_TypeDef:PWM_Type:PWMԴѡ +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void PWM_ITConfigEX(PWM_Type_TypeDef PWM_Type, FunctionalState NewState, PriorityStatus Priority) +{ + + if ((PWM_Type == PWM0_Type)) + { + PWM_ITConfig(NewState, Priority); + } + else + { + TXINX = PWM_Type; + + if (NewState == DISABLE) + { + ET2 = 0; + } + else + { + ET2 = 1; + } + + if (Priority == LOW) + { + IPT2 = 0; + } + else + { + IPT2 = 1; + } + } +} + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_pwr.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_pwr.c new file mode 100644 index 0000000..285df16 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_pwr.c @@ -0,0 +1,62 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_pwr.c +// : +// ģ鹦 : PWR̼⺯Cļ +// ֲб: +// : 2020/8/18 +// 汾 : V1.0 +// ˵ :ļԪ92FϵеƬ +//************************************************************* +#include "sc92f_pwr.h" + +/************************************************** +*:void PWR_DeInit(void) +*:PWRؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void PWR_DeInit(void) +{ + PCON &= 0XFC; +} + +/************************************************** +*:void PWR_EnterSTOPMode(void) +*:MCUSTOPģʽ +*ڲ:void +*ڲ:void +**************************************************/ +void PWR_EnterSTOPMode(void) +{ + PCON |= 0X02; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); +} + +/************************************************** +*:void PWR_EnterIDLEMode(void) +*:MCUIDLEģʽ +*ڲ:void +*ڲ:void +**************************************************/ +void PWR_EnterIDLEMode(void) +{ + PCON |= 0X01; + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); + _nop_(); +} + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi.c new file mode 100644 index 0000000..87be19b --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi.c @@ -0,0 +1,425 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ssi.c +// : +// ģ鹦 : SSI̼⺯Cļ +// ֲб: +// : 2021/08/20 +// 汾 : V1.10001 +// ˵ : +//************************************************************* + +#include "sc92f_ssi.h" + +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F84Ax) || defined (SC92F74Ax)\ + || defined (SC92F83Ax) || defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) || defined (SC92F827X)\ + || defined (SC92F837X) || defined (SC92FWxx) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) || defined (SC92F848x) || defined (SC92F748x)\ + || defined (SC92F859x) || defined (SC92F759x) +/************************************************** +*:void SSI_DeInit(void) +*:SSIؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void SSI_DeInit(void) +{ + OTCON &= 0X3F; + SSCON0 = 0X00; + SSCON1 = 0X00; + SSCON2 = 0X00; + SSDAT = 0X00; + IE1 &= (~0X01); + IP1 &= (~0X01); +} + +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +/************************************************** +*:SSI_PinSelection(SSI_PinSelection_TypeDef PinSeletion) +*:SSIѡ +*ڲ: +SSI_PinSelection_TypeDef:PinSeletion:ѡSSIΪP10P27P26P21P22P23 +*ڲ:void +**************************************************/ +void SSI_PinSelection(SSI_PinSelection_TypeDef + PinSeletion) +{ + OTCON = OTCON & 0XDF | PinSeletion; +} +#endif + +/************************************************** +*:void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase,SPI_TXE_INT_TypeDef SPI_TXE_INT) +*:SPIʼú +*ڲ: +SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +SPI_Mode_TypeDef:Mode:SPIģʽѡ +SPI_ClockPolarity_TypeDef:ClockPolarity:SPIʱӼѡ +SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ +*ڲ:void +**************************************************/ +void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT) +{ + OTCON = (OTCON & 0X3F) | 0X40; + SSCON1 = SSCON1 & (~0X05) | FirstBit | + SPI_TXE_INT; + SSCON0 = SSCON0 & 0X80 | BaudRatePrescaler | Mode + | ClockPolarity | ClockPhase; +} + +/***************************************************** +*:void SSI_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI_SPI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SSCON0 |= 0X80; + } + else + { + SSCON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI_SPI_SendData(uint8_t Data) +*:SPI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void SSI_SPI_SendData(uint8_t Data) +{ + SSDAT = Data; +} + +/***************************************************** +*:uint8_t SSI_SPI_ReceiveData(void) +*:SSDATеֵ +*ڲ:void +*ڲ: +uint8_t:SPIյ8λ +*****************************************************/ +uint8_t SSI_SPI_ReceiveData(void) +{ + return SSDAT; +} + +/************************************************** +*:void SSI_TWI_Init(uint8_t TWI_Address) +*:TWIʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void SSI_TWI_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0X3F | 0X80; + SSCON1 = TWI_Address << 1; +} + +/************************************************** +*:void SSI_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI_TWI_AcknowledgeConfig(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SSCON0 |= 0X08; + } + else + { + SSCON0 &= 0XF7; + } +} + +/************************************************** +*:void SSI_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:ͨõַӦʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI_TWI_GeneralCallCmd(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SSCON1 |= 0X01; + } + else + { + SSCON1 &= 0XFE; + } +} + +/************************************************** +*:FlagStatus SSI_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +*:ȡTWI״̬ +*ڲ: +SSI_TWIState_TypeDef:SSI_TWIState:TWI״̬״̬ +*ڲ:void +**************************************************/ +FlagStatus SSI_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +{ + if((SSCON0&0x07) == SSI_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void SSI_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ:FunctionalState NewState /رѡ +*ڲ:void +*****************************************************/ +void SSI_TWI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SSCON0 |= 0X80; + } + else + { + SSCON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void SSI_TWI_SendData(uint8_t Data) +{ + SSDAT = Data; +} + +/***************************************************** +*:uint8_t SSI_TWI_ReceiveData(void) +*:SSDATеֵ +*ڲ:void +*ڲ: +uint8_t:TWIյ8λ +*****************************************************/ +uint8_t SSI_TWI_ReceiveData(void) +{ + return SSDAT; +} + +/************************************************** +*:void SSI_UART1_Init(uint32_t UART1Fsys, uint32_t BaudRate, UART1_Mode_TypeDef Mode, UART1_RX_TypeDef RxMode) +*:UART1ʼú +*ڲ: +uint32_t:UART1Fsys:ϵͳʱƵ +uint32_t:BaudRate: +UART1_Mode_TypeDef:Mode:UART1ģʽ +UART1_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void SSI_UART1_Init(uint32_t UART1Fsys, + uint32_t BaudRate, UART1_Mode_TypeDef Mode, + UART1_RX_TypeDef RxMode) +{ + + #if defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) + OTCON |= 0xC0; + SSCON0 = SSCON0 & 0X0F | Mode | RxMode; + SSCON2 = UART1Fsys / 16 / BaudRate / 256; + SSCON1 = UART1Fsys / 16 / BaudRate % 256; + + #else + OTCON |= 0xC0; + SSCON0 = SSCON0 & 0X0F | Mode | RxMode; + SSCON2 = UART1Fsys / BaudRate / 256; + SSCON1 = UART1Fsys / BaudRate % 256; + + #endif + + +} + +bit SSI_FLAG = 0; +/***************************************************** +*:void SSI_UART1_SendData8(uint8_t Data) +*:UART18λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void SSI_UART1_SendData8(uint8_t Data) +{ + SSI_FLAG = 1; + SSDAT = Data; + while( SSI_FLAG == 1 ); +} + + + +/***************************************************** +*:uint8_t SSI_UART1_ReceiveData8(void) +*:SSDATеֵ +*ڲ:void +*ڲ: +uint8_t:UARTյ8λ +*****************************************************/ +uint8_t SSI_UART1_ReceiveData8(void) +{ + return SSDAT; +} + +/***************************************************** +*:void SSI_UART1_SendData9(uint16_t Data) +*:UART19λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void SSI_UART1_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if(Data_9Bit) + { + SSCON0 |= 0x08; + } + else + { + SSCON0 &= 0xf7; + } + + SSDAT = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t SSI_UART1_ReceiveData9(void) +*:SSDATеֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t SSI_UART1_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = SSDAT + ((uint16_t)(SSCON0 & 0X04) << 6); + SSCON0 &= 0XFB; + return Data9; +} + +/***************************************************** +*:void SSI_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:SSIжϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void SSI_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState != DISABLE) + { + IE1 |= 0x01; + } + else + { + IE1 &= 0xFE; + } + + /************************************************************/ + if(Priority != LOW) + { + IP1 |= 0x01; + } + else + { + IP1 &= 0xFE; + } +} + +/***************************************************** +*:FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG) +*:SSI־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ȡı־λ +*ڲ: +FlagStatus:SSI־λ״̬ +*****************************************************/ +FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef + SSI_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + if((SSI_FLAG & SSCON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((SSI_FLAG & SSCON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +*:SSI־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +{ + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + SSCON1 &= (~SSI_FLAG); + } + else + { + SSCON0 &= (~SSI_FLAG); + } +} +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi0.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi0.c new file mode 100644 index 0000000..e9ec582 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi0.c @@ -0,0 +1,392 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ssi0.c +// : +// ģ鹦 : SSI0̼⺯Cļ +// ֲб: +// : 2021/07/23 +// 汾 : V1.10000 +// ˵ : +//************************************************************* + +#include "sc92f_ssi.h" + +#if defined (SC92F742x) || defined (SC92F7490) +/************************************************** +*:void SSI0_DeInit(void) +*:SSI0ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void SSI0_DeInit(void) +{ + OTCON &= 0XCF; + SS0CON0 = 0X00; + SS0CON1 = 0X00; + SS0CON2 = 0X00; + SS0DAT = 0X00; + IE &= (~0X10); + IP &= (~0X10); +} + +/************************************************** +*:void SSI0_SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase,SPI_TXE_INT_TypeDef SPI_TXE_INT) +*:SPIʼú +*ڲ: +SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +SPI_Mode_TypeDef:Mode:SPIģʽѡ +SPI_ClockPolarity_TypeDef:ClockPolarityLSPIʱӼѡ +SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ +*ڲ:void +**************************************************/ +void SSI0_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT) +{ + OTCON = (OTCON & 0XCF) | 0X10; + SS0CON1 = SS0CON1 & (~0X05) | FirstBit | + SPI_TXE_INT; + SS0CON0 = SS0CON0 & 0X80 | BaudRatePrescaler | + Mode | ClockPolarity | ClockPhase; +} + +/***************************************************** +*:void SSI0_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI0_SPI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SS0CON0 |= 0X80; + } + else + { + SS0CON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI0_SPI_SendData(uint8_t Data) +*:SPI +*ڲ: +uint8_t:Data:S{PI͵8λ +*ڲ:void +*****************************************************/ +void SSI0_SPI_SendData(uint8_t Data) +{ + SS0DAT = Data; +} + +/***************************************************** +*:uint8_t SSI0_SPI_ReceiveData(void) +*:SS0DATеֵ +*ڲ:void +*ڲ: +uint8_t:SPIյ8λ +*****************************************************/ +uint8_t SSI0_SPI_ReceiveData(void) +{ + return SS0DAT; +} + +/************************************************** +*:void SSI0_TWI_Init(uint8_t TWI_Address) +*:TWIʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void SSI0_TWI_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0XCF | 0X20; + SS0CON1 = TWI_Address << 1; +} + +/************************************************** +*:void SSI0_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI0_TWI_AcknowledgeConfig(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SS0CON0 |= 0X08; + } + else + { + SS0CON0 &= 0XF7; + } +} + +/************************************************** +*:void SSI0_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:ͨõַӦʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI0_TWI_GeneralCallCmd(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SS0CON1 |= 0X01; + } + else + { + SS0CON1 &= 0XFE; + } +} + +/************************************************** +*:FlagStatus SSI0_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +*:ȡTWI״̬ +*ڲ: +SSI_TWIState_TypeDef:SSI_TWIState:TWI״̬״̬ +*ڲ:void +**************************************************/ +FlagStatus SSI0_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +{ + if((SS0CON0&0x07) == SSI_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void SSI0_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI0_TWI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SS0CON0 |= 0X80; + } + else + { + SS0CON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI0_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:TWI͵8λ +*ڲ:void +*****************************************************/ +void SSI0_TWI_SendData(uint8_t Data) +{ + SS0DAT = Data; +} + +/***************************************************** +*:uint8_t SSI0_TWI_ReceiveData(void) +*:SS0DATеֵ +*ڲ:void +*ڲ: +uint8_t:TWIյ8λ +*****************************************************/ +uint8_t SSI0_TWI_ReceiveData(void) +{ + return SS0DAT; +} + +/************************************************** +*:void SSI0_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, UART_Mode_TypeDef Mode, UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +UART_Mode_TypeDef:Mode:UART1ģʽ +UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void SSI0_UART_Init(uint32_t UARTFsys, + uint32_t BaudRate, UART_Mode_TypeDef Mode, + UART_RX_TypeDef RxMode) +{ + OTCON |= 0x30; + SS0CON0 = SS0CON0 & 0X0F | Mode | RxMode; + SS0CON2 = UARTFsys / BaudRate / 256; + SS0CON1 = UARTFsys / BaudRate % 256; +} + +/***************************************************** +*:void SSI0_UART_SendData8(uint8_t Data) +*:UART8λ +*ڲ: +uint8_t:Data:UART͵8λ +*ڲ:void +*****************************************************/ +void SSI0_UART_SendData8(uint8_t Data) +{ + SS0DAT = Data; +} + +/***************************************************** +*:uint8_t SSI0_UART_ReceiveData8(void) +*:SS0DATеֵ +*ڲ:void +*ڲ: +uint8_t:UARTյ8λ +*****************************************************/ +uint8_t SSI0_UART_ReceiveData8(void) +{ + return SS0DAT; +} + +/***************************************************** +*:void SSI0_UART_SendData9(uint16_t Data) +*:UART9λ +*ڲ: +Data:͵ +*ڲ:void +*****************************************************/ +void SSI0_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if(Data_9Bit) + { + SS0CON0 |= 0x08; + } + else + { + SS0CON0 &= 0xf7; + } + + SS0DAT = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t SSI0_UART_ReceiveData9(void) +*:SS0DATеֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t SSI0_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = SS0DAT + ((uint16_t)(SS0CON0 & 0X04) << + 6); + SS0CON0 &= 0XFB; + return Data9; +} + +/***************************************************** +*:void SSI0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:SSI0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void SSI0_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + //жʹ/ر + if(NewState != DISABLE) + { + IE |= 0x10; + } + else + { + IE &= ~0x10; + } + + //жȼ + if(Priority != LOW) + { + IP |= 0x10; + } + else + { + IP &= ~0x10; + } +} + +/***************************************************** +*:FlagStatus SSI0_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG) +*:SSI0־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ȡı־λ +*ڲ: +FlagStatus:SSI־λ״̬ +*****************************************************/ +FlagStatus SSI0_GetFlagStatus(SSI_Flag_TypeDef + SSI_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + if((SSI_FLAG & SS0CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((SSI_FLAG & SS0CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void SSI0_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +*:SSI0־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void SSI0_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +{ + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + SS0CON1 &= (~SSI_FLAG); + } + else + { + SS0CON0 &= (~SSI_FLAG); + } +} +#endif + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi1.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi1.c new file mode 100644 index 0000000..afb2d84 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_ssi1.c @@ -0,0 +1,392 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_ssi1.c +// : +// ģ鹦 : SSI1̼⺯Cļ +// ֲб: +// : 2021/09/06 +// 汾 : V1.0001 +// ˵ : +//************************************************************* + +#include "sc92f_ssi.h" + +#if defined (SC92F742x) || defined (SC92F7490) +/************************************************** +*:void SSI1_DeInit(void) +*:SSI1ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void SSI1_DeInit(void) +{ + OTCON &= 0X3F; + SS1CON0 = 0X00; + SS1CON1 = 0X00; + SS1CON2 = 0X00; + SS1DAT = 0X00; + IE1 &= (~0X01); + IP1 &= (~0X01); +} + +/************************************************** +*:void SSI1_SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase,SPI_TXE_INT_TypeDef SPI_TXE_INT) +*:SPIʼú +*ڲ: +SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +SPI_Mode_TypeDef:Mode:SPIģʽѡ +SPI_ClockPolarity_TypeDef:ClockPolarityLSPIʱӼѡ +SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ +*ڲ:void +**************************************************/ +void SSI1_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + SPI_Mode_TypeDef Mode, + SPI_ClockPolarity_TypeDef ClockPolarity, + SPI_ClockPhase_TypeDef ClockPhase, + SPI_TXE_INT_TypeDef SPI_TXE_INT) +{ + OTCON = (OTCON & 0X3F) | 0X40; + SS1CON1 = SS1CON1 & (~0X05) | FirstBit | + SPI_TXE_INT; + SS1CON0 = SS1CON0 & 0X80 | BaudRatePrescaler | + Mode | ClockPolarity | ClockPhase; +} + +/***************************************************** +*:void SSI1_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI1_SPI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SS1CON0 |= 0X80; + } + else + { + SS1CON0 &= (~0X80); + } +} + +/***************************************************** +*:void SSI1_SPI_SendData(uint8_t Data) +*:SPI +*ڲ: +uint8_t:Data:S{PI͵8λ +*ڲ:void +*****************************************************/ +void SSI1_SPI_SendData(uint8_t Data) +{ + SS1DAT = Data; +} + +/***************************************************** +*:uint8_t SSI1_SPI_ReceiveData(void) +*:SS1DATеֵ +*ڲ:void +*ڲ: +uint8_t:SPIյ8λ +*****************************************************/ +uint8_t SSI1_SPI_ReceiveData(void) +{ + return SS1DAT; +} + +/************************************************** +*:void SSI1_TWI_Init(uint8_t TWI_Address) +*:TWIʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void SSI1_TWI_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0X3F | 0X80; + SS1CON1 = TWI_Address << 1; +} + +/************************************************** +*:void SSI1_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI1_TWI_AcknowledgeConfig(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SS1CON0 |= 0X08; + } + else + { + SS1CON0 &= 0XF7; + } +} + +/************************************************** +*:void SSI1_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:ͨõַӦʹ/ʧѡ +*ڲ:void +**************************************************/ +void SSI1_TWI_GeneralCallCmd(FunctionalState + NewState) +{ + if (NewState != DISABLE) + { + SS1CON1 |= 0X01; + } + else + { + SS1CON1 &= 0XFE; + } +} + +/***************************************************** +*:void SSI1_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void SSI1_TWI_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SS1CON0 |= 0X80; + } + else + { + SS1CON0 &= (~0X80); + } +} + +/************************************************** +*:FlagStatus SSI0_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +*:ȡTWI״̬ +*ڲ: +SSI_TWIState_TypeDef:SSI_TWIState:TWI״̬״̬ +*ڲ:void +**************************************************/ +FlagStatus SSI1_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) +{ + if((SS1CON0&0x07) == SSI_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void SSI1_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:TWI͵8λ +*ڲ:void +*****************************************************/ +void SSI1_TWI_SendData(uint8_t Data) +{ + SS1DAT = Data; +} + +/***************************************************** +*:uint8_t SSI1_TWI_ReceiveData(void) +*:SS1DATеֵ +*ڲ:void +*ڲ: +uint8_t:TWIյ8λ +*****************************************************/ +uint8_t SSI1_TWI_ReceiveData(void) +{ + return SS1DAT; +} + +/************************************************** +*:void SSI1_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, UART_Mode_TypeDef Mode, UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +UART_Mode_TypeDef:Mode:UART1ģʽ +UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void SSI1_UART_Init(uint32_t UARTFsys, + uint32_t BaudRate, UART_Mode_TypeDef Mode, + UART_RX_TypeDef RxMode) +{ + OTCON |= 0xC0; + SS1CON0 = SS1CON0 & 0X0F | Mode | RxMode; + SS1CON2 = UARTFsys / BaudRate / 256; + SS1CON1 = UARTFsys / BaudRate % 256; +} + +/***************************************************** +*:void SSI1_UART_SendData8(uint8_t Data) +*:UART8λ +*ڲ: +uint8_t:Data:UART͵8λ +*ڲ:void +*****************************************************/ +void SSI1_UART_SendData8(uint8_t Data) +{ + SS1DAT = Data; +} + +/***************************************************** +*:uint8_t SSI1_UART_ReceiveData8(void) +*:SS0DATеֵ +*ڲ:void +*ڲ: +uint8_t:UARTյ8λ +*****************************************************/ +uint8_t SSI1_UART_ReceiveData8(void) +{ + return SS1DAT; +} + +/***************************************************** +*:void SSI1_UART_SendData9(uint16_t Data) +*:UART9λ +*ڲ: +Data:͵ +*ڲ:void +*****************************************************/ +void SSI1_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if(Data_9Bit) + { + SS1CON0 |= 0x08; + } + else + { + SS1CON0 &= 0xf7; + } + + SS1DAT = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t SSI1_UART_ReceiveData9(void) +*:SS1DATеֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t SSI1_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = SS1DAT + ((uint16_t)(SS1CON0 & 0X04) << + 6); + SS1CON0 &= 0XFB; + return Data9; +} + +/***************************************************** +*:void SSI1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:SSI1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void SSI1_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + //жʹ/ر + if(NewState != DISABLE) + { + IE1 |= 0x01; + } + else + { + IE1 &= 0xFE; + } + + //жȼ + if(Priority != LOW) + { + IP1 |= 0x01; + } + else + { + IP1 &= 0xFE; + } +} + +/***************************************************** +*:FlagStatus SSI1_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG) +*:SSI1־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ȡı־λ +*ڲ: +FlagStatus:SSI־λ״̬ +*****************************************************/ +FlagStatus SSI1_GetFlagStatus(SSI_Flag_TypeDef + SSI_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + if((SSI_FLAG & SS1CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((SSI_FLAG & SS1CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void SSI1_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +*:SSI1־״̬ +*ڲ: +SSI_Flag_TypeDef:SSI_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void SSI1_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) +{ + if((SSI_FLAG == SPI_FLAG_SPIF) || + (SSI_FLAG == SPI_FLAG_WCOL) || + (SSI_FLAG == SPI_FLAG_TXE)) + { + SS1CON1 &= (~SSI_FLAG); + } + else + { + SS1CON0 &= (~SSI_FLAG); + } +} +#endif + +/******************* (C) COPYRIGHT 2018 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer0.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer0.c new file mode 100644 index 0000000..a178d70 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer0.c @@ -0,0 +1,165 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_tiemr0.c +// : ԪӦŶ +// ģ鹦: TIMER0̼⺯Cļ +// : 2022323 +// 汾: V1.10002 +// ˵: +//************************************************************* + +#include "sc92f_timer0.h" + +/************************************************** +*:void TIM0_DeInit(void) +*:TIMER0ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void TIM0_DeInit(void) +{ + TMOD &= 0XF0; + TCON &= 0XCD; + TMCON &= 0XFE; + TH0 = 0X00; + TL0 = 0X00; + ET0 = 0; + IPT0 = 0; +} + +/************************************************** +*:void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef TIM0_PrescalerSelection, TIM0_CountMode_TypeDef TIM0_CountMode) +*:TIMER0ú +*ڲ: +TIM0_PresSel_TypeDef:TIM0_PrescalerSelection:ԤƵѡ +TIM0_CountMode_TypeDef:TIM0_CountMode:/ʱģʽѡ +*ڲ:void +**************************************************/ +void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef + TIM0_PrescalerSelection, + TIM0_CountMode_TypeDef TIM0_CountMode) +{ + if(TIM0_PrescalerSelection == + TIM0_PRESSEL_FSYS_D12) + { + TMCON &= 0XFE; + } + else + if(TIM0_PrescalerSelection == + TIM0_PRESSEL_FSYS_D1) + { + TMCON |= 0X01; + } + + if(TIM0_CountMode == TIM0_MODE_TIMER) + { + TMOD &= 0xFB; + } + else + if(TIM0_CountMode == TIM0_MODE_COUNTER) + { + TMOD |= 0x04; + } +} + +/************************************************** +*:void TIM0_WorkMode0Config(uint16_t TIM0_SetCounter) +*:TIMER0ģʽ0ú +*ڲ: +uint16_t:TIM0_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM0_WorkMode0Config(uint16_t + TIM0_SetCounter) +{ + TMOD &= 0XFC; + TL0 = (uint8_t)TIM0_SetCounter; + TH0 = (TIM0_SetCounter >> 5); +} + +/************************************************** +*:void TIM0_WorkMode1Config(uint16_t TIM0_SetCounter) +*:TIMER0ģʽ1ú +*ڲ: +uint16_t:TIM0_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM0_WorkMode1Config(uint16_t + TIM0_SetCounter) +{ + TMOD &= 0XFC; + TMOD |= 0X01; + TL0 = TIM0_SetCounter % 256; + TH0 = TIM0_SetCounter / 256; +} + +/************************************************** +*:void TIM0_WorkMode2Config(uint8_t TIM0_SetCounter) +*:TIMER0ģʽ2ú +*ڲ: +uint8_t:TIM0_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM0_WorkMode2Config(uint8_t TIM0_SetCounter) +{ + TMOD &= 0XFC; + TMOD |= 0X02; + TL0 = TIM0_SetCounter; + TH0 = TIM0_SetCounter; +} + +/************************************************** +*:void TIM0_WorkModeConfig(TIM0_WorkMode_TypeDef TIM0_WorkMode, uint16_t TIM0_SetCounter1, uint16_t TIM0_SetCounter2) +*:TIMER0ģʽú +*ڲ: +TIM0_WorkMode_TypeDef:TIM0_WorkMode:TIMER0ģʽѡ +uint16_t:TIM0_SetCounter1:TIMER0ֵ1 +uint16_t:TIM0_SetCounter2:TIMER0ֵ2 +*ڲ:void +**************************************************/ +void TIM0_WorkModeConfig(TIM0_WorkMode_TypeDef + TIM0_WorkMode, uint16_t TIM0_SetCounter1, + uint16_t TIM0_SetCounter2) +{ + switch (TIM0_WorkMode) + { + case TIM0_WORK_MODE0: + TIM0_WorkMode0Config(TIM0_SetCounter1); + break; + + case TIM0_WORK_MODE1: + TIM0_WorkMode1Config(TIM0_SetCounter1); + break; + + case TIM0_WORK_MODE2: + TIM0_WorkMode2Config(TIM0_SetCounter1); + break; + + case TIM0_WORK_MODE3: + TIM0_WorkMode3Config(TIM0_SetCounter1, + TIM0_SetCounter2); + break; + default: + break; + } +} + +/************************************************** +*:void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, uint8_t TIM1_SetCounter) +*:TIMER0ģʽ3ú +*ڲ: +uint8_t:TIM0_SetCounter:TIMER0_TL0ֵ +uint8_t:TIM1_SetCounter +TIMER0_TH0ֵ +*ڲ:void +**************************************************/ +void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, + uint8_t TIM1_SetCounter) +{ + TMOD |= 0X03; + TL0 = TIM0_SetCounter; + TH0 = TIM1_SetCounter; +} + + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer1.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer1.c new file mode 100644 index 0000000..cc1974b --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer1.c @@ -0,0 +1,140 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_timer1.c +// : ԪӦŶ +// ģ鹦: TIMER1̼⺯Cļ +// ֲб: +// : 2022323 +// 汾: V1.10001 +// ˵:ļSC92FϵоƬ +//************************************************************* +#include "sc92f_timer1.h" + +/************************************************** +*:void TIM1_DeInit(void) +*:TIMER1ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void TIM1_DeInit(void) +{ + TMOD &= 0X0F; + TCON &= 0X37; + TMCON &= 0XFD; + TH1 = 0X00; + TL1 = 0X00; + ET1 = 0; + IPT1 = 0; +} + +/************************************************** +*:void TIM1_TimeBaseInit(TIM1_PresSel_TypeDef TIM1_PrescalerSelection, TIM1_CountMode_TypeDef TIM1_CountMode) +*:TIMER1ú +*ڲ: +TIM1_PresSel_TypeDef:TIM1_PrescalerSelection:ԤƵѡ +TIM1_CountMode_TypeDef:TIM1_CountMode:/ʱģʽѡ +*ڲ:void +**************************************************/ +void TIM1_TimeBaseInit(TIM1_PresSel_TypeDef TIM1_PrescalerSelection, + TIM1_CountMode_TypeDef TIM1_CountMode) +{ + //жǷҪзƵ + if(TIM1_PrescalerSelection == TIM1_PRESSEL_FSYS_D12) + { + TMCON &= 0xFD; + } + else if(TIM1_PrescalerSelection == TIM1_PRESSEL_FSYS_D1) + { + TMCON |= 0x02; + } + + //TIM1ģʽ + if(TIM1_CountMode == TIM1_MODE_TIMER) + { + TMOD &= 0xBF; + } + else if(TIM1_CountMode == TIM1_MODE_COUNTER) + { + TMOD |= 0x40; + } +} + +/************************************************** +*:void TIM1_WorkMode0Config(uint16_t TIM1_SetCounter) +*:TIMER1ģʽ0ú +*ڲ: +uint16_t:TIM1_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM1_WorkMode0Config(uint16_t + TIM1_SetCounter) +{ + TMOD &= 0XCF; + TL1 = (uint8_t)TIM1_SetCounter; + TH1 = (TIM1_SetCounter >> 5); +} + +/************************************************** +*:void TIM1_WorkMode1Config(uint16_t TIM1_SetCounter) +*:TIMER1ģʽ1ú +*ڲ: +uint16_t:TIM1_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM1_WorkMode1Config(uint16_t + TIM1_SetCounter) +{ + TMOD &= 0XCF; + TMOD |= 0X10; + TL1 = TIM1_SetCounter % 256; + TH1 = TIM1_SetCounter / 256; +} + +/************************************************** +*:void TIM1_WorkMode2Config(uint8_t TIM1_SetCounter) +*:TIMER1ģʽ2ú +*ڲ: +uint8_t:TIM1_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM1_WorkMode2Config(uint8_t TIM1_SetCounter) +{ + TMOD &= 0XCF; + TMOD |= 0X20; + TL1 = TIM1_SetCounter; + TH1 = TIM1_SetCounter; +} + +/************************************************** +*:void TIM1_WorkModeConfig(TIM1_WorkMode_TypeDef TIM1_WorkMode, uint16_t TIM1_SetCounter) +*:TIMER1ģʽú +*ڲ: +TIM1_WorkMode_TypeDef:TIM1_WorkMode:TIMER1ģʽѡ +uint16_t:TIM1_SetCounter:TIMER1ֵ +*ڲ:void +**************************************************/ +void TIM1_WorkModeConfig(TIM1_WorkMode_TypeDef + TIM1_WorkMode, uint16_t TIM1_SetCounter) +{ + switch(TIM1_WorkMode) + { + case TIM1_WORK_MODE0: + TIM1_WorkMode0Config(TIM1_SetCounter); + break; + + case TIM1_WORK_MODE1: + TIM1_WorkMode1Config(TIM1_SetCounter); + break; + + case TIM1_WORK_MODE2: + TIM1_WorkMode2Config(TIM1_SetCounter); + break; + + default: + break; + } +} + + + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer2.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer2.c new file mode 100644 index 0000000..a9ea6a1 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer2.c @@ -0,0 +1,541 @@ +//************************************************************ +// Copyright (c) 深圳市赛元微电子有限公司 +// 文件名称: sc92f_timer2.c +// 作者: 赛元应用团队 +// 模块功能: TIMER2固件库函数C文件 +// 最后更正日期: 2022年3月23日 +// 版本: V1.10004 +// 说明: 该文件仅适用于SC92F系列芯片 +//************************************************************* + +#include "sc92f_timer2.h" + +#if !defined (SC92L853x) && !defined(SC92L753x) + +/************************************************** +*函数名称:void TIM2_DeInit(void) +*函数功能:TIMER2相关寄存器复位至缺省值 +*入口参数:void +*出口参数:void +**************************************************/ +void TIM2_DeInit(void) +{ + T2CON = 0X00; +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) && !defined (SC92F735X) + T2MOD = 0X00; +#endif + TMCON &= 0XFB; + TH2 = 0X00; + TL2 = 0X00; + RCAP2H = 0X00; + RCAP2L = 0X00; + ET2 = 0; + IPT2 = 0; +} + +/************************************************** +*函数名称:void TIM2_TimeBaseInit(TIM2_PresSel_TypeDef TIM2_PrescalerSelection,TIM2_CountMode_TypeDef TIM2_CountMode, TIM2_CountDirection_TypeDef TIM2_CountDirection) +*函数功能:TIMER2基本设置配置函数 +*入口参数: +TIM2_PresSel_TypeDef:TIM2_PrescalerSelection:预分频选择 +TIM2_CountMode_TypeDef:TIM2_CountMode:计数/定时模式选择 +TIM2_CountDirection_TypeDef:TIM2_CountDirection:计数方向选择 +*出口参数:void +**************************************************/ +void TIM2_TimeBaseInit(TIM2_PresSel_TypeDef + TIM2_PrescalerSelection, + TIM2_CountMode_TypeDef TIM2_CountMode, + TIM2_CountDirection_TypeDef TIM2_CountDirection) +{ + if(TIM2_PrescalerSelection == TIM2_PRESSEL_FSYS_D12) + { + TMCON &= 0XFB; + } + else if(TIM2_PrescalerSelection == TIM2_PRESSEL_FSYS_D1) + { + TMCON |= 0X04; + } + + + +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) && !defined (SC92F735X)\ + && !defined (SC92F825X) && !defined (SC92F835X) + + if(TIM2_CountDirection == TIM2_COUNTDIRECTION_UP) + { + T2MOD &= 0XFE; + } + else if(TIM2_CountDirection == + TIM2_COUNTDIRECTION_DOWN_UP) + { + T2MOD |= 0X01; + } + + if(TIM2_CountMode == TIM2_MODE_TIMER) + { + T2CON &= 0XFD; + } + else if(TIM2_CountMode == TIM2_MODE_COUNTER) + { + T2CON |= 0X02; + } + + +#else + TIM2_CountMode = 1; + TIM2_CountDirection = 0; +#endif + +} + + +/************************************************** +*函数名称:void TIM2_WorkMode1Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式1配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode1Config(uint16_t + TIM2_SetCounter) +{ + RCAP2L = TIM2_SetCounter % 256; + RCAP2H = TIM2_SetCounter / 256; + TL2 = RCAP2L; + TH2 = RCAP2H; +} + +/************************************************** +*函数名称:void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef TIM2_WorkMode, uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式配置函数 +*入口参数: +TIM2_WorkMode_TypeDef:TIM2_WorkMode:TIMER2工作模式选择 +uint16_t:TIM2_SetCounter:TIMER2计数初值配置 +*出口参数:void +**************************************************/ +void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef + TIM2_WorkMode, uint16_t TIM2_SetCounter) +{ + switch(TIM2_WorkMode) + { + case TIM2_WORK_MODE1: + TIM2_WorkMode1Config(TIM2_SetCounter); + break; +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) && !defined (SC92F735X) && !defined (SC92F725X) + case TIM2_WORK_MODE0: + TIM2_WorkMode0Config(TIM2_SetCounter); + break; + + case TIM2_WORK_MODE3: + TIM2_WorkMode3Config(TIM2_SetCounter); + break; +#endif + default: + break; + } +} + +#if !defined (SC92F730x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F725X) && !defined (SC92F735X) +/************************************************** +*函数名称:void TIM2_WorkMode0Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式0配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode0Config(uint16_t + TIM2_SetCounter) +{ + T2CON |= 0x09; + TL2 = TIM2_SetCounter % 256; + TH2 = TIM2_SetCounter / 256; +} + +/************************************************** +*函数名称:void TIM2_WorkMode3Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式3配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode3Config(uint16_t + TIM2_SetCounter) +{ + RCAP2L = TIM2_SetCounter % 256; + RCAP2H = TIM2_SetCounter / 256; + T2MOD |= 0X02; +} + +/***************************************************** +*函数名称:void TIM2_SetEXEN2(FunctionalState NewState) +*函数功能:TIMER2_EXEN2配置函数 +*入口参数: +FunctionalState:NewState:EXEN2使能选择 +*出口参数:void +*****************************************************/ +void TIM2_SetEXEN2(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + EXEN2 = 0; + } + else + { + EXEN2 = 1; + } +} +#endif + +/***************************************************** +*函数名称:void TIM2_Cmd(FunctionalState NewState) +*函数功能:TIMER2功能开关函数 +*入口参数: +FunctionalState:NewState:功能启动/关闭选择 +*出口参数:void +*****************************************************/ +void TIM2_Cmd(FunctionalState NewState) +{ + if(NewState == DISABLE) + { + TR2 = 0; + } + else + { + TR2 = 1; + } +} + +/***************************************************** +*函数名称:void TIM2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*函数功能:TIMER2中断初始化 +*入口参数: +FunctionalState:NewState:中断使能/关闭选择 +PriorityStatus:Priority:中断优先级选择 +*出口参数:void +*****************************************************/ +void TIM2_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState == DISABLE) + { + ET2 = 0; + } + else + { + ET2 = 1; + } + + /************************************************************/ + if(Priority == LOW) + { + IPT2 = 0; + } + else + { + IPT2 = 1; + } +} + +/***************************************************** +*函数名称:FlagStatus TIM2_GetFlagStatus(void) +*函数功能:获得TIMER2中断标志状态 +*入口参数:void +*出口参数: +FlagStatus:TIMER2中断标志状态 +*****************************************************/ +FlagStatus TIM2_GetFlagStatus(TIM2_Flag_TypeDef + TIM2_Flag) +{ + FlagStatus status = RESET; + + if((TIM2_Flag & T2CON) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/***************************************************** +*函数名称:void TIM2_ClearFlag(void) +*函数功能:清除TIMER2中断标志状态 +*入口参数:void +*出口参数:void +*****************************************************/ +void TIM2_ClearFlag(TIM2_Flag_TypeDef TIM2_Flag) +{ + T2CON &= (~TIM2_Flag); +} + +#else + +/************************************************** +*函数名称:void TIM2_DeInit(void) +*函数功能:TIMER2相关寄存器复位至初始值 +*入口参数:void +*出口参数:void +**************************************************/ +void TIM2_DeInit() +{ + TXINX = 0x02; //TIMER2选择 + TXCON = 0X00; + TXMOD = 0X00; + RCAPXH = 0X00; + RCAPXL = 0X00; + THX = 0X00; + TLX = 0X00; + IE1 &= 0X3F; + IP1 &= 0X3F; + ET2 = 0; + IPT2 = 0; +} + +/************************************************** +*函数名称:void TIM2_PrescalerSelection(TIM2_PresSel_TypeDef TIM2_PrescalerSelection) +*函数功能:TIMER2 预分频选择 +*入口参数: +TIM2_PresSel_TypeDef:TIM2_PrescalerSelection:预分频选择 +*出口参数:void +**************************************************/ +void TIM2_PrescalerSelection(TIM2_PresSel_TypeDef TIM2_PrescalerSelection) +{ + TXINX = 0x02; + + if (TIM2_PrescalerSelection == TIM2_PRESSEL_FSYS_D12) + { + TXMOD &= 0X7F; + } + else if (TIM2_PrescalerSelection == TIM2_PRESSEL_FSYS_D1) + { + TXMOD |= 0X80; + } +} + +/************************************************** +*函数名称:void TIM2_TimeBaseInit(TIM2_CountMode_TypeDef TIM2_CountMode, TIM2_CountDirection_TypeDef TIM2_CountDirection) +*函数功能:TIM2基本设置配置函数 +*入口参数: +TIM2_CountMode_TypeDef:TIM2_CountMode:计数/定时模式选择 +TIM2_CountDirection_TypeDef:TIM2_CountDirection:计数方向选择 +*出口参数:void +**************************************************/ +void TIM2_TimeBaseInit(TIM2_PresSel_TypeDef TIM2_PrescalerSelection, + TIM2_CountMode_TypeDef TIM2_CountMode, + TIM2_CountDirection_TypeDef TIM2_CountDirection) +{ + TXINX = 0x02; + + TXMOD &= 0X7F; + TXMOD = TIM2_PrescalerSelection<<7; + + if (TIM2_CountMode == TIM2_MODE_TIMER) + { + TXCON &= 0XFD; + } + else if (TIM2_CountMode == TIM2_MODE_COUNTER) + { + TXCON |= 0X02; + } + + if (TIM2_CountDirection == TIM2_COUNTDIRECTION_UP) + { + TXMOD &= 0XFE; + } + else if (TIM2_CountDirection == TIM2_COUNTDIRECTION_DOWN_UP) + { + TXMOD |= 0X01; + } +} + +/************************************************** +*函数名称:void TIM2_WorkMode0Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式0配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode0Config(uint16_t TIM2_SetCounter) +{ + TXINX = 0x02; + CP = 1; + TLX = TIM2_SetCounter % 256; + THX = TIM2_SetCounter / 256; +} + +/************************************************** +*函数名称:void TIM2_WorkMode1Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式1配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode1Config(uint16_t TIM2_SetCounter) +{ + TXINX = 0x02; + RCAPXL = TIM2_SetCounter % 256; + RCAPXH = TIM2_SetCounter / 256; + + TLX = RCAPXL; + THX = RCAPXH; +} + +/************************************************** +*函数名称:void TIM2_WorkMode3Config(uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式3配置函数 +*入口参数: +uint16_t:TIM2_SetCounter:配置计数初值 +*出口参数:void +**************************************************/ +void TIM2_WorkMode3Config(uint16_t TIM2_SetCounter) +{ + TXINX = 0x02; + RCAPXL = TIM2_SetCounter % 256; + RCAPXH = TIM2_SetCounter / 256; + TXMOD |= 0X02; +} +/************************************************** +*函数名称:void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef TIM2_WorkMode, uint16_t TIM2_SetCounter) +*函数功能:TIMER2工作模式配置函数 +*入口参数: +TIM2_WorkMode_TypeDef:TIM2_WorkMode:TIMER2工作模式选择 +uint16_t:TIM2_SetCounter:TIMER2计数初值配置 +*出口参数:void +**************************************************/ +void TIM2_WorkModeConfig(TIM2_WorkMode_TypeDef TIM2_WorkMode, uint16_t TIM2_SetCounter) +{ + switch (TIM2_WorkMode) + { + case TIM2_WORK_MODE0: + TIM2_WorkMode0Config(TIM2_SetCounter); + break; + + case TIM2_WORK_MODE1: + TIM2_WorkMode1Config(TIM2_SetCounter); + break; + + case TIM2_WORK_MODE3: + TIM2_WorkMode3Config(TIM2_SetCounter); + break; + + default: + break; + } +} +/***************************************************** +*函数名称:void TIM2_SetEXEN2(FunctionalState NewState) +*函数功能:TIMER2_EXEN2配置函数 +*入口参数: +FunctionalState:NewState:EXEN2使能选择 +*出口参数:void +*****************************************************/ +void TIM2_SetEXEN2(FunctionalState NewState) +{ + TXINX = 0x02; + + if (NewState == DISABLE) + { + EXENX = 0; + } + else + { + EXENX = 1; + } +} + +/***************************************************** +*函数名称:void TIM2_Cmd(FunctionalState NewState) +*函数功能:TIMER2功能开关函数 +*入口参数: +FunctionalState:NewState:功能启动/关闭选择 +*出口参数:void +*****************************************************/ +void TIM2_Cmd(FunctionalState NewState) +{ + TXINX = 0x02; + + if (NewState == DISABLE) + { + TRX = 0; + } + else + { + TRX = 1; + } +} + +/***************************************************** +*函数名称:void TIM2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*函数功能:TIMER2 +*入口参数: +FunctionalState:NewState:中断使能/关闭选择 +PriorityStatus:Priority:中断优先级选择 +*出口参数:void +*****************************************************/ +void TIM2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + TXINX = 0x02; + + if (NewState == DISABLE) + { + ET2 = 0; + } + else + { + ET2 = 1; + } + + if (Priority == LOW) + { + IPT2 = 0; + } + else + { + IPT2 = 1; + } +} + +/***************************************************** +*函数名称:FlagStatus TIM2_GetFlagStatus(void) +*函数功能:获得TIMER2中断标志状态 +*入口参数: +TIM2_Flag_TypeDef:TIM2_Flag:TIMER2标志选择 +*出口参数: +FlagStatus:TIMER2中断标志状态 +*****************************************************/ +FlagStatus TIM2_GetFlagStatus(TIM2_Flag_TypeDef TIM2_Flag) +{ + FlagStatus status = RESET; + TXINX = 0x02; + + if ((TIM2_Flag & TXCON) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/***************************************************** +*函数名称:void TIMX_ClearFlag(void) +*函数功能:清除TIMER2中断标志状态 +*入口参数: +TIM2_Flag_TypeDef:TIM2_Flag:TIMER2标志选择 +*出口参数:void +*****************************************************/ +void TIM2_ClearFlag(TIM2_Flag_TypeDef TIM2_Flag) +{ + TXINX = 0x02; + TXCON &= (~TIM2_Flag); +} + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer3.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer3.c new file mode 100644 index 0000000..4adab11 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer3.c @@ -0,0 +1,280 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timerx.c +// : +// ģ鹦 : TIMER3̼⺯Cļ +// : 2022/01/14 +// 汾 : V1.1000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_timer3.h" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void TIMX_DeInit(void) +*:TIMER3ؼĴλʼֵ +*ڲ:void +*ڲ:void +**************************************************/ +void TIM3_DeInit() +{ + TXINX = 0x03; //TIMER3 ѡ + TXCON = 0X00; + TXMOD = 0X00; + RCAPXH = 0X00; + RCAPXL = 0X00; + THX = 0X00; + TLX = 0X00; + IE1 &= 0X3F; + IP1 &= 0X3F; + ET2 = 0; + IPT2 = 0; +} + +/************************************************** +*:void TIM3_PrescalerSelection(TIMX_TimerSelect_TypeDef TIMX_TimerSelect, TIMX_PresSel_TypeDef TIMX_PrescalerSelection) +*:TIMER3 ԤƵѡ +*ڲ: +TIM3_PresSel_TypeDef:TIM3_PrescalerSelection:ԤƵѡ +*ڲ:void +**************************************************/ +void TIM3_PrescalerSelection(TIM3_PresSel_TypeDef TIM3_PrescalerSelection) +{ + TXINX = 0x03; + + if(TIM3_PrescalerSelection == TIM3_PRESSEL_FSYS_D12) + { + TXMOD &= 0X7F; + } + else + if(TIM3_PrescalerSelection == TIM3_PRESSEL_FSYS_D1) + { + TXMOD |= 0X80; + } +} + +/************************************************** +*:void TIM3_WorkMode1Config(uint16_t TIM3_SetCounter) +*:TIMER3ģʽ1ú +*ڲ: +uint16_t TIM3_SetCounter üֵ +*ڲ:void +**************************************************/ +void TIM3_WorkMode1Config(uint16_t TIM3_SetCounter) +{ + TXINX = 0x03; + RCAPXL = TIM3_SetCounter % 256; + RCAPXH = TIM3_SetCounter / 256; + + TLX = RCAPXL; + THX = RCAPXH; +} + +/***************************************************** +*:void TIM3_Cmd(FunctionalState NewState) +*:TIMER3ܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void TIM3_Cmd(FunctionalState NewState) +{ + TXINX = 0x03; + + if (NewState == DISABLE) + { + TRX = 0; + } + else + { + TRX = 1; + } +} + +/***************************************************** +*:void TIM3_ITConfig(TIM3_TimerSelect_TypeDef TIM3_TimerSelect, FunctionalState NewState, PriorityStatus Priority) +*:TIMER3жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void TIM3_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + TXINX = 0x03; + + if(NewState == DISABLE) + { + IE1 &= 0XBF; + } + else + { + IE1 |= 0X40; + } + + if(Priority == LOW) + { + IP1 &= 0XBF; + } + else + { + IP1 |= 0X40; + } +} + +/***************************************************** +*:FlagStatus TIM3_GetFlagStatus(void) +*:TIMER3жϱ־״̬ +*ڲ: +TIM3_Flag_TypeDef:TIM3_Flag:TIMER3־ѡ +*ڲ: +FlagStatus:TIMER3жϱ־״̬ +*****************************************************/ +FlagStatus TIM3_GetFlagStatus(TIM3_Flag_TypeDef TIM3_Flag) +{ + FlagStatus status = RESET; + TXINX = 0x03; + + if((TIM3_Flag & TXCON) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/***************************************************** +*:void TIM3_ClearFlag(TIM3_Flag_TypeDef TIM3_Flag) +*:TIMER3жϱ־״̬ +*ڲ: +TIM3_Flag_TypeDef:TIM3_Flag:TIMER3־ѡ +*ڲ:void +*****************************************************/ +void TIM3_ClearFlag(TIM3_Flag_TypeDef TIM3_Flag) +{ + TXINX = 0x03; + TXCON &= (~TIM3_Flag); +} + + +/************************************************** +*:void TIM3_TimeBaseInit(TIM3_CountMode_TypeDef TIM3_CountMode, TIM3_CountDirection_TypeDef TIM3_CountDirection) +*:TIM3ú +*ڲ: +TIM3_CountMode_TypeDef:TIM3_CountMode:/ʱģʽѡ +TIM3_CountDirection_TypeDef:TIM3_CountDirection:ѡ +*ڲ:void +**************************************************/ +void TIM3_TimeBaseInit(TIM3_CountMode_TypeDef TIM3_CountMode, + TIM3_CountDirection_TypeDef TIM3_CountDirection) +{ + TXINX = 0x03; + + if(TIM3_CountMode == TIM3_MODE_TIMER) + { + TXCON &= 0XFD; + } + else + if(TIM3_CountMode == TIM3_MODE_COUNTER) + { + TXCON |= 0X02; + } + + /************************************************************/ + if(TIM3_CountDirection == TIM3_COUNTDIRECTION_UP) + { + TXMOD &= 0XFE; + } + else + if(TIM3_CountDirection == TIM3_COUNTDIRECTION_DOWN_UP) + { + TXMOD |= 0X01; + } +} + +/************************************************** +*:void TIM3_WorkMode0Config(uint16_t TIM3_SetCounter) +*:TIMER3ģʽ0ú +*ڲ: +uint16_t:TIM3_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM3_WorkMode0Config(uint16_t TIM3_SetCounter) +{ + TXINX = 0x03; + CP = 1; + TLX = TIM3_SetCounter % 256; + THX = TIM3_SetCounter / 256; +} +/************************************************** +*:void TIM3_WorkMode3Config(uint16_t TIM3_SetCounter) +*:TIMER3ģʽ3ú +*ڲ: +uint16_t:TIM3_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM3_WorkMode3Config(uint16_t TIM3_SetCounter) +{ + TXINX = 0x03; + RCAPXL = TIM3_SetCounter % 256; + RCAPXH = TIM3_SetCounter / 256; + TXMOD |= 0X02; +} +/************************************************** +*:void TIM3_WorkModeConfig(TIM3_WorkMode_TypeDef TIM3_WorkMode, uint16_t TIM3_SetCounter) +*:TIMER3ģʽú +*ڲ: +TIM3_WorkMode_TypeDef:TIM3_WorkMode:TIMER3ģʽѡ +uint16_t:TIM3_SetCounter:TIMER3ֵ +*ڲ:void +**************************************************/ +void TIM3_WorkModeConfig(TIM3_WorkMode_TypeDef TIM3_WorkMode, uint16_t TIM3_SetCounter) +{ + switch (TIM3_WorkMode) + { + case TIM3_WORK_MODE0: + TIM3_WorkMode0Config(TIM3_SetCounter); + break; + + case TIM3_WORK_MODE1: + TIM3_WorkMode1Config(TIM3_SetCounter); + break; + + case TIM3_WORK_MODE3: + TIM3_WorkMode3Config(TIM3_SetCounter); + break; + + default: + break; + } +} +/***************************************************** +*:void TIM3_SetEXEN3(FunctionalState NewState) +*:TIMER3_EXEN3ú +*ڲ: +FunctionalState:NewState:EXEN3ʹѡ +*ڲ:void +*****************************************************/ +void TIM3_SetEXEN3(FunctionalState NewState) +{ + TXINX = 0x03; + + if (NewState == DISABLE) + { + EXENX = 0; + } + else + { + EXENX = 1; + } +} + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer4.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer4.c new file mode 100644 index 0000000..6c649b7 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_timer4.c @@ -0,0 +1,278 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_timer4.c +// : +// ģ鹦 : TIMER4̼⺯Cļ +// : 2022/01/18 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_timer4.h" + + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void TIM4_DeInit(void) +*:TIMER4ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void TIM4_DeInit() +{ + TXINX = 0x04; //TIMER4 ѡ + TXCON = 0X00; + TXMOD = 0X00; + RCAPXH = 0X00; + RCAPXL = 0X00; + THX = 0X00; + TLX = 0X00; + IE1 &= 0X3F; + IP1 &= 0X3F; + ET2 = 0; + IPT2 = 0; +} + +/************************************************** +*:void TIM4_PrescalerSelection(TIM4_PresSel_TypeDef TIM4_PrescalerSelection) +*:TIMER4 ԤƵѡ +*ڲ: +TIM4_PresSel_TypeDef:TIM4_PrescalerSelection:ԤƵѡ +*ڲ:void +**************************************************/ +void TIM4_PrescalerSelection(TIM4_PresSel_TypeDef TIM4_PrescalerSelection) +{ + TXINX = 0x04; + + if (TIM4_PrescalerSelection == TIM4_PRESSEL_FSYS_D12) + { + TXMOD &= 0X7F; + } + else if (TIM4_PrescalerSelection == TIM4_PRESSEL_FSYS_D1) + { + TXMOD |= 0X80; + } +} + +/************************************************** +*:void TIM4_WorkMode1Config(uint16_t TIM4_SetCounter) +*:TIMER4ģʽ1ú +*ڲ: +uint16_t:TIM4_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM4_WorkMode1Config(uint16_t TIM4_SetCounter) +{ + TXINX = 0x04; + RCAPXL = TIM4_SetCounter % 256; + RCAPXH = TIM4_SetCounter / 256; + + TLX = RCAPXL; + THX = RCAPXH; +} + +/***************************************************** +*:void TIM4_Cmd(FunctionalState NewState) +*:TIMER4ܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void TIM4_Cmd(FunctionalState NewState) +{ + TXINX = 0x04; + + if (NewState == DISABLE) + { + TRX = 0; + } + else + { + TRX = 1; + } +} + +/***************************************************** +*:void TIMX_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:TIMER4жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void TIM4_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + TXINX = 0x04; + + if (NewState == DISABLE) + { + IE1 &= 0X7F; + } + else + { + IE1 |= 0X80; + } + + if (Priority == LOW) + { + IP1 &= 0X7F; + } + else + { + IP1 |= 0X80; + } +} + +/***************************************************** +*:FlagStatus TIM4_GetFlagStatus(TIM4_Flag_TypeDef TIM4_Flag) +*:TIMER4жϱ־״̬ +*ڲ: +TIM4_Flag_TypeDef:TIM4_Flag:TIMER4־ѡ +*ڲ: +FlagStatus:TIMER4жϱ־״̬ +*****************************************************/ +FlagStatus TIM4_GetFlagStatus(TIM4_Flag_TypeDef TIM4_Flag) +{ + FlagStatus status = RESET; + TXINX = 0x04; + + if ((TIM4_Flag & TXCON) != (uint8_t)RESET) + { + status = SET; + } + else + { + status = RESET; + } + + return status; +} + +/***************************************************** +*:void TIM4_ClearFlag(TIM4_Flag_TypeDef TIM4_Flag) +*:TIMER4жϱ־״̬ +*ڲ: +TIM4_Flag_TypeDef:TIM4_Flag:TIMER4־ѡ +*ڲ:void +*****************************************************/ +void TIM4_ClearFlag(TIM4_Flag_TypeDef TIM4_Flag) +{ + TXINX = 0x04; + TXCON &= (~TIM4_Flag); +} + +/************************************************** +*:void TIM4_TimeBaseInit(TIM4_CountMode_TypeDef TIM4_CountMode, TIM4_CountDirection_TypeDef TIM4_CountDirection) +*:TIM4ú +*ڲ: +TIM4_CountMode_TypeDef:TIM4_CountMode:/ʱģʽѡ +TIM4_CountDirection_TypeDef:TIM4_CountDirection:ѡ +*ڲ:void +**************************************************/ +void TIM4_TimeBaseInit(TIM4_CountMode_TypeDef TIM4_CountMode, + TIM4_CountDirection_TypeDef TIM4_CountDirection) +{ + TXINX = 0x04; + + if (TIM4_CountMode == TIM4_MODE_TIMER) + { + TXCON &= 0XFD; + } + else if (TIM4_CountMode == TIM4_MODE_COUNTER) + { + TXCON |= 0X02; + } + + /************************************************************/ + if (TIM4_CountDirection == TIM4_COUNTDIRECTION_UP) + { + TXMOD &= 0XFE; + } + else if (TIM4_CountDirection == TIM4_COUNTDIRECTION_DOWN_UP) + { + TXMOD |= 0X01; + } +} + +/************************************************** +*:void TIM4_WorkMode0Config(uint16_t TIM4_SetCounter) +*:TIMER4ģʽ0ú +*ڲ: +uint16_t:TIM4_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM4_WorkMode0Config(uint16_t TIM4_SetCounter) +{ + TXINX = 0x04; + CP = 1; + TLX = TIM4_SetCounter % 256; + THX = TIM4_SetCounter / 256; +} + +/************************************************** +*:void TIM4_WorkMode3Config(uint16_t TIM4_SetCounter) +*:TIMER2ģʽ3ú +*ڲ: +uint16_t:TIM2_SetCounter:üֵ +*ڲ:void +**************************************************/ +void TIM4_WorkMode3Config(uint16_t TIM4_SetCounter) +{ + TXINX = 0x04; + RCAPXL = TIM4_SetCounter % 256; + RCAPXH = TIM4_SetCounter / 256; + TXMOD |= 0X02; +} + +/************************************************** +*:void TIM4_WorkModeConfig(TIM4_WorkMode_TypeDef TIM4_WorkMode, uint16_t TIM4_SetCounter) +*:TIMER4ģʽú +*ڲ: +TIM4_WorkMode_TypeDef:TIM4_WorkMode:TIMER2ģʽѡ +uint16_t:TIM4_SetCounter:TIMER2ֵ +*ڲ:void +**************************************************/ +void TIM4_WorkModeConfig(TIM4_WorkMode_TypeDef TIM4_WorkMode, uint16_t TIM4_SetCounter) +{ + switch (TIM4_WorkMode) + { + case TIM4_WORK_MODE0: + TIM4_WorkMode0Config(TIM4_SetCounter); + break; + + case TIM4_WORK_MODE1: + TIM4_WorkMode1Config(TIM4_SetCounter); + break; + + case TIM4_WORK_MODE3: + TIM4_WorkMode3Config(TIM4_SetCounter); + break; + + default: + break; + } +} + +/***************************************************** +*:void TIM4_SetEXEN4(FunctionalState NewState) +*:TIMER4_EXEN4ú +*ڲ: +FunctionalState:NewState:EXEN4ʹѡ +*ڲ:void +*****************************************************/ +void TIM4_SetEXEN4(FunctionalState NewState) +{ + TXINX = 0x04; + + if (NewState == DISABLE) + { + EXENX = 0; + } + else + { + EXENX = 1; + } +} + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_uart0.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_uart0.c new file mode 100644 index 0000000..b26511f --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_uart0.c @@ -0,0 +1,388 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92f_uart0.c +// : +// ģ鹦 : UART0̼⺯Cļ +// ֲб: +// : 2022/01/01 +// 汾 : V1.10005 +// ˵ :ļԪ92F/93F/92LϵеƬ +//************************************************************* + +#include "sc92f_uart0.h" + +#if !defined (SC92F742x) && !defined (SC92F827X) && !defined (SC92F837X) && !defined (SC92F7490) + +/************************************************** +*:void UART0_DeInit(void) +*:UART0ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void UART0_DeInit(void) +{ +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) + OTCON &= 0XEF; +#endif + SCON = 0X00; + PCON &= 0X7F; + IE &= 0XEF; + IP &= 0XEF; +} + +#if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) +/************************************************** +*:UART0_PinSelection(UART0_PinSelection_TypeDef PinSeletion) +*:UART0ѡ +*ڲ: +UART0_PinSelection_TypeDef:PinSeletion:ѡUART0ΪP15P16P11P20 +*ڲ:void +**************************************************/ +void UART0_PinSelection(UART0_PinSelection_TypeDef + PinSeletion) +{ + OTCON = OTCON & 0XDF | PinSeletion; +} +#endif + +/************************************************** +*:void UART0_Init(uint32_t Uart0Fsys, uint32_t BaudRate, UART0_Mode_Typedef Mode,UART0_Clock_Typedef ClockMode, UART0_RX_Typedef RxMode) +*:UART0ʼú +*ڲ: +uint32_t:Uart0Fsys:ϵͳʱƵ +uint32_t:BaudRate: +UART0_Mode_Typedef:Mode:UART0ģʽ +UART0_Clock_Typedef:ClockMode:ʱԴTIMER1/TIMER2 +UART0_RX_Typedef:RxMode:ѡ +*ڲ:void +**************************************************/ +void UART0_Init(uint32_t Uart0Fsys, uint32_t BaudRate, + UART0_Mode_Typedef Mode, UART0_Clock_Typedef ClockMode, + UART0_RX_Typedef RxMode) +{ +#if defined (SC92F725X) || defined (SC92F735X) || defined (SC92F730x ) || defined (SC92F732X) || defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) + { + SCON = SCON & 0X2F | Mode | RxMode; //UARTģʽ,ýλ + + if(Mode == UART0_Mode_8B || + Mode == UART0_Mode_11B_BaudRateFix) + { + if(BaudRate == UART0_BaudRate_FsysDIV12 || + BaudRate == UART0_BaudRate_FsysDIV64) + { + PCON &= 0X7F; + } + else if(BaudRate == UART0_BaudRate_FsysDIV4 || + BaudRate == UART0_BaudRate_FsysDIV32) + { + PCON |= 0X80; + } + } + else + { + T2CON = (T2CON & 0xCF) | (ClockMode & + 0X30); //òʱԴ + + if((ClockMode & 0X70) == 0X00) + { + TMOD |= 0X20; + if(ClockMode & 0x80) + { + PCON |= 0X80; + Uart0Fsys = Uart0Fsys * 2; + } + else + { + PCON &= 0X7F; + } + + if(ClockMode & 0x0F) + { + TMCON |= 0x02; + } + else + { + TMCON &= 0xFD; + Uart0Fsys = Uart0Fsys / 12; + } + + TH1 = 256 - (Uart0Fsys / 32 / BaudRate); + TL1 = TH1; + TR1 = 1; + } + else if((ClockMode & 0X70) == 0X30) + { + if(ClockMode & 0x0F) + { + TMCON |= 0x04; + } + else + { + TMCON &= 0xFB; + Uart0Fsys = Uart0Fsys / 12; + } + + RCAP2H = (65536 - Uart0Fsys / 32 / BaudRate) / + 256; + RCAP2L = (65536 - Uart0Fsys / 32 / BaudRate) % + 256; + TR2 = 1; + } + } + } +#elif defined (SC92F848x) || defined (SC92F748x) || defined (SC92F859x) || defined (SC92F759x) + { + SCON = (SCON & 0X2F) | Mode | RxMode; //UARTģʽ,ýλ + + if(Mode == UART0_Mode_8B) + { + if(BaudRate == UART0_BaudRate_FsysDIV12) + { + PCON &= 0X7F; + } + else if(BaudRate == UART0_BaudRate_FsysDIV4) + { + PCON |= 0X80; + } + } + else + { + T2CON = (T2CON & 0xCF) | + (ClockMode & 0x30); //òʱԴ + + if(ClockMode & 0x80) + { + PCON |= 0x80; + Uart0Fsys = Uart0Fsys / 16; + } + else + { + PCON &= 0x7F; + } + + if((ClockMode & 0x7F) == UART0_CLOCK_TIMER1) + { + TH1 = (Uart0Fsys / BaudRate) / 256; + TL1 = (Uart0Fsys / BaudRate) % 256; + TR1 = 0; + } + else if((ClockMode & 0x7F) == UART0_CLOCK_TIMER2) + { + RCAP2H = (Uart0Fsys / BaudRate) / 256; + RCAP2L = (Uart0Fsys / BaudRate) % 256; + TR2 = 1; + } + } + } +#elif defined (SC92L853x) || defined (SC92L753x) + { + SCON = (SCON & 0X2F) | Mode | RxMode; //UARTģʽ,ýλ + + /* UART0ѡΪ8λ˫ͬͨģʽж˿ϵͳʱӵ12Ƶ4Ƶ*/ + if(Mode == UART0_Mode_8B) + { + if(BaudRate == UART0_BaudRate_FsysDIV12) + { + PCON &= 0X7F; + } + else if(BaudRate == UART0_BaudRate_FsysDIV4) + { + PCON |= 0X80; + } + } + /* UART0ѡģʽ1/3Ϊɱ */ + else + { + TXCON = (TXCON & 0xCF) | ClockMode; //òʱԴ + + /* ģʽ1/3ϵͳʱӵ1Ƶ16Ƶ */ + if(ClockMode & 0x80) + { + PCON |= 0x80; + Uart0Fsys = Uart0Fsys / 16; + } + else + { + PCON &= 0x7F; + } + + /* UART0ʱԴ */ + if((ClockMode & 0x7F) == UART0_CLOCK_TIMER1)//UART0ʱԴΪTIMER1 + { + TH1 = (Uart0Fsys / BaudRate) / 256; + TL1 = (Uart0Fsys / BaudRate) % 256; + TR1 = 0; + } + else if((ClockMode & 0x7F) == UART0_CLOCK_TIMER2)//UART0ʱԴΪTIMER2 + { + RCAPXH = (Uart0Fsys / BaudRate) / 256; + RCAPXL = (Uart0Fsys / BaudRate) % 256; + TRX = 1; + } + } + } + +#else + { + SCON = (SCON & 0X2F) | Mode | + RxMode; //UARTģʽ,ýλ + + if(Mode == UART0_Mode_8B) + { + if(BaudRate == UART0_BaudRate_FsysDIV12) + { + PCON &= 0X7F; + } + else if(BaudRate == UART0_BaudRate_FsysDIV4) + { + PCON |= 0X80; + } + } + else + { + T2CON = (T2CON & 0xCF) | + (ClockMode & 0x30); //òʱԴ + + if(ClockMode == UART0_CLOCK_TIMER1) + { + TH1 = (Uart0Fsys / BaudRate) / 256; + TL1 = (Uart0Fsys / BaudRate) % 256; + TR1 = 0; + } + else if(ClockMode == UART0_CLOCK_TIMER2) + { + RCAP2H = (Uart0Fsys / BaudRate) / 256; + RCAP2L = (Uart0Fsys / BaudRate) % 256; +#if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) + TR2 = 1; +#endif + } + } + } +#endif +} + +/***************************************************** +*:void UART0_SendData8(uint8_t Data) +*:UART08λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void UART0_SendData8(uint8_t Data) +{ + SBUF = Data; +} + +/************************************************** +*:uint8_t UART0_ReceiveData8(void) +*:SBUFеֵ +*ڲ:void +*ڲ: +uint8_t:UARTյ8λ +**************************************************/ +uint8_t UART0_ReceiveData8(void) +{ + return SBUF; +} + +/***************************************************** +*:void UART0_SendData9(uint16_t Data) +*:UART09λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void UART0_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if(Data_9Bit) + { + SCON |= 0X08; + } + else + { + SCON &= 0XF7; + } + + SBUF = (uint8_t)Data; +} + +/************************************************** +*:uint16_t UART0_ReceiveData9(void) +*:SBUFеֵھλֵ +*ڲ:void +*ڲ: +uint16_t:UARTյ +**************************************************/ +uint16_t UART0_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = SBUF + ((uint16_t)(SCON & 0X04) << 6); + SCON &= 0XFB; + return Data9; +} + +/***************************************************** +*:void UART0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:UART0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void UART0_ITConfig(FunctionalState NewState, + PriorityStatus Priority) +{ + if(NewState == DISABLE) + { + EUART = 0; + } + else + { + EUART = 1; + } + + //жȼ + if(Priority == LOW) + { + IPUART = 0; + } + else + { + IPUART = 1; + } +} + +/***************************************************** +*:FlagStatus UART0_GetFlagStatus(UART0_Flag_Typedef UART0_Flag) +*:UART0жϱ־״̬ +*ڲ: +UART0_GetFlagStatus:UART0_Flag:жϱ־λѡ +*ڲ: +FlagStatus:UART0жϱ־λ״̬ +*****************************************************/ +//FlagStatus UART0_GetFlagStatus(UART0_Flag_Typedef +// UART0_Flag) +//{ +// return (bool)(SCON & UART0_Flag); +//} + +/***************************************************** +*:void UART0_ClearFlag(UART0_Flag_Typedef UART0_Flag) +*:UART0жϱ־״̬ +*ڲ: +UART0_Flag_Typedef;UART0_Flag:жϱ־λѡ +*ڲ:void +*****************************************************/ +//void UART0_ClearFlag(UART0_Flag_Typedef +// UART0_Flag) +//{ +// SCON &= (~UART0_Flag); +//} + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_usci0.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_usci0.c new file mode 100644 index 0000000..16a302a --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_usci0.c @@ -0,0 +1,529 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_usci0.c +// : +// ģ鹦 : USCI0̼⺯Cļ +// : 2022/01/05 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_usci0.h" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void USCI0_DeInit(void) +*:USCI0ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI0_DeInit(void) +{ + OTCON &= 0XCF; + US0CON0 = 0X00; + US0CON1 = 0X00; + US0CON2 = 0X00; + US0CON3 = 0X00; + IE1 &= (~0X01); + IP1 &= (~0X01); +} + +/************************************************** +*:void USCI0_SPI_Init(USCI0_SPI_FirstBit_TypeDef FirstBit, USCI0_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,USCI0_SPI_Mode_TypeDef Mode, + USCI0_SPI_ClockPolarity_TypeDef ClockPolarity, USCI0_SPI_ClockPhase_TypeDef ClockPhase,USCI0_SPI_TXE_INT_TypeDef SPI_TXE_INT,USCI0_TransmissionMode_TypeDef TransmissionMode) +*:SPIʼú +*ڲ: +USCI0_SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +USCI0_SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +USCI0_SPI_Mode_TypeDef:Mode:SPIģʽѡ +USCI0_SPI_ClockPolarity_TypeDef:ClockPolarity:SPIʱӼѡ +USCI0_SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +USCI0_SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ,ùSC92FXX1XоƬЧ +USCI0_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16λ +*ڲ:void +**************************************************/ +void USCI0_SPI_Init(USCI0_SPI_FirstBit_TypeDef FirstBit, + USCI0_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI0_SPI_Mode_TypeDef Mode, + USCI0_SPI_ClockPolarity_TypeDef ClockPolarity, USCI0_SPI_ClockPhase_TypeDef ClockPhase, + USCI0_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI0_TransmissionMode_TypeDef TransmissionMode) +{ + + OTCON = (OTCON & 0XCF) | 0X10; +#if defined(SC92L853x) || defined(SC92L753x) + SPI_TXE_INT = USCI0_SPI_TXE_DISINT; //SPI_TXE_INTùڸоƬЧ + US0CON1 = US0CON1 & (~0X05) | FirstBit | TransmissionMode; +#endif + US0CON0 = US0CON0 & 0X80 | BaudRatePrescaler | Mode | ClockPolarity | ClockPhase; +} + +/************************************************** +*:void USCI0_TransmissionMode(USCI0_TransmissionMode_TypeDef TransmissionMode) +*:SPI ģʽú +*ڲ: +USCI0_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16eλ +*ڲ:void +**************************************************/ +void USCI0_TransmissionMode(USCI0_TransmissionMode_TypeDef TransmissionMode) +{ + if (TransmissionMode == USCI0_SPI_DATA8) + { + US0CON1 &= 0xFD; + } + else + { + US0CON1 |= 0x02; + } +} + +/***************************************************** +*:void USCI0_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI0_SPI_Cmd(FunctionalState NewState) +{ + OTCON = (OTCON & 0XCF) | 0X10; + + if (NewState != DISABLE) + { + US0CON0 |= 0X80; + } + else + { + US0CON0 &= (~0X80); + } +} +/***************************************************** +*:void USCI0_SPI_SendData_8(uint8_t Data) +*:USCI0 SPI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_SPI_SendData_8(uint8_t Data) +{ + US0CON2 = Data; +} + +/***************************************************** +*:uint8_t USCI0_SPI_ReceiveData_8(void) +*:US0CON2еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI0_SPI_ReceiveData_8(void) +{ + return US0CON2; +} + +/***************************************************** +*:void USCI0_SPI_SendData_16(uint16_t Data) +*:US0CON2 SPI +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_SPI_SendData_16(uint16_t Data) +{ + US0CON3 = (uint8_t)(Data >> 8); + US0CON2 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI0_SPI_ReceiveData_16(void) +*:US0CON2еֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI0_SPI_ReceiveData_16(void) +{ + uint16_t SPI_data; + SPI_data = (uint16_t)((US0CON3 << 8) | US0CON2); + return SPI_data; +} + +/************************************************** +*:void USCI0_TWI_Slave_Init(uint8_t TWI_Address) +*:USCI0 TWIӻʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void USCI0_TWI_Slave_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0XCF | 0X20; + US0CON2 = TWI_Address << 1; +} + +/************************************************** +*:void USCI0_TWI_MasterCommunicationRate(USCI0_TWI_MasterCommunicationRate_TypeDef TWI_MasterCommunicationRate) +*:USCI0 TWIģʽͨѶ趨 +*ڲ: +USCI0_TWI_MasterCommunicationRate_TypeDef:TWI_MasterCommunicationRate:TWIģʽͨѶ +*ڲ:void +**************************************************/ +void USCI0_TWI_MasterCommunicationRate(USCI0_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate) +{ + OTCON = OTCON & 0XCF | 0X20; + US0CON1 |= TWI_MasterCommunicationRate; +} + +/************************************************** +*:void USCI0_TWI_Start(void) +*:USCI0 TWI ʼλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI0_TWI_Start(void) +{ + US0CON1 |= 0x20; +} + +/************************************************** +*:void USCI0_TWI_MasterModeStop(void) +*:USCI0 TWIģʽֹͣλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI0_TWI_MasterModeStop(void) +{ + US0CON1 |= 0x10; +} + +/************************************************** +*:void USCI0_TWI_SlaveClockExtension(void) +*:USCI0 TWIӻģʽʱӳλ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +**************************************************/ +void USCI0_TWI_SlaveClockExtension(FunctionalState NewState) +{ + OTCON = OTCON & 0XCF | 0X20; + + if (NewState != DISABLE) + { + US0CON1 |= 0x40; + } + else + { + US0CON1 &= 0XBF; + } +} + +/************************************************** +*:void USCI0_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI0_TWI_AcknowledgeConfig(FunctionalState NewState) +{ + OTCON = OTCON & 0XCF | 0X20; + + if (NewState != DISABLE) + { + US0CON0 |= 0X08; + } + else + { + US0CON0 &= 0XF7; + } +} + +/************************************************** +*:void USCI0_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:ͨõַӦʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI0_TWI_GeneralCallCmd(FunctionalState NewState) +{ + OTCON = OTCON & 0XCF | 0X20; + + if (NewState != DISABLE) + { + US0CON2 |= 0X01; + } + else + { + US0CON2 &= 0XFE; + } +} + +/***************************************************** +*:FlagStatus USCI0_GetTWIStatus(USCI0_TWIState_TypeDef USCI0_TWIState) +*:ȡTWI״̬ +*ڲ: +USCI0_TWIState_TypeDef:USCI0_TWIState:TWI״̬ +*ڲ: +FlagStatus:USCI0_SC־״̬ +*****************************************************/ +FlagStatus USCI0_GetTWIStatus(USCI0_TWIState_TypeDef USCI0_TWIState) +{ + if ((US0CON0 & 0x07) == USCI0_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void USCI0_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI0_TWI_Cmd(FunctionalState NewState) +{ + OTCON = OTCON & 0XCF | 0X20; + + if (NewState != DISABLE) + { + US0CON0 |= 0X80; + } + else + { + US0CON0 &= (~0X80); + } +} + +/***************************************************** +*:void USCI0_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_TWI_SendData(uint8_t Data) +{ + US0CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI0_TWI_SendData(void) +*:US0CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI0_TWI_ReceiveData(void) +{ + return US0CON3; +} + +/************************************************** +*:void USCI0_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI0_UART_Mode_TypeDef Mode, USCI0_UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +USCI0_UART_Mode_TypeDef:Mode:UART1ģʽ +USCI0_UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void USCI0_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI0_UART_Mode_TypeDef Mode, + USCI0_UART_RX_TypeDef RxMode) +{ + OTCON |= 0x30; + US0CON0 = US0CON0 & 0X0F | Mode | RxMode; + + if (Mode == USCI0_UART_Mode_8B) + { + if (BaudRate == USCI0_UART_BaudRate_FsysDIV12) + { + US0CON0 &= 0XDF; + } + else if (BaudRate == USCI0_UART_BaudRate_FsysDIV4) + { + US0CON0 |= 0X20; + } + } + else + { + US0CON2 = UARTFsys / BaudRate / 256; + US0CON1 = UARTFsys / BaudRate % 256; + } +} + +/***************************************************** +*:void USCI0_UART_SendData8(uint8_t Data) +*:USCI0 UART18λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_UART_SendData8(uint8_t Data) +{ + US0CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI0_UART_ReceiveData8(void) +*:US0CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI0_UART_ReceiveData8(void) +{ + return US0CON3; +} + +/***************************************************** +*:void USCI0_UART_SendData9(uint16_t Data) +*:UART19λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI0_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if (Data_9Bit) + { + US0CON0 |= 0x08; + } + else + { + US0CON0 &= 0xf7; + } + + US0CON3 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI0_UART_ReceiveData9(void) +*:US0CON3еֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI0_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = US0CON3 + ((uint16_t)(US0CON0 & 0X04) << 6); + return Data9; +} + +/***************************************************** +*:void USCI0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:USCI0жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void USCI0_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE1 |= 0x01; + } + else + { + IE1 &= 0xFE; + } + + /************************************************************/ + if (Priority != LOW) + { + IP1 |= 0x01; + } + else + { + IP1 &= 0xFE; + } +} + +/***************************************************** +*:FlagStatus USCI0_GetFlagStatus(USCI0_Flag_TypeDef USCI0_FLAG) +*:USCI0־״̬ +*ڲ: +USCI0_Flag_TypeDef:USCI0_FLAG:ȡı־λ +*ڲ: +FlagStatus:USCI0־״̬ +*****************************************************/ +FlagStatus USCI0_GetFlagStatus(USCI0_Flag_TypeDef USCI0_FLAG) +{ + FlagStatus bitstatus = RESET; +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI0_FLAG == USCI0_SPI_FLAG_SPIF) || (USCI0_FLAG == USCI0_SPI_FLAG_WCOL) || (USCI0_FLAG == USCI0_TWI_FLAG_TXRXnE)) +#endif + { + if ((USCI0_FLAG & US0CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((USCI0_FLAG & US0CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void USCI0_ClearFlag(USCI0_Flag_TypeDef USCI0_FLAG) +*:USCI0־״̬ +*ڲ: +USCI0_Flag_TypeDef:USCI0_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void USCI0_ClearFlag(USCI0_Flag_TypeDef USCI0_FLAG) +{ +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI0_FLAG == USCI0_SPI_FLAG_SPIF) || (USCI0_FLAG == USCI0_SPI_FLAG_WCOL) || (USCI0_FLAG == USCI0_TWI_FLAG_TXRXnE)) +#endif + { + US0CON1 &= (~USCI0_FLAG); //ĴUS0CON1 + } + else if ((USCI0_FLAG == USCI0_UART_FLAG_TI) || (USCI0_FLAG == USCI0_UART_FLAG_RI)) + { +#if defined(SC92L853x) || defined(SC92L753x) + US0CON0 = US0CON0 & 0xFC | USCI0_FLAG;//д1 +#endif + } + else + { + US0CON0 &= (~USCI0_FLAG); //ĴUS0CON0 + } +} + +/***************************************************** +*:void USCI0_TWI_SendAddr(uint8_t Addr,USCI0_TWI_RWType RW) +*:TWI͵ַд +*ڲ: +uint8_t:Addr:͵ĵַ 0~127 +USCI0_TWI_RWType:RW:д +*ڲ:void +*****************************************************/ +void USCI0_TWI_SendAddr(uint8_t Addr, USCI0_TWI_RWType RW) +{ + US0CON3 = (Addr << 1) | RW; +} + +#endif + +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_usci1.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_usci1.c new file mode 100644 index 0000000..95e0773 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_usci1.c @@ -0,0 +1,528 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ : sc92F_USCI1.c +// : +// ģ鹦 : USCI1̼⺯Cļ +// : 2022/01/05 +// 汾 : V1.10000 +// ˵ :ļSC92FϵоƬ +//************************************************************* + +#include "sc92f_usci1.h" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void USCI1_DeInit(void) +*:USCI1ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI1_DeInit(void) +{ + OTCON &= 0X3F; + US1CON0 = 0X00; + US1CON1 = 0X00; + US1CON2 = 0X00; + US1CON3 = 0X00; + IE2 &= (~0X01); + IP2 &= (~0X01); +} + +/************************************************** +*:void USCI1_SPI_Init(USCI1_SPI_FirstBit_TypeDef FirstBit, USCI1_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,USCI1_SPI_Mode_TypeDef Mode, + USCI1_SPI_ClockPolarity_TypeDef ClockPolarity, USCI1_SPI_ClockPhase_TypeDef ClockPhase,USCI1_SPI_TXE_INT_TypeDef SPI_TXE_INT,USCI1_TransmissionMode_TypeDef TransmissionMode) +*:SPIʼú +*ڲ: +USCI1_SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +USCI1_SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +USCI1_SPI_Mode_TypeDef:Mode:SPIģʽѡ +USCI1_SPI_ClockPolarity_TypeDef:ClockPolarity:SPIʱӼѡ +USCI1_SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +USCI1_SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ,ùSC92FXX1XоƬЧ +USCI1_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16λ +*ڲ:void +**************************************************/ +void USCI1_SPI_Init(USCI1_SPI_FirstBit_TypeDef FirstBit, + USCI1_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI1_SPI_Mode_TypeDef Mode, + USCI1_SPI_ClockPolarity_TypeDef ClockPolarity, USCI1_SPI_ClockPhase_TypeDef ClockPhase, + USCI1_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI1_TransmissionMode_TypeDef TransmissionMode) +{ + + OTCON = (OTCON & 0X3F) | 0X40; +#if defined(SC92L853x) || defined(SC92L753x) + SPI_TXE_INT = USCI1_SPI_TXE_DISINT; //SPI_TXE_INTùЧ + US1CON1 = US1CON1 & (~0X05) | FirstBit | TransmissionMode; +#endif + US1CON0 = US1CON0 & 0X80 | BaudRatePrescaler | Mode | ClockPolarity | ClockPhase; +} + +/************************************************** +*:void USCI1_TransmissionMode(USCI1_TransmissionMode_TypeDef TransmissionMode) +*:SPI ģʽú +*ڲ: +USCI1_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16eλ +*ڲ:void +**************************************************/ +void USCI1_TransmissionMode(USCI1_TransmissionMode_TypeDef TransmissionMode) +{ + if (TransmissionMode == USCI1_SPI_DATA8) + { + US1CON1 &= 0xFD; + } + else + { + US1CON1 |= 0x02; + } +} + +/***************************************************** +*:void USCI1_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI1_SPI_Cmd(FunctionalState NewState) +{ + OTCON = (OTCON & 0X3F) | 0X40; + + if (NewState != DISABLE) + { + US1CON0 |= 0X80; + } + else + { + US1CON0 &= (~0X80); + } +} +/***************************************************** +*:void USCI1_SPI_SendData_8(uint8_t Data) +*:USCI1 SPI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_SPI_SendData_8(uint8_t Data) +{ + US1CON2 = Data; +} + +/***************************************************** +*:uint8_t USCI1_SPI_ReceiveData_8(void) +*:US1CON2еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI1_SPI_ReceiveData_8(void) +{ + return US1CON2; +} + +/***************************************************** +*:void USCI1_SPI_SendData_16(uint16_t Data) +*:US1CON2 SPI +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_SPI_SendData_16(uint16_t Data) +{ + US1CON3 = (uint8_t)(Data >> 8); + US1CON2 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI1_SPI_ReceiveData_16(void) +*:US1CON2еֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI1_SPI_ReceiveData_16(void) +{ + uint16_t SPI_data; + SPI_data = (uint16_t)((US1CON3 << 8) | US1CON2); + return SPI_data; +} + +/************************************************** +*:void USCI1_TWI_Slave_Init(uint8_t TWI_Address) +*:USCI1 TWIӻʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void USCI1_TWI_Slave_Init(uint8_t TWI_Address) +{ + OTCON = OTCON & 0X3F | 0X80; + US1CON2 = TWI_Address << 1; +} + +/************************************************** +*:void USCI1_TWI_MasterCommunicationRate(USCI1_TWI_MasterCommunicationRate_TypeDef TWI_MasterCommunicationRate) +*:USCI1 TWIģʽͨѶ趨 +*ڲ: +USCI1_TWI_MasterCommunicationRate_TypeDef:TWI_MasterCommunicationRate:TWIģʽͨѶ +*ڲ:void +**************************************************/ +void USCI1_TWI_MasterCommunicationRate(USCI1_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate) +{ + OTCON = OTCON & 0X3F | 0X80; + US1CON1 |= TWI_MasterCommunicationRate; +} + +/************************************************** +*:void USCI1_TWI_Start(void) +*:USCI1 TWI ʼλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI1_TWI_Start(void) +{ + US1CON1 |= 0x20; +} + +/************************************************** +*:void USCI1_TWI_MasterModeStop(void) +*:USCI1 TWIģʽֹͣλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI1_TWI_MasterModeStop(void) +{ + US1CON1 |= 0x10; +} + +/************************************************** +*:void USCI1_TWI_SlaveClockExtension(FunctionalState NewState) +*:USCI1 TWIӻģʽʱӳλ +*ڲ: +FunctionalState:NewState:ʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI1_TWI_SlaveClockExtension(FunctionalState NewState) +{ + OTCON = OTCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US1CON1 |= 0x40; + } + else + { + US1CON1 &= 0XBF; + } +} + +/************************************************** +*:void USCI1_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI1_TWI_AcknowledgeConfig(FunctionalState NewState) +{ + OTCON = OTCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US1CON0 |= 0X08; + } + else + { + US1CON0 &= 0XF7; + } +} + +/************************************************** +*:void USCI1_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI1_TWI_GeneralCallCmd(FunctionalState NewState) +{ + OTCON = OTCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US1CON2 |= 0X01; + } + else + { + US1CON2 &= 0XFE; + } +} + +/***************************************************** +*:FlagStatus USCI1_GetTWIStatus(USCI1_TWIState_TypeDef USCI1_TWIState) +*:ȡTWI״̬ +*ڲ: +USCI1_TWIState_TypeDef:USCI1_TWIState:TWI״̬ +*ڲ: +FlagStatus:USCI1_TWI־״̬ +*****************************************************/ +FlagStatus USCI1_GetTWIStatus(USCI1_TWIState_TypeDef USCI1_TWIState) +{ + if ((US1CON0 & 0x07) == USCI1_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void USCI1_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI1_TWI_Cmd(FunctionalState NewState) +{ + OTCON = OTCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US1CON0 |= 0X80; + } + else + { + US1CON0 &= (~0X80); + } +} + +/***************************************************** +*:void USCI1_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_TWI_SendData(uint8_t Data) +{ + US1CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI1_TWI_SendData(void) +*:US1CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI1_TWI_ReceiveData(void) +{ + return US1CON3; +} + +/************************************************** +*:void USCI1_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI1_UART_Mode_TypeDef Mode, USCI1_UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +USCI1_UART_Mode_TypeDef:Mode:UART1ģʽ +USCI1_UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void USCI1_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI1_UART_Mode_TypeDef Mode, + USCI1_UART_RX_TypeDef RxMode) +{ + OTCON |= 0xC0; + US1CON0 = US1CON0 & 0X0F | Mode | RxMode; + + if (Mode == USCI1_UART_Mode_8B) + { + if (BaudRate == USCI1_UART_BaudRate_FsysDIV12) + { + US1CON0 &= 0XDF; + } + else if (BaudRate == USCI1_UART_BaudRate_FsysDIV4) + { + US1CON0 |= 0X20; + } + } + else + { + US1CON2 = UARTFsys / BaudRate / 256; + US1CON1 = UARTFsys / BaudRate % 256; + } +} + +/***************************************************** +*:void USCI1_UART_SendData8(uint8_t Data) +*:USCI1 UART18λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_UART_SendData8(uint8_t Data) +{ + US1CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI1_UART_ReceiveData8(void) +*:US1CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI1_UART_ReceiveData8(void) +{ + return US1CON3; +} + +/***************************************************** +*:void USCI1_UART_SendData9(uint16_t Data) +*:UART19λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI1_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if (Data_9Bit) + { + US1CON0 |= 0x08; + } + else + { + US1CON0 &= 0xf7; + } + + US1CON3 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI1_UART_ReceiveData9(void) +*:US1CON3еֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI1_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = US1CON3 + ((uint16_t)(US1CON0 & 0X04) << 6); + return Data9; +} + +/***************************************************** +*:void USCI1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:USCI1жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void USCI1_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE2 |= 0x01; + } + else + { + IE2 &= 0xFE; + } + + /************************************************************/ + if (Priority != LOW) + { + IP2 |= 0x01; + } + else + { + IP2 &= 0xFE; + } +} + +/***************************************************** +*:FlagStatus USCI1_GetFlagStatus(USCI1_Flag_TypeDef USCI1_FLAG) +*:USCI1־״̬ +*ڲ: +USCI1_Flag_Typedef:USCI1_Flag:жϱ־λѡ +*ڲ: +FlagStatus:USCI1־״̬ +*****************************************************/ +FlagStatus USCI1_GetFlagStatus(USCI1_Flag_TypeDef USCI1_FLAG) +{ + FlagStatus bitstatus = RESET; +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI1_FLAG == USCI1_SPI_FLAG_SPIF) || (USCI1_FLAG == USCI1_SPI_FLAG_WCOL) || (USCI1_FLAG == USCI1_TWI_FLAG_TXRXnE)) +#endif + { + if ((USCI1_FLAG & US1CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((USCI1_FLAG & US1CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void USCI1_ClearFlag(USCI1_Flag_TypeDef USCI1_FLAG) +*:USCI1־״̬ +*ڲ: +USCI1_Flag_TypeDef:USCI1_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void USCI1_ClearFlag(USCI1_Flag_TypeDef USCI1_FLAG) +{ +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI1_FLAG == USCI1_SPI_FLAG_SPIF) || (USCI1_FLAG == USCI1_SPI_FLAG_WCOL) || (USCI1_FLAG == USCI1_TWI_FLAG_TXRXnE)) +#endif + { + US1CON1 &= (~USCI1_FLAG); //ĴUS1CON1 + } + else if ((USCI1_FLAG == USCI1_UART_FLAG_TI) || (USCI1_FLAG == USCI1_UART_FLAG_RI)) + { +#if defined(SC92L853x) || defined(SC92L753x) + US1CON0 = US1CON0 & 0xFC | USCI1_FLAG; //д1 +#endif + } + else + { + US1CON0 &= (~USCI1_FLAG); //ĴUS1CON0 + } +} + +/***************************************************** +*:void USCI1_TWI_SendAddr(uint8_t Addr,USCI1_TWI_RWType RW) +*:TWI͵ַд +*ڲ: +uint8_t:Addr:͵ĵַ 0~127 +USCI1_TWI_RWType:RW:д +*ڲ:void +*****************************************************/ +void USCI1_TWI_SendAddr(uint8_t Addr, USCI1_TWI_RWType RW) +{ + US1CON3 = (Addr << 1) | RW; +} + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_usci2.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_usci2.c new file mode 100644 index 0000000..4059545 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_usci2.c @@ -0,0 +1,535 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92F_usci2.c +// : ԪӦŶ +// ģ鹦: USCI2̼⺯Cļ +// : 2022/01/05 +// 汾: V1.10001 +// ˵: ļSC92ϵоƬ +//************************************************************* + +/* ͷļ */ +#include "sc92f_usci2.h" + +#if defined (SC92L853x) || defined (SC92L753x) +/************************************************** +*:void USCI2_DeInit(void) +*:USCI2ؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI2_DeInit(void) +{ + TMCON &= 0X3F; + US2CON0 = 0X00; + US2CON1 = 0X00; + US2CON2 = 0X00; + US2CON3 = 0X00; + IE2 &= (~0X02); + IP2 &= (~0X02); +} + +/************************************************** +*:void USCI2_SPI_Init(USCI2_SPI_FirstBit_TypeDef FirstBit, USCI2_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler,USCI2_SPI_Mode_TypeDef Mode, + USCI2_SPI_ClockPolarity_TypeDef ClockPolarity, USCI2_SPI_ClockPhase_TypeDef ClockPhase,USCI2_SPI_TXE_INT_TypeDef SPI_TXE_INT,USCI2_TransmissionMode_TypeDef TransmissionMode) +*:SPIʼú +*ڲ: +USCI2_SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB +USCI2_SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ +USCI2_SPI_Mode_TypeDef:Mode:SPIģʽѡ +USCI2_SPI_ClockPolarity_TypeDef:ClockPolarity:SPIʱӼѡ +USCI2_SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ +USCI2_SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ,ùSC92FXX1XоƬЧ +USCI2_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16λ +*ڲ:void +**************************************************/ +void USCI2_SPI_Init(USCI2_SPI_FirstBit_TypeDef FirstBit, + USCI2_SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, USCI2_SPI_Mode_TypeDef Mode, + USCI2_SPI_ClockPolarity_TypeDef ClockPolarity, USCI2_SPI_ClockPhase_TypeDef ClockPhase, + USCI2_SPI_TXE_INT_TypeDef SPI_TXE_INT, USCI2_TransmissionMode_TypeDef TransmissionMode) +{ + TMCON = (TMCON & 0X3F) | 0X40; +#if defined(SC92L853x) || defined(SC92L753x) + SPI_TXE_INT = USCI2_SPI_TXE_DISINT; //SPI_TXE_INTùSC92FXX1XоƬЧ + US2CON1 = US2CON1 & (~0X05) | FirstBit | TransmissionMode; + +#endif +#if defined(SC92L853x) || defined(SC92L753x) + US2CON1 = US2CON1 & (~0X05) | FirstBit | SPI_TXE_INT | TransmissionMode; +#endif + US2CON0 = US2CON0 & 0X80 | BaudRatePrescaler | Mode | ClockPolarity | ClockPhase; +} + +/************************************************** +*:void USCI2_TransmissionMode(USCI2_TransmissionMode_TypeDef TransmissionMode) +*:SPI ģʽú +*ڲ: +USCI2_TransmissionMode_TypeDef:TransmissionMode:SPIģʽѡ 8/16eλ +*ڲ:void +**************************************************/ +void USCI2_TransmissionMode(USCI2_TransmissionMode_TypeDef TransmissionMode) +{ + + TMCON = (TMCON & 0X3F) | 0X40; + if (TransmissionMode == USCI2_SPI_DATA8) + { + US2CON1 &= 0xFD; + } + else + { + US2CON1 |= 0x02; + } +} + +/***************************************************** +*:void USCI2_SPI_Cmd(FunctionalState NewState) +*:SPIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI2_SPI_Cmd(FunctionalState NewState) +{ + TMCON = (TMCON & 0X3F) | 0X40; + + if (NewState != DISABLE) + { + US2CON0 |= 0X80; + } + else + { + US2CON0 &= (~0X80); + } +} + +/***************************************************** +*:void USCI2_SPI_SendData_8(uint8_t Data) +*:USCI2 SPI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_SPI_SendData_8(uint8_t Data) +{ + US2CON2 = Data; +} + +/***************************************************** +*:uint8_t USCI2_SPI_ReceiveData_8(void) +*:US2CON2еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI2_SPI_ReceiveData_8(void) +{ + return US2CON2; +} + +/***************************************************** +*:void USCI2_SPI_SendData_16(uint16_t Data) +*:US2CON2 SPI +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_SPI_SendData_16(uint16_t Data) +{ + US2CON3 = (uint8_t)(Data >> 8); + US2CON2 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI2_SPI_ReceiveData_16(void) +*:US2CON2еֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI2_SPI_ReceiveData_16(void) +{ + uint16_t SPI_data; + SPI_data = (uint16_t)((US2CON3 << 8) | US2CON2); + return SPI_data; +} + +/************************************************** +*:void USCI2_TWI_Slave_Init(uint8_t TWI_Address) +*:USCI2 TWI ӻʼú +*ڲ: +uint8_t:TWI_Address:TWIΪӻʱ7λӻַ +*ڲ:void +**************************************************/ +void USCI2_TWI_Slave_Init(uint8_t TWI_Address) +{ + TMCON = TMCON & 0X3F | 0X80; + US2CON2 = TWI_Address << 1; +} + +/************************************************** +*:void USCI2_TWI_MasterCommunicationRate(USCI2_TWI_MasterCommunicationRate_TypeDef TWI_MasterCommunicationRate) +*:USCI2 TWIģʽͨѶ趨 +*ڲ: +USCI2_TWI_MasterCommunicationRate_TypeDef:TWI_MasterCommunicationRate:TWIģʽͨѶ +*ڲ:void +**************************************************/ +void USCI2_TWI_MasterCommunicationRate(USCI2_TWI_MasterCommunicationRate_TypeDef + TWI_MasterCommunicationRate) +{ + TMCON = TMCON & 0X3F | 0X80; //ѡusci2ΪTWI + + US2CON1 = TWI_MasterCommunicationRate; +} + +/************************************************** +*:void USCI2_TWI_Start(void) +*:USCI2 TWI ʼλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI2_TWI_Start(void) +{ + US2CON1 |= 0x20; +} + +/************************************************** +*:void USCI2_TWI_MasterModeStop(void) +*:USCI2 TWIģʽֹͣλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI2_TWI_MasterModeStop(void) +{ + US2CON1 |= 0x10; +} + +/************************************************** +*:void USCI2_TWI_SlaveClockExtension(void) +*:USCI2 TWIӻģʽʱӳλ +*ڲ:void +*ڲ:void +**************************************************/ +void USCI2_TWI_SlaveClockExtension(FunctionalState NewState) +{ + TMCON = TMCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US2CON1 |= 0x40; + } + else + { + US2CON1 &= 0XBF; + } +} + +/************************************************** +*:void USCI2_TWI_AcknowledgeConfig(FunctionalState NewState) +*:TWIӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI2_TWI_AcknowledgeConfig(FunctionalState NewState) +{ + TMCON = TMCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US2CON0 |= 0X08; + } + else + { + US2CON0 &= 0XF7; + } +} + +/************************************************** +*:void USCI2_TWI_GeneralCallCmd(FunctionalState NewState) +*:TWIͨõַӦʹܺ +*ڲ: +FunctionalState:NewState:Ӧʹ/ʧѡ +*ڲ:void +**************************************************/ +void USCI2_TWI_GeneralCallCmd(FunctionalState NewState) +{ + TMCON = TMCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US2CON2 |= 0X01; + } + else + { + US2CON2 &= 0XFE; + } +} + +/***************************************************** +*:FlagStatus USCI2_GetTWIStatus(USCI2_TWIState_TypeDef USCI2_TWIState) +*:ȡTWI״̬ +*ڲ: +USCI2_TWIState_TypeDef:USCI2_TWIState:TWI״̬ +*ڲ: +FlagStatus:USCI2_TWI־״̬ +*****************************************************/ +FlagStatus USCI2_GetTWIStatus(USCI2_TWIState_TypeDef USCI2_TWIState) +{ + if ((US2CON0 & 0x07) == USCI2_TWIState) + return SET; + else + return RESET; +} + +/***************************************************** +*:void USCI2_TWI_Cmd(FunctionalState NewState) +*:TWIܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void USCI2_TWI_Cmd(FunctionalState NewState) +{ + TMCON = TMCON & 0X3F | 0X80; + + if (NewState != DISABLE) + { + US2CON0 |= 0X80; + } + else + { + US2CON0 &= (~0X80); + } +} + +/***************************************************** +*:void USCI2_TWI_SendData(uint8_t Data) +*:TWI +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_TWI_SendData(uint8_t Data) +{ + US2CON3 = Data; +} +/***************************************************** +*:void USCI2_TWI_SendAddr(uint8_t Addr,USCI2_TWI_RWType RW) +*:TWI͵ַд +*ڲ: +uint8_t:Addr:͵ĵַ +USCI2_TWI_RWType:RW:д +*ڲ:void +*****************************************************/ +void USCI2_TWI_SendAddr(uint8_t Addr, USCI2_TWI_RWType RW) +{ + US2CON3 = (Addr << 1) | RW; +} +/***************************************************** +*:uint8_t USCI2_TWI_ReceiveData(void) +*:US2CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI2_TWI_ReceiveData(void) +{ + return US2CON3; +} + +/************************************************** +*:void USCI2_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI2_UART_Mode_TypeDef Mode, USCI2_UART_RX_TypeDef RxMode) +*:UARTʼú +*ڲ: +uint32_t:UARTFsys:ϵͳʱƵ +uint32_t:BaudRate: +USCI2_UART_Mode_TypeDef:Mode:UART1ģʽ +USCI2_UART_RX_TypeDef:RxMode:ѡ +*ڲ:void +**************************************************/ +void USCI2_UART_Init(uint32_t UARTFsys, uint32_t BaudRate, USCI2_UART_Mode_TypeDef Mode, + USCI2_UART_RX_TypeDef RxMode) +{ + TMCON |= 0xC0; + US2CON0 = US2CON0 & 0X0F | Mode | RxMode; + + if (Mode == USCI2_UART_Mode_8B) + { + if (BaudRate == USCI2_UART_BaudRate_FsysDIV12) + { + US2CON0 &= 0XDF; + } + else if (BaudRate == USCI2_UART_BaudRate_FsysDIV4) + { + US2CON0 |= 0X20; + } + } + else + { + US2CON2 = UARTFsys / BaudRate / 256; + US2CON1 = UARTFsys / BaudRate % 256; + } +} + +/***************************************************** +*:void USCI2_UART_SendData8(uint8_t Data) +*:USCI2 UART18λ +*ڲ: +uint8_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_UART_SendData8(uint8_t Data) +{ + US2CON3 = Data; +} + +/***************************************************** +*:uint8_t USCI2_UART_ReceiveData8(void) +*:US2CON3еֵ +*ڲ:void +*ڲ: +uint8_t:յ +*****************************************************/ +uint8_t USCI2_UART_ReceiveData8(void) +{ + return US2CON3; +} + +/***************************************************** +*:void USCI2_UART_SendData9(uint16_t Data) +*:UART9λ +*ڲ: +uint16_t:Data:͵ +*ڲ:void +*****************************************************/ +void USCI2_UART_SendData9(uint16_t Data) +{ + uint8_t Data_9Bit; + Data_9Bit = (Data >> 8); + + if (Data_9Bit) + { + US2CON0 |= 0x08; + } + else + { + US2CON0 &= 0xf7; + } + + US2CON3 = (uint8_t)Data; +} + +/***************************************************** +*:uint16_t USCI2_UART_ReceiveData9(void) +*:US2CON3еֵھλֵ +*ڲ:void +*ڲ: +uint16_t:յ +*****************************************************/ +uint16_t USCI2_UART_ReceiveData9(void) +{ + uint16_t Data9; + Data9 = US2CON3 + ((uint16_t)(US2CON0 & 0X04) << 6); + return Data9; +} + +/***************************************************** +*:void USCI2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +*:USCI2жϳʼ +*ڲ: +FunctionalState:NewState:жʹ/رѡ +PriorityStatus:Priority:жȼѡ +*ڲ:void +*****************************************************/ +void USCI2_ITConfig(FunctionalState NewState, PriorityStatus Priority) +{ + if (NewState != DISABLE) + { + IE2 |= 0x02; + } + else + { + IE2 &= 0xFD; + } + + /************************************************************/ + if (Priority != LOW) + { + IP2 |= 0x02; + } + else + { + IP2 &= 0xFD; + } +} + +/***************************************************** +*:FlagStatus USCI2_GetFlagStatus(USCI2_Flag_TypeDef USCI2_FLAG) +*:USCI2־״̬ +*ڲ: +USCI2_Flag_Typedef:USCI2_Flag:ȡı־λ +*ڲ: +FlagStatus:USCI2־״̬ +*****************************************************/ +FlagStatus USCI2_GetFlagStatus(USCI2_Flag_TypeDef USCI2_FLAG) +{ + FlagStatus bitstatus = RESET; + +#if defined(SC92L853x) || defined(SC92L753x) + + if ((USCI2_FLAG == USCI2_SPI_FLAG_SPIF) || (USCI2_FLAG == USCI2_SPI_FLAG_WCOL)) +#endif + { + if ((USCI2_FLAG & US2CON1) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if ((USCI2_FLAG & US2CON0) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/***************************************************** +*:void USCI2_ClearFlag(USCI2_Flag_TypeDef USCI2_FLAG) +*:USCI2־״̬ +*ڲ: +USCI2_Flag_TypeDef:USCI2_FLAG:ı־λ +*ڲ:void +*****************************************************/ +void USCI2_ClearFlag(USCI2_Flag_TypeDef USCI2_FLAG) +{ +#if defined(SC92L853x) || defined(SC92L753x) + if ((USCI2_FLAG == USCI2_SPI_FLAG_SPIF) || (USCI2_FLAG == USCI2_SPI_FLAG_WCOL) || (USCI2_FLAG == USCI2_TWI_FLAG_TXRXnE)) +#endif + { + US2CON1 &= (~USCI2_FLAG); //ĴUS2CON1 + } + else if ((USCI2_FLAG == USCI2_UART_FLAG_TI) || (USCI2_FLAG == USCI2_UART_FLAG_RI)) + { +#if defined(SC92L853x) || defined(SC92L753x) + US2CON0 = US2CON0 & 0xFC | USCI2_FLAG; //д1 +#endif + } + else + { + US2CON0 &= (~USCI2_FLAG); //ĴUS2CON0 + } +} + +#endif +/******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ diff --git a/Keil_C/FWLib/SC92F_Lib/src/sc92f_wdt.c b/Keil_C/FWLib/SC92F_Lib/src/sc92f_wdt.c new file mode 100644 index 0000000..c5737c2 --- /dev/null +++ b/Keil_C/FWLib/SC92F_Lib/src/sc92f_wdt.c @@ -0,0 +1,58 @@ +//************************************************************ +// Copyright (c) Ԫ΢޹˾ +// ļ: sc92f_wdt.c +// : +// ģ鹦: WDT̼⺯Cļ +// : 2022323 +// 汾: V1.10002 +// ˵: +//************************************************************* + +#include "sc92f_wdt.h" + +/************************************************** +*:void WDT_DeInit(void) +*:WDTؼĴλȱʡֵ +*ڲ:void +*ڲ:void +**************************************************/ +void WDT_DeInit(void) +{ + WDTCON = 0X00; +} + +/************************************************** +*:void WDT_Init(WDT_OverflowTime_TypeDef OverflowTime) +*:WDTʼú +*ڲ: +WDT_OverflowTime_TypeDef:OverflowTime:WDTʱѡ +*ڲ:void +**************************************************/ +void WDT_Init(WDT_OverflowTime_TypeDef + OverflowTime) +{ + WDTCON = (WDTCON & 0XF8) | OverflowTime; +} + +/***************************************************** +*:void WDT_Cmd(FunctionalState NewState) +*:WDTܿغ +*ڲ: +FunctionalState:NewState:/رѡ +*ڲ:void +*****************************************************/ +void WDT_Cmd(FunctionalState NewState) +{ + OPINX = 0XC1; + + if(NewState == DISABLE) + { + OPREG &= 0X7F; + } + else + { + OPREG |= 0X80; + } +} + +/******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/Keil_C/List/CallBackFunction.lst b/Keil_C/List/CallBackFunction.lst new file mode 100644 index 0000000..0b7e6c5 --- /dev/null +++ b/Keil_C/List/CallBackFunction.lst @@ -0,0 +1,43 @@ +C51 COMPILER V9.59.0.0 CALLBACKFUNCTION 01/18/2024 10:03:10 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE CALLBACKFUNCTION +OBJECT MODULE PLACED IN ..\Output\CallBackFunction.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\User\CallBackFunction.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE + -INCDIR(..\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\CallBackFunction.l + -st) OBJECT(..\Output\CallBackFunction.obj) + +line level source + + 1 //*************************************************************************************************** + 2 // CopyRight (c) + 3 // File Name : CallBackFunction.c + 4 // Function : Write the logic you want to implement in the function body + 5 // Version : V3.0 + 6 // Date : 2022.07.14 + 7 //*************************************************************************************************** + 8 #include "SC_Init.h" + 9 #include "SC_it.h" + 10 #include "..\Drivers\SCDriver_list.h" + 11 #include "HeadFiles\SysFunVarDefine.h" + 12 /**************************************Generated by EasyCodeCube*************************************/ + 13 + 14 /*************************************.Generated by EasyCodeCube.************************************/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = ---- ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/CompCtrlDefine.lst b/Keil_C/List/CompCtrlDefine.lst new file mode 100644 index 0000000..1e843c0 --- /dev/null +++ b/Keil_C/List/CompCtrlDefine.lst @@ -0,0 +1,43 @@ +C51 COMPILER V9.59.0.0 COMPCTRLDEFINE 01/18/2024 10:03:10 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE COMPCTRLDEFINE +OBJECT MODULE PLACED IN ..\Output\CompCtrlDefine.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\User\CompCtrlDefine.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE IN + -CDIR(..\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\CompCtrlDefine.lst) + -OBJECT(..\Output\CompCtrlDefine.obj) + +line level source + + 1 //********************************************************************** + 2 // CopyRight (c) + 3 // File Name : CompCtrlDefine.C + 4 // Function : Store composite control define + 5 // Version : V3.2.0 + 6 // Date : 2022.02.16 + 7 ///********************************************************************* + 8 #include "SC_Init.h" + 9 #include "SC_it.h" + 10 #include "..\Drivers\SCDriver_list.h" + 11 #include "HeadFiles\SysFunVarDefine.h" + 12 /**************************************Generated by EasyCodeCube*************************************/ + 13 + 14 /*************************************.Generated by EasyCodeCube.************************************/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = ---- ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/SC_Init.lst b/Keil_C/List/SC_Init.lst new file mode 100644 index 0000000..889e0f2 --- /dev/null +++ b/Keil_C/List/SC_Init.lst @@ -0,0 +1,212 @@ +C51 COMPILER V9.59.0.0 SC_INIT 01/18/2024 10:03:08 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE SC_INIT +OBJECT MODULE PLACED IN ..\Output\SC_Init.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\User\SC_Init.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE INCDIR(.. + -\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\SC_Init.lst) OBJECT(..\Outp + -ut\SC_Init.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) + 3 // FileName : SC_Init.c + 4 // Function : Contains the MCU initialization function and its C file + 5 // Instructions : + 6 //************************************************************* + 7 + 8 #include "SC_Init.h" // MCU initialization header file, including all firmware library header files + 9 #include "..\Drivers\SCDriver_list.h" + 10 #include "HeadFiles\SC_itExtern.h" + 11 + 12 #include "motor.h" + 13 + 14 //************************************************************* + 15 + 16 + 17 /***********************user_code_area*********************/ + 18 /**/ + 19 /**/ + 20 /**********************.user_code_area.********************/ + 21 + 22 /***************************************************** + 23 *: SC_Init + 24 *: MCUʼ + 25 *ڲvoid + 26 *ڲvoid + 27 *****************************************************/ + 28 void SC_Init(void) + 29 { + 30 1 SC_GPIO_Init(); + 31 1 SC_OPTION_Init(); + 32 1 SC_SSI_Init(); + 33 1 SC_TIM0_Init(); + 34 1 SC_TIM1_Init(); + 35 1 //SC_ADC_Init(); + 36 1 /*write initial function here*/ + 37 1 //οѹ + 38 1 ADC_VrefConfig(ADC_VREF_VDD); //ADC_VREF_VDD ADC_VREF_2_4V + 39 1 EA = 1; + 40 1 //ݳʼ + 41 1 motor_data[0] = 0x00;//00 ֱг 01 г + 42 1 motor_data[1] = 0x00;//00 ֹͣ 01 02 еʼλ 03 еλ + 43 1 motor_data[2] = 0x00;//00 㶯 01 + 44 1 motor_data[3] = 0x00;//00 ״̬ 01 ʼ 02 + 45 1 motor_data[4] = 0x00;//ѹ8λ + 46 1 motor_data[5] = 0x00;//ѹ8λ + 47 1 motor_data[6] = 0x00;//ѹ8λ + 48 1 motor_data[7] = 0x00;//ѹ8λ + 49 1 motor_data[8] = 0x00;//ȸ8λ + 50 1 motor_data[9] = 0x00;//ȵ8λ + 51 1 } + 52 + 53 /***************************************************** + C51 COMPILER V9.59.0.0 SC_INIT 01/18/2024 10:03:08 PAGE 2 + + 54 *: SC_OPTION_Init + 55 *: OPTIONóʼ + 56 *ڲvoid + 57 *ڲvoid + 58 *****************************************************/ + 59 void SC_OPTION_Init(void) + 60 { + 61 1 /*OPTION_Init write here*/ + 62 1 } + 63 + 64 /***************************************************** + 65 *: SC_GPIO_Init + 66 *: GPIOʼ + 67 *ڲvoid + 68 *ڲvoid + 69 *****************************************************/ + 70 void SC_GPIO_Init(void) + 71 { + 72 1 GPIO_Init(GPIO1, GPIO_PIN_4,GPIO_MODE_IN_HI); + 73 1 GPIO_Init(GPIO1, GPIO_PIN_5,GPIO_MODE_IN_HI); + 74 1 GPIO_Init(GPIO1, GPIO_PIN_6,GPIO_MODE_OUT_PP); + 75 1 GPIO_Init(GPIO1, GPIO_PIN_7,GPIO_MODE_IN_HI); + 76 1 GPIO_Init(GPIO2, GPIO_PIN_7,GPIO_MODE_OUT_PP); + 77 1 GPIO_Init(GPIO2, GPIO_PIN_6,GPIO_MODE_OUT_PP); + 78 1 GPIO_Init(GPIO2, GPIO_PIN_5,GPIO_MODE_OUT_PP); + 79 1 GPIO_Init(GPIO0, GPIO_PIN_7,GPIO_MODE_OUT_PP); + 80 1 GPIO_Init(GPIO0, GPIO_PIN_6,GPIO_MODE_OUT_PP); + 81 1 GPIO_Init(GPIO0, GPIO_PIN_5,GPIO_MODE_IN_HI); + 82 1 GPIO_Init(GPIO0, GPIO_PIN_4,GPIO_MODE_IN_PU); + 83 1 GPIO_Init(GPIO0, GPIO_PIN_3,GPIO_MODE_OUT_PP); + 84 1 GPIO_Init(GPIO0, GPIO_PIN_2,GPIO_MODE_OUT_PP); + 85 1 GPIO_Init(GPIO0, GPIO_PIN_1,GPIO_MODE_OUT_PP); + 86 1 GPIO_Init(GPIO0, GPIO_PIN_0,GPIO_MODE_OUT_PP); + 87 1 /*GPIO_Init write here*/ + 88 1 } + 89 + 90 /***************************************************** + 91 *: SC_UART0_Init + 92 *: UART0ʼ + 93 *ڲvoid + 94 *ڲvoid + 95 *****************************************************/ + 96 void SC_UART0_Init(void) + 97 { + 98 1 /*UART0_Init write here*/ + 99 1 } + 100 + 101 /***************************************************** + 102 *: SC_TIM0_Init + 103 *: TIMER0ʼ + 104 *ڲvoid + 105 *ڲvoid + 106 *****************************************************/ + 107 void SC_TIM0_Init(void) + 108 { + 109 1 TIM0_TimeBaseInit(TIM0_PRESSEL_FSYS_D12,TIM0_MODE_TIMER); + 110 1 TIM0_WorkModeConfig(TIM0_WORK_MODE1,55536, 0); + 111 1 TIM0_ITConfig(ENABLE,LOW); + 112 1 TIM0_Cmd(ENABLE); + 113 1 /*TIM0_Init write here*/ + 114 1 } + 115 + C51 COMPILER V9.59.0.0 SC_INIT 01/18/2024 10:03:08 PAGE 3 + + 116 /***************************************************** + 117 *: SC_TIM1_Init + 118 *: TIMER1ʼ + 119 *ڲvoid + 120 *ڲvoid + 121 *****************************************************/ + 122 void SC_TIM1_Init(void) + 123 { + 124 1 TIM1_TimeBaseInit(TIM1_PRESSEL_FSYS_D1,TIM1_MODE_TIMER); + 125 1 TIM1_WorkModeConfig(TIM1_WORK_MODE1,53536); + 126 1 TIM1_ITConfig(ENABLE,LOW); + 127 1 TIM1_Cmd(ENABLE); + 128 1 /*TIM1_Init write here*/ + 129 1 } + 130 + 131 /***************************************************** + 132 *: SC_ADC_Init + 133 *: ADCʼ + 134 *ڲvoid + 135 *ڲvoid + 136 *****************************************************/ + 137 void SC_ADC_Init(void) + 138 { + 139 1 //ADתƵ + 140 1 ADC_Init(ADC_PRESSEL_FHRC_D32,ADC_Cycle_6Cycle); + 141 1 //οѹ + 142 1 ADC_VrefConfig(ADC_VREF_VDD); + 143 1 /*AIN0ģʽ*/ + 144 1 //ADC_EAINConfig(ADC_EAIN_0,ENABLE); + 145 1 + 146 1 /*AIN2ģʽ*/ + 147 1 //ADC_EAINConfig(ADC_EAIN_2,ENABLE); + 148 1 + 149 1 /*AIN1ģʽ*/ + 150 1 ADC_EAINConfig(ADC_EAIN_1,ENABLE); + 151 1 //AD1 ʹ + 152 1 ADC_ChannelConfig(ADC_CHANNEL_1,ENABLE); + 153 1 //ADж + 154 1 ADC_ITConfig(ENABLE,LOW); + 155 1 //ADʼת + 156 1 ADC_Cmd(ENABLE); + 157 1 /*ADC_Init write here*/ + 158 1 + 159 1 + 160 1 } + 161 + 162 + 163 /***************************************************** + 164 *: SC_SSI_Init + 165 *: SSIʼ + 166 *ڲvoid + 167 *ڲvoid + 168 *****************************************************/ + 169 void SC_SSI_Init(void) + 170 { + 171 1 GPIO_Init(GPIO2, GPIO_PIN_1,GPIO_MODE_IN_PU); + 172 1 GPIO_Init(GPIO2, GPIO_PIN_0,GPIO_MODE_IN_PU); + 173 1 SSI_UART1_Init(12000000,9600,UART1_Mode_10B,UART1_RX_ENABLE); + 174 1 SSI_ITConfig(ENABLE,LOW); + 175 1 /*SSI_Init write here*/ + 176 1 } + 177 + C51 COMPILER V9.59.0.0 SC_INIT 01/18/2024 10:03:08 PAGE 4 + + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 322 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/SC_it.lst b/Keil_C/List/SC_it.lst new file mode 100644 index 0000000..4e85671 --- /dev/null +++ b/Keil_C/List/SC_it.lst @@ -0,0 +1,256 @@ +C51 COMPILER V9.59.0.0 SC_IT 01/18/2024 10:03:08 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE SC_IT +OBJECT MODULE PLACED IN ..\Output\SC_it.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\User\SC_it.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE INCDIR(..\F + -WLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\SC_it.lst) OBJECT(..\Output\S + -C_it.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) + 3 // FileName : SC_it.c + 4 // Function : Interrupt Service Routine + 5 // Instructions : + 6 // Date : 2022/03/03 + 7 // Version : V1.0002 + 8 //************************************************************* + 9 /********************Includes************************************************************************/ + 10 #include "SC_it.h" + 11 #include "..\Drivers\SCDriver_list.h" + 12 #include "HeadFiles\SC_itExtern.h" + 13 #include "uart1.h" + 14 #include "motor.h" + 15 #include "adc.h" + 16 + 17 #define IT_5S_CNT 5000 //5000 + 18 #define IT_2S_CNT 2000 //2000 + 19 #define IT_1S_CNT 1000 //1000 + 20 #define IT_100MS_CNT 100 //100 + 21 #define IT_10MS_CNT 10 //10 + 22 #define IT_1MS_CNT 1 //1 + 23 #define IT_2MS_CNT 2 //2 + 24 #define IT_3MS_CNT 3 //3 + 25 #define IT_4MS_CNT 4 //4 + 26 #define IT_5MS_CNT 5 //5 + 27 + 28 bit it_5s_flag = 0; //5sʱ־ + 29 unsigned int xdata it_5s_cnt = 0; + 30 + 31 bit it_2s_flag = 0; //2sʱ־ + 32 unsigned int xdata it_2s_cnt = 0; + 33 + 34 bit it_1s_flag = 0; //1sʱ־ + 35 unsigned int xdata it_1s_cnt = 0; + 36 + 37 bit it_100ms_flag = 0; //100msʱ־ + 38 unsigned int xdata it_100ms_cnt = 0; + 39 + 40 bit it_10ms_flag = 0; //10msʱ־ + 41 unsigned int xdata it_10ms_cnt = 0; + 42 + 43 bit it_1ms_flag = 0; //1msʱ־ + 44 unsigned int xdata it_1ms_cnt = 0; + 45 + 46 bit it_2ms_flag = 0; //2msʱ־ + 47 unsigned int xdata it_2ms_cnt = 0; + 48 + 49 bit it_3ms_flag = 0; //3msʱ־ + 50 unsigned int xdata it_3ms_cnt = 0; + 51 + 52 bit it_4ms_flag = 0; //4msʱ־ + 53 unsigned int xdata it_4ms_cnt = 0; + C51 COMPILER V9.59.0.0 SC_IT 01/18/2024 10:03:08 PAGE 2 + + 54 + 55 bit it_5ms_flag = 0; //5msʱ־ + 56 unsigned int xdata it_5ms_cnt = 0; + 57 /**************************************Generated by EasyCodeCube*************************************/ + 58 + 59 /*************************************.Generated by EasyCodeCube.************************************/ + 60 + 61 void Timer0Interrupt() interrupt 1 + 62 { + 63 1 /*TIM0_it write here begin*/ + 64 1 + 65 1 TH0 = 0xFC;//8λֵ + 66 1 TL0 = 0x17;//8λֵ + 67 1 + 68 1 /*TIM0_it write here*/ + 69 1 /**/ + 70 1 /**//*<6>*/ + 71 1 //Timer0Interrupt + 72 1 { + 73 2 /**//*<7>*/ + 74 2 //5 + 75 2 it_5s_cnt++; + 76 2 if(it_5s_cnt >= IT_5S_CNT) + 77 2 { + 78 3 it_5s_flag = 1; + 79 3 it_5s_cnt = 0; + 80 3 } + 81 2 + 82 2 //2 + 83 2 it_2s_cnt++; + 84 2 if(it_2s_cnt >= IT_2S_CNT) + 85 2 { + 86 3 it_2s_flag = 1; + 87 3 it_2s_cnt = 0; + 88 3 } + 89 2 + 90 2 // + 91 2 it_1s_cnt++; + 92 2 if(it_1s_cnt >= IT_1S_CNT) + 93 2 { + 94 3 it_1s_flag = 1; + 95 3 it_1s_cnt = 0; + 96 3 } + 97 2 + 98 2 //100 + 99 2 it_100ms_cnt++; + 100 2 if(it_100ms_cnt >= IT_100MS_CNT) + 101 2 { + 102 3 it_100ms_flag = 1; + 103 3 it_100ms_cnt = 0; + 104 3 } + 105 2 + 106 2 //10 + 107 2 it_10ms_cnt++; + 108 2 if(it_10ms_cnt >= IT_10MS_CNT) + 109 2 { + 110 3 it_10ms_flag = 1; + 111 3 it_10ms_cnt = 0; + 112 3 } + 113 2 + 114 2 + 115 2 /**//*<7>*/ + C51 COMPILER V9.59.0.0 SC_IT 01/18/2024 10:03:08 PAGE 3 + + 116 2 /**/ + 117 2 } + 118 1 /**//*<6>*/ + 119 1 /**/ + 120 1 /*Timer0Interrupt Flag Clear begin*/ + 121 1 /*Timer0Interrupt Flag Clear end*/ + 122 1 } + 123 + 124 + 125 void Timer1Interrupt() interrupt 3 + 126 { + 127 1 /*TIM1_it write here begin*/ + 128 1 + 129 1 TIM1_Mode1SetReloadCounter(53536); + 130 1 + 131 1 /*TIM1_it write here*/ + 132 1 /**/ + 133 1 /**/ + 134 1 { + 135 2 /**//*<7>*/ + 136 2 //1 + 137 2 it_1ms_cnt++; + 138 2 if(it_1ms_cnt >= IT_1MS_CNT) + 139 2 { + 140 3 it_1ms_flag = 1; + 141 3 it_1ms_cnt = 0; + 142 3 } + 143 2 + 144 2 //2 + 145 2 it_2ms_cnt++; + 146 2 if(it_2ms_cnt >= IT_2MS_CNT) + 147 2 { + 148 3 it_2ms_flag = 1; + 149 3 it_2ms_cnt = 0; + 150 3 } + 151 2 + 152 2 //3 + 153 2 it_3ms_cnt++; + 154 2 if(it_3ms_cnt >= IT_3MS_CNT) + 155 2 { + 156 3 it_3ms_flag = 1; + 157 3 it_3ms_cnt = 0; + 158 3 } + 159 2 + 160 2 //4 + 161 2 it_4ms_cnt++; + 162 2 if(it_4ms_cnt >= IT_4MS_CNT) + 163 2 { + 164 3 it_4ms_flag = 1; + 165 3 it_4ms_cnt = 0; + 166 3 } + 167 2 + 168 2 //5 + 169 2 it_5ms_cnt++; + 170 2 if(it_5ms_cnt >= IT_5MS_CNT) + 171 2 { + 172 3 it_5ms_flag = 1; + 173 3 it_5ms_cnt = 0; + 174 3 } + 175 2 /**//*<7>*/ + 176 2 /**/ + 177 2 } + C51 COMPILER V9.59.0.0 SC_IT 01/18/2024 10:03:08 PAGE 4 + + 178 1 /*Timer1Interrupt Flag Clear begin*/ + 179 1 /*Timer1Interrupt Flag Clear end*/ + 180 1 } + 181 + 182 void ADCInterrupt() interrupt 6 + 183 { + 184 1 // /*ADC_it write here begin*/ + 185 1 + 186 1 // /**/ + 187 1 // /**/ + 188 1 + 189 1 + 190 1 /*ADCInterrupt Flag Clear end*/ + 191 1 ADC_ClearFlag(); + 192 1 } + 193 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) \ + 194 || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F8003)||defined ( + -SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F83Ax) \ + 195 || defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F740x) || defined (SC92FWxx) || defined (SC9 + -3F743x) || defined (SC93F833x) || defined (SC93F843x)\ + 196 || defined (SC92F848x) || defined (SC92F748x)|| defined (SC92F859x) || defined (SC92F759x) + 197 extern bit SSI_FLAG; + 198 void SSIInterrupt() interrupt 7 + 199 { + 200 1 /*SSI_it write here begin*/ + 201 1 if(SSI_GetFlagStatus(UART1_FLAG_TI) == SET) //UART1жϱ־λTI + 202 1 { + 203 2 SSI_FLAG = 0; + 204 2 SSI_ClearFlag(UART1_FLAG_TI); + 205 2 } + 206 1 + 207 1 if(SSI_GetFlagStatus(UART1_FLAG_RI) == SET)//UART1жϱ־λRI + 208 1 { + 209 2 unsigned char ch = 0; + 210 2 ch = SSI_UART1_ReceiveData8(); + 211 2 receive_ttl_data(ch);//Ŵжڣ + 212 2 SSI_ClearFlag(UART1_FLAG_RI); + 213 2 } + 214 1 /*SSIInterrupt Flag Clear end*/ + 215 1 } + 216 + 217 #endif + 218 + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 588 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = 20 1 + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = 10 ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/STARTUP.lst b/Keil_C/List/STARTUP.lst new file mode 100644 index 0000000..c5121ab --- /dev/null +++ b/Keil_C/List/STARTUP.lst @@ -0,0 +1,254 @@ +A51 MACRO ASSEMBLER STARTUP 01/18/2024 10:03:14 PAGE 1 + + +MACRO ASSEMBLER A51 V8.2.7.0 +OBJECT MODULE PLACED IN ..\Output\STARTUP.obj +ASSEMBLER INVOKED BY: D:\Keil_v5\C51\BIN\A51.EXE STARTUP.A51 SET(LARGE) DEBUG PRINT(..\List\STARTUP.lst) OBJECT(..\Outpu + t\STARTUP.obj) EP + +LOC OBJ LINE SOURCE + + 1 $nomod51 + 2 ;------------------------------------------------------------------------------ + 3 ; This file is part of the C51 Compiler package + 4 ; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc. + 5 ; Version 8.01 + 6 ; + 7 ; *** <<< Use Configuration Wizard in Context Menu >>> *** + 8 ;------------------------------------------------------------------------------ + 9 ; STARTUP.A51: This code is executed after processor reset. + 10 ; + 11 ; To translate this file use A51 with the following invocation: + 12 ; + 13 ; A51 STARTUP.A51 + 14 ; + 15 ; To link the modified STARTUP.OBJ file to your application use the following + 16 ; Lx51 invocation: + 17 ; + 18 ; Lx51 your object file list, STARTUP.OBJ controls + 19 ; + 20 ;------------------------------------------------------------------------------ + 21 ; + 22 ; User-defined Power-On Initialization of Memory + 23 ; + 24 ; With the following EQU statements the initialization of memory + 25 ; at processor reset can be defined: + 26 ; + 27 ; IDATALEN: IDATA memory size <0x0-0x100> + 28 ; Note: The absolute start-address of IDATA memory is always 0 + 29 ; The IDATA space overlaps physically the DATA and BIT areas. + 0100 30 IDATALEN EQU 100H + 31 ; + 32 ; XDATASTART: XDATA memory start address <0x0-0xFFFF> + 33 ; The absolute start address of XDATA memory + 0000 34 XDATASTART EQU 0 + 35 ; + 36 ; XDATALEN: XDATA memory size <0x0-0xFFFF> + 37 ; The length of XDATA memory in bytes. + 0100 38 XDATALEN EQU 100H + 39 ; + 40 ; PDATASTART: PDATA memory start address <0x0-0xFFFF> + 41 ; The absolute start address of PDATA memory + 0000 42 PDATASTART EQU 0H + 43 ; + 44 ; PDATALEN: PDATA memory size <0x0-0xFF> + 45 ; The length of PDATA memory in bytes. + 0000 46 PDATALEN EQU 0H + 47 ; + 48 ; + 49 ;------------------------------------------------------------------------------ + 50 ; + 51 ; Reentrant Stack Initialization + 52 ; + 53 ; The following EQU statements define the stack pointer for reentrant + 54 ; functions and initialized it: + 55 ; + 56 ; Stack Space for reentrant functions in the SMALL model. + 57 ; IBPSTACK: Enable SMALL model reentrant stack + A51 MACRO ASSEMBLER STARTUP 01/18/2024 10:03:14 PAGE 2 + + 58 ; Stack space for reentrant functions in the SMALL model. + 0000 59 IBPSTACK EQU 0 ; set to 1 if small reentrant is used. + 60 ; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF> + 61 ; Set the top of the stack to the highest location. + 0100 62 IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 + 63 ; + 64 ; + 65 ; Stack Space for reentrant functions in the LARGE model. + 66 ; XBPSTACK: Enable LARGE model reentrant stack + 67 ; Stack space for reentrant functions in the LARGE model. + 0000 68 XBPSTACK EQU 0 ; set to 1 if large reentrant is used. + 69 ; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF> + 70 ; Set the top of the stack to the highest location. + 0000 71 XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1 + 72 ; + 73 ; + 74 ; Stack Space for reentrant functions in the COMPACT model. + 75 ; PBPSTACK: Enable COMPACT model reentrant stack + 76 ; Stack space for reentrant functions in the COMPACT model. + 0000 77 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. + 78 ; + 79 ; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF> + 80 ; Set the top of the stack to the highest location. + 0100 81 PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 + 82 ; + 83 ; + 84 ;------------------------------------------------------------------------------ + 85 ; + 86 ; Memory Page for Using the Compact Model with 64 KByte xdata RAM + 87 ; Compact Model Page Definition + 88 ; + 89 ; Define the XDATA page used for PDATA variables. + 90 ; PPAGE must conform with the PPAGE set in the linker invocation. + 91 ; + 92 ; Enable pdata memory page initalization + 0000 93 PPAGEENABLE EQU 0 ; set to 1 if pdata object are used. + 94 ; + 95 ; PPAGE number <0x0-0xFF> + 96 ; uppermost 256-byte address of the page used for PDATA variables. + 0000 97 PPAGE EQU 0 + 98 ; + 99 ; SFR address which supplies uppermost address byte <0x0-0xFF> + 100 ; most 8051 variants use P2 as uppermost address byte + 00A0 101 PPAGE_SFR DATA 0A0H + 102 ; + 103 ; + 104 ;------------------------------------------------------------------------------ + 105 + 106 ; Standard SFR Symbols + 00E0 107 ACC DATA 0E0H + 00F0 108 B DATA 0F0H + 0081 109 SP DATA 81H + 0082 110 DPL DATA 82H + 0083 111 DPH DATA 83H + 112 + 113 NAME ?C_STARTUP + 114 + 115 + 116 ?C_C51STARTUP SEGMENT CODE + 117 ?STACK SEGMENT IDATA + 118 +---- 119 RSEG ?STACK +0000 120 DS 1 + 121 + 122 EXTRN CODE (?C_START) + 123 PUBLIC ?C_STARTUP + A51 MACRO ASSEMBLER STARTUP 01/18/2024 10:03:14 PAGE 3 + + 124 +---- 125 CSEG AT 0 +0000 020000 F 126 ?C_STARTUP: LJMP STARTUP1 + 127 +---- 128 RSEG ?C_C51STARTUP + 129 +0000 130 STARTUP1: + 131 + 132 IF IDATALEN <> 0 +0000 78FF 133 MOV R0,#IDATALEN - 1 +0002 E4 134 CLR A +0003 F6 135 IDATALOOP: MOV @R0,A +0004 D8FD 136 DJNZ R0,IDATALOOP + 137 ENDIF + 138 + 139 IF XDATALEN <> 0 +0006 900000 140 MOV DPTR,#XDATASTART +0009 7F00 141 MOV R7,#LOW (XDATALEN) + 142 IF (LOW (XDATALEN)) <> 0 + MOV R6,#(HIGH (XDATALEN)) +1 + ELSE +000B 7E01 145 MOV R6,#HIGH (XDATALEN) + 146 ENDIF +000D E4 147 CLR A +000E F0 148 XDATALOOP: MOVX @DPTR,A +000F A3 149 INC DPTR +0010 DFFC 150 DJNZ R7,XDATALOOP +0012 DEFA 151 DJNZ R6,XDATALOOP + 152 ENDIF + 153 + 154 IF PPAGEENABLE <> 0 + MOV PPAGE_SFR,#PPAGE + ENDIF + 157 + 158 IF PDATALEN <> 0 + MOV R0,#LOW (PDATASTART) + MOV R7,#LOW (PDATALEN) + CLR A + PDATALOOP: MOVX @R0,A + INC R0 + DJNZ R7,PDATALOOP + ENDIF + 166 + 167 IF IBPSTACK <> 0 + EXTRN DATA (?C_IBP) + + MOV ?C_IBP,#LOW IBPSTACKTOP + ENDIF + 172 + 173 IF XBPSTACK <> 0 + EXTRN DATA (?C_XBP) + + MOV ?C_XBP,#HIGH XBPSTACKTOP + MOV ?C_XBP+1,#LOW XBPSTACKTOP + ENDIF + 179 + 180 IF PBPSTACK <> 0 + EXTRN DATA (?C_PBP) + MOV ?C_PBP,#LOW PBPSTACKTOP + ENDIF + 184 +0014 758100 F 185 MOV SP,#?STACK-1 + 186 + 187 ; This code is required if you use L51_BANK.A51 with Banking Mode 4 + 188 ; Code Banking + 189 ; Select Bank 0 for L51_BANK.A51 Mode 4 + A51 MACRO ASSEMBLER STARTUP 01/18/2024 10:03:14 PAGE 4 + + 190 + + + + + 195 ; +0017 020000 F 196 LJMP ?C_START + 197 + 198 END + A51 MACRO ASSEMBLER STARTUP 01/18/2024 10:03:14 PAGE 5 + +SYMBOL TABLE LISTING +------ ----- ------- + + +N A M E T Y P E V A L U E ATTRIBUTES + +?C_C51STARTUP. . . C SEG 001AH REL=UNIT +?C_START . . . . . C ADDR ----- EXT +?C_STARTUP . . . . C ADDR 0000H A +?STACK . . . . . . I SEG 0001H REL=UNIT +ACC. . . . . . . . D ADDR 00E0H A +B. . . . . . . . . D ADDR 00F0H A +DPH. . . . . . . . D ADDR 0083H A +DPL. . . . . . . . D ADDR 0082H A +IBPSTACK . . . . . N NUMB 0000H A +IBPSTACKTOP. . . . N NUMB 0100H A +IDATALEN . . . . . N NUMB 0100H A +IDATALOOP. . . . . C ADDR 0003H R SEG=?C_C51STARTUP +PBPSTACK . . . . . N NUMB 0000H A +PBPSTACKTOP. . . . N NUMB 0100H A +PDATALEN . . . . . N NUMB 0000H A +PDATASTART . . . . N NUMB 0000H A +PPAGE. . . . . . . N NUMB 0000H A +PPAGEENABLE. . . . N NUMB 0000H A +PPAGE_SFR. . . . . D ADDR 00A0H A +SP . . . . . . . . D ADDR 0081H A +STARTUP1 . . . . . C ADDR 0000H R SEG=?C_C51STARTUP +XBPSTACK . . . . . N NUMB 0000H A +XBPSTACKTOP. . . . N NUMB 0000H A +XDATALEN . . . . . N NUMB 0100H A +XDATALOOP. . . . . C ADDR 000EH R SEG=?C_C51STARTUP +XDATASTART . . . . N NUMB 0000H A + + +REGISTER BANK(S) USED: 0 + + +ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/SysFunVarDefine.lst b/Keil_C/List/SysFunVarDefine.lst new file mode 100644 index 0000000..b83be66 --- /dev/null +++ b/Keil_C/List/SysFunVarDefine.lst @@ -0,0 +1,43 @@ +C51 COMPILER V9.59.0.0 SYSFUNVARDEFINE 01/18/2024 10:03:09 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE SYSFUNVARDEFINE +OBJECT MODULE PLACED IN ..\Output\SysFunVarDefine.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\User\SysFunVarDefine.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE I + -NCDIR(..\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\SysFunVarDefine.lst + -) OBJECT(..\Output\SysFunVarDefine.obj) + +line level source + + 1 //********************************************************************** + 2 // CopyRight (c) + 3 // File Name : SysFunVarDefine.c + 4 // Function : Store var control and function control define + 5 // Version : V2.0 + 6 // Date : 2021.08.04 + 7 //********************************************************************** + 8 #include "SC_Init.h" + 9 #include "SC_it.h" + 10 #include "..\Drivers\SCDriver_list.h" + 11 #include "HeadFiles\SysFunVarDefine.h" + 12 /**************************************Generated by EasyCodeCube*************************************/ + 13 + 14 /*************************************.Generated by EasyCodeCube.************************************/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = ---- ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/Uart1.lst b/Keil_C/List/Uart1.lst new file mode 100644 index 0000000..a002b77 --- /dev/null +++ b/Keil_C/List/Uart1.lst @@ -0,0 +1,838 @@ +C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE UART1 +OBJECT MODULE PLACED IN ..\Output\Uart1.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\Apps\Uart1.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE INCDIR(..\F + -WLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\Uart1.lst) OBJECT(..\Output\U + -art1.obj) + +line level source + + 1 /********************************Copyright (c)**********************************\ + 2 ** + 3 ** (c) Copyright 2019, China, JS. + 4 ** All Rights Reserved + 5 ** + 6 ** + 7 **----------------------------------ļϢ------------------------------------ + 8 ** ļ: ttl_usart.c + 9 ** : 2022-05-11 + 10 ** ĵ: ttl_usart + 11 ** + 12 **----------------------------------汾Ϣ------------------------------------ + 13 ** 汾: V0.1 + 14 ** 汾˵: ʼ汾 + 15 ** + 16 ********************************End of Head************************************/ + 17 + 18 /* Includes ------------------------------------------------------------------*/ + 19 + 20 /** + 21 * @file uart.c + 22 * @author Nations + 23 * @version v1.0.0 + 24 * + 25 * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + 26 */ + 27 + 28 #include + 29 + 30 + 31 #include "SC_Init.h" //MCU Init headerInclude all IC resource headers + 32 #include "SC_it.h" + 33 #include "..\Drivers\SCDriver_list.h" + 34 #include "HeadFiles\SysFunVarDefine.h" + 35 + 36 #include "Uart1.h" + 37 #include "Motor.h" + 38 + 39 //΢ʱ + 40 void DelayUs(unsigned int delay) + 41 { + 42 1 unsigned int i = 0, j = 0; + 43 1 for(i = 0; i < delay; i++) + 44 1 { + 45 2 for(j = 0; j < 125; j++); + 46 2 } + 47 1 } + 48 + 49 //ʱ + 50 void DelayMs(unsigned int delay) + 51 { + 52 1 unsigned int i = 0; + 53 1 for(i = 0; i < delay; i++) + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 2 + + 54 1 { + 55 2 DelayUs(1000); + 56 2 } + 57 1 } + 58 + 59 #define HD_VER 0001 //Ӳ汾 + 60 #define SW_VER 0001 //汾 + 61 + 62 #define TTL_SEND_BUFF_LEN 60 //ݳ + 63 #define TTL_RECEIVE_BUFF_LEN 60 //ݳ + 64 + 65 //---------------------------------------------------------------- + 66 //uart1ڽusbתttlĴ + 67 //---------------------------------------------------------------- + 68 + 69 //ŷ͵ + 70 uint8_t xdata motor_data[10]; + 71 + 72 //buff + 73 uint8_t xdata ttl_send_len = 0; + 74 uint8_t xdata ttl_send_buff[TTL_SEND_BUFF_LEN] = {0}; + 75 + 76 //buff + 77 uint8_t xdata ttl_receive_len = 0; + 78 uint8_t xdata ttl_receive_buff[TTL_RECEIVE_BUFF_LEN] = {0}; + 79 + 80 //ճʱ + 81 uint8_t xdata ttl_receive_flag = 0; + 82 uint8_t xdata ttl_receive_cnt = 0; + 83 uint8_t xdata ttl_receive_interval = 0; + 84 + 85 #define DATA_LEN TTL_RECEIVE_BUFF_LEN //һݳ + 86 #define UART_ORDER_SOF 0x05 //ʼ + 87 #define UART_ORDER_END 0x1B // + 88 #define FIXED_LEN 0x0B //̶ //ȡRW + 89 + 90 uint16_t xdata SUR_DEVICE_ADDR = 0x00A1; //PC //0x00A1; //豸 + 91 uint16_t xdata OBJ_DEVICE_ADDR = 0x00B1; // //0x00B1; //PCȺ FFFF 0000 + 92 + 93 uint8_t xdata order_flag = 0; + 94 unsigned int xdata checksum = 0, re_status = 0, rec_len = 0, data_len = 0, shouldaccept = 0; + 95 + 96 // + 97 void UART1_SendData(uint8_t dat) + 98 { + 99 1 SSI_UART1_SendData8(dat); + 100 1 } + 101 + 102 // + 103 void UART1_Send_Char(uint8_t dat) + 104 { + 105 1 SSI_UART1_SendData8(dat); + 106 1 } + 107 + 108 //ʼ + 109 void InitUart_Data(void) + 110 { + 111 1 order_flag = 0; + 112 1 rec_len = 0; + 113 1 re_status = 0; + 114 1 shouldaccept = 0; + 115 1 + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 3 + + 116 1 ttl_receive_flag = 0; + 117 1 ttl_receive_cnt = 0; + 118 1 + 119 1 checksum = 0; + 120 1 + 121 1 for(data_len = 0; data_len < DATA_LEN; data_len++) + 122 1 { + 123 2 ttl_receive_buff[data_len] = 0; + 124 2 } + 125 1 + 126 1 data_len = 0; + 127 1 + 128 1 // UART_Send_Char(0xdd); + 129 1 } + 130 + 131 + 132 + 133 /* Private function prototypes -----------------------------------------------*/ + 134 /* Private functions ---------------------------------------------------------*/ + 135 //---------------------------------------------------------------- + 136 //մ1 + 137 //---------------------------------------------------------------- + 138 /**************************************************************************************************** + 139 * @brief Download a file via serial port + 140 * @param None + 141 * @retval None + 142 **************************************************************************************************/ + 143 void start_ttl_receive_timer(uint32_t ms) + 144 { + 145 1 if(ms == 0) + 146 1 { + 147 2 return; + 148 2 } + 149 1 + 150 1 ttl_receive_flag = 1; + 151 1 ttl_receive_cnt = 0; + 152 1 ttl_receive_interval = ms; + 153 1 } + 154 + 155 /**************************************************************************************************** + 156 * @brief Upload a file via serial port. + 157 * @param None + 158 * @retval None + 159 **************************************************************************************************/ + 160 void over_ttl_receive_timer(void) + 161 { + 162 1 ttl_receive_flag = 0; + 163 1 ttl_receive_cnt = 0; + 164 1 ttl_receive_interval = 0; + 165 1 + 166 1 InitUart_Data(); + 167 1 + 168 1 // UART2_Send_Char(0xed); + 169 1 } + 170 + 171 /**************************************************************************************************** + 172 * @brief Display the Main Menu on HyperTerminal + 173 * @param None + 174 * @retval None + 175 **************************************************************************************************/ + 176 void clear_ttl_receive_timer(void) + 177 { + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 4 + + 178 1 uint16_t i = 0; + 179 1 ttl_receive_len = 0; + 180 1 ttl_receive_flag = 0; + 181 1 ttl_receive_cnt = 0; + 182 1 ttl_receive_interval = 0; + 183 1 + 184 1 for(i = 0; i < TTL_RECEIVE_BUFF_LEN; i++) + 185 1 { + 186 2 ttl_receive_buff[i] = 0; + 187 2 } + 188 1 } + 189 + 190 //شӦǷɵĽ + 191 //0ûʱ 1ʱ + 192 uint8_t judge_ttl_receive_timer(void) + 193 { + 194 1 if(ttl_receive_flag == 2) + 195 1 { + 196 2 return 1; + 197 2 } + 198 1 else + 199 1 { + 200 2 return 0; + 201 2 } + 202 1 } + 203 + 204 /**************************************************************************************************** + 205 * @brief Display the Main Menu on HyperTerminal + 206 * @param None + 207 * @retval None + 208 **************************************************************************************************/ + 209 //ڴѭеļʱ + 210 void process_ttl_receive_timer(void) + 211 { + 212 1 if(ttl_receive_flag == 1) + 213 1 { + 214 2 ttl_receive_cnt++; + 215 2 } + 216 1 + 217 1 if((ttl_receive_interval > 0) && (ttl_receive_cnt >= ttl_receive_interval)) + 218 1 { + 219 2 over_ttl_receive_timer(); + 220 2 } + 221 1 } + 222 + 223 #define TTL_OVER_TIME 10 + 224 /**************************************************************************************************** + 225 * @brief Display the Main Menu on HyperTerminal + 226 * @param None + 227 * @retval None + 228 **************************************************************************************************/ + 229 //Ŵжڣ + 230 void receive_ttl_data(uint8_t rx_data) + 231 { + 232 1 //ܳ󳤶 + 233 1 if(ttl_receive_len < TTL_RECEIVE_BUFF_LEN) + 234 1 { + 235 2 //ʼʱ + 236 2 start_ttl_receive_timer(TTL_OVER_TIME); + 237 2 + 238 2 //ڽݷ + 239 2 Do_Receive_Uart_For_Module(rx_data); + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 5 + + 240 2 } + 241 1 else // + 242 1 { + 243 2 //ʱ + 244 2 over_ttl_receive_timer(); + 245 2 + 246 2 InitUart_Data(); + 247 2 + 248 2 //UART_Send_Char(0xcc); + 249 2 } + 250 1 } + 251 + 252 #define CRC_PRESET 0xFFFF + 253 #define CRC_POLYNOM 0x4204 + 254 /*--------------------------------------------------------------------------- + 255 ÷ʽunsigned int ModbusCRC16(unsigned char *data_value, unsigned char length) + 256 ˵CRCУ + 257 ---------------------------------------------------------------------------*/ + 258 unsigned int ModbusCRC16(unsigned char *data_value, unsigned char length) + 259 { + 260 1 unsigned int crc_value = CRC_PRESET; + 261 1 unsigned char i; + 262 1 data_value++; + 263 1 while(length-- != 0) + 264 1 {//ModbusCRC16(PData, Num + FIXED_LEN - 3); + 265 2 for(i = 0x01; i != 0; i <<= 1) + 266 2 { + 267 3 if((crc_value & 0x0001) != 0) + 268 3 { + 269 4 crc_value >>= 1; + 270 4 crc_value ^= CRC_POLYNOM; + 271 4 } + 272 3 else + 273 3 { + 274 4 crc_value >>= 1; + 275 4 } + 276 3 + 277 3 if((*data_value & i) != 0) + 278 3 { + 279 4 crc_value ^= CRC_POLYNOM; + 280 4 } + 281 3 } + 282 2 data_value++; + 283 2 } + 284 1 return(crc_value); + 285 1 } + 286 + 287 /*--------------------------------------------------------------------------- + 288 ÷ʽunsigned int VerfiyRC(unsigned char *data_value, unsigned char length) + 289 ˵У + 290 ͷβ̶У⣬У + 291 -----------------------------------------------------------------------------*/ + 292 unsigned char VerfiyRC(unsigned char data_value[], unsigned char length) //У飬crcУ + 293 { + 294 1 unsigned char i; + 295 1 unsigned char V_b = data_value[1]; + 296 1 + 297 1 for(i = 0x00; i < length; i++) + 298 1 { + 299 2 //У + 300 2 V_b ^= data_value[i]; + 301 2 } + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 6 + + 302 1 + 303 1 return(V_b); + 304 1 } + 305 + 306 //ʱ + 307 void Uart_Send_Delay(unsigned int delay) + 308 { + 309 1 unsigned int i = 0, j = 0; + 310 1 + 311 1 for(i = 0; i < delay; i++) + 312 1 { + 313 2 for(j = 0; j < 125; j++); + 314 2 } + 315 1 } + 316 + 317 //У + 0X1B + 318 #define VERFIY_TYPE 0 + 319 + 320 /* + 321 SOF 1ֽ 0x05 ʼֽ + 322 Len 2ֽ + 323 Fou_adr 2ֽ Դַ + 324 Com_adr 2ֽ Ŀַ0ffΪ㲥ַ + 325 Cmd16 2ֽ + 326 Request-data Nֽ + 327 XOR 2ֽ У + 328 END 0x1B ֽ + 329 */ + 330 + 331 // + 332 void send_set_resp(unsigned int OrderNum, unsigned int addr, unsigned char Num, unsigned char sData[]) + 333 { + 334 1 unsigned int xdata xor_data = 0; + 335 1 unsigned char xdata PData[TTL_SEND_BUFF_LEN]; + 336 1 unsigned char xdata i = 0; + 337 1 + 338 1 PData[0] = UART_ORDER_SOF; //һֽ + 339 1 PData[1] = (Num + FIXED_LEN) / 0x100; // 8λ + 340 1 PData[2] = (Num + FIXED_LEN) % 0x100; // 8λ + 341 1 PData[3] = (addr >> 8) & 0xff; //Դַ + 342 1 PData[4] = addr & 0xff; //Դַ + 343 1 PData[5] = (SUR_DEVICE_ADDR >> 8) & 0xff; //Ŀַ + 344 1 PData[6] = SUR_DEVICE_ADDR & 0xff; //Ŀַ + 345 1 PData[7] = (OrderNum >> 8) & 0xff; // -1 + 346 1 PData[8] = OrderNum & 0xff; // -2 + 347 1 + 348 1 // PData[6] = RW_Flag; //д־ + 349 1 + 350 1 for(i = 0; i < Num; i++) // + 351 1 { + 352 2 PData[FIXED_LEN - 2 + i] = sData[i]; // + 353 2 } + 354 1 + 355 1 //У + 356 1 if(VERFIY_TYPE) //У + ĩβֽ 2ֽ + 357 1 { + 358 2 xor_data = VerfiyRC(PData, Num + FIXED_LEN - 2); + 359 2 PData[FIXED_LEN + Num - 2] = xor_data; + 360 2 PData[FIXED_LEN + Num - 1] = 00; + 361 2 } + 362 1 else //CRCУ 2ֽ + 363 1 { + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 7 + + 364 2 xor_data = ModbusCRC16(PData, Num + FIXED_LEN - 3); + 365 2 PData[FIXED_LEN + Num - 2] = (xor_data) & 0xff; + 366 2 PData[FIXED_LEN + Num - 1] = (xor_data >> 8) & 0xff; + 367 2 } + 368 1 + 369 1 PData[FIXED_LEN + Num] = UART_ORDER_END; // ĩβֽ + 370 1 + 371 1 //ȫ + 372 1 for(i = 0; i < (Num + FIXED_LEN + 1); i++) //һԷ + 373 1 { + 374 2 UART1_Send_Char(PData[i]); + 375 2 //ʱ + 376 2 Uart_Send_Delay(50); + 377 2 } + 378 1 } + 379 + 380 + 381 + 382 //ַǷΪַ + 383 uint8_t Check_Resive_Addr(uint16_t addr) + 384 { + 385 1 //ȷǷΪյַ + 386 1 if((OBJ_DEVICE_ADDR == addr) || (0xFFFF == addr) || (0x0000 == addr) || (0x00B1 == addr)) + 387 1 { + 388 2 return 1; + 389 2 } + 390 1 else + 391 1 { + 392 2 InitUart_Data(); //2 + 393 2 return 0; + 394 2 } + 395 1 } + 396 + 397 + 398 //жϣôڽڣ + 399 void Do_Receive_Uart_For_Module(unsigned char ch) + 400 { + 401 1 switch(re_status) + 402 1 { + 403 2 case 0 : //0x05 1ֽ ʼ + 404 2 { + 405 3 if(ch == UART_ORDER_SOF) + 406 3 { + 407 4 rec_len = 0; + 408 4 ttl_receive_buff[rec_len] = ch; + 409 4 re_status = 1; + 410 4 shouldaccept = 0; + 411 4 // UART2_Send_Char(0xaa); + 412 4 } + 413 3 } + 414 2 break; + 415 2 case 1: // 2ֽ + 416 2 { + 417 3 rec_len++; + 418 3 ttl_receive_buff[rec_len] = ch; + 419 3 + 420 3 if(rec_len >= 2) + 421 3 { + 422 4 re_status = 2; + 423 4 shouldaccept = ttl_receive_buff[1] * 0x100 + ttl_receive_buff[2]; + 424 4 + 425 4 if(shouldaccept >= TTL_RECEIVE_BUFF_LEN - 1) + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 8 + + 426 4 { + 427 5 InitUart_Data(); + 428 5 return; + 429 5 } + 430 4 } + 431 3 } + 432 2 break; + 433 2 case 2: // 2ֽ 05 00 0B 00 C1 00 A1 F0 01 87 1B + 434 2 { + 435 3 rec_len++; + 436 3 + 437 3 if(rec_len >= TTL_RECEIVE_BUFF_LEN - 1) + 438 3 { + 439 4 InitUart_Data(); + 440 4 return; + 441 4 } + 442 3 + 443 3 ttl_receive_buff[rec_len] = ch; // + 444 3 + 445 3 if(rec_len >= shouldaccept) //жǷ + 446 3 { + 447 4 // uint8_t i = 0; + 448 4 // UART2_Send_Char(0x30); + 449 4 // UART2_Send_Char(rec_len); + 450 4 // UART2_Send_Char(shouldaccept); + 451 4 // UART2_Send_Char(FIXED_LEN - 1); + 452 4 + 453 4 // UART2_Send_Char(rec_len); + 454 4 // for( i = 0;i < shouldaccept;i++) UART2_Send_Char(ttl_receive_buff[i]); + 455 4 + 456 4 //ȴҪڹ̶ + 457 4 // if(rec_len >= FIXED_LEN - 1) + 458 4 // { + 459 4 //жϽĿַǷԼ + 460 4 // int adr = ttl_receive_buff[3]; + 461 4 // adr = adr << 8; + 462 4 // adr |= ttl_receive_buff[4]; + 463 4 int adr = ttl_receive_buff[5]; + 464 4 adr = adr << 8; + 465 4 adr |= ttl_receive_buff[6]; + 466 4 + 467 4 //UART2_TxByte(0xAA); + 468 4 //UART2_TxByte(ttl_receive_buff[3]); + 469 4 //UART2_TxByte(ttl_receive_buff[4]); + 470 4 // + 471 4 if(Check_Resive_Addr(adr)) + 472 4 { + 473 5 // + 474 5 unsigned int order = 0; + 475 5 order = ttl_receive_buff[7]; + 476 5 order = order << 8; + 477 5 order += ttl_receive_buff[8]; + 478 5 + 479 5 // //Ŀַ + 480 5 // OBJ_DEVICE_ADDR = ttl_receive_buff[3]; + 481 5 // OBJ_DEVICE_ADDR <<= 8; + 482 5 // OBJ_DEVICE_ADDR += ttl_receive_buff[4]; + 483 5 + 484 5 //UART2_Send_Char(order / 0x100); + 485 5 //UART2_Send_Char(order % 0x100); + 486 5 //UART2_TxByte(0xBB); + 487 5 //UART2_TxByte(ttl_receive_buff[7]); + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 9 + + 488 5 //UART2_TxByte(ttl_receive_buff[8]); + 489 5 + 490 5 switch(order) + 491 5 { + 492 6 //=================== =================================================== + 493 6 //豸 + 494 6 //====================================================================== + 495 6 case 0xF001 : // + 496 6 { + 497 7 order_flag = 1; + 498 7 } + 499 6 break; + 500 6 + 501 6 case 0xF0C1 : //豸Ϣ + 502 6 { + 503 7 order_flag = 2; + 504 7 } + 505 6 break; + 506 6 + 507 6 //====================================================================== + 508 6 //豸Ϣ + 509 6 //====================================================================== + 510 6 case 0xF111 : //Ʋ + 511 6 { + 512 7 order_flag = 3; + 513 7 // UART2_Send_Char(0x33); + 514 7 } + 515 6 break; + 516 6 + 517 6 //====================================================================== + 518 6 //豸Ϣ + 519 6 //====================================================================== + 520 6 case 0xF112 : // ״̬¶ + 521 6 { + 522 7 order_flag = 4; + 523 7 } + 524 6 break; + 525 6 case 0xF102 : // ״̬¶ + 526 6 { + 527 7 order_flag = 4; + 528 7 } + 529 6 break; + 530 6 + 531 6 //====================================================================== + 532 6 // + 533 6 //====================================================================== + 534 6 default : + 535 6 { + 536 7 InitUart_Data(); + 537 7 } + 538 6 break; + 539 6 } + 540 5 } + 541 4 else + 542 4 { + 543 5 InitUart_Data(); + 544 5 return; + 545 5 } + 546 4 } + 547 3 // } + 548 3 } + 549 2 break; + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 10 + + 550 2 + 551 2 default : + 552 2 InitUart_Data(); + 553 2 break; + 554 2 } + 555 1 } + 556 + 557 //ݳ + 558 uint8_t Get_Data_Len(void) + 559 { + 560 1 uint16_t Re_Len = 0; + 561 1 Re_Len = (ttl_receive_buff[1] * 0x100 + ttl_receive_buff[2]) - FIXED_LEN; + 562 1 return Re_Len; + 563 1 } + 564 + 565 //У + 566 unsigned char Check_VerfiyData(void) + 567 { + 568 1 return 1; //ڼ䣬֤ + 569 1 + 570 1 if(VERFIY_TYPE) //У + ĩβֽ + 571 1 { + 572 2 unsigned char v_A = 0; + 573 2 unsigned char v_B = 0; + 574 2 v_A = ttl_receive_buff[shouldaccept]; + 575 2 v_B = VerfiyRC(ttl_receive_buff, shouldaccept - 2); + 576 2 + 577 2 if(v_A == v_B) //ݵ + 578 2 { + 579 3 //βͬ + 580 3 if(ttl_receive_buff[shouldaccept + 1] == UART_ORDER_END) + 581 3 { + 582 4 + 583 4 } + 584 3 else + 585 3 { + 586 4 return 0; + 587 4 } + 588 3 } + 589 2 else + 590 2 { + 591 3 return 0; + 592 3 } + 593 2 } + 594 1 else //жCRCУ + 595 1 { + 596 2 unsigned int CRC16 = 0; + 597 2 unsigned int Get_CRC16 = 0; + 598 2 CRC16 = ttl_receive_buff[shouldaccept]; + 599 2 CRC16 = CRC16 << 8; + 600 2 CRC16 += ttl_receive_buff[shouldaccept - 1]; + 601 2 + 602 2 Get_CRC16 = ModbusCRC16(ttl_receive_buff, shouldaccept - 2); + 603 2 + 604 2 if(CRC16 == Get_CRC16) //ݵ + 605 2 { + 606 3 + 607 3 } + 608 2 else + 609 2 { + 610 3 InitUart_Data(); + 611 3 return 0; + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 11 + + 612 3 } + 613 2 } + 614 1 + 615 1 return 1; + 616 1 } + 617 + 618 + 619 //ݽշ(ôѭ) + 620 void Deal_Uart_Data_For_Module(void) + 621 { + 622 1 if(order_flag) //нյָ + 623 1 { + 624 2 //У + 625 2 if(Check_VerfiyData() == 1) // + 626 2 { + 627 3 switch(order_flag) + 628 3 { + 629 4 //-------------------------------------------------------------------- + 630 4 // + 631 4 //-------------------------------------------------------------------- + 632 4 case 1 : //ݽ + 633 4 { + 634 5 uint8_t xdata i = 0; //ʱ + 635 5 uint8_t xdata len = 0; // + 636 5 uint8_t xdata temp[DATA_LEN]; + 637 5 + 638 5 //ͱ־ + 639 5 send_flag = 0; + 640 5 + 641 5 //ݳ + 642 5 len = Get_Data_Len(); + 643 5 + 644 5 // + 645 5 for(i = 0; i < len; i++) + 646 5 { + 647 6 temp[i] = ttl_receive_buff[i + FIXED_LEN - 2]; + 648 6 } + 649 5 + 650 5 //г ֱг + 651 5 Travle_Flag = temp[0]; //0 ֱ 1 + 652 5 Motor_Run = temp[1]; //0 ֹͣ 1 2 еʼ 3 е + 653 5 Run_Mode = temp[2]; //0 㶯 1 һ 2 + 654 5 + 655 5 Run_Step = temp[3]; //жȦΪһ + 656 5 Run_Step <<= 8; + 657 5 Run_Step += temp[4]; + 658 5 + 659 5 Run_Inter = temp[5]; //мʱ + 660 5 Run_Inter <<= 8; + 661 5 Run_Inter += temp[6]; + 662 5 + 663 5 Run_Stop = temp[7]; //㡱ֹͣʱ + 664 5 Run_Stop <<= 8; + 665 5 Run_Stop += temp[8]; + 666 5 + 667 5 ClrRunmotorStep();// + 668 5 + 669 5 } + 670 4 break; + 671 4 + 672 4 case 2 : // + 673 4 { + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 12 + + 674 5 uint8_t i = 0; + 675 5 uint8_t len = 0; + 676 5 uint8_t temp[DATA_LEN]; + 677 5 + 678 5 send_set_resp(0xF0C1, OBJ_DEVICE_ADDR, len, temp); + 679 5 + 680 5 } + 681 4 break; + 682 4 + 683 4 //-------------------------------------------------------------------- + 684 4 //LED + 685 4 //-------------------------------------------------------------------- + 686 4 case 3 : //F111 05 00 0C 00 A1 00 C1 F1 01 05 03 50 87 1B + 687 4 { + 688 5 u8 addr = 0; + 689 5 addr = ttl_receive_buff[FIXED_LEN - 2]; + 690 5 if(addr == ((SUR_DEVICE_ADDR & 0xf0) == 0xC0)) + 691 5 { + 692 6 + 693 6 } + 694 5 } + 695 4 break; + 696 4 + 697 4 //====================================================================== + 698 4 // + 699 4 //====================================================================== + 700 4 case 4 : // + 701 4 { + 702 5 + 703 5 + 704 5 } + 705 4 break; + 706 4 + 707 4 //-------------------------------------------------------------------- + 708 4 //ʵʱϢ + 709 4 //-------------------------------------------------------------------- + 710 4 case 5 : // + 711 4 { + 712 5 uint8_t len = 0; + 713 5 uint8_t temp[DATA_LEN]; + 714 5 + 715 5 + 716 5 + 717 5 temp[0] = (SUR_DEVICE_ADDR >> 8) & 0xff; + 718 5 temp[1] = (SUR_DEVICE_ADDR >> 0) & 0xff; + 719 5 + 720 5 // //汾 4 + 721 5 temp[2] = HD_VER >> 8; //HD_VER 0101 //Ӳ汾 + 722 5 temp[3] = HD_VER & 0xff; + 723 5 + 724 5 temp[4] = SW_VER >> 8; //SW_VER 0101 //汾 + 725 5 temp[5] = SW_VER & 0xff; + 726 5 + 727 5 len = 6; + 728 5 send_set_resp(0xF113, OBJ_DEVICE_ADDR, len, temp); + 729 5 } + 730 4 break; + 731 4 case 6 : // ַ + 汾 F1D3 05 00 0D 00 A1 00 00 F1 D3 00 C1 07 A9 1B + 732 4 { + 733 5 + 734 5 uint8_t i = 0; + 735 5 uint8_t len = 0; + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 13 + + 736 5 uint8_t temp[DATA_LEN]; + 737 5 + 738 5 //ݳ + 739 5 len = Get_Data_Len(); + 740 5 + 741 5 for(i = 0; i < len; i++) + 742 5 { + 743 6 temp[i] = ttl_receive_buff[i + FIXED_LEN - 2]; + 744 6 } + 745 5 + 746 5 + 747 5 send_set_resp(0xF1C3, OBJ_DEVICE_ADDR, len, temp); + 748 5 } + 749 4 break; + 750 4 case 7 : //³ + 751 4 { + 752 5 + 753 5 } + 754 4 break; + 755 4 + 756 4 //-------------------------------------------------------------------- + 757 4 //豸Ϣ + 758 4 //-------------------------------------------------------------------- + 759 4 case 10 : //F115 05 00 0A 00 C1 00 A1 F1 05 50 87 1B + 760 4 { + 761 5 + 762 5 + 763 5 } + 764 4 break; + 765 4 + 766 4 + 767 4 default : + 768 4 { + 769 5 + 770 5 } + 771 4 break; + 772 4 } + 773 3 } + 774 2 + 775 2 // + 776 2 InitUart_Data(); + 777 2 } + 778 1 } + 779 + 780 +*** WARNING C294 IN LINE 358 OF ..\Apps\Uart1.c: unreachable code +*** WARNING C294 IN LINE 572 OF ..\Apps\Uart1.c: unreachable code +*** WARNING C294 IN LINE 596 OF ..\Apps\Uart1.c: unreachable code + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 1870 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = 150 154 + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- + C51 COMPILER V9.59.0.0 UART1 01/18/2024 10:03:11 PAGE 14 + +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 3 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/adc.lst b/Keil_C/List/adc.lst new file mode 100644 index 0000000..4e7c7a7 --- /dev/null +++ b/Keil_C/List/adc.lst @@ -0,0 +1,116 @@ +C51 COMPILER V9.59.0.0 ADC 01/18/2024 10:03:11 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE ADC +OBJECT MODULE PLACED IN ..\Output\adc.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\Apps\adc.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE INCDIR(..\FWL + -ib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\adc.lst) OBJECT(..\Output\adc.o + -bj) + +line level source + + 1 #include "SC_Init.h" //MCU Init headerInclude all IC resource headers + 2 #include "SC_it.h" + 3 #include "..\Drivers\SCDriver_list.h" + 4 #include "HeadFiles\SysFunVarDefine.h" + 5 + 6 #include "adc.h" + 7 #include "Uart1.h" + 8 + 9 unsigned int xdata ADC_Value0 = 0,ADC_Value1 = 0,ADC_Value2 = 0; + 10 + 11 unsigned int xdata ADC_NUM1=0; + 12 //ȡadcתֵ + 13 unsigned int ADC_Convert(void) + 14 { + 15 1 unsigned int xdata Tad = 0,MinAd1 = 0x0fff,MaxAd1 = 0x0000,MinAd2 = 0x0fff,MaxAd2 = 0x0000,TempAdd = + -0; + 16 1 unsigned char xdata t = 0; + 17 1 for(t = 0;t < 10;t++) + 18 1 { + 19 2 ADCCON |= 0X40; //ʼ ADC ת + 20 2 while(!(ADCCON & 0x20));//ȴ ADC תɣͬͺŵתɱ־λλòͬͺ Bit5,ͺ + -Bit4,չ + 21 2 //жϱ־λ + 22 2 ADCCON &= ~(0X20); + 23 2 Tad = ((unsigned int)ADCVH << 4) + (ADCVL >> 4); //ȡһתֵ + 24 2 ADC_NUM1=Tad; + 25 2 if(Tad > MaxAd1) + 26 2 { + 27 3 MaxAd1 = Tad;//õǰֵ + 28 3 } + 29 2 // else + 30 2 // { + 31 2 // if(Tad > MaxAd2) + 32 2 // MaxAd2 = Tad; + 33 2 // } + 34 2 if (Tad < MinAd1) + 35 2 { + 36 3 MinAd1 = Tad;//õǰСֵ + 37 3 } + 38 2 // else + 39 2 // { + 40 2 // if(Tad > MinAd2) + 41 2 // MinAd2 = Tad; + 42 2 // } + 43 2 TempAdd += Tad; + 44 2 } + 45 1 + 46 1 //תֵۼ + 47 1 TempAdd -= MinAd1;//ȥСֵ + 48 1 TempAdd -= MaxAd1;//ȥֵ + 49 1 // TempAdd -= MinAd2;//ȥڶСֵ + 50 1 // TempAdd -= MaxAd2;//ȥڶֵ + 51 1 //TempAdd = TempAdd / 16; + C51 COMPILER V9.59.0.0 ADC 01/18/2024 10:03:11 PAGE 2 + + 52 1 TempAdd >>= 3; //ƽֵ + 53 1 return TempAdd; + 54 1 } + 55 + 56 //лADC + 57 void ADC_channel(unsigned char ADC_Channel) + 58 { + 59 1 ADCCFG0 = 0x07; + 60 1 ADCCON = 0xE0 | ADC_Channel; + 61 1 } + 62 + 63 extern uint8_t xdata motor_data[]; + 64 void ADC_Multichannel(void) + 65 { + 66 1 uint8_t xdata temp_h,temp_l; //߰λ͵Ͱλ + 67 1 + 68 1 ADC_channel(1); //ADC л AIN1 ڣɼѹź + 69 1 ADC_Value1 = ADC_Convert(); // ADC תתֵ + 70 1 temp_h = (ADC_Value1 & 0xff00) >> 8;//8λֵ + 71 1 temp_l = ADC_Value1 & 0x00ff; //8λֵ + 72 1 motor_data[4] = temp_h; + 73 1 motor_data[5] = temp_l; + 74 1 + 75 1 ADC_channel(2); //ADC л AIN2 ڣɼź + 76 1 ADC_Value2 = ADC_Convert(); // ADC תתֵ + 77 1 temp_h = (ADC_Value2 & 0xff00) >> 8;//8λֵ + 78 1 temp_l = ADC_Value2 & 0x00ff; //8λֵ + 79 1 motor_data[6] = temp_h; + 80 1 motor_data[7] = temp_l; + 81 1 } + 82 + 83 + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 295 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = 8 10 + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/main.lst b/Keil_C/List/main.lst new file mode 100644 index 0000000..54d3f83 --- /dev/null +++ b/Keil_C/List/main.lst @@ -0,0 +1,89 @@ +C51 COMPILER V9.59.0.0 MAIN 01/18/2024 10:03:08 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE MAIN +OBJECT MODULE PLACED IN ..\Output\main.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\User\main.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE INCDIR(..\FW + -Lib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\main.lst) OBJECT(..\Output\mai + -n.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) + 3 // FileName : main.c + 4 // Module Function : + 5 // Instructions : Contains the MCU initialization function and its H file + 6 //************************************************************ + 7 /********************Includes************************************************************************/ + 8 #include "SC_Init.h" //MCU Init headerInclude all IC resource headers + 9 #include "SC_it.h" + 10 #include "..\Drivers\SCDriver_list.h" + 11 #include "HeadFiles\SysFunVarDefine.h" + 12 + 13 #include + 14 #include "test.h" + 15 #include "uart1.h" + 16 #include "motor.h" + 17 #include "adc.h" + 18 + 19 /**************************************Generated by EasyCodeCube*************************************/ + 20 + 21 + 22 /*************************************.Generated by EasyCodeCube.************************************/ + 23 /***************************************************************************************************** + 24 * Function Name: main + 25 * Description : This function implements main function. + 26 * Arguments : None + 27 * Return Value : None + 28 ******************************************************************************************************/ + 29 void main(void) + 30 { + 31 1 SC_Init(); /*** MCU init***/ + 32 1 InitUart_Data();//ݳʼ + 33 1 + 34 1 /*****MainLoop*****/ + 35 1 while(1) + 36 1 { + 37 2 /**//*<5>*/ + 38 2 //ݽշ(ôѭ) + 39 2 Deal_Uart_Data_For_Module(); + 40 2 + 41 2 //иģʽ + 42 2 Deal_Motor();//һ1-5 + 43 2 + 44 2 //ɼADC + 45 2 if(it_10ms_flag == 1)//10 + 46 2 { + 47 3 it_10ms_flag = 0; + 48 3 ADC_Multichannel();//ADCݲɼ + 49 3 } + 50 2 + 51 2 //ָʾ + 52 2 led_test(); + 53 2 + C51 COMPILER V9.59.0.0 MAIN 01/18/2024 10:03:08 PAGE 2 + + 54 2 } + 55 1 } + 56 + 57 + 58 + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 29 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/motor.lst b/Keil_C/List/motor.lst new file mode 100644 index 0000000..eec6c67 --- /dev/null +++ b/Keil_C/List/motor.lst @@ -0,0 +1,1065 @@ +C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE MOTOR +OBJECT MODULE PLACED IN ..\Output\motor.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\Apps\motor.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE INCDIR(..\F + -WLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\motor.lst) OBJECT(..\Output\m + -otor.obj) + +line level source + + 1 #include "motor.h" + 2 + 3 #define STEP_LIN 16 //ֱг̲λֵ + 4 #define STEP_ROT 20 //г̲λֵ + 5 #define DATA_LEN 10 //г̲λֵ + 6 + 7 bit Travle_Flag = 0; //0 ֱ 1 + 8 char xdata Motor_Run = 0; //0 ֹͣ 1 2 еʼ 3 е + 9 char xdata Run_Mode = 0; //0 㶯 1 һ 2 + 10 unsigned int xdata Run_Step = 0; //в + 11 unsigned int xdata Run_Inter = 0; //мʱ + 12 unsigned int xdata Run_Stop = 0; //㡱ֹͣʱ + 13 unsigned int xdata Run_mm = 0; //нȣmm/תǶȣ㣩 + 14 unsigned int xdata Run_num = 0; //г̵תȦ + 15 unsigned int xdata ct_num = 0; // + 16 + 17 bit mov_flag = 0; //־ + 18 bit send_flag = 0; //ͱ־ + 19 bit seat_flag = 0; //λñ־ + 20 bit motor_dire = 1; //ת + 21 bit flag = 0; + 22 + 23 + 24 // + 25 unsigned char xdata Runmotor_step = 0; + 26 + 27 // + 28 unsigned int xdata Runmotor_Nums = 0; + 29 + 30 // + 31 void motor_start(void) + 32 { + 33 1 GPIO_Init(GPIO1, GPIO_PIN_7,GPIO_MODE_OUT_PP);//Ϊģʽյź + 34 1 GPIO_WriteHigh(GPIO1,GPIO_PIN_7); + 35 1 motor_data[1] = 0x01;//Ӧ01 + 36 1 } + 37 + 38 //ֹͣ + 39 void motor_stop(void) + 40 { + 41 1 GPIO_WriteHigh(GPIO1,GPIO_PIN_7); + 42 1 GPIO_Init(GPIO1, GPIO_PIN_7,GPIO_MODE_IN_HI);//Ϊģʽ޷յź + 43 1 motor_data[1] = 0x00;//ֹͣӦ00 + 44 1 } + 45 + 46 //ת + 47 void FWD(void) + 48 { + 49 1 GPIO_WriteLow(GPIO1,GPIO_PIN_6);//ŵƽõͣת + 50 1 } + 51 + 52 //ת + 53 void REV(void) + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 2 + + 54 { + 55 1 GPIO_WriteHigh(GPIO1,GPIO_PIN_6);//ŵƽøߣת + 56 1 } + 57 + 58 + 59 + 60 // + 61 void ClrRunmotorStep(void) + 62 { + 63 1 // + 64 1 Runmotor_step = 0; + 65 1 // + 66 1 Runmotor_Nums = 0; + 67 1 //0 + 68 1 mov_flag = 0; + 69 1 //ͱ0 + 70 1 send_flag = 0; + 71 1 //λñ0 + 72 1 seat_flag = 0; + 73 1 } + 74 + 75 // + 76 void Deal_Motor(void) + 77 { + 78 1 //жֱг̻ǽг + 79 1 if(Travle_Flag == 0)//ֱг̡תһȦˮƽλ5mm + 80 1 { + 81 2 motor_data[0] = 0x00;//00 ֱг 01 г + 82 2 //жϵֹͣУеʼλǽλ + 83 2 if( Motor_Run == 0)//ֹͣ + 84 2 { + 85 3 motor_stop(); + 86 3 } + 87 2 else if(Motor_Run == 1)// + 88 2 { + 89 3 if(Motor_Run >= 1 && Runmotor_step == 0) + 90 3 { + 91 4 Runmotor_step = 1; + 92 4 } + 93 3 + 94 3 //жϵзʽǵ㶯㶯ΪһͷΪ + 95 3 if(Run_Mode == 0)//㶯 + 96 3 { + 97 4 motor_data[2] = 0x00;//ʱ + 98 4 mov_step();//㶯 + 99 4 } + 100 3 else if(Run_Mode == 1)//һܻԽλء + 101 3 { + 102 4 motor_data[2] = 0x01;//ʱ + 103 4 mov_loop1();//һ + 104 4 } + 105 3 else if(Run_Mode == 2)//ܻԽλء + 106 3 { + 107 4 motor_data[2] = 0x02;//ʱ + 108 4 //ѭʼ--ʼ㡱һͣʼ + 109 4 mov_loop2();// + 110 4 } + 111 3 else//ʼ + 112 3 { + 113 4 motor_stop(); + 114 4 } + 115 3 } + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 3 + + 116 2 else if(Motor_Run == 2)//еʼλ + 117 2 { + 118 3 mov_begin();//صʼλ + 119 3 } + 120 2 else if(Motor_Run == 3)//еλ + 121 2 { + 122 3 mov_end();//ƶλ + 123 3 } + 124 2 else//ݴ + 125 2 SC_Init(); + 126 2 } + 127 1 else //г̡תһȦת4 + 128 1 { + 129 2 motor_data[0] = 0x01;//00 ֱг 01 г + 130 2 //жϵֹͣУеʼλǽλ + 131 2 if( Motor_Run == 0)//ֹͣ + 132 2 { + 133 3 motor_stop(); + 134 3 } + 135 2 else if(Motor_Run == 1)// + 136 2 { + 137 3 if(Motor_Run >= 1 && Runmotor_step == 0) + 138 3 { + 139 4 Runmotor_step = 1; + 140 4 } + 141 3 + 142 3 //жϵзʽǵ㶯㶯ΪһͷΪ + 143 3 if(Run_Mode == 0)//㶯 + 144 3 { + 145 4 motor_data[2] = 0x00;//ʱ + 146 4 mov_step_ang();//㶯 + 147 4 } + 148 3 else if(Run_Mode == 1)//һ + 149 3 { + 150 4 motor_data[2] = 0x01;//ʱ + 151 4 mov_loop1_ang();//תһȦ + 152 4 } + 153 3 else if(Run_Mode == 2)// + 154 3 { + 155 4 motor_data[2] = 0x02;//ʱ + 156 4 if(seat_flag == 0) + 157 4 { + 158 5 if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0) //жǷ񵽴λ + 159 5 { + 160 6 motor_stop(); //ֹͣ + 161 6 Run_mm = 0; + 162 6 seat_flag = 1;//λñ + 163 6 } + 164 5 else + 165 5 { + 166 6 REV(); //ת + 167 6 motor_start(); // + 168 6 motor_mov(1); //ṩź + 169 6 } + 170 5 } + 171 4 else + 172 4 { + 173 5 mov_loop2_ang();//תһȦ + 174 5 } + 175 4 } + 176 3 else//ʼ + 177 3 { + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 4 + + 178 4 motor_stop(); + 179 4 } + 180 3 } + 181 2 else if(Motor_Run == 2 || Motor_Run == 3)//еʼλ + 182 2 { + 183 3 mov_begin();//صʼλ + 184 3 } + 185 2 else//ݴ + 186 2 SC_Init(); + 187 2 } + 188 1 } + 189 + 190 + 191 /***************************************************** + 192 *: motor_mov + 193 *: ٶȿ + 194 *˵speed ٶ趨ֵ1Ϊ죬5Ϊ + 195 *****************************************************/ + 196 void motor_mov(unsigned int speed) + 197 { + 198 1 switch(speed)//Ƶٶȣ趨嵵ٶ + 199 1 { + 200 2 //2ms + 201 2 case 1: + 202 2 { + 203 3 if(it_1ms_flag) //1msʱ־ + 204 3 { + 205 4 it_1ms_flag = 0;//ʱ־ + 206 4 if(mov_flag) + 207 4 { + 208 5 mov_flag = 0; + 209 5 GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + 210 5 } + 211 4 else + 212 4 { + 213 5 mov_flag = 1; + 214 5 GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + 215 5 } + 216 4 Runmotor_Nums++; //д + 217 4 } + 218 3 } + 219 2 break; + 220 2 //4ms + 221 2 case 2: + 222 2 { + 223 3 if(it_2ms_flag)//2msʱ־ + 224 3 { + 225 4 it_2ms_flag = 0;//ʱ־ + 226 4 if(mov_flag) + 227 4 { + 228 5 mov_flag = 0; + 229 5 GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + 230 5 } + 231 4 else + 232 4 { + 233 5 mov_flag = 1; + 234 5 GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + 235 5 } + 236 4 Runmotor_Nums++; //д + 237 4 } + 238 3 } + 239 2 break; + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 5 + + 240 2 //6ms + 241 2 case 3: + 242 2 { + 243 3 if(it_3ms_flag)//3msʱ־ + 244 3 { + 245 4 it_3ms_flag = 0;//ʱ־ + 246 4 if(mov_flag) + 247 4 { + 248 5 mov_flag = 0; + 249 5 GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + 250 5 } + 251 4 else + 252 4 { + 253 5 mov_flag = 1; + 254 5 GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + 255 5 } + 256 4 Runmotor_Nums++; //д + 257 4 } + 258 3 } + 259 2 break; + 260 2 //8ms + 261 2 case 4: + 262 2 { + 263 3 if(it_4ms_flag)//4msʱ־ + 264 3 { + 265 4 it_4ms_flag = 0;//ʱ־ + 266 4 if(mov_flag) + 267 4 { + 268 5 mov_flag = 0; + 269 5 GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + 270 5 } + 271 4 else + 272 4 { + 273 5 mov_flag = 1; + 274 5 GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + 275 5 } + 276 4 Runmotor_Nums++; //д + 277 4 } + 278 3 } + 279 2 break; + 280 2 //10ms + 281 2 case 5: + 282 2 { + 283 3 if(it_5ms_flag)//5msʱ־ + 284 3 { + 285 4 it_5ms_flag = 0;//ʱ־ + 286 4 if(mov_flag) + 287 4 { + 288 5 mov_flag = 0; + 289 5 GPIO_WriteHigh(GPIO1,GPIO_PIN_7);//P1.7 + 290 5 } + 291 4 else + 292 4 { + 293 5 mov_flag = 1; + 294 5 GPIO_WriteLow(GPIO1,GPIO_PIN_7);//P1.7 + 295 5 } + 296 4 Runmotor_Nums++; //д + 297 4 } + 298 3 } + 299 2 break; + 300 2 default : + 301 2 break; + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 6 + + 302 2 } + 303 1 } + 304 + 305 + 306 + 307 //Уһֱг̣ + 308 void mov_loop1(void) + 309 { + 310 1 if(Run_Step == 0) return;//Ϊ0 + 311 1 + 312 1 switch(Runmotor_step) + 313 1 { + 314 2 case 1 : //׼ + 315 2 { + 316 3 + 317 3 FWD(); //ת + 318 3 motor_dire = 1; + 319 3 Run_mm = 0; + 320 3 Run_num = 0; + 321 3 motor_data[2] = 0x00; //ʱ + 322 3 Runmotor_Nums = 0; //д + 323 3 mov_flag = 0; + 324 3 Runmotor_step++; + 325 3 } + 326 2 break; + 327 2 case 2 : //й + 328 2 { + 329 3 if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 0) //դźж + 330 3 { + 331 4 if(it_1s_flag) //1msʱ־ + 332 4 { + 333 5 it_1s_flag = 0;//ʱ־ + 334 5 Runmotor_Nums++; + 335 5 } + 336 4 if(Runmotor_Nums >= Run_Stop)//ʱ + 337 4 { + 338 5 Runmotor_step++; + 339 5 motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + 340 5 motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + 341 5 motor_seat(); //ȡǰλ + 342 5 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 343 5 } + 344 4 } + 345 3 else + 346 3 { + 347 4 if(send_flag == 0) + 348 4 { + 349 5 send_flag = 1; + 350 5 motor_seat();//ȡǰλ + 351 5 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 352 5 } + 353 4 motor_start(); // + 354 4 motor_mov(1); //1 + 355 4 Run_mm = 1; //ƶ0 + 356 4 Runmotor_Nums = 0; // + 357 4 Runmotor_step = 6; + 358 4 } + 359 3 } + 360 2 break; + 361 2 case 3 : //ʱ + 362 2 { + 363 3 if(motor_dire == 1) + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 7 + + 364 3 { + 365 4 motor_start(); // + 366 4 motor_mov(1); //1 + 367 4 if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + 368 4 { + 369 5 Runmotor_Nums = 0; // + 370 5 motor_stop(); //ֹͣ + 371 5 motor_data[1] = 0x01; //Ӧ01 + 372 5 motor_data[3] = 0x03; //򡪡ʼ + 373 5 Run_mm++; //ƶ1 + 374 5 ct_num = Run_mm; // + 375 5 motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + 376 5 motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + 377 5 Runmotor_step++; + 378 5 } + 379 4 } + 380 3 else + 381 3 { + 382 4 motor_start(); // + 383 4 motor_mov(1); //1 + 384 4 if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + 385 4 { + 386 5 Runmotor_Nums = 0; // + 387 5 motor_stop(); //ֹͣ + 388 5 motor_data[1] = 0x01; //Ӧ01 + 389 5 motor_data[3] = 0x04; //򡪡ʼ + 390 5 ct_num = ct_num - 1; // + 391 5 Run_mm = ct_num; //ƶ1 + 392 5 motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + 393 5 motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + 394 5 Runmotor_step++; + 395 5 } + 396 4 } + 397 3 } + 398 2 break; + 399 2 case 4 : //ʱ + 400 2 { + 401 3 if(it_1ms_flag) //1msʱ־ + 402 3 { + 403 4 it_1ms_flag = 0;//ʱ־ + 404 4 Runmotor_Nums++; + 405 4 } + 406 3 if(Runmotor_Nums >= Run_Inter)//ʱ + 407 3 { + 408 4 + 409 4 Runmotor_Nums = 0; + 410 4 Runmotor_step++; + 411 4 send_flag = 0; + 412 4 //motor_seat(); //ȡǰλ + 413 4 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 414 4 } + 415 3 + 416 3 } + 417 2 break; + 418 2 case 5 : + 419 2 { + 420 3 if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 1 )//դźж + 421 3 { + 422 4 if(flag == 0) + 423 4 { + 424 5 Runmotor_Nums = 0; + 425 5 Runmotor_step = 3; + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 8 + + 426 5 if(motor_dire == 1) + 427 5 { + 428 6 REV(); + 429 6 flag = 1; + 430 6 motor_dire = 0; + 431 6 } + 432 5 else + 433 5 { + 434 6 Motor_Run = 2; //бǸı䣬صʼλ + 435 6 } + 436 5 } + 437 4 else + 438 4 { + 439 5 Runmotor_step = 3; + 440 5 } + 441 4 } + 442 3 else + 443 3 { + 444 4 Runmotor_step = 3; + 445 4 flag = 0 ; + 446 4 } + 447 3 } + 448 2 break; + 449 2 case 6 : + 450 2 { + 451 3 if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0)//ʼλ + 452 3 { + 453 4 FWD();//ת + 454 4 motor_dire = 1;//ת + 455 4 } + 456 3 if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//λ + 457 3 { + 458 4 REV();//ת + 459 4 motor_dire = 0;//ת + 460 4 } + 461 3 Runmotor_step = 2; + 462 3 } + 463 2 break; + 464 2 default : + 465 2 { + 466 3 + 467 3 } + 468 2 break; + 469 2 } + 470 1 } + 471 + 472 //Уһг̣ + 473 void mov_loop1_ang(void) + 474 { + 475 1 if(Run_Step == 0) return;//Ϊ0 + 476 1 + 477 1 switch(Runmotor_step) + 478 1 { + 479 2 case 1 : //׼ + 480 2 { + 481 3 FWD();//ת + 482 3 motor_dire = 1; + 483 3 motor_data[2] = 0x00;//ʱ + 484 3 Runmotor_Nums = 0; //д + 485 3 mov_flag = 0; + 486 3 Run_mm = 0; + 487 3 Run_num = 0; + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 9 + + 488 3 Runmotor_step++; + 489 3 } + 490 2 break; + 491 2 case 2 : //й + 492 2 { + 493 3 if(motor_dire == 1) + 494 3 { + 495 4 FWD();//ת + 496 4 motor_start(); // + 497 4 motor_mov(1); //1 + 498 4 if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + 499 4 { + 500 5 Runmotor_Nums = 0; // + 501 5 motor_stop(); //ֹͣ + 502 5 motor_data[1] = 0x01; //Ӧ01 + 503 5 motor_data[3] = 0x03; //򡪡ʼ + 504 5 Run_mm++; //ƶ1 + 505 5 Run_num = Run_mm * Run_Step; + 506 5 motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + 507 5 motor_data[9] = Run_num & 0x00ff; //ȵ8λ + 508 5 Runmotor_step++; + 509 5 } + 510 4 } + 511 3 else + 512 3 { + 513 4 REV();//ת + 514 4 motor_start(); // + 515 4 motor_mov(1); //1 + 516 4 if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + 517 4 { + 518 5 Runmotor_Nums = 0; // + 519 5 motor_stop(); //ֹͣ + 520 5 motor_data[1] = 0x01; //Ӧ01 + 521 5 motor_data[3] = 0x04; //򡪡ʼ + 522 5 Run_mm--; //ƶ1 + 523 5 Run_num = Run_mm * Run_Step; + 524 5 motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + 525 5 motor_data[9] = Run_num & 0x00ff; //ȵ8λ + 526 5 Runmotor_step++; + 527 5 } + 528 4 } + 529 3 } + 530 2 break; + 531 2 case 3 : //ʱ + 532 2 { + 533 3 if(it_1ms_flag) //1msʱ־ + 534 3 { + 535 4 it_1ms_flag = 0;//ʱ־ + 536 4 Runmotor_Nums++; + 537 4 } + 538 3 if(Runmotor_Nums >= Run_Inter)//ʱ + 539 3 { + 540 4 Runmotor_Nums = 0; + 541 4 Runmotor_step++; + 542 4 //motor_seat(); //ȡǰλ + 543 4 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 544 4 } + 545 3 } + 546 2 break; + 547 2 case 4 : + 548 2 { + 549 3 if(Run_num >= Run_Stop * 10&& motor_dire == 1)//жϴǷת趨ĽǶ + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 10 + + 550 3 { + 551 4 motor_dire = 0; + 552 4 Runmotor_step = 2; + 553 4 } + 554 3 else if(Run_num <= 0 && motor_dire == 0) + 555 3 { + 556 4 //motor_dire = 1; + 557 4 Motor_Run = 1; + 558 4 } + 559 3 else + 560 3 { + 561 4 Runmotor_step = 2; + 562 4 } + 563 3 } + 564 2 break; + 565 2 default : + 566 2 { + 567 3 + 568 3 } + 569 2 break; + 570 2 } + 571 1 } + 572 + 573 + 574 //Уֱг̣ + 575 void mov_loop2(void) + 576 { + 577 1 if(Run_Step == 0) return;//Ϊ0 + 578 1 + 579 1 switch(Runmotor_step) + 580 1 { + 581 2 case 1 : //׼ + 582 2 { + 583 3 + 584 3 FWD();//ת + 585 3 motor_dire = 1; + 586 3 motor_data[2] = 0x00;//ʱ + 587 3 Runmotor_Nums = 0; //д + 588 3 mov_flag = 0; // + 589 3 Runmotor_step++; + 590 3 } + 591 2 break; + 592 2 case 2 : //й + 593 2 { + 594 3 if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 0)//դźж + 595 3 { + 596 4 + 597 4 if(it_1s_flag) //1msʱ־ + 598 4 { + 599 5 it_1s_flag = 0;//ʱ־ + 600 5 Runmotor_Nums++; + 601 5 } + 602 4 if(Runmotor_Nums >= Run_Stop)//ʱ + 603 4 { + 604 5 Runmotor_step++; + 605 5 motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + 606 5 motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + 607 5 motor_seat(); //ȡǰλ + 608 5 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 609 5 }//Run_mm = 1; //ƶ1 + 610 4 + 611 4 } + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 11 + + 612 3 else + 613 3 { + 614 4 if(send_flag == 0) + 615 4 { + 616 5 send_flag = 1; + 617 5 motor_seat();//ȡǰλ + 618 5 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 619 5 } + 620 4 motor_start(); // + 621 4 motor_mov(1); //1 + 622 4 Run_mm = 1; //ƶ0 + 623 4 Runmotor_Nums = 0; // + 624 4 Runmotor_step = 6; + 625 4 } + 626 3 } + 627 2 break; + 628 2 case 3 : //ʱ + 629 2 { + 630 3 if(motor_dire == 1) + 631 3 { + 632 4 motor_start(); // + 633 4 motor_mov(1); //1 + 634 4 if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + 635 4 { + 636 5 Runmotor_Nums = 0; // + 637 5 motor_stop(); //ֹͣ + 638 5 motor_data[1] = 0x01; //Ӧ01 + 639 5 motor_data[3] = 0x03; //򡪡ʼ + 640 5 Run_mm++; //ƶ1 + 641 5 ct_num = Run_mm; // + 642 5 motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + 643 5 motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + 644 5 Runmotor_step++; + 645 5 } + 646 4 } + 647 3 else + 648 3 { + 649 4 motor_start(); // + 650 4 motor_mov(1); //1 + 651 4 if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + 652 4 { + 653 5 Runmotor_Nums = 0; // + 654 5 motor_stop(); //ֹͣ + 655 5 motor_data[1] = 0x01; //Ӧ01 + 656 5 motor_data[3] = 0x04; //򡪡ʼ + 657 5 ct_num = ct_num - 1; // + 658 5 Run_mm = ct_num; //ƶ1 + 659 5 motor_data[8] = ((Run_mm * Run_Step) & 0xff00) >> 8;//ȸ8λ + 660 5 motor_data[9] = (Run_mm * Run_Step) & 0x00ff; //ȵ8λ + 661 5 Runmotor_step++; + 662 5 } + 663 4 } + 664 3 } + 665 2 break; + 666 2 case 4 : //ʱ + 667 2 { + 668 3 if(it_1ms_flag) //1msʱ־ + 669 3 { + 670 4 it_1ms_flag = 0;//ʱ־ + 671 4 Runmotor_Nums++; + 672 4 } + 673 3 if(Runmotor_Nums >= Run_Inter)//ʱ + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 12 + + 674 3 { + 675 4 + 676 4 Runmotor_Nums = 0; + 677 4 Runmotor_step++; + 678 4 send_flag = 0; + 679 4 //motor_seat(); //ȡǰλ + 680 4 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 681 4 } + 682 3 + 683 3 } + 684 2 break; + 685 2 case 5 : + 686 2 { + 687 3 if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 1 )//դźж + 688 3 { + 689 4 if(flag == 0) + 690 4 { + 691 5 Runmotor_Nums = 0; + 692 5 Runmotor_step = 3; + 693 5 if(motor_dire == 1) + 694 5 { + 695 6 REV(); + 696 6 flag = 1; + 697 6 motor_dire = 0; + 698 6 } + 699 5 else + 700 5 { + 701 6 FWD(); + 702 6 flag = 1; + 703 6 motor_dire = 1; + 704 6 } + 705 5 } + 706 4 else + 707 4 { + 708 5 Runmotor_step = 3; + 709 5 } + 710 4 } + 711 3 else + 712 3 { + 713 4 Runmotor_step = 3; + 714 4 flag = 0 ; + 715 4 } + 716 3 } + 717 2 break; + 718 2 case 6 : + 719 2 { + 720 3 if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0)//ʼλ + 721 3 { + 722 4 FWD();//ת + 723 4 motor_dire = 1;//ת + 724 4 } + 725 3 if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//λ + 726 3 { + 727 4 REV();//ת + 728 4 motor_dire = 0;//ת + 729 4 } + 730 3 Runmotor_step = 2; + 731 3 } + 732 2 break; + 733 2 + 734 2 default : + 735 2 { + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 13 + + 736 3 + 737 3 } + 738 2 break; + 739 2 } + 740 1 } + 741 + 742 //Уг̣ + 743 void mov_loop2_ang(void) + 744 { + 745 1 if(Run_Step == 0) return;//Ϊ0 + 746 1 + 747 1 switch(Runmotor_step) + 748 1 { + 749 2 case 1 : //׼ + 750 2 { + 751 3 FWD();//ת + 752 3 motor_dire = 1; + 753 3 motor_data[2] = 0x00;//ʱ + 754 3 Runmotor_Nums = 0; //д + 755 3 mov_flag = 0; + 756 3 Runmotor_step++; + 757 3 } + 758 2 break; + 759 2 case 2 : //й + 760 2 { + 761 3 if(motor_dire == 1) + 762 3 { + 763 4 FWD();//ת + 764 4 motor_start(); // + 765 4 motor_mov(1); //1 + 766 4 if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + 767 4 { + 768 5 Runmotor_Nums = 0; // + 769 5 motor_stop(); //ֹͣ + 770 5 motor_data[1] = 0x01; //Ӧ01 + 771 5 motor_data[3] = 0x03; //򡪡ʼ + 772 5 Run_mm++; //ƶ1 + 773 5 Run_num = Run_mm * Run_Step; + 774 5 motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + 775 5 motor_data[9] = Run_num & 0x00ff; //ȵ8λ + 776 5 Runmotor_step++; + 777 5 } + 778 4 } + 779 3 else + 780 3 { + 781 4 REV();//ת + 782 4 motor_start(); // + 783 4 motor_mov(1); //1 + 784 4 if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + 785 4 { + 786 5 Runmotor_Nums = 0; // + 787 5 motor_stop(); //ֹͣ + 788 5 motor_data[1] = 0x01; //Ӧ01 + 789 5 motor_data[3] = 0x04; //򡪡ʼ + 790 5 Run_mm--; //ƶ1 + 791 5 Run_num = Run_mm * Run_Step; + 792 5 motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + 793 5 motor_data[9] = Run_num & 0x00ff; //ȵ8λ + 794 5 Runmotor_step++; + 795 5 } + 796 4 } + 797 3 } + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 14 + + 798 2 break; + 799 2 case 3 : //ʱ + 800 2 { + 801 3 if(it_1ms_flag) //1msʱ־ + 802 3 { + 803 4 it_1ms_flag = 0;//ʱ־ + 804 4 Runmotor_Nums++; + 805 4 } + 806 3 if(Runmotor_Nums >= Run_Inter)//ʱ + 807 3 { + 808 4 Runmotor_Nums = 0; + 809 4 Runmotor_step++; + 810 4 //motor_seat(); //ȡǰλ + 811 4 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 812 4 } + 813 3 } + 814 2 break; + 815 2 case 4 : + 816 2 { + 817 3 if(Run_num >= Run_Stop * 10)//жϴǷת趨ĽǶ + 818 3 { + 819 4 motor_dire = 0; + 820 4 Runmotor_step = 2; + 821 4 } + 822 3 else if(Run_num <= 0) + 823 3 { + 824 4 motor_dire = 1; + 825 4 Runmotor_step = 2; + 826 4 } + 827 3 else + 828 3 { + 829 4 Runmotor_step = 2; + 830 4 } + 831 3 } + 832 2 break; + 833 2 default : + 834 2 { + 835 3 + 836 3 } + 837 2 break; + 838 2 } + 839 1 } + 840 + 841 //㶯Уֱг̣ + 842 void mov_step(void) + 843 { + 844 1 if(Run_Step == 0) return;//Ϊ0 + 845 1 + 846 1 switch(Runmotor_step) + 847 1 { + 848 2 case 1 : //׼ + 849 2 { + 850 3 motor_start(); // + 851 3 if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0)//жǷ񵽴ʼλ + 852 3 FWD(); //ת + 853 3 if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//жǷ񵽴λ + 854 3 REV(); //ת + 855 3 Runmotor_Nums = 0; //д + 856 3 mov_flag = 0; + 857 3 Runmotor_step++; + 858 3 } + 859 2 break; + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 15 + + 860 2 case 2 : //й + 861 2 { + 862 3 motor_mov(1);//1 + 863 3 if(Runmotor_Nums >= (Run_Step * STEP_LIN))//һϸ + 864 3 { + 865 4 Runmotor_Nums = 0; + 866 4 motor_stop(); //ֹͣ + 867 4 Runmotor_step++; + 868 4 Run_mm++; //ƶ1 + 869 4 Run_num = Run_mm * Run_Step; + 870 4 motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + 871 4 motor_data[9] = Run_num & 0x00ff; //ȵ8λ + 872 4 // motor_seat(); //ȡǰλ + 873 4 // send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 874 4 } + 875 3 } + 876 2 break; + 877 2 case 3 : + 878 2 { + 879 3 if(it_1ms_flag) //1msʱ־ + 880 3 { + 881 4 it_1ms_flag = 0;//ʱ־ + 882 4 Runmotor_Nums++; + 883 4 } + 884 3 if(Runmotor_Nums >= 50)//ʱ + 885 3 { + 886 4 Runmotor_Nums = 0; + 887 4 Runmotor_step++; + 888 4 motor_seat(); //ȡǰλ + 889 4 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 890 4 } + 891 3 } + 892 2 break; + 893 2 case 4 : + 894 2 { + 895 3 Runmotor_step = 0; + 896 3 Motor_Run = 0; //б + 897 3 } + 898 2 break; + 899 2 default : + 900 2 { + 901 3 + 902 3 } + 903 2 break; + 904 2 } + 905 1 } + 906 + 907 //㶯Уг̣ + 908 void mov_step_ang(void) + 909 { + 910 1 if(Run_Step == 0) return;//Ϊ0 + 911 1 + 912 1 switch(Runmotor_step) + 913 1 { + 914 2 case 1 : //׼ + 915 2 { + 916 3 motor_start(); // + 917 3 FWD(); //ת + 918 3 Runmotor_Nums = 0; //д + 919 3 mov_flag = 0; + 920 3 Runmotor_step++; + 921 3 } + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 16 + + 922 2 break; + 923 2 case 2 : //й + 924 2 { + 925 3 motor_mov(1);//1 + 926 3 if(Runmotor_Nums >= (Run_Step * STEP_ROT))//һϸ + 927 3 { + 928 4 Runmotor_Nums = 0; + 929 4 motor_stop(); //ֹͣ + 930 4 Run_mm++; //ƶ1 + 931 4 Run_num = Run_mm * Run_Step; + 932 4 motor_data[8] = (Run_num & 0xff00) >> 8;//ȸ8λ + 933 4 motor_data[9] = Run_num & 0x00ff; //ȵ8λ + 934 4 motor_seat(); //ȡǰλ + 935 4 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 936 4 Runmotor_step++; + 937 4 } + 938 3 } + 939 2 break; + 940 2 case 3 : + 941 2 { + 942 3 Runmotor_step = 0; + 943 3 Motor_Run = 0; //б + 944 3 if(Run_num >= 3600) //жϴǷתһȦ + 945 3 Run_mm = 0; + 946 3 } + 947 2 break; + 948 2 default : + 949 2 { + 950 3 + 951 3 } + 952 2 break; + 953 2 } + 954 1 } + 955 + 956 //صʼλ + 957 void mov_begin(void) + 958 { + 959 1 motor_data[1] = 0x02; //еʼλӦ02 + 960 1 motor_data[8] = 0x00; //ȸ8λ + 961 1 motor_data[9] = 0x00; //ȵ8λ + 962 1 REV(); //ת + 963 1 motor_start(); // + 964 1 if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0) //жǷ񵽴λ + 965 1 { + 966 2 motor_stop(); //ֹͣ + 967 2 Run_mm = 0; + 968 2 Run_num = 0; + 969 2 if(send_flag == 1) + 970 2 { + 971 3 send_flag = 0; + 972 3 motor_seat(); //ȡǰλ + 973 3 send_set_resp(0xF001, OBJ_DEVICE_ADDR, DATA_LEN, motor_data);//ݷ + 974 3 } + 975 2 } + 976 1 else + 977 1 motor_mov(1); //ṩ + 978 1 } + 979 + 980 //صλ + 981 void mov_end(void) + 982 { + 983 1 motor_data[1] = 0x03; //еλӦ03 + C51 COMPILER V9.59.0.0 MOTOR 01/18/2024 10:03:10 PAGE 17 + + 984 1 FWD(); //ת + 985 1 motor_start(); // + 986 1 //Run_mm = 0; + 987 1 if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//жǷ񵽴λ + 988 1 motor_stop(); //ֹͣ + 989 1 else + 990 1 motor_mov(1); //ṩ + 991 1 } + 992 + 993 //λж + 994 void motor_seat(void) + 995 { + 996 1 if(GPIO_ReadPin(GPIO1,GPIO_PIN_4) == 0) //ʼλش + 997 1 motor_data[3] = 0x01; //ʱ + 998 1 else if(GPIO_ReadPin(GPIO1,GPIO_PIN_5) == 0)//ڽλش + 999 1 motor_data[3] = 0x02; //ʱ +1000 1 else if(GPIO_ReadPin(GPIO0,GPIO_PIN_5) == 0)//ͨդ +1001 1 motor_data[3] = 0x03; //ʱ +1002 1 else //״̬ +1003 1 motor_data[3] = 0x00; //ʱ +1004 1 } + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 3818 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = 17 ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = 6 ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/sc92f_adc.lst b/Keil_C/List/sc92f_adc.lst new file mode 100644 index 0000000..506218d --- /dev/null +++ b/Keil_C/List/sc92f_adc.lst @@ -0,0 +1,535 @@ +C51 COMPILER V9.59.0.0 SC92F_ADC 01/18/2024 10:03:13 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE SC92F_ADC +OBJECT MODULE PLACED IN ..\Output\sc92f_adc.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_adc.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) + - BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\sc92f_adc. + -lst) OBJECT(..\Output\sc92f_adc.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ: sc92f_adc.c + 4 // : ԪӦŶ + 5 // ģ鹦: ADC̼⺯Cļ + 6 // : 2022323 + 7 // 汾: V1.10005 + 8 // ˵: + 9 //************************************************************* + 10 + 11 /* ͷļ */ + 12 #include "sc92f_adc.h" + 13 + 14 #if !defined(SC92F827X) && !defined(SC92F837X) + 15 /************************************************** + 16 *:void ADC_DeInit(void) + 17 *:ADCؼĴλȱʡֵ + 18 *ڲ:void + 19 *ڲ:void + 20 **************************************************/ + 21 void ADC_DeInit(void) + 22 { + 23 1 ADCCON = 0x00; + 24 1 ADCCFG0 = 0X00; + 25 1 ADCCFG1 = 0X00; + 26 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 27 1 || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC + -92F84Ax) || defined(SC92F74Ax)\ + 28 1 || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F848x) || defined(SC92F748x) || defined (SC92F + -859x) || defined (SC92F759x)\ + 29 1 || defined (SC92L853x) || defined (SC92L753x) + 30 1 ADCCFG2 = 0X00; + 31 1 #endif + 32 1 ADCVL = 0X00; + 33 1 ADCVH = 0X00; + 34 1 EADC = 0; + 35 1 IPADC = 0; + 36 1 } + 37 + 38 /************************************************** + 39 *:void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, ADC_Cycle_TypeDef ADC_Cycle) + 40 *:ADCʼú + 41 *ڲ: + 42 ADC_PresSel_TypeDef:ADC_PrescalerSelection:ԤƵѡ + 43 ADC_Cycle_TypeDef:ADC_Cycle:ʱѡ + 44 *ڲ:void + 45 **************************************************/ + 46 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 47 || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(SC + -92F84Ax) || defined(SC92F74Ax)\ + 48 || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92FWxx) || defined(SC92F848x) || defined(SC92F74 + C51 COMPILER V9.59.0.0 SC92F_ADC 01/18/2024 10:03:13 PAGE 2 + + -8x)\ + 49 || defined (SC92F859x) || defined (SC92F759x) + 50 void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, + 51 ADC_Cycle_TypeDef ADC_Cycle) + 52 { + 53 1 /* ADCʱӷƵͲ */ + 54 1 ADCCFG2 = ADC_PrescalerSelection | ADC_Cycle; + 55 1 } + 56 #elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) + void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, + ADC_Cycle_TypeDef ADC_Cycle) + { + /* ADCʱӷƵͲ */ + ADCCFG1 = ADC_PrescalerSelection | ADC_Cycle; + } + #elif defined(SC92F742x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F730x) || defined(SC92 + -F732X) || defined(SC92F7490)\ + || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) + void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, + ADC_Cycle_TypeDef ADC_Cycle) + { + ADC_Cycle = 0; //SC92F742x޴˹ + /* ADCʱӷƵ */ + ADCCON = (ADCCON & 0xDF) | ADC_PrescalerSelection; + } + #elif defined (SC92L853x) || defined (SC92L753x) + void ADC_Init(ADC_PresSel_TypeDef ADC_PrescalerSelection, ADC_Cycle_TypeDef ADC_Cycle) + { + ADC_Cycle = 0x00; //92LϵЧ + /* ADCʱӷƵ */ + ADCCFG2 = ADC_PrescalerSelection; + } + #endif + 80 + 81 /************************************************** + 82 *:void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) + 83 *:ADCúʹع + 84 *ڲ: + 85 ADC_Channel_TypeDef:ADC_Channel:ADCѡ + 86 FunctionalState:NewState:ADCxʹ/رѡ + 87 *ڲ:void + 88 **************************************************/ + 89 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 90 || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(S + -C92F84Ax) || defined(SC92F74Ax)\ + 91 || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92FWxx) || defined(SC92F848x) || defined(SC92F7 + -48x)\ + 92 || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + 93 void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) + 94 { + 95 1 uint16_t TempReg; + 96 1 /* ADCתͨ */ + 97 1 ADCCON = (ADCCON & 0XE0) | ADC_Channel; + 98 1 + 99 1 /* ADCⲿͨ */ + 100 1 if (ADC_Channel < ADC_CHANNEL_VDD_D4) //ڲͨ + 101 1 { + 102 2 TempReg = (0x0001 << ADC_Channel); + 103 2 if (NewState == DISABLE)// ʹADCͨ + 104 2 { + 105 3 ADCCFG0 &= (~(uint8_t)TempReg); + C51 COMPILER V9.59.0.0 SC92F_ADC 01/18/2024 10:03:13 PAGE 3 + + 106 3 ADCCFG1 &= (~(uint8_t)(TempReg >> 8)); + 107 3 } + 108 2 else // ʧADCͨ + 109 2 { + 110 3 ADCCFG0 |= ((uint8_t)TempReg); + 111 3 ADCCFG1 |= ((uint8_t)(TempReg >> 8)); + 112 3 } + 113 2 } + 114 1 } + 115 #elif defined(SC92F7003) || defined(SC92F8003) || defined(SC92F740x) || defined(SC92F7490) + void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) + { + uint8_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0xE0) | ADC_Channel; + + /* ADCͨ */ + if (ADC_Channel < ADC_CHANNEL_VDD_D4) //ڲͨ + { + TempReg = (0x01 << ADC_Channel); + if (ADC_Channel < ADC_CHANNEL_VDD_D4) + { + if (NewState == DISABLE) //ʧADCͨ + { + ADCCFG0 &= (~TempReg); + } + else //ʹADCͨ + { + ADCCFG0 |= TempReg; + } + } + } + } + #elif defined(SC92F742x) || defined(SC92F730x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92 + -F732X) + void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) + { + uint16_t TempReg; + /* ADCתͨ */ + ADCCON = (ADCCON & 0xF0) | ADC_Channel; + + /* ADCͨ */ + if (ADC_Channel < ADC_CHANNEL_VDD_D4) //ڲͨ + { + TempReg = (0x0001 << ADC_Channel); + if (NewState == DISABLE) + { + ADCCFG0 &= (~(uint8_t)TempReg); + ADCCFG1 &= (~(uint8_t)(TempReg >> 8)); + } + else + { + ADCCFG0 |= ((uint8_t)TempReg); + ADCCFG1 |= ((uint8_t)(TempReg >> 8)); + } + } + } + #elif defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) + void ADC_ChannelConfig(ADC_Channel_TypeDef ADC_Channel, FunctionalState NewState) + { + uint16_t TempReg; + /* ADCתͨ */ + C51 COMPILER V9.59.0.0 SC92F_ADC 01/18/2024 10:03:13 PAGE 4 + + ADCCON = (ADCCON & 0xF0) | ADC_Channel; + + /* ADCͨ */ + if (ADC_Channel < ADC_CHANNEL_Temp) //ⲿͨ + { + TempReg = (0x0001 << ADC_Channel); + if (NewState == DISABLE) + { + ADCCFG0 &= (~(uint8_t)TempReg); + ADCCFG1 &= (~(uint8_t)(TempReg >> 8)); + } + else + { + ADCCFG0 |= ((uint8_t)TempReg); + ADCCFG1 |= ((uint8_t)(TempReg >> 8)); + } + } + else if (ADC_Channel == ADC_CHANNEL_Temp) //ڲ¶Ȳͨ + { + if (NewState == DISABLE) + { + TSCFG &= 0X7F; + } + else + { + /* ADCοѹѡڲ2.4VΪο */ + OPINX = 0xC2; + OPREG = OPREG & 0X7F | 0x80; + + TSCFG |= 0x80; + } + } + else if (ADC_Channel == ADC_CHANNEL_9_PGA) //ɱŴͨ + { + unsigned char code *IFBAddr = 0x3D; + if (NewState == DISABLE) + { + ADCCFG1 &= (~(uint8_t)0x02); //رͨ9 + PGACON &= 0x7F; //ʹPGA + } + /* ȡPGAڲУ׼ֵ */ + else + { + ADCCFG1 |= ((uint8_t)0x02); //PGAͨͨ9ãʹͨ9 + + IAPADE = 0x01; //ָָ IFB + PGACFG = *(IFBAddr); //ȡУ׼ֵ + IAPADE = 0x00; //ָָ ROM + + PGACON |= 0x80; //ʹPGA + } + } + } + #endif + 221 + 222 /************************************************** + 223 *:void ADC_EAINConfig(uint16_t ADC_Channel, FunctionalState NewState) + 224 *:ӦADCΪģģʽ + 225 *ڲ: + 226 ADC_EAIN_TypeDef:ADC_EAIN_Select:ѡҪõADC + 227 FunctionalState:NewState:ADCͨʹ/رѡ + 228 *ڲ:void + C51 COMPILER V9.59.0.0 SC92F_ADC 01/18/2024 10:03:13 PAGE 5 + + 229 **************************************************/ + 230 void ADC_EAINConfig(uint16_t ADC_EAIN_Select, + 231 FunctionalState NewState) + 232 { + 233 1 if (NewState == DISABLE) + 234 1 { + 235 2 ADCCFG0 &= (~(uint8_t)ADC_EAIN_Select); + 236 2 #if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB) || defined + - (SC92F84Ax_2) || defined (SC92F74Ax_2)\ + 237 2 || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)||defined + - (SC92F84Ax) || defined (SC92F74Ax)\ + 238 2 || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F848x) || defined(SC92F748x) || defined(SC92F + -859x) || defined (SC92F759x)\ + 239 2 || defined (SC92L853x) || defined (SC92L753x) + 240 2 ADCCFG1 &= (~(uint8_t)(ADC_EAIN_Select >> 8)); + 241 2 #endif + 242 2 } + 243 1 else + 244 1 { + 245 2 ADCCFG0 |= ((uint8_t)ADC_EAIN_Select); + 246 2 #if defined (SC92F854x) || defined (SC92F754x) || defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)\ + 247 2 || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defin + -ed (SC92F84Ax) || defined (SC92F74Ax)\ + 248 2 || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F848x) || defined(SC92F748x) || defined(SC92F + -859x) || defined (SC92F759x)\ + 249 2 || defined (SC92L853x) || defined (SC92L753x) + 250 2 ADCCFG1 |= ((uint8_t)(ADC_EAIN_Select >> 8)); + 251 2 #endif + 252 2 } + 253 1 } + 254 /***************************************************** + 255 *:void ADC_Cmd(FunctionalState NewState) + 256 *:ADCܿغ + 257 *ڲ: + 258 FunctionalState:NewState:/رѡ + 259 *ڲ:void + 260 *****************************************************/ + 261 void ADC_Cmd(FunctionalState NewState) + 262 { + 263 1 if (NewState == DISABLE) + 264 1 { + 265 2 ADCCON &= 0X7F; + 266 2 } + 267 1 else + 268 1 { + 269 2 ADCCON |= 0x80; + 270 2 } + 271 1 } + 272 + 273 /***************************************************** + 274 *:uint16_t ADC_GetConversionValue(void) + 275 *:һADת + 276 *ڲ:void + 277 *ڲ:uint16_t + 278 *****************************************************/ + 279 unsigned int ADC_GetConversionValue(void) + 280 { + 281 1 return ((ADCVH << 4) + (ADCVL >> 4)); + 282 1 } + 283 + 284 /***************************************************** + C51 COMPILER V9.59.0.0 SC92F_ADC 01/18/2024 10:03:13 PAGE 6 + + 285 *:FlagStatus ADC_GetFlagStatus(void) + 286 *:ADCжϱ־״̬ + 287 *ڲ:void + 288 *ڲ: + 289 FlagStatus:ADCжϱ־״̬ + 290 *****************************************************/ + 291 FlagStatus ADC_GetFlagStatus(void) + 292 { + 293 1 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)\ + 294 1 || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)||defined + - (SC92F84Ax) || defined (SC92F74Ax)\ + 295 1 || defined (SC92F83Ax) || defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F8003) || defined + -(SC92F740x) || defined (SC92FWxx)\ + 296 1 || defined(SC92F848x) || defined(SC92F748x) || defined(SC92F859x) || defined (SC92F759x) || defined (SC92 + -L853x) || defined (SC92L753x) + 297 1 return (bool)(ADCCON & 0x20); + 298 1 #elif defined(SC92F742x) || defined(SC92F730x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92 + -F732X) || defined(SC92F7490) || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) + return (bool)(ADCCON & 0x10); + #endif + 301 1 } + 302 + 303 /***************************************************** + 304 *:void ADC_ClearFlag(void) + 305 *:ADCжϱ־״̬ + 306 *ڲ:void + 307 *ڲ:void + 308 *****************************************************/ + 309 void ADC_ClearFlag(void) + 310 { + 311 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 312 1 || defined(SC92F846xB) || defined(SC92F746xB) || defined(SC92F836xB) || defined(SC92F736xB) || defined(S + -C92F84Ax) || defined(SC92F74Ax)\ + 313 1 || defined(SC92F83Ax) || defined(SC92F73Ax) || defined(SC92F8003) || defined(SC92F740x) || defined(SC92F + -848x) || defined(SC92F748x)\ + 314 1 || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92L753x) + 315 1 ADCCON &= 0xdf; + 316 1 #endif + 317 1 #if defined(SC92F742x) || defined(SC92F730x) || defined(SC92F725X) || defined(SC92F735X) || defined(SC92F7 + -32X) || defined(SC92F7490) || defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) + ADCCON &= 0xef; + #endif + 320 1 } + 321 + 322 #if defined(SC93F833x) || defined(SC93F843x) || defined(SC93F743x) + unsigned int ADC_TS_StandardData = 0x8000; + + /***************************************************** + *:void ADC_TSCmd(PriorityStatus NewState) + *:ADC ¶ȴܿغ + *ڲ: + FunctionalState:NewState:/رѡ + *ڲ:void + *****************************************************/ + void ADC_TSCmd(FunctionalState NewState) + { + if (NewState == DISABLE) + { + TSCFG &= 0X7F; + } + C51 COMPILER V9.59.0.0 SC92F_ADC 01/18/2024 10:03:13 PAGE 7 + + else + { + TSCFG |= 0X80; + } + } + + /***************************************************** + *:void ADC_CHOPConfig(PriorityStatus NewState) + *:߻͵offsetӦÿλ + *ڲ: + PriorityStatus:NewState:¶ȴ/ѡ + *ڲ:void + *****************************************************/ + void ADC_CHOPConfig(PriorityStatus NewState) + { + if (NewState == LOW) + { + TSCFG &= 0XFE; + } + else + { + TSCFG |= 0x01; + } + } + + /***************************************************** + *:void ADC_CHOPConfig(PriorityStatus NewState) + *:ȡʱADC 25ʱתֵ + *ڲ:void + *ڲ:void + *****************************************************/ + uint16_t ADC_Get_TS_StandardData(void) + { + unsigned int code *IFBAddr = 0x3E; + IAPADE = 0x01; //ָָ IFB + ADC_TS_StandardData = *(IFBAddr); + IAPADE = 0x00; //ָָ ROM + return ADC_TS_StandardData; + } + + /***************************************************** + *:void ADC_GetTSValue(void) + *:ֱӻȡfloat¶ֵȡ¶ʱرж + *ڲ:void + *ڲ: + float:¶ֵ + *****************************************************/ + float ADC_GetTSValue(void) + { + unsigned char EADC_Flag = EADC; //ȡEA־λ״̬ + unsigned int ADC_Value1 = 0, ADC_Value2 = 0, ADC_Value = 0; + unsigned int code *IFBAddr = 0x3E; + + ADC_Get_TS_StandardData(); + disableInterrupts(); //رж + ADC_CHOPConfig(LOW); //͵offsetӦÿλ + ADC_StartConversion(); //ʼADת + while(!ADC_GetFlagStatus()); //ȴת + ADC_ClearFlag(); //ת־λ + ADC_Value1 = ADC_GetConversionValue(); //ȡһADתֵ + ADC_CHOPConfig(HIGH); //ߵoffsetӦÿλ + ADC_StartConversion(); //ʼADת + C51 COMPILER V9.59.0.0 SC92F_ADC 01/18/2024 10:03:13 PAGE 8 + + while(!ADC_GetFlagStatus()); //ȴת + ADC_ClearFlag(); //ת־λ + ADC_Value2 = ADC_GetConversionValue(); //ȡڶADתֵ + ADC_Value = (ADC_Value1 + ADC_Value2) / 2; //ȡADƽֵ + + if (EADC_Flag) //ԭǰEA־λ + { + enableInterrupts(); + } + return (25 + ((float)ADC_Value - (float)ADC_TS_StandardData) / 8); + } + + /***************************************************** + *:ADC_PGAConfig(ADC_PGACOM_TypeDef ADC_PGACOM,ADC_PGAGAN_TypeDef ADC_PGAGAN,ADC_PGAIPT_TypeDef ADC + -_PGAIPT) + *:PGA + *ڲ: + ADC_PGACOM_TypeDef:ADC_PGACOM:PGAģѹѡ + ADC_PGAGAN_TypeDef:ADC_PGAGAN:PGAŴ + ADC_PGAIPT_TypeDef:ADC_PGAIPT:PGAͬ/ѡ + *ڲ:void + *****************************************************/ + void ADC_PGAConfig(ADC_PGACOM_TypeDef ADC_PGACOM, ADC_PGAGAN_TypeDef ADC_PGAGAN, ADC_PGAIPT_TypeDef ADC_PG + -AIPT) + { + PGACON &= 0x8F; + PGACON |= (ADC_PGACOM | ADC_PGAGAN | ADC_PGAIPT); + } + + /***************************************************** + *:void ADC_PGACmd(PriorityStatus NewState) + *:ADC PGAܿغ + *ڲ: + FunctionalState:NewState:/رѡ + *ڲ:void + *****************************************************/ + void ADC_PGACmd(PriorityStatus NewState) + { + if (NewState == LOW) + { + PGACON &= 0XFE; + } + else + { + PGACON |= 0x01; + } + } + #endif + 446 + 447 + 448 /***************************************************** + 449 *:void ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) + 450 *:ADC οѹѡ + 451 *ڲ: + 452 ADC_Vref_TypeDef:ADC_Vref:ѡADCοѹ + 453 *ڲ:void + 454 *****************************************************/ + 455 void ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) + 456 { + 457 1 OPINX = 0xC2; + 458 1 OPREG = OPREG & 0X7F | ADC_Vref; + 459 1 } + C51 COMPILER V9.59.0.0 SC92F_ADC 01/18/2024 10:03:13 PAGE 9 + + 460 #endif + 461 + 462 /******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 162 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/sc92f_chksum.lst b/Keil_C/List/sc92f_chksum.lst new file mode 100644 index 0000000..755f619 --- /dev/null +++ b/Keil_C/List/sc92f_chksum.lst @@ -0,0 +1,61 @@ +C51 COMPILER V9.01 SC92F_CHKSUM 09/11/2020 09:49:58 PAGE 1 +C51 COMPILER V9.01, COMPILATION OF MODULE SC92F_CHKSUM +OBJECT MODULE PLACED IN ..\Output\sc92f_chksum.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_chksum.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib + -\inc;..\User) DEBUG PRINT(..\List\sc92f_chksum.lst) OBJECT(..\Output\sc92f_chksum.obj) +line level source + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 #include "sc92f_chksum.h" + 13 + 14 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined + -(SC92F736xB) || defined (SC92F8003)|| defined (SC92F742x) + 15 + 21 void CHKSUM_DeInit(void) + 22 { + 23 1 OPERCON &= 0XFE; + 24 1 CHKSUML = 0X00; + 25 1 CHKSUMH = 0X00; + 26 1 } + 27 + 28 + 34 void CHKSUM_StartOperation(void) + 35 { + 36 1 OPERCON |= 0X01; + 37 1 while(OPERCON & 0x01); + 38 1 } + 39 + 40 + 46 uint16_t CHKSUM_GetCheckValue(void) + 47 { + 48 1 uint16_t checktemp; + 49 1 + 50 1 checktemp = (uint16_t)(CHKSUMH << 8)+ (uint16_t)CHKSUML; + 51 1 return checktemp; + 52 1 } + 53 #endif + 54 +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 33 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/sc92f_gpio.lst b/Keil_C/List/sc92f_gpio.lst new file mode 100644 index 0000000..0ee441b --- /dev/null +++ b/Keil_C/List/sc92f_gpio.lst @@ -0,0 +1,603 @@ +C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE SC92F_GPIO +OBJECT MODULE PLACED IN ..\Output\sc92f_gpio.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_gpio.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE + -) BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\sc92f_gpi + -o.lst) OBJECT(..\Output\sc92f_gpio.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : sc92f_gpio.c + 4 // : + 5 // ģ鹦 : GPIO̼⺯Cļ + 6 // ֲб : + 7 // : 2022/01/11 + 8 // 汾 : V1.10004 + 9 // ˵ : ļԪ92F/93F/92LϵеƬ + 10 //************************************************************* + 11 + 12 + 13 #include "sc92f_gpio.h" + 14 + 15 /************************************************** + 16 *:void GPIO_DeInit(void) + 17 *:GPIOؼĴλȱʡֵ + 18 *ڲ:void + 19 *ڲ:void + 20 **************************************************/ + 21 void GPIO_DeInit(void) + 22 { + 23 1 P0CON = 0x00; + 24 1 P0PH = 0x00; + 25 1 P0 = 0; + 26 1 P1CON = 0x00; + 27 1 P1PH = 0x00; + 28 1 P1 = 0; + 29 1 P2CON = 0x00; + 30 1 P2PH = 0x00; + 31 1 P2 = 0; + 32 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 33 1 || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + P3CON = 0x00; + P3PH = 0x00; + P3 = 0; + P4CON = 0x00; + P4PH = 0x00; + P4 = 0; + #endif + 41 1 #if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F7003) && !defined(S + -C92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) + 42 1 P5CON = 0x00; + 43 1 P5PH = 0x00; + 44 1 P5 = 0; + 45 1 #endif + 46 1 } + 47 + 48 /************************************************** + 49 *:void GPIO_Init(GPIO_TypeDef GPIOx, uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode) + 50 *:GPIOģʽóʼ + 51 *ڲ: + C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 2 + + 52 GPIO_TypeDef:GPIOx:ѡGPIO + 53 GPIO_Pin_TypeDef:PortPins:ѡGPIOܽPxy + 54 GPIO_Mode_TypeDef:GPIO_Mode:ѡGPIOģʽ롢롢 + 55 *ڲ:void + 56 **************************************************/ + 57 void GPIO_Init(GPIO_TypeDef GPIOx, + 58 uint8_t PortPins, GPIO_Mode_TypeDef GPIO_Mode) + 59 { + 60 1 if (GPIOx == GPIO0) + 61 1 { + 62 2 if (GPIO_Mode == GPIO_MODE_IN_HI) + 63 2 { + 64 3 P0CON &= ~PortPins; + 65 3 P0PH &= ~PortPins; + 66 3 } + 67 2 + 68 2 if (GPIO_Mode == GPIO_MODE_IN_PU) + 69 2 { + 70 3 P0CON &= ~PortPins; + 71 3 P0PH |= PortPins; + 72 3 } + 73 2 + 74 2 if (GPIO_Mode == GPIO_MODE_OUT_PP) + 75 2 { + 76 3 P0CON |= PortPins; + 77 3 } + 78 2 } + 79 1 else if (GPIOx == GPIO1) + 80 1 { + 81 2 if (GPIO_Mode == GPIO_MODE_IN_HI) + 82 2 { + 83 3 P1CON &= ~PortPins; + 84 3 P1PH &= ~PortPins; + 85 3 } + 86 2 + 87 2 if (GPIO_Mode == GPIO_MODE_IN_PU) + 88 2 { + 89 3 P1CON &= ~PortPins; + 90 3 P1PH |= PortPins; + 91 3 } + 92 2 + 93 2 if (GPIO_Mode == GPIO_MODE_OUT_PP) + 94 2 { + 95 3 P1CON |= PortPins; + 96 3 } + 97 2 } + 98 1 else if (GPIOx == GPIO2) + 99 1 { + 100 2 if (GPIO_Mode == GPIO_MODE_IN_HI) + 101 2 { + 102 3 P2CON &= ~PortPins; + 103 3 P2PH &= ~PortPins; + 104 3 } + 105 2 + 106 2 if (GPIO_Mode == GPIO_MODE_IN_PU) + 107 2 { + 108 3 P2CON &= ~PortPins; + 109 3 P2PH |= PortPins; + 110 3 } + 111 2 + 112 2 if (GPIO_Mode == GPIO_MODE_OUT_PP) + 113 2 { + C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 3 + + 114 3 P2CON |= PortPins; + 115 3 } + 116 2 } + 117 1 + 118 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 119 1 || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + else if (GPIOx == GPIO3) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P3CON &= ~PortPins; + P3PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P3CON &= ~PortPins; + P3PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P3CON |= PortPins; + } + } + else if (GPIOx == GPIO4) + { + if (GPIO_Mode == GPIO_MODE_IN_HI) + { + P4CON &= ~PortPins; + P4PH &= ~PortPins; + } + + if (GPIO_Mode == GPIO_MODE_IN_PU) + { + P4CON &= ~PortPins; + P4PH |= PortPins; + } + + if (GPIO_Mode == GPIO_MODE_OUT_PP) + { + P4CON |= PortPins; + } + } + + #endif + 160 1 #if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F7003) && !defined(S + -C92F8003) && !defined(SC92F740x) && !defined(SC92F827X) && !defined(SC92F837X) + 161 1 else if (GPIOx == GPIO5) + 162 1 { + 163 2 if (GPIO_Mode == GPIO_MODE_IN_HI) + 164 2 { + 165 3 P5CON &= ~PortPins; + 166 3 P5PH &= ~PortPins; + 167 3 } + 168 2 + 169 2 if (GPIO_Mode == GPIO_MODE_IN_PU) + 170 2 { + 171 3 P5CON &= ~PortPins; + 172 3 P5PH |= PortPins; + 173 3 } + C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 4 + + 174 2 + 175 2 if (GPIO_Mode == GPIO_MODE_OUT_PP) + 176 2 { + 177 3 P5CON |= PortPins; + 178 3 } + 179 2 } + 180 1 + 181 1 #endif + 182 1 } + 183 + 184 /************************************************** + 185 *:void GPIO_Write(GPIO_TypeDef GPIOx, uint8_t PortVal) + 186 *:GPIOڸֵ + 187 *ڲ: + 188 GPIO_TypeDef:GPIOx:ѡGPIO + 189 uint8_t:PortVal:GPIOڵֵ + 190 *ڲ:void + 191 **************************************************/ + 192 void GPIO_Write(GPIO_TypeDef GPIOx, + 193 uint8_t PortVal) + 194 { + 195 1 if (GPIOx == GPIO0) + 196 1 { + 197 2 P0 = PortVal; + 198 2 } + 199 1 + 200 1 if (GPIOx == GPIO1) + 201 1 { + 202 2 P1 = PortVal; + 203 2 } + 204 1 + 205 1 if (GPIOx == GPIO2) + 206 1 { + 207 2 P2 = PortVal; + 208 2 } + 209 1 + 210 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 211 1 || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + + if (GPIOx == GPIO3) + { + P3 = PortVal; + } + + if (GPIOx == GPIO4) + { + P4 = PortVal; + } + + #endif + 224 1 #if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(S + -C92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + 225 1 + 226 1 if (GPIOx == GPIO5) + 227 1 { + 228 2 P5 = PortVal; + 229 2 } + 230 1 + 231 1 #endif + 232 1 } + 233 + C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 5 + + 234 /************************************************** + 235 *:void GPIO_WriteHigh(GPIO_TypeDef GPIOx, uint8_t PortPins) + 236 *:GPIOڹܽPxyλ + 237 *ڲ: + 238 GPIO_TypeDef:GPIOx:ѡGPIO + 239 GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy + 240 *ڲ:void + 241 **************************************************/ + 242 void GPIO_WriteHigh(GPIO_TypeDef GPIOx, + 243 uint8_t PortPins) + 244 { + 245 1 if (GPIOx == GPIO0) + 246 1 { + 247 2 P0 |= PortPins; + 248 2 } + 249 1 + 250 1 if (GPIOx == GPIO1) + 251 1 { + 252 2 P1 |= PortPins; + 253 2 } + 254 1 + 255 1 if (GPIOx == GPIO2) + 256 1 { + 257 2 P2 |= PortPins; + 258 2 } + 259 1 + 260 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 261 1 || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + - + + if (GPIOx == GPIO3) + { + P3 |= PortPins; + } + + if (GPIOx == GPIO4) + { + P4 |= PortPins; + } + + #endif + 274 1 #if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(S + -C92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + 275 1 + 276 1 if (GPIOx == GPIO5) + 277 1 { + 278 2 P5 |= PortPins; + 279 2 } + 280 1 + 281 1 #endif + 282 1 } + 283 + 284 /************************************************** + 285 *:void GPIO_WriteLow(GPIO_TypeDef GPIOx, uint8_t PortPins) + 286 *:GPIOڹܽPxyλ + 287 *ڲ: + 288 GPIO_TypeDef:GPIOx:ѡGPIO + 289 GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy + 290 *ڲ:void + 291 **************************************************/ + 292 void GPIO_WriteLow(GPIO_TypeDef GPIOx, + C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 6 + + 293 uint8_t PortPins) + 294 { + 295 1 if (GPIOx == GPIO0) + 296 1 { + 297 2 P0 &= ~PortPins; + 298 2 } + 299 1 + 300 1 if (GPIOx == GPIO1) + 301 1 { + 302 2 P1 &= ~PortPins; + 303 2 } + 304 1 + 305 1 if (GPIOx == GPIO2) + 306 1 { + 307 2 P2 &= ~PortPins; + 308 2 } + 309 1 + 310 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 311 1 || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + + if (GPIOx == GPIO3) + { + P3 &= ~PortPins; + } + + if (GPIOx == GPIO4) + { + P4 &= ~PortPins; + } + + #endif + 324 1 #if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(S + -C92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + 325 1 + 326 1 if (GPIOx == GPIO5) + 327 1 { + 328 2 P5 &= ~PortPins; + 329 2 } + 330 1 + 331 1 #endif + 332 1 } + 333 + 334 /************************************************** + 335 *:uint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx) + 336 *:GPIOPxֵ + 337 *ڲ: + 338 GPIO_TypeDef:GPIOx:ѡGPIO + 339 *ڲ:uint8_t Pxֵ + 340 **************************************************/ + 341 uint8_t GPIO_ReadPort(GPIO_TypeDef GPIOx) + 342 { + 343 1 if (GPIOx == GPIO0) + 344 1 { + 345 2 return P0; + 346 2 } + 347 1 else if (GPIOx == GPIO1) + 348 1 { + 349 2 return P1; + 350 2 } + 351 1 else if (GPIOx == GPIO2) + 352 1 { + C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 7 + + 353 2 return P2; + 354 2 } + 355 1 + 356 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 357 1 || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + else if (GPIOx == GPIO3) + { + return P3; + } + else if (GPIOx == GPIO4) + { + return P4; + } + + #endif + 368 1 #if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(S + -C92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + 369 1 else if (GPIOx == GPIO5) + 370 1 { + 371 2 return P5; + 372 2 } + 373 1 + 374 1 #endif + 375 1 else + 376 1 { + 377 2 return 0; + 378 2 } + 379 1 } + 380 + 381 /************************************************** + 382 *:BitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, uint8_t PortPins) + 383 *:GPIOڹܽPxyֵ + 384 *ڲ: + 385 GPIO_TypeDef:GPIOx:ѡGPIO + 386 GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy + 387 *ڲ:BitStatus Pxyֵ + 388 **************************************************/ + 389 BitStatus GPIO_ReadPin(GPIO_TypeDef GPIOx, + 390 uint8_t PortPins) + 391 { + 392 1 if (GPIOx == GPIO0) + 393 1 { + 394 2 return ((bit)(P0 & PortPins)); + 395 2 } + 396 1 else if (GPIOx == GPIO1) + 397 1 { + 398 2 return ((bit)(P1 & PortPins)); + 399 2 } + 400 1 else if (GPIOx == GPIO2) + 401 1 { + 402 2 return ((bit)(P2 & PortPins)); + 403 2 } + 404 1 + 405 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 406 1 || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) + else if (GPIOx == GPIO3) + { + return ((bit)(P3 & PortPins)); + } + else if (GPIOx == GPIO4) + C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 8 + + { + return ((bit)(P4 & PortPins)); + } + + #endif + 417 1 #if !defined(SC92F730x) && !defined(SC92F725X) && !defined(SC92F735X) && !defined(SC92F8003) && !defined(S + -C92F740x) && !defined(SC92F827X) && !defined(SC92F837X) && !defined(SC92F7003) + 418 1 else if (GPIOx == GPIO5) + 419 1 { + 420 2 return ((bit)(P5 & PortPins)); + 421 2 } + 422 1 + 423 1 #endif + 424 1 return 0; + 425 1 } + 426 + 427 + 428 /************************************************** + 429 *:void GPIO_IOH_Config(GPIO_TypeDef GPIOx, uint8_t PortPins,GPIO_IOH_Grade_TypeDef GPIO_IOH_Grade) + 430 *:GPIOڹܽIOH + 431 *ڲ: + 432 GPIO_TypeDef:GPIOx:ѡGPIO + 433 GPIO_Pin_TypeDef:PortPins:ѡGPIOڹܽPxy + 434 GPIO_IOH_Grade_TypeDef:GPIO_IOH_Grade:IOȼ + 435 *ڲ:BitStatus Pxyֵ + 436 **************************************************/ + 437 #if !defined(SC92F7003) && !defined(SC92F8003) && !defined(SC92F740x) + 438 void GPIO_IOH_Config(GPIO_TypeDef GPIOx, GPIO_Pin_TypeDef PortPins, GPIO_IOH_Grade_TypeDef GPIO_IOH_Grade) + 439 { + 440 1 #if defined(SC92F854x) || defined(SC92F754x) || defined(SC92F844xB) || defined(SC92F744xB) || defined(SC92 + -F84Ax_2) || defined(SC92F74Ax_2)\ + 441 1 || defined(SC92FWxx) || defined(SC92F859x) || defined(SC92F759x) || defined (SC92L853x) || defined (SC92 + -L753x) + switch (GPIOx) + { + case GPIO0: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON0 &= 0xFC; + IOHCON0 |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON0 &= 0xF3; + IOHCON0 |= GPIO_IOH_Grade << 2; + } + break; + case GPIO1: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON0 &= 0xCF; + IOHCON0 |= GPIO_IOH_Grade << 4; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON0 &= 0x3F; + IOHCON0 |= GPIO_IOH_Grade << 6; + } + break; + case GPIO2: + if (PortPins == GPIO_PIN_LNIB) + { + C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 9 + + IOHCON1 &= 0xFC; + IOHCON1 |= GPIO_IOH_Grade; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON1 &= 0xF3; + IOHCON1 |= GPIO_IOH_Grade << 2; + } + break; + #if defined (SC92L853x) || defined (SC92L753x) + case GPIO5: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON1 &= 0xCF; + IOHCON1 |= GPIO_IOH_Grade << 4; + } + else if (PortPins == GPIO_PIN_HNIB) + { + IOHCON1 &= 0x3f; + IOHCON1 |= GPIO_IOH_Grade << 6; + } + break; + #else + case GPIO3: + if (PortPins == GPIO_PIN_LNIB) + { + IOHCON1 &= 0xCF; + IOHCON1 |= GPIO_IOH_Grade << 4; + } + break; + #endif + default: + break; + } + #else + 506 1 switch (GPIOx) + 507 1 { + 508 2 case GPIO0: + 509 2 if (PortPins == GPIO_PIN_LNIB) + 510 2 { + 511 3 IOHCON &= 0xFC; + 512 3 IOHCON |= GPIO_IOH_Grade; + 513 3 } + 514 2 else if (PortPins == GPIO_PIN_HNIB) + 515 2 { + 516 3 IOHCON &= 0xF3; + 517 3 IOHCON |= GPIO_IOH_Grade << 2; + 518 3 } + 519 2 break; + 520 2 case GPIO2: + 521 2 if (PortPins == GPIO_PIN_LNIB) + 522 2 { + 523 3 IOHCON &= 0xFC; + 524 3 IOHCON |= GPIO_IOH_Grade; + 525 3 } + 526 2 else if (PortPins == GPIO_PIN_HNIB) + 527 2 { + 528 3 IOHCON &= 0xF3; + 529 3 IOHCON |= GPIO_IOH_Grade << 2; + 530 3 } + 531 2 break; + 532 2 default: + C51 COMPILER V9.59.0.0 SC92F_GPIO 01/18/2024 10:03:13 PAGE 10 + + 533 2 break; + 534 2 } + 535 1 #endif + 536 1 } + 537 #endif + 538 + 539 /******************* (C) COPYRIGHT 2021 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 541 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/sc92f_option.lst b/Keil_C/List/sc92f_option.lst new file mode 100644 index 0000000..4086911 --- /dev/null +++ b/Keil_C/List/sc92f_option.lst @@ -0,0 +1,217 @@ +C51 COMPILER V9.59.0.0 SC92F_OPTION 01/18/2024 10:03:13 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE SC92F_OPTION +OBJECT MODULE PLACED IN ..\Output\sc92f_option.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_option.c LARGE OBJECTADVANCED OPTIMIZE(8,SI + -ZE) BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\sc92f_o + -ption.lst) OBJECT(..\Output\sc92f_option.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : sc92f_option.c + 4 // : + 5 // ģ鹦 : Customer OptionĴCļ + 6 // ֲб: + 7 // : 2022/01/24 + 8 // 汾 : V1.0005 + 9 // ˵ : + 10 //************************************************************* + 11 + 12 #include "sc92f_option.h" + 13 + 14 /***************************************************** + 15 *:void OPTION_WDT_Cmd(FunctionalState NewState) + 16 *:WDTܿغ + 17 *ڲ: + 18 FunctionalState:NewState:/رѡ + 19 *ڲ:void + 20 *****************************************************/ + 21 void OPTION_WDT_Cmd(FunctionalState NewState) + 22 { + 23 1 OPINX = 0XC1; + 24 1 + 25 1 if(NewState == DISABLE) + 26 1 { + 27 2 OPREG &= 0X7F; + 28 2 } + 29 1 else + 30 1 { + 31 2 OPREG |= 0X80; + 32 2 } + 33 1 } + 34 + 35 /***************************************************** + 36 *:void OPTION_XTIPLL_Cmd(FunctionalState NewState) + 37 *:Ӿʹ + 38 *ڲ: + 39 FunctionalState:NewState:/رѡ + 40 *ڲ:void + 41 *****************************************************/ + 42 #if !defined(SC92F848x) && !defined(SC92F748x) + 43 void OPTION_XTIPLL_Cmd(FunctionalState NewState) + 44 { + 45 1 OPINX = 0XC1; + 46 1 + 47 1 if(NewState == DISABLE) + 48 1 { + 49 2 OPREG &= 0XBF; + 50 2 } + 51 1 else + 52 1 { + 53 2 OPREG |= 0X40; + C51 COMPILER V9.59.0.0 SC92F_OPTION 01/18/2024 10:03:13 PAGE 2 + + 54 2 } + 55 1 } + 56 #endif + 57 /***************************************************** + 58 *:void OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef SYSCLK_PresSel) + 59 *:ϵͳʱӷƵʼ + 60 *ڲ: + 61 SYSCLK_PresSel_TypeDef:SYSCLK_PresSel:ѡϵͳʱӷƵ + 62 *ڲ:void + 63 *****************************************************/ + 64 void OPTION_SYSCLK_Init(SYSCLK_PresSel_TypeDef + 65 SYSCLK_PresSel) + 66 { + 67 1 OPINX = 0XC1; + 68 1 OPREG = OPREG & 0XCF | SYSCLK_PresSel; + 69 1 } + 70 + 71 /***************************************************** + 72 *:void OPTION_RST_PIN_Cmd(FunctionalState NewState) + 73 *:ⲿλܽţP17ʹ + 74 *ڲ: + 75 FunctionalState:NewState:ʹ/رѡ + 76 *ڲ:void + 77 *****************************************************/ + 78 #if !defined(SC92F848x) && !defined(SC92F748x) && !defined(SC92F859x) && !defined (SC92F759x) && !define + -d(SC92L853x) && !defined (SC92L753x) + 79 void OPTION_RST_PIN_Cmd(FunctionalState NewState) + 80 { + 81 1 OPINX = 0XC1; + 82 1 + 83 1 if(NewState == DISABLE) + 84 1 { + 85 2 OPREG |= 0X08; + 86 2 } + 87 1 else + 88 1 { + 89 2 OPREG &= 0XF7; + 90 2 } + 91 1 } + 92 #endif + 93 + 94 /***************************************************** + 95 *:void OPTION_LVR_Init(LVR_Config_TypeDef LVR_Config) + 96 *:LVR ѹѡ + 97 *ڲ: + 98 LVR_Config_TypeDef:LVR_Config:ѡLVRѹ + 99 *ڲ:void + 100 *****************************************************/ + 101 void OPTION_LVR_Init(LVR_Config_TypeDef + 102 LVR_Config) + 103 { + 104 1 OPINX = 0XC1; + 105 1 OPREG = OPREG & 0XF8 | LVR_Config; + 106 1 } + 107 + 108 /***************************************************** + 109 *:void OPTION_ADC_VrefConfig(ADC_Vref_TypeDef ADC_Vref) + 110 *:ADC οѹѡ + 111 *ڲ: + 112 ADC_Vref_TypeDef:ADC_Vref:ѡADCοѹ + 113 *ڲ:void + 114 *****************************************************/ + C51 COMPILER V9.59.0.0 SC92F_OPTION 01/18/2024 10:03:13 PAGE 3 + + 115 void OPTION_ADC_VrefConfig(ADC_Vref_TypeDef + 116 ADC_Vref) + 117 { + 118 1 OPINX = 0xC2; + 119 1 OPREG = OPREG & 0X7F | ADC_Vref; + 120 1 } + 121 + 122 /************************************************** + 123 *:void OPTION_IAP_SetOperateRange(IAP_OperateRange_TypeDef IAP_OperateRange) + 124 *:IAPķΧ + 125 *ڲ: + 126 IAP_OperateRange_TypeDef:IAP_OperateRange:IAPΧ + 127 *ڲ:void + 128 **************************************************/ + 129 void OPTION_IAP_SetOperateRange( + 130 IAP_OperateRange_TypeDef IAP_OperateRange) + 131 { + 132 1 OPINX = 0xC2; + 133 1 OPREG = (OPREG & 0xF3) | IAP_OperateRange; + 134 1 } + 135 + 136 #if defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB)|| defined + - (SC92F83Ax)\ + 137 || defined (SC92F73Ax) || defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F740x)\ + 138 || defined (SC92F8003) || defined (SC92F7003) + 139 /***************************************************** + 140 *:void OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef XTIPLL_Range) + 141 *:ⲿƵƵʷΧ + 142 *ڲ: + 143 XTIPLL_Range_TypeDef:XTIPLL_Range:ⲿƵѡ + 144 *ڲ:void + 145 *****************************************************/ + 146 void OPTION_XTIPLL_SetRange(XTIPLL_Range_TypeDef + 147 XTIPLL_Range) + 148 { + 149 1 OPINX = 0XC2; + 150 1 OPREG = OPREG & 0XBF | XTIPLL_Range; + 151 1 } + 152 #endif + 153 + 154 #if defined (SC92F742x)||defined (SC92F83Ax) || defined (SC92F73Ax)|| defined (SC92F84Ax) || defined (SC92 + -F74Ax) \ + 155 ||defined (SC92F74Ax_2)||defined (SC92F84Ax_2)||defined (SC92F844xB)||defined (SC92F744xB) \ + 156 ||defined (SC92F859x) || defined (SC92F759x) ||defined (SC92F848x) || defined (SC92F748x) || defined (SC + -92L853x) || defined (SC92L753x) + /************************************************** + *:void OPTION_JTG_Cmd(FunctionalState NewState) + *:JTAGģʽʹܿ + *ڲ: + FunctionalState:NewState:/رѡ + *ڲ:void + **************************************************/ + void OPTION_JTG_Cmd(FunctionalState NewState) + { + OPINX = 0xC2; + + if(NewState == DISABLE) + { + OPREG |= 0X10; //1 JTAGЧ + } + else + { + C51 COMPILER V9.59.0.0 SC92F_OPTION 01/18/2024 10:03:13 PAGE 4 + + OPREG &= 0XEF; //0 JTAGЧ + } + } + #endif + 178 /******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 106 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/sc92f_pwm.lst b/Keil_C/List/sc92f_pwm.lst new file mode 100644 index 0000000..218dac2 --- /dev/null +++ b/Keil_C/List/sc92f_pwm.lst @@ -0,0 +1,613 @@ +C51 COMPILER V9.01 SC92F_PWM 09/11/2020 09:48:38 PAGE 1 +C51 COMPILER V9.01, COMPILATION OF MODULE SC92F_PWM +OBJECT MODULE PLACED IN ..\Output\sc92f_pwm.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_pwm.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib\in + -c;..\User) DEBUG PRINT(..\List\sc92f_pwm.lst) OBJECT(..\Output\sc92f_pwm.obj) +line level source + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 #include "sc92f_pwm.h" + 13 + 14 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2) + uint16_t xdata PWMREG[8] _at_ 0x740; + uint16_t pwm_tmpreg[8] = {0,0,0,0,0,0,0,0}; + void PWM_DeInit(void) + { + static uint8_t i; + PWMCFG = 0X00; + PWMCON = 0X00; + IE1 &= 0XFD; + IP1 &= 0XFD; + for(i=0;i<8;i++) + { + PWMREG[i] = 0; + } + } + void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) + { + PWM_Period -= 1; + PWMCFG = (PWMCFG & 0XCF) | PWM_PresSel; + PWMCFG = (PWMCFG & 0XF0) | (uint8_t)(PWM_Period / 256); + PWMCON = (uint8_t)(PWM_Period & 0X00FF); + } + void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + { + uint8_t i; + for(i=0;i<8;i++) + { + if(PWM_OutputPin&(0x01<> 2); + } + void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + { + if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + { + PWMCON |= PWM_OutputPin; + } + else + { + PWMCON &= (~PWM_OutputPin); + } + } + void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) + { + if(PWM_Polarity == PWM_POLARITY_INVERT) + { + PWMCFG |= PWM_OutputPin; + } + else + { + PWMCFG &= (~PWM_OutputPin); + } + } + void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) + { + PWMDTYB &= 0X7F; + switch(PWM_OutputPin) + { + case PWM0: + PWMDTYA = PWMDTYA & 0xfc | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM1: + PWMDTYA = PWMDTYA & 0xf3 | ((PWM_DutyCycle % 4) << 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM2: + PWMDTYA = PWMDTYA & 0xcf | ((PWM_DutyCycle % 4) << 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM3: + PWMDTYB = PWMDTYB & 0xfc | (PWM_DutyCycle % 4); + PWMDTY3 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM4: + PWMDTYB = PWMDTYB & 0xf3 | ((PWM_DutyCycle % 4) << 2); + PWMDTY4 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM5: + PWMDTYB = PWMDTYB & 0xcf | ((PWM_DutyCycle % 4) << 4); + PWMDTY5 = (uint8_t)(PWM_DutyCycle >> 2); + break; + default: + break; + } + } + void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t P + -WM_DutyCycle) + { + PWMDTYB |= 0X80; + switch(PWM_ComplementaryOutputPin) + { + case PWM0PWM3: + PWMDTYA = PWMDTYA & 0xfc | (PWM_DutyCycle % 4); + PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM1PWM4: + PWMDTYA = PWMDTYA & 0xf3 | ((PWM_DutyCycle % 4) << 2); + PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + break; + case PWM2PWM5: + PWMDTYA = PWMDTYA & 0xcf | ((PWM_DutyCycle % 4) << 4); + PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + break; + default: + break; + } + } + void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) + { + PWMDTY3 = (PWM012_RisingDeadTime | (PWM345_fallingDeadTime << 4)); + } + void PWM_Cmd(FunctionalState NewState) + { + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } + } + void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) + { + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= 0XFD; + } + if(Priority == LOW) + { + IP1 &= 0XFD; + } + else + { + IP1 |= 0X02; + } + } + FlagStatus PWM_GetFlagStatus(void) + { + return (FlagStatus)(PWMCON & 0X40); + } + void PWM_ClearFlag(void) + { + PWMCON &= 0XBF; + } + #endif + 422 + 423 + 424 + 425 + 426 + 427 + 428 + 429 + 430 + 431 #if defined (SC92F8003) + 432 + 438 void PWM_DeInit(void) + 439 { + 440 1 PWMCFG = 0X00; + 441 1 PWMCON0 = 0X00; + 442 1 PWMPRD = 0X00; + 443 1 PWMDTYA = 0X00; + 444 1 PWMDTY0 = 0X00; + 445 1 PWMDTY1 = 0X00; + 446 1 PWMDTY2 = 0X00; + 447 1 PWMCON1 = 0X00; + 448 1 PWMDTYB = 0X00; + 449 1 PWMDTY3 = 0X00; + 450 1 PWMDTY4 = 0X00; + 451 1 PWMDTY5 = 0X00; + 452 1 PWMDTY6 = 0X00; + 453 1 IE1 &= 0XFD; + 454 1 IP1 &= 0XFD; + 455 1 } + 456 + 457 + 464 void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) + 465 { + 466 1 PWM_Period -= 1; + 467 1 PWMCON0 = (PWMCON0 & 0XCC) | PWM_PresSel | (uint8_t)(PWM_Period & 0X0003); + 468 1 PWMPRD = (uint8_t)(PWM_Period >> 2); + 469 1 } + 470 + 471 + 478 void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + 479 { + 480 1 if(PWM_OutputState == PWM_OUTPUTSTATE_ENABLE) + 481 1 { + 482 2 PWMCON1 |= PWM_OutputPin; + 483 2 } + 484 1 else + 485 1 { + 486 2 PWMCON1 &= (~PWM_OutputPin); + 487 2 } + 488 1 } + 489 + 490 + 496 void PWM_PWM2Selection(PWM2_OutputPin_TypeDef PWM2_OutputPin) + 497 { + 498 1 PWMCON0 = PWMCON0 & 0XFB | PWM2_OutputPin; + 499 1 } + 500 + 501 + 507 void PWM_PWM5Selection(PWM5_OutputPin_TypeDef PWM5_OutputPin) + 508 { + 509 1 PWMCON0 = PWMCON0 & 0XF7 | PWM5_OutputPin; + 510 1 } + 511 + 512 + 519 void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) + 520 { + 521 1 if(PWM_Polarity == PWM_POLARITY_INVERT) + 522 1 { + 523 2 PWMCFG |= PWM_OutputPin; + 524 2 } + 525 1 else + 526 1 { + 527 2 PWMCFG &= (~PWM_OutputPin); + 528 2 } + 529 1 } + 530 + 531 + 538 void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) + 539 { + 540 1 if(PWM_OutputPin!=PWM6) + 541 1 { + 542 2 PWMCON1 &= 0X7F; + 543 2 } + 544 1 switch(PWM_OutputPin) + 545 1 { + 546 2 case PWM0: + 547 2 PWMDTYA = PWMDTYA & 0XFC | (PWM_DutyCycle % 4); + 548 2 PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + 549 2 break; + 550 2 case PWM1: + 551 2 PWMDTYA = PWMDTYA & 0XF3 | ((PWM_DutyCycle % 4) << 2); + 552 2 PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + 553 2 break; + 554 2 case PWM2: + 555 2 PWMDTYA = PWMDTYA & 0XCF | ((PWM_DutyCycle % 4) << 4); + 556 2 PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + 557 2 break; + 558 2 case PWM3: + 559 2 PWMDTYA = PWMDTYA & 0X3F | ((PWM_DutyCycle % 4) << 6); + 560 2 PWMDTY3 = (uint8_t)(PWM_DutyCycle >> 2); + 561 2 break; + 562 2 case PWM4: + 563 2 PWMDTYB = PWMDTYB & 0XFC | (PWM_DutyCycle % 4); + 564 2 PWMDTY4 = (uint8_t)(PWM_DutyCycle >> 2); + 565 2 break; + 566 2 case PWM5: + 567 2 PWMDTYB = PWMDTYB & 0XF3 | ((PWM_DutyCycle % 4) << 2); + 568 2 PWMDTY5 = (uint8_t)(PWM_DutyCycle >> 2); + 569 2 break; + 570 2 case PWM6: + 571 2 PWMDTYB = PWMDTYB & 0XCF | ((PWM_DutyCycle % 4) << 4); + 572 2 PWMDTY6 = (uint8_t)(PWM_DutyCycle >> 2); + 573 2 break; + 574 2 default: + 575 2 break; + 576 2 } + 577 1 } + 578 + 579 + 586 void PWM_ComplementaryModeConfig(PWM_ComplementaryOutputPin_TypeDef PWM_ComplementaryOutputPin, uint16_t P + -WM_DutyCycle) + 587 { + 588 1 PWMCON1 |= 0X80; + 589 1 switch(PWM_ComplementaryOutputPin) + 590 1 { + 591 2 case PWM0PWM3: + 592 2 PWMDTYA = PWMDTYA & 0XFC | (PWM_DutyCycle % 4); + 593 2 PWMDTY0 = (uint8_t)(PWM_DutyCycle >> 2); + 594 2 break; + 595 2 case PWM1PWM4: + 596 2 PWMDTYA = PWMDTYA & 0XF3 | ((PWM_DutyCycle % 4) << 2); + 597 2 PWMDTY1 = (uint8_t)(PWM_DutyCycle >> 2); + 598 2 break; + 599 2 case PWM2PWM5: + 600 2 PWMDTYA = PWMDTYA & 0XCF | ((PWM_DutyCycle % 4) << 4); + 601 2 PWMDTY2 = (uint8_t)(PWM_DutyCycle >> 2); + 602 2 break; + 603 2 default: + 604 2 break; + 605 2 } + 606 1 } + 607 + 608 + 615 void PWM_DeadTimeConfig(uint8_t PWM012_RisingDeadTime, uint8_t PWM345_fallingDeadTime) + 616 { + 617 1 PWMDTY3 = (PWM012_RisingDeadTime | (PWM345_fallingDeadTime << 4)); + 618 1 } + 619 + 620 + 626 void PWM_Cmd(FunctionalState NewState) + 627 { + 628 1 if (NewState != DISABLE) + 629 1 { + 630 2 PWMCON0 |= 0X80; + 631 2 } + 632 1 else + 633 1 { + 634 2 PWMCON0 &= ~0X80; + 635 2 } + 636 1 } + 637 + 638 + 645 void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) + 646 { + 647 1 if (NewState != DISABLE) + 648 1 { + 649 2 IE1 |= 0X02; + 650 2 } + 651 1 else + 652 1 { + 653 2 IE1 &= 0XFD; + 654 2 } + 655 1 + 656 1 if(Priority == LOW) + 657 1 { + 658 2 IP1 &= 0XFD; + 659 2 } + 660 1 else + 661 1 { + 662 2 IP1 |= 0X02; + 663 2 } + 664 1 } + 665 + 666 + 672 FlagStatus PWM_GetFlagStatus(void) + 673 { + 674 1 return (FlagStatus)(PWMCON0 & 0X40); + 675 1 } + 676 + 677 + 683 void PWM_ClearFlag(void) + 684 { + 685 1 PWMCON0 &= 0XBF; + 686 1 } + 687 #endif + 688 + 689 + 690 + 691 + 692 + 693 + 694 + 695 + 696 + 697 + 698 + 699 + 700 #if defined (SC92F742x) + void PWM_DeInit(void) + { + PWMCFG0 = 0X00; + PWMCON = 0X00; + PWMPRD = 0X00; + PWMCFG1 = 0X00; + PWMDTY0 = 0X00; + PWMDTY1 = 0X00; + PWMDTY2 = 0X00; + PWMDTY3 = 0X00; + PWMDTY4 = 0X00; + PWMDTY5 = 0X00; + IE1 &= ~0X02; + IP1 &= ~0X02; + } + void PWM_Init(PWM_PresSel_TypeDef PWM_PresSel, uint16_t PWM_Period) + { + PWM_Period -= 1; + PWMCON = (PWMCON & 0XF8) | PWM_PresSel; + PWMPRD = PWM_Period; + } + void PWM_OutputStateConfig(uint8_t PWM_OutputPin, PWM_OutputState_TypeDef PWM_OutputState) + { + if(PWM_OutputState==PWM_OUTPUTSTATE_DISABLE) + { + PWMCON = PWMCON & (~(PWM_OutputPin&0x38)); + PWMCFG0 = PWMCFG0 & (~(PWM_OutputPin&0x07)); + } + else + { + PWMCON = PWMCON | (PWM_OutputPin&0x38); + PWMCFG0 = PWMCFG0 |(PWM_OutputPin&0x07); + } + } + void PWM_PolarityConfig(uint8_t PWM_OutputPin, PWM_Polarity_TypeDef PWM_Polarity) + { + if(PWM_Polarity==PWM_POLARITY_NON_INVERT) + { + PWMCFG0 = PWMCFG0 & (~(PWM_OutputPin&0x38)); + PWMCFG1 = PWMCFG1 & (~((PWM_OutputPin<<3)&0x38)); + } + else + { + PWMCFG0 = PWMCFG0 | (PWM_OutputPin&0x38); + PWMCFG1 = PWMCFG1 |((PWM_OutputPin<<3)&0x38); + } + } + void PWM_IndependentModeConfig(PWM_OutputPin_TypeDef PWM_OutputPin, uint16_t PWM_DutyCycle) + { + switch(PWM_OutputPin) + { + case PWM0: + PWMDTY0 = PWM_DutyCycle; + break; + case PWM1: + PWMDTY1 = PWM_DutyCycle; + break; + case PWM2: + PWMDTY2 = PWM_DutyCycle; + break; + case PWM3: + PWMDTY3 = PWM_DutyCycle; + break; + case PWM4: + PWMDTY4 = PWM_DutyCycle; + break; + case PWM5: + PWMDTY5 = PWM_DutyCycle; + break; + default: + break; + } + } + void PWM_Cmd(FunctionalState NewState) + { + if (NewState != DISABLE) + { + PWMCON |= 0X80; + } + else + { + PWMCON &= ~0X80; + } + } + void PWM_ITConfig(FunctionalState NewState, PriorityStatus Priority) + { + if (NewState != DISABLE) + { + IE1 |= 0X02; + } + else + { + IE1 &= ~0X02; + } + if(Priority == LOW) + { + IP1 &= ~0X02; + } + else + { + IP1 |= 0X02; + } + } + FlagStatus PWM_GetFlagStatus(void) + { + return (FlagStatus)(PWMCON & 0X40); + } + void PWM_ClearFlag(void) + { + PWMCON &= 0XBF; + } + #endif + 881 + 882 +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 504 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/sc92f_pwr.lst b/Keil_C/List/sc92f_pwr.lst new file mode 100644 index 0000000..005b1b8 --- /dev/null +++ b/Keil_C/List/sc92f_pwr.lst @@ -0,0 +1,67 @@ +C51 COMPILER V9.01 SC92F_PWR 09/11/2020 09:48:39 PAGE 1 +C51 COMPILER V9.01, COMPILATION OF MODULE SC92F_PWR +OBJECT MODULE PLACED IN ..\Output\sc92f_pwr.obj +COMPILER INVOKED BY: E:\Keil\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_pwr.c OMF2 BROWSE INCDIR(..\FWLib\SC92F_Lib\in + -c;..\User) DEBUG PRINT(..\List\sc92f_pwr.lst) OBJECT(..\Output\sc92f_pwr.obj) +line level source + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 #include "sc92f_pwr.h" + 12 + 13 + 19 void PWR_DeInit(void) + 20 { + 21 1 PCON &= 0XFC; + 22 1 } + 23 + 24 + 30 void PWR_EnterSTOPMode(void) + 31 { + 32 1 PCON |= 0X02; + 33 1 _nop_(); + 34 1 _nop_(); + 35 1 _nop_(); + 36 1 _nop_(); + 37 1 _nop_(); + 38 1 _nop_(); + 39 1 _nop_(); + 40 1 _nop_(); + 41 1 } + 42 + 43 + 49 void PWR_EnterIDLEMode(void) + 50 { + 51 1 PCON |= 0X01; + 52 1 _nop_(); + 53 1 _nop_(); + 54 1 _nop_(); + 55 1 _nop_(); + 56 1 _nop_(); + 57 1 _nop_(); + 58 1 _nop_(); + 59 1 _nop_(); + 60 1 } + 61 + 62 +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 28 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/sc92f_ssi.lst b/Keil_C/List/sc92f_ssi.lst new file mode 100644 index 0000000..4ae92d4 --- /dev/null +++ b/Keil_C/List/sc92f_ssi.lst @@ -0,0 +1,475 @@ +C51 COMPILER V9.59.0.0 SC92F_SSI 01/18/2024 10:03:12 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE SC92F_SSI +OBJECT MODULE PLACED IN ..\Output\sc92f_ssi.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_ssi.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) + - BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\sc92f_ssi. + -lst) OBJECT(..\Output\sc92f_ssi.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ : sc92f_ssi.c + 4 // : + 5 // ģ鹦 : SSI̼⺯Cļ + 6 // ֲб: + 7 // : 2021/08/20 + 8 // 汾 : V1.10001 + 9 // ˵ : + 10 //************************************************************* + 11 + 12 #include "sc92f_ssi.h" + 13 + 14 #if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined ( + -SC92F84Ax_2) || defined (SC92F74Ax_2)\ + 15 || defined (SC92F846xB) || defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defin + -ed (SC92F84Ax) || defined (SC92F74Ax)\ + 16 || defined (SC92F83Ax) || defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F8003) || defined ( + -SC92F740x) || defined (SC92F827X)\ + 17 || defined (SC92F837X) || defined (SC92FWxx) || defined (SC93F833x) || defined (SC93F843x) || defined (S + -C93F743x) || defined (SC92F848x) || defined (SC92F748x)\ + 18 || defined (SC92F859x) || defined (SC92F759x) + 19 /************************************************** + 20 *:void SSI_DeInit(void) + 21 *:SSIؼĴλȱʡֵ + 22 *ڲ:void + 23 *ڲ:void + 24 **************************************************/ + 25 void SSI_DeInit(void) + 26 { + 27 1 OTCON &= 0X3F; + 28 1 SSCON0 = 0X00; + 29 1 SSCON1 = 0X00; + 30 1 SSCON2 = 0X00; + 31 1 SSDAT = 0X00; + 32 1 IE1 &= (~0X01); + 33 1 IP1 &= (~0X01); + 34 1 } + 35 + 36 #if defined (SC92F7003) || defined (SC92F8003) || defined (SC92F740x) + /************************************************** + *:SSI_PinSelection(SSI_PinSelection_TypeDef PinSeletion) + *:SSIѡ + *ڲ: + SSI_PinSelection_TypeDef:PinSeletion:ѡSSIΪP10P27P26P21P22P23 + *ڲ:void + **************************************************/ + void SSI_PinSelection(SSI_PinSelection_TypeDef + PinSeletion) + { + OTCON = OTCON & 0XDF | PinSeletion; + } + #endif + C51 COMPILER V9.59.0.0 SC92F_SSI 01/18/2024 10:03:12 PAGE 2 + + 50 + 51 /************************************************** + 52 *:void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler + -,SPI_Mode_TypeDef Mode, + 53 SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase,SPI_TXE_INT_TypeDef SPI + -_TXE_INT) + 54 *:SPIʼú + 55 *ڲ: + 56 SPI_FirstBit_TypeDef:FirstBit:ȴλѡMSB/LSB + 57 SPI_BaudRatePrescaler_TypeDef:BaudRatePrescaler:SPIʱƵѡ + 58 SPI_Mode_TypeDef:Mode:SPIģʽѡ + 59 SPI_ClockPolarity_TypeDef:ClockPolarity:SPIʱӼѡ + 60 SPI_ClockPhase_TypeDef:ClockPhase:SPIʱλѡ + 61 SPI_TXE_INT_TypeDef:SPI_TXE_INT:ͻжѡ + 62 *ڲ:void + 63 **************************************************/ + 64 void SSI_SPI_Init(SPI_FirstBit_TypeDef FirstBit, + 65 SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, + 66 SPI_Mode_TypeDef Mode, + 67 SPI_ClockPolarity_TypeDef ClockPolarity, + 68 SPI_ClockPhase_TypeDef ClockPhase, + 69 SPI_TXE_INT_TypeDef SPI_TXE_INT) + 70 { + 71 1 OTCON = (OTCON & 0X3F) | 0X40; + 72 1 SSCON1 = SSCON1 & (~0X05) | FirstBit | + 73 1 SPI_TXE_INT; + 74 1 SSCON0 = SSCON0 & 0X80 | BaudRatePrescaler | Mode + 75 1 | ClockPolarity | ClockPhase; + 76 1 } + 77 + 78 /***************************************************** + 79 *:void SSI_SPI_Cmd(FunctionalState NewState) + 80 *:SPIܿغ + 81 *ڲ: + 82 FunctionalState:NewState:/رѡ + 83 *ڲ:void + 84 *****************************************************/ + 85 void SSI_SPI_Cmd(FunctionalState NewState) + 86 { + 87 1 if(NewState != DISABLE) + 88 1 { + 89 2 SSCON0 |= 0X80; + 90 2 } + 91 1 else + 92 1 { + 93 2 SSCON0 &= (~0X80); + 94 2 } + 95 1 } + 96 + 97 /***************************************************** + 98 *:void SSI_SPI_SendData(uint8_t Data) + 99 *:SPI + 100 *ڲ: + 101 uint8_t:Data:͵ + 102 *ڲ:void + 103 *****************************************************/ + 104 void SSI_SPI_SendData(uint8_t Data) + 105 { + 106 1 SSDAT = Data; + 107 1 } + 108 + 109 /***************************************************** + C51 COMPILER V9.59.0.0 SC92F_SSI 01/18/2024 10:03:12 PAGE 3 + + 110 *:uint8_t SSI_SPI_ReceiveData(void) + 111 *:SSDATеֵ + 112 *ڲ:void + 113 *ڲ: + 114 uint8_t:SPIյ8λ + 115 *****************************************************/ + 116 uint8_t SSI_SPI_ReceiveData(void) + 117 { + 118 1 return SSDAT; + 119 1 } + 120 + 121 /************************************************** + 122 *:void SSI_TWI_Init(uint8_t TWI_Address) + 123 *:TWIʼú + 124 *ڲ: + 125 uint8_t:TWI_Address:TWIΪӻʱ7λӻַ + 126 *ڲ:void + 127 **************************************************/ + 128 void SSI_TWI_Init(uint8_t TWI_Address) + 129 { + 130 1 OTCON = OTCON & 0X3F | 0X80; + 131 1 SSCON1 = TWI_Address << 1; + 132 1 } + 133 + 134 /************************************************** + 135 *:void SSI_TWI_AcknowledgeConfig(FunctionalState NewState) + 136 *:TWIӦʹܺ + 137 *ڲ: + 138 FunctionalState:NewState:Ӧʹ/ʧѡ + 139 *ڲ:void + 140 **************************************************/ + 141 void SSI_TWI_AcknowledgeConfig(FunctionalState + 142 NewState) + 143 { + 144 1 if (NewState != DISABLE) + 145 1 { + 146 2 SSCON0 |= 0X08; + 147 2 } + 148 1 else + 149 1 { + 150 2 SSCON0 &= 0XF7; + 151 2 } + 152 1 } + 153 + 154 /************************************************** + 155 *:void SSI_TWI_GeneralCallCmd(FunctionalState NewState) + 156 *:TWIͨõַӦʹܺ + 157 *ڲ: + 158 FunctionalState:NewState:ͨõַӦʹ/ʧѡ + 159 *ڲ:void + 160 **************************************************/ + 161 void SSI_TWI_GeneralCallCmd(FunctionalState + 162 NewState) + 163 { + 164 1 if (NewState != DISABLE) + 165 1 { + 166 2 SSCON1 |= 0X01; + 167 2 } + 168 1 else + 169 1 { + 170 2 SSCON1 &= 0XFE; + 171 2 } + C51 COMPILER V9.59.0.0 SC92F_SSI 01/18/2024 10:03:12 PAGE 4 + + 172 1 } + 173 + 174 /************************************************** + 175 *:FlagStatus SSI_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) + 176 *:ȡTWI״̬ + 177 *ڲ: + 178 SSI_TWIState_TypeDef:SSI_TWIState:TWI״̬״̬ + 179 *ڲ:void + 180 **************************************************/ + 181 FlagStatus SSI_GetTWIStatus(SSI_TWIState_TypeDef SSI_TWIState) + 182 { + 183 1 if((SSCON0&0x07) == SSI_TWIState) + 184 1 return SET; + 185 1 else + 186 1 return RESET; + 187 1 } + 188 + 189 /***************************************************** + 190 *:void SSI_TWI_Cmd(FunctionalState NewState) + 191 *:TWIܿغ + 192 *ڲ:FunctionalState NewState /رѡ + 193 *ڲ:void + 194 *****************************************************/ + 195 void SSI_TWI_Cmd(FunctionalState NewState) + 196 { + 197 1 if(NewState != DISABLE) + 198 1 { + 199 2 SSCON0 |= 0X80; + 200 2 } + 201 1 else + 202 1 { + 203 2 SSCON0 &= (~0X80); + 204 2 } + 205 1 } + 206 + 207 /***************************************************** + 208 *:void SSI_TWI_SendData(uint8_t Data) + 209 *:TWI + 210 *ڲ: + 211 uint8_t:Data:͵ + 212 *ڲ:void + 213 *****************************************************/ + 214 void SSI_TWI_SendData(uint8_t Data) + 215 { + 216 1 SSDAT = Data; + 217 1 } + 218 + 219 /***************************************************** + 220 *:uint8_t SSI_TWI_ReceiveData(void) + 221 *:SSDATеֵ + 222 *ڲ:void + 223 *ڲ: + 224 uint8_t:TWIյ8λ + 225 *****************************************************/ + 226 uint8_t SSI_TWI_ReceiveData(void) + 227 { + 228 1 return SSDAT; + 229 1 } + 230 + 231 /************************************************** + 232 *:void SSI_UART1_Init(uint32_t UART1Fsys, uint32_t BaudRate, UART1_Mode_TypeDef Mode, UART1_RX_Typ + -eDef RxMode) + C51 COMPILER V9.59.0.0 SC92F_SSI 01/18/2024 10:03:12 PAGE 5 + + 233 *:UART1ʼú + 234 *ڲ: + 235 uint32_t:UART1Fsys:ϵͳʱƵ + 236 uint32_t:BaudRate: + 237 UART1_Mode_TypeDef:Mode:UART1ģʽ + 238 UART1_RX_TypeDef:RxMode:ѡ + 239 *ڲ:void + 240 **************************************************/ + 241 void SSI_UART1_Init(uint32_t UART1Fsys, + 242 uint32_t BaudRate, UART1_Mode_TypeDef Mode, + 243 UART1_RX_TypeDef RxMode) + 244 { + 245 1 + 246 1 #if defined (SC93F833x) || defined (SC93F843x) || defined (SC93F743x) + OTCON |= 0xC0; + SSCON0 = SSCON0 & 0X0F | Mode | RxMode; + SSCON2 = UART1Fsys / 16 / BaudRate / 256; + SSCON1 = UART1Fsys / 16 / BaudRate % 256; + + #else + 253 1 OTCON |= 0xC0; + 254 1 SSCON0 = SSCON0 & 0X0F | Mode | RxMode; + 255 1 SSCON2 = UART1Fsys / BaudRate / 256; + 256 1 SSCON1 = UART1Fsys / BaudRate % 256; + 257 1 + 258 1 #endif + 259 1 + 260 1 + 261 1 } + 262 + 263 bit SSI_FLAG = 0; + 264 /***************************************************** + 265 *:void SSI_UART1_SendData8(uint8_t Data) + 266 *:UART18λ + 267 *ڲ: + 268 uint8_t:Data:͵ + 269 *ڲ:void + 270 *****************************************************/ + 271 void SSI_UART1_SendData8(uint8_t Data) + 272 { + 273 1 SSI_FLAG = 1; + 274 1 SSDAT = Data; + 275 1 while( SSI_FLAG == 1 ); + 276 1 } + 277 + 278 + 279 + 280 /***************************************************** + 281 *:uint8_t SSI_UART1_ReceiveData8(void) + 282 *:SSDATеֵ + 283 *ڲ:void + 284 *ڲ: + 285 uint8_t:UARTյ8λ + 286 *****************************************************/ + 287 uint8_t SSI_UART1_ReceiveData8(void) + 288 { + 289 1 return SSDAT; + 290 1 } + 291 + 292 /***************************************************** + 293 *:void SSI_UART1_SendData9(uint16_t Data) + 294 *:UART19λ + C51 COMPILER V9.59.0.0 SC92F_SSI 01/18/2024 10:03:12 PAGE 6 + + 295 *ڲ: + 296 uint16_t:Data:͵ + 297 *ڲ:void + 298 *****************************************************/ + 299 void SSI_UART1_SendData9(uint16_t Data) + 300 { + 301 1 uint8_t Data_9Bit; + 302 1 Data_9Bit = (Data >> 8); + 303 1 + 304 1 if(Data_9Bit) + 305 1 { + 306 2 SSCON0 |= 0x08; + 307 2 } + 308 1 else + 309 1 { + 310 2 SSCON0 &= 0xf7; + 311 2 } + 312 1 + 313 1 SSDAT = (uint8_t)Data; + 314 1 } + 315 + 316 /***************************************************** + 317 *:uint16_t SSI_UART1_ReceiveData9(void) + 318 *:SSDATеֵھλֵ + 319 *ڲ:void + 320 *ڲ: + 321 uint16_t:յ + 322 *****************************************************/ + 323 uint16_t SSI_UART1_ReceiveData9(void) + 324 { + 325 1 uint16_t Data9; + 326 1 Data9 = SSDAT + ((uint16_t)(SSCON0 & 0X04) << 6); + 327 1 SSCON0 &= 0XFB; + 328 1 return Data9; + 329 1 } + 330 + 331 /***************************************************** + 332 *:void SSI_ITConfig(FunctionalState NewState, PriorityStatus Priority) + 333 *:SSIжϳʼ + 334 *ڲ: + 335 FunctionalState:NewState:жʹ/رѡ + 336 PriorityStatus:Priority:жȼѡ + 337 *ڲ:void + 338 *****************************************************/ + 339 void SSI_ITConfig(FunctionalState NewState, + 340 PriorityStatus Priority) + 341 { + 342 1 if(NewState != DISABLE) + 343 1 { + 344 2 IE1 |= 0x01; + 345 2 } + 346 1 else + 347 1 { + 348 2 IE1 &= 0xFE; + 349 2 } + 350 1 + 351 1 /************************************************************/ + 352 1 if(Priority != LOW) + 353 1 { + 354 2 IP1 |= 0x01; + 355 2 } + 356 1 else + C51 COMPILER V9.59.0.0 SC92F_SSI 01/18/2024 10:03:12 PAGE 7 + + 357 1 { + 358 2 IP1 &= 0xFE; + 359 2 } + 360 1 } + 361 + 362 /***************************************************** + 363 *:FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef SSI_FLAG) + 364 *:SSI־״̬ + 365 *ڲ: + 366 SSI_Flag_TypeDef:SSI_FLAG:ȡı־λ + 367 *ڲ: + 368 FlagStatus:SSI־λ״̬ + 369 *****************************************************/ + 370 FlagStatus SSI_GetFlagStatus(SSI_Flag_TypeDef + 371 SSI_FLAG) + 372 { + 373 1 FlagStatus bitstatus = RESET; + 374 1 + 375 1 if((SSI_FLAG == SPI_FLAG_SPIF) || + 376 1 (SSI_FLAG == SPI_FLAG_WCOL) || + 377 1 (SSI_FLAG == SPI_FLAG_TXE)) + 378 1 { + 379 2 if((SSI_FLAG & SSCON1) != (uint8_t)RESET) + 380 2 { + 381 3 bitstatus = SET; + 382 3 } + 383 2 else + 384 2 { + 385 3 bitstatus = RESET; + 386 3 } + 387 2 } + 388 1 else + 389 1 { + 390 2 if((SSI_FLAG & SSCON0) != (uint8_t)RESET) + 391 2 { + 392 3 bitstatus = SET; + 393 3 } + 394 2 else + 395 2 { + 396 3 bitstatus = RESET; + 397 3 } + 398 2 } + 399 1 + 400 1 return bitstatus; + 401 1 } + 402 + 403 /***************************************************** + 404 *:void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) + 405 *:SSI־״̬ + 406 *ڲ: + 407 SSI_Flag_TypeDef:SSI_FLAG:ı־λ + 408 *ڲ:void + 409 *****************************************************/ + 410 void SSI_ClearFlag(SSI_Flag_TypeDef SSI_FLAG) + 411 { + 412 1 if((SSI_FLAG == SPI_FLAG_SPIF) || + 413 1 (SSI_FLAG == SPI_FLAG_WCOL) || + 414 1 (SSI_FLAG == SPI_FLAG_TXE)) + 415 1 { + 416 2 SSCON1 &= (~SSI_FLAG); + 417 2 } + 418 1 else + C51 COMPILER V9.59.0.0 SC92F_SSI 01/18/2024 10:03:12 PAGE 8 + + 419 1 { + 420 2 SSCON0 &= (~SSI_FLAG); + 421 2 } + 422 1 } + 423 #endif + 424 + 425 /******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 413 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- 16 + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = 1 ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/sc92f_timer0.lst b/Keil_C/List/sc92f_timer0.lst new file mode 100644 index 0000000..e9f8230 --- /dev/null +++ b/Keil_C/List/sc92f_timer0.lst @@ -0,0 +1,202 @@ +C51 COMPILER V9.59.0.0 SC92F_TIMER0 01/18/2024 10:03:12 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE SC92F_TIMER0 +OBJECT MODULE PLACED IN ..\Output\sc92f_timer0.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_timer0.c LARGE OBJECTADVANCED OPTIMIZE(8,SI + -ZE) BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\sc92f_t + -imer0.lst) OBJECT(..\Output\sc92f_timer0.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ: sc92f_tiemr0.c + 4 // : ԪӦŶ + 5 // ģ鹦: TIMER0̼⺯Cļ + 6 // : 2022323 + 7 // 汾: V1.10002 + 8 // ˵: + 9 //************************************************************* + 10 + 11 #include "sc92f_timer0.h" + 12 + 13 /************************************************** + 14 *:void TIM0_DeInit(void) + 15 *:TIMER0ؼĴλȱʡֵ + 16 *ڲ:void + 17 *ڲ:void + 18 **************************************************/ + 19 void TIM0_DeInit(void) + 20 { + 21 1 TMOD &= 0XF0; + 22 1 TCON &= 0XCD; + 23 1 TMCON &= 0XFE; + 24 1 TH0 = 0X00; + 25 1 TL0 = 0X00; + 26 1 ET0 = 0; + 27 1 IPT0 = 0; + 28 1 } + 29 + 30 /************************************************** + 31 *:void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef TIM0_PrescalerSelection, TIM0_CountMode_TypeDef TIM0 + -_CountMode) + 32 *:TIMER0ú + 33 *ڲ: + 34 TIM0_PresSel_TypeDef:TIM0_PrescalerSelection:ԤƵѡ + 35 TIM0_CountMode_TypeDef:TIM0_CountMode:/ʱģʽѡ + 36 *ڲ:void + 37 **************************************************/ + 38 void TIM0_TimeBaseInit(TIM0_PresSel_TypeDef + 39 TIM0_PrescalerSelection, + 40 TIM0_CountMode_TypeDef TIM0_CountMode) + 41 { + 42 1 if(TIM0_PrescalerSelection == + 43 1 TIM0_PRESSEL_FSYS_D12) + 44 1 { + 45 2 TMCON &= 0XFE; + 46 2 } + 47 1 else + 48 1 if(TIM0_PrescalerSelection == + 49 1 TIM0_PRESSEL_FSYS_D1) + 50 1 { + 51 2 TMCON |= 0X01; + 52 2 } + C51 COMPILER V9.59.0.0 SC92F_TIMER0 01/18/2024 10:03:12 PAGE 2 + + 53 1 + 54 1 if(TIM0_CountMode == TIM0_MODE_TIMER) + 55 1 { + 56 2 TMOD &= 0xFB; + 57 2 } + 58 1 else + 59 1 if(TIM0_CountMode == TIM0_MODE_COUNTER) + 60 1 { + 61 2 TMOD |= 0x04; + 62 2 } + 63 1 } + 64 + 65 /************************************************** + 66 *:void TIM0_WorkMode0Config(uint16_t TIM0_SetCounter) + 67 *:TIMER0ģʽ0ú + 68 *ڲ: + 69 uint16_t:TIM0_SetCounter:üֵ + 70 *ڲ:void + 71 **************************************************/ + 72 void TIM0_WorkMode0Config(uint16_t + 73 TIM0_SetCounter) + 74 { + 75 1 TMOD &= 0XFC; + 76 1 TL0 = (uint8_t)TIM0_SetCounter; + 77 1 TH0 = (TIM0_SetCounter >> 5); + 78 1 } + 79 + 80 /************************************************** + 81 *:void TIM0_WorkMode1Config(uint16_t TIM0_SetCounter) + 82 *:TIMER0ģʽ1ú + 83 *ڲ: + 84 uint16_t:TIM0_SetCounter:üֵ + 85 *ڲ:void + 86 **************************************************/ + 87 void TIM0_WorkMode1Config(uint16_t + 88 TIM0_SetCounter) + 89 { + 90 1 TMOD &= 0XFC; + 91 1 TMOD |= 0X01; + 92 1 TL0 = TIM0_SetCounter % 256; + 93 1 TH0 = TIM0_SetCounter / 256; + 94 1 } + 95 + 96 /************************************************** + 97 *:void TIM0_WorkMode2Config(uint8_t TIM0_SetCounter) + 98 *:TIMER0ģʽ2ú + 99 *ڲ: + 100 uint8_t:TIM0_SetCounter:üֵ + 101 *ڲ:void + 102 **************************************************/ + 103 void TIM0_WorkMode2Config(uint8_t TIM0_SetCounter) + 104 { + 105 1 TMOD &= 0XFC; + 106 1 TMOD |= 0X02; + 107 1 TL0 = TIM0_SetCounter; + 108 1 TH0 = TIM0_SetCounter; + 109 1 } + 110 + 111 /************************************************** + 112 *:void TIM0_WorkModeConfig(TIM0_WorkMode_TypeDef TIM0_WorkMode, uint16_t TIM0_SetCounter1, uint16_ + -t TIM0_SetCounter2) + 113 *:TIMER0ģʽú + C51 COMPILER V9.59.0.0 SC92F_TIMER0 01/18/2024 10:03:12 PAGE 3 + + 114 *ڲ: + 115 TIM0_WorkMode_TypeDef:TIM0_WorkMode:TIMER0ģʽѡ + 116 uint16_t:TIM0_SetCounter1:TIMER0ֵ1 + 117 uint16_t:TIM0_SetCounter2:TIMER0ֵ2 + 118 *ڲ:void + 119 **************************************************/ + 120 void TIM0_WorkModeConfig(TIM0_WorkMode_TypeDef + 121 TIM0_WorkMode, uint16_t TIM0_SetCounter1, + 122 uint16_t TIM0_SetCounter2) + 123 { + 124 1 switch (TIM0_WorkMode) + 125 1 { + 126 2 case TIM0_WORK_MODE0: + 127 2 TIM0_WorkMode0Config(TIM0_SetCounter1); + 128 2 break; + 129 2 + 130 2 case TIM0_WORK_MODE1: + 131 2 TIM0_WorkMode1Config(TIM0_SetCounter1); + 132 2 break; + 133 2 + 134 2 case TIM0_WORK_MODE2: + 135 2 TIM0_WorkMode2Config(TIM0_SetCounter1); + 136 2 break; + 137 2 + 138 2 case TIM0_WORK_MODE3: + 139 2 TIM0_WorkMode3Config(TIM0_SetCounter1, + 140 2 TIM0_SetCounter2); + 141 2 break; + 142 2 default: + 143 2 break; + 144 2 } + 145 1 } + 146 + 147 /************************************************** + 148 *:void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, uint8_t TIM1_SetCounter) + 149 *:TIMER0ģʽ3ú + 150 *ڲ: + 151 uint8_t:TIM0_SetCounter:TIMER0_TL0ֵ + 152 uint8_t:TIM1_SetCounter + 153 TIMER0_TH0ֵ + 154 *ڲ:void + 155 **************************************************/ + 156 void TIM0_WorkMode3Config(uint8_t TIM0_SetCounter, + 157 uint8_t TIM1_SetCounter) + 158 { + 159 1 TMOD |= 0X03; + 160 1 TL0 = TIM0_SetCounter; + 161 1 TH0 = TIM1_SetCounter; + 162 1 } + 163 + 164 + 165 /******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 204 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- 2 + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + C51 COMPILER V9.59.0.0 SC92F_TIMER0 01/18/2024 10:03:12 PAGE 4 + + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/sc92f_timer1.lst b/Keil_C/List/sc92f_timer1.lst new file mode 100644 index 0000000..6c624a3 --- /dev/null +++ b/Keil_C/List/sc92f_timer1.lst @@ -0,0 +1,174 @@ +C51 COMPILER V9.59.0.0 SC92F_TIMER1 01/18/2024 10:03:13 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE SC92F_TIMER1 +OBJECT MODULE PLACED IN ..\Output\sc92f_timer1.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\FWLib\SC92F_Lib\src\sc92f_timer1.c LARGE OBJECTADVANCED OPTIMIZE(8,SI + -ZE) BROWSE INCDIR(..\FWLib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\sc92f_t + -imer1.lst) OBJECT(..\Output\sc92f_timer1.obj) + +line level source + + 1 //************************************************************ + 2 // Copyright (c) Ԫ΢޹˾ + 3 // ļ: sc92f_timer1.c + 4 // : ԪӦŶ + 5 // ģ鹦: TIMER1̼⺯Cļ + 6 // ֲб: + 7 // : 2022323 + 8 // 汾: V1.10001 + 9 // ˵:ļSC92FϵоƬ + 10 //************************************************************* + 11 #include "sc92f_timer1.h" + 12 + 13 /************************************************** + 14 *:void TIM1_DeInit(void) + 15 *:TIMER1ؼĴλȱʡֵ + 16 *ڲ:void + 17 *ڲ:void + 18 **************************************************/ + 19 void TIM1_DeInit(void) + 20 { + 21 1 TMOD &= 0X0F; + 22 1 TCON &= 0X37; + 23 1 TMCON &= 0XFD; + 24 1 TH1 = 0X00; + 25 1 TL1 = 0X00; + 26 1 ET1 = 0; + 27 1 IPT1 = 0; + 28 1 } + 29 + 30 /************************************************** + 31 *:void TIM1_TimeBaseInit(TIM1_PresSel_TypeDef TIM1_PrescalerSelection, TIM1_CountMode_TypeDef TIM1 + -_CountMode) + 32 *:TIMER1ú + 33 *ڲ: + 34 TIM1_PresSel_TypeDef:TIM1_PrescalerSelection:ԤƵѡ + 35 TIM1_CountMode_TypeDef:TIM1_CountMode:/ʱģʽѡ + 36 *ڲ:void + 37 **************************************************/ + 38 void TIM1_TimeBaseInit(TIM1_PresSel_TypeDef TIM1_PrescalerSelection, + 39 TIM1_CountMode_TypeDef TIM1_CountMode) + 40 { + 41 1 //жǷҪзƵ + 42 1 if(TIM1_PrescalerSelection == TIM1_PRESSEL_FSYS_D12) + 43 1 { + 44 2 TMCON &= 0xFD; + 45 2 } + 46 1 else if(TIM1_PrescalerSelection == TIM1_PRESSEL_FSYS_D1) + 47 1 { + 48 2 TMCON |= 0x02; + 49 2 } + 50 1 + 51 1 //TIM1ģʽ + 52 1 if(TIM1_CountMode == TIM1_MODE_TIMER) + C51 COMPILER V9.59.0.0 SC92F_TIMER1 01/18/2024 10:03:13 PAGE 2 + + 53 1 { + 54 2 TMOD &= 0xBF; + 55 2 } + 56 1 else if(TIM1_CountMode == TIM1_MODE_COUNTER) + 57 1 { + 58 2 TMOD |= 0x40; + 59 2 } + 60 1 } + 61 + 62 /************************************************** + 63 *:void TIM1_WorkMode0Config(uint16_t TIM1_SetCounter) + 64 *:TIMER1ģʽ0ú + 65 *ڲ: + 66 uint16_t:TIM1_SetCounter:üֵ + 67 *ڲ:void + 68 **************************************************/ + 69 void TIM1_WorkMode0Config(uint16_t + 70 TIM1_SetCounter) + 71 { + 72 1 TMOD &= 0XCF; + 73 1 TL1 = (uint8_t)TIM1_SetCounter; + 74 1 TH1 = (TIM1_SetCounter >> 5); + 75 1 } + 76 + 77 /************************************************** + 78 *:void TIM1_WorkMode1Config(uint16_t TIM1_SetCounter) + 79 *:TIMER1ģʽ1ú + 80 *ڲ: + 81 uint16_t:TIM1_SetCounter:üֵ + 82 *ڲ:void + 83 **************************************************/ + 84 void TIM1_WorkMode1Config(uint16_t + 85 TIM1_SetCounter) + 86 { + 87 1 TMOD &= 0XCF; + 88 1 TMOD |= 0X10; + 89 1 TL1 = TIM1_SetCounter % 256; + 90 1 TH1 = TIM1_SetCounter / 256; + 91 1 } + 92 + 93 /************************************************** + 94 *:void TIM1_WorkMode2Config(uint8_t TIM1_SetCounter) + 95 *:TIMER1ģʽ2ú + 96 *ڲ: + 97 uint8_t:TIM1_SetCounter:üֵ + 98 *ڲ:void + 99 **************************************************/ + 100 void TIM1_WorkMode2Config(uint8_t TIM1_SetCounter) + 101 { + 102 1 TMOD &= 0XCF; + 103 1 TMOD |= 0X20; + 104 1 TL1 = TIM1_SetCounter; + 105 1 TH1 = TIM1_SetCounter; + 106 1 } + 107 + 108 /************************************************** + 109 *:void TIM1_WorkModeConfig(TIM1_WorkMode_TypeDef TIM1_WorkMode, uint16_t TIM1_SetCounter) + 110 *:TIMER1ģʽú + 111 *ڲ: + 112 TIM1_WorkMode_TypeDef:TIM1_WorkMode:TIMER1ģʽѡ + 113 uint16_t:TIM1_SetCounter:TIMER1ֵ + 114 *ڲ:void + C51 COMPILER V9.59.0.0 SC92F_TIMER1 01/18/2024 10:03:13 PAGE 3 + + 115 **************************************************/ + 116 void TIM1_WorkModeConfig(TIM1_WorkMode_TypeDef + 117 TIM1_WorkMode, uint16_t TIM1_SetCounter) + 118 { + 119 1 switch(TIM1_WorkMode) + 120 1 { + 121 2 case TIM1_WORK_MODE0: + 122 2 TIM1_WorkMode0Config(TIM1_SetCounter); + 123 2 break; + 124 2 + 125 2 case TIM1_WORK_MODE1: + 126 2 TIM1_WorkMode1Config(TIM1_SetCounter); + 127 2 break; + 128 2 + 129 2 case TIM1_WORK_MODE2: + 130 2 TIM1_WorkMode2Config(TIM1_SetCounter); + 131 2 break; + 132 2 + 133 2 default: + 134 2 break; + 135 2 } + 136 1 } + 137 + 138 + 139 + 140 /******************* (C) COPYRIGHT 2020 SinOne Microelectronics *****END OF FILE****/ + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 157 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = ---- ---- + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/List/test.lst b/Keil_C/List/test.lst new file mode 100644 index 0000000..2b821f9 --- /dev/null +++ b/Keil_C/List/test.lst @@ -0,0 +1,111 @@ +C51 COMPILER V9.59.0.0 TEST 01/18/2024 10:03:10 PAGE 1 + + +C51 COMPILER V9.59.0.0, COMPILATION OF MODULE TEST +OBJECT MODULE PLACED IN ..\Output\test.obj +COMPILER INVOKED BY: D:\Keil_v5\C51\BIN\C51.EXE ..\Apps\test.c LARGE OBJECTADVANCED OPTIMIZE(8,SIZE) BROWSE INCDIR(..\FW + -Lib\SC92F_Lib\inc;..\User;..\Apps;..\Apps;..\User) DEFINE(SC92F836xB) DEBUG PRINT(..\List\test.lst) OBJECT(..\Output\tes + -t.obj) + +line level source + + 1 #include "test.h" + 2 + 3 extern bit it_5s_flag; + 4 extern bit it_2s_flag; + 5 extern bit it_1s_flag; + 6 + 7 extern bit it_10ms_flag; + 8 bit led_flag = 0;//ledƿر־ + 9 bit motor_flag = 0;//־ + 10 + 11 /***************************************************** + 12 *: led_test + 13 *: IOڡʱڲú + 14 *ڲvoid + 15 *ڲvoid + 16 *****************************************************/ + 17 void led_test() + 18 { + 19 1 //ָʾ + 20 1 if(it_1s_flag == 1)//1 + 21 1 { + 22 2 it_1s_flag = 0; + 23 2 if(led_flag) + 24 2 { + 25 3 led_flag = 0; + 26 3 GPIO_WriteHigh(GPIO0,GPIO_PIN_0);//P0.01ledƹر + 27 3 GPIO_WriteHigh(GPIO2,GPIO_PIN_6);//P2.61ledƹر + 28 3 GPIO_WriteHigh(GPIO2,GPIO_PIN_7);//P2.71ledƹر + 29 3 } + 30 2 else + 31 2 { + 32 3 led_flag = 1; + 33 3 GPIO_WriteLow(GPIO0,GPIO_PIN_0);//P0.00led + 34 3 GPIO_WriteLow(GPIO2,GPIO_PIN_6);//P2.60led + 35 3 GPIO_WriteLow(GPIO2,GPIO_PIN_7);//P2.70led + 36 3 } + 37 2 } + 38 1 } + 39 + 40 /***************************************************** + 41 *: motor_test + 42 *: Ʋú + 43 *ڲvoid + 44 *ڲvoid + 45 *****************************************************/ + 46 void motor_test() + 47 { + 48 1 bit t1,t2; + 49 1 t1 = GPIO_ReadPin(GPIO1,GPIO_PIN_4); + 50 1 t2 = GPIO_ReadPin(GPIO1,GPIO_PIN_5); + 51 1 motor_start(); + 52 1 motor_mov(2); + 53 1 if(~t1) + C51 COMPILER V9.59.0.0 TEST 01/18/2024 10:03:10 PAGE 2 + + 54 1 { + 55 2 FWD(); + 56 2 } + 57 1 if(~t2) + 58 1 { + 59 2 REV(); + 60 2 } + 61 1 if(it_5s_flag)//2붨ʱжϱ־ + 62 1 { + 63 2 it_5s_flag = 0;//־λ + 64 2 if(motor_flag) + 65 2 { + 66 3 motor_flag = 0; + 67 3 FWD();//ת + 68 3 GPIO_WriteLow(GPIO0,GPIO_PIN_0);//P0.00led + 69 3 } + 70 2 else + 71 2 { + 72 3 motor_flag = 1; + 73 3 REV();//ת + 74 3 GPIO_WriteHigh(GPIO0,GPIO_PIN_0);//P0.01ledƹر + 75 3 } + 76 2 + 77 2 } + 78 1 } + 79 + 80 + + +MODULE INFORMATION: STATIC OVERLAYABLE + CODE SIZE = 156 ---- + CONSTANT SIZE = ---- ---- + XDATA SIZE = ---- ---- + PDATA SIZE = ---- ---- + DATA SIZE = ---- ---- + IDATA SIZE = ---- ---- + BIT SIZE = 2 2 + EDATA SIZE = ---- ---- + HDATA SIZE = ---- ---- + XDATA CONST SIZE = ---- ---- + FAR CONST SIZE = ---- ---- +END OF MODULE INFORMATION. + + +C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S) diff --git a/Keil_C/Project/STARTUP.A51 b/Keil_C/Project/STARTUP.A51 new file mode 100644 index 0000000..7cf4ad8 --- /dev/null +++ b/Keil_C/Project/STARTUP.A51 @@ -0,0 +1,198 @@ +$NOMOD51 +;------------------------------------------------------------------------------ +; This file is part of the C51 Compiler package +; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc. +; Version 8.01 +; +; *** <<< Use Configuration Wizard in Context Menu >>> *** +;------------------------------------------------------------------------------ +; STARTUP.A51: This code is executed after processor reset. +; +; To translate this file use A51 with the following invocation: +; +; A51 STARTUP.A51 +; +; To link the modified STARTUP.OBJ file to your application use the following +; Lx51 invocation: +; +; Lx51 your object file list, STARTUP.OBJ controls +; +;------------------------------------------------------------------------------ +; +; User-defined Power-On Initialization of Memory +; +; With the following EQU statements the initialization of memory +; at processor reset can be defined: +; +; IDATALEN: IDATA memory size <0x0-0x100> +; Note: The absolute start-address of IDATA memory is always 0 +; The IDATA space overlaps physically the DATA and BIT areas. +IDATALEN EQU 100H +; +; XDATASTART: XDATA memory start address <0x0-0xFFFF> +; The absolute start address of XDATA memory +XDATASTART EQU 0 +; +; XDATALEN: XDATA memory size <0x0-0xFFFF> +; The length of XDATA memory in bytes. +XDATALEN EQU 100H +; +; PDATASTART: PDATA memory start address <0x0-0xFFFF> +; The absolute start address of PDATA memory +PDATASTART EQU 0H +; +; PDATALEN: PDATA memory size <0x0-0xFF> +; The length of PDATA memory in bytes. +PDATALEN EQU 0H +; +; +;------------------------------------------------------------------------------ +; +; Reentrant Stack Initialization +; +; The following EQU statements define the stack pointer for reentrant +; functions and initialized it: +; +; Stack Space for reentrant functions in the SMALL model. +; IBPSTACK: Enable SMALL model reentrant stack +; Stack space for reentrant functions in the SMALL model. +IBPSTACK EQU 0 ; set to 1 if small reentrant is used. +; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF> +; Set the top of the stack to the highest location. +IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +; Stack Space for reentrant functions in the LARGE model. +; XBPSTACK: Enable LARGE model reentrant stack +; Stack space for reentrant functions in the LARGE model. +XBPSTACK EQU 0 ; set to 1 if large reentrant is used. +; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1 +; +; +; Stack Space for reentrant functions in the COMPACT model. +; PBPSTACK: Enable COMPACT model reentrant stack +; Stack space for reentrant functions in the COMPACT model. +PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. +; +; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +;------------------------------------------------------------------------------ +; +; Memory Page for Using the Compact Model with 64 KByte xdata RAM +; Compact Model Page Definition +; +; Define the XDATA page used for PDATA variables. +; PPAGE must conform with the PPAGE set in the linker invocation. +; +; Enable pdata memory page initalization +PPAGEENABLE EQU 0 ; set to 1 if pdata object are used. +; +; PPAGE number <0x0-0xFF> +; uppermost 256-byte address of the page used for PDATA variables. +PPAGE EQU 0 +; +; SFR address which supplies uppermost address byte <0x0-0xFF> +; most 8051 variants use P2 as uppermost address byte +PPAGE_SFR DATA 0A0H +; +; +;------------------------------------------------------------------------------ + +; Standard SFR Symbols +ACC DATA 0E0H +B DATA 0F0H +SP DATA 81H +DPL DATA 82H +DPH DATA 83H + + NAME ?C_STARTUP + + +?C_C51STARTUP SEGMENT CODE +?STACK SEGMENT IDATA + + RSEG ?STACK + DS 1 + + EXTRN CODE (?C_START) + PUBLIC ?C_STARTUP + + CSEG AT 0 +?C_STARTUP: LJMP STARTUP1 + + RSEG ?C_C51STARTUP + +STARTUP1: + +IF IDATALEN <> 0 + MOV R0,#IDATALEN - 1 + CLR A +IDATALOOP: MOV @R0,A + DJNZ R0,IDATALOOP +ENDIF + +IF XDATALEN <> 0 + MOV DPTR,#XDATASTART + MOV R7,#LOW (XDATALEN) + IF (LOW (XDATALEN)) <> 0 + MOV R6,#(HIGH (XDATALEN)) +1 + ELSE + MOV R6,#HIGH (XDATALEN) + ENDIF + CLR A +XDATALOOP: MOVX @DPTR,A + INC DPTR + DJNZ R7,XDATALOOP + DJNZ R6,XDATALOOP +ENDIF + +IF PPAGEENABLE <> 0 + MOV PPAGE_SFR,#PPAGE +ENDIF + +IF PDATALEN <> 0 + MOV R0,#LOW (PDATASTART) + MOV R7,#LOW (PDATALEN) + CLR A +PDATALOOP: MOVX @R0,A + INC R0 + DJNZ R7,PDATALOOP +ENDIF + +IF IBPSTACK <> 0 +EXTRN DATA (?C_IBP) + + MOV ?C_IBP,#LOW IBPSTACKTOP +ENDIF + +IF XBPSTACK <> 0 +EXTRN DATA (?C_XBP) + + MOV ?C_XBP,#HIGH XBPSTACKTOP + MOV ?C_XBP+1,#LOW XBPSTACKTOP +ENDIF + +IF PBPSTACK <> 0 +EXTRN DATA (?C_PBP) + MOV ?C_PBP,#LOW PBPSTACKTOP +ENDIF + + MOV SP,#?STACK-1 + +; This code is required if you use L51_BANK.A51 with Banking Mode 4 +; Code Banking +; Select Bank 0 for L51_BANK.A51 Mode 4 +#if 0 +; Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4. +EXTRN CODE (?B_SWITCH0) + CALL ?B_SWITCH0 ; init bank mechanism to code bank 0 +#endif +; + LJMP ?C_START + + END diff --git a/Keil_C/Project/SinOne.soc b/Keil_C/Project/SinOne.soc new file mode 100644 index 0000000000000000000000000000000000000000..b1ac53340d45b009b2163c9fae7db151b9968399 GIT binary patch literal 254 zcmeZc@MBP52xmxT$YaQ2C}l8WFaSam1_p+|KyddiBaj6YUzV-kAG$CRwR-OVOwibO5i#~w% z6}$l9oM~rNSy*=QKgpfB=iED)JHO1`-ik`vQBGAAb)hqzs;-(Ybs*`(qLf=%+*nR8 zrL$JBh_i$qJWnMPNhPck1Pg)PCaqMYb(yQj%(cdFp^*2bL7GcLP zfz@W?Y@n0S^+4r+>FBR-h@K0Al&0@J>*)5bqnr7e`thT$z}NO_mFD~0MC+-eam&Zz z_rKVPN2_=5et|#p+^aO>k&I8YaJRwcj#2YD!xX;OVTp?U)kPKTx~{y++OsSl{?$@# zb^lyHCsb{4+ot+&-aPSl7`5NL#WUs_yKfdBvi literal 0 HcmV?d00001 diff --git a/Keil_C/Project/magent_test.uvgui.admin b/Keil_C/Project/magent_test.uvgui.admin new file mode 100644 index 0000000..5483c71 --- /dev/null +++ b/Keil_C/Project/magent_test.uvgui.admin @@ -0,0 +1,1860 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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-16776800
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### uVision Project, (C) Keil Software
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-16776800
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### uVision Project, (C) Keil Software
+ + + + <project name> + 0x0 + MCS-51 + 8 + + + SC92F8003 + SC92Fxx Series + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0-0xFF) CLOCK(16000000) + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 0 + SC92F8003.H + + + + + + + + + + + 0 + 0 + + + + SOC\ + SOC\ + + 0 + 0 + 0 + 0 + 1 + + ..\Output\ + project name + 1 + 0 + 1 + 1 + 1 + ..\List\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -p51 + S8051.DLL + + TP51.DLL + -p51 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 9 + + + + + + + + + + + + + + SinOne_Chip\SOC_Debug_Driver\SinOne_Chip_Debug_Driver.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4101 + + 0 + SinOne_Chip\SOC_Debug_Driver\SinOne_Chip_Debug_Driver.dll + "" () + + + + + 0 + + + + 2 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 0 + 0x0 + 0x100 + + + 0 + 0x0 + 0x100 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 9 + 2 + 0 + 1 + 1 + 0 + + + + + ..\FWLib\SC92F_Lib\inc;..\User + + + + 0 + 1 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 2 + 1 + + REMOVEUNUSED + + + + + + CODE(C:0X100), +CONST(C:0X100) + + + + + + + + + + + + + + + + + + + + + User + + + main.c + 1 + ..\User\main.c + + + SC_Init.c + 1 + ..\User\SC_Init.c + + + SC_it.c + 1 + ..\User\SC_it.c + + + SysFunVarDefine.c + 1 + ..\User\SysFunVarDefine.c + + + CompCtrlDefine.c + 1 + ..\User\CompCtrlDefine.c + + + + + Apps + + + Drivers + + + FWLib + + + sc92f_gpio.c + 1 + ..\FWLib\SC92F_Lib\src\sc92f_gpio.c + + + sc92f_option.c + 1 + ..\FWLib\SC92F_Lib\src\sc92f_option.c + + + + + Startup + + + STARTUP.A51 + 2 + .\STARTUP.A51 + + + + + + + + diff --git a/Keil_C/User/CallBackFunction.c b/Keil_C/User/CallBackFunction.c new file mode 100644 index 0000000..0502a44 --- /dev/null +++ b/Keil_C/User/CallBackFunction.c @@ -0,0 +1,14 @@ +//*************************************************************************************************** +// CopyRight (c) +// File Name : CallBackFunction.c +// Function : Write the logic you want to implement in the function body +// Version : V3.0 +// Date : 2022.07.14 +//*************************************************************************************************** +#include "SC_Init.h" +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/Keil_C/User/CompCtrlDefine.c b/Keil_C/User/CompCtrlDefine.c new file mode 100644 index 0000000..b57b2a5 --- /dev/null +++ b/Keil_C/User/CompCtrlDefine.c @@ -0,0 +1,14 @@ +//********************************************************************** +// CopyRight (c) +// File Name : CompCtrlDefine.C +// Function : Store composite control define +// Version : V3.2.0 +// Date : 2022.02.16 +///********************************************************************* +#include "SC_Init.h" +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/Keil_C/User/HeadFiles/CompCtrlDefine.h b/Keil_C/User/HeadFiles/CompCtrlDefine.h new file mode 100644 index 0000000..023e171 --- /dev/null +++ b/Keil_C/User/HeadFiles/CompCtrlDefine.h @@ -0,0 +1,13 @@ +//********************************************************************** +// CopyRight (c) +// File Name : CompCtrlDefine.h +// Function : Store composite control define +// Version : V3.2.0 +// Date : 2022.02.16 +///********************************************************************* +#ifndef COMP_CTRL_DEFINE_H + #define COMP_CTRL_DEFINE_H +#endif +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/Keil_C/User/HeadFiles/CustomType.h b/Keil_C/User/HeadFiles/CustomType.h new file mode 100644 index 0000000..98be2a6 --- /dev/null +++ b/Keil_C/User/HeadFiles/CustomType.h @@ -0,0 +1,19 @@ +//********************************************************************** +// CopyRight (c) +// File Name : CustomType.h +// Function : +// Version : V3.2.0 +// Date : 2022.02.16 +//********************************************************************** + +/***********************user_code_area*********************/ +/**/ +/**/ +/**********************.user_code_area.********************/ + +#ifndef CUSTOM_TYPE_H + #define CUSTOM_TYPE_H +#endif +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/Keil_C/User/HeadFiles/FunctionType.h b/Keil_C/User/HeadFiles/FunctionType.h new file mode 100644 index 0000000..d78c6e5 --- /dev/null +++ b/Keil_C/User/HeadFiles/FunctionType.h @@ -0,0 +1,19 @@ +//********************************************************************** +// CopyRight (c) +// File Name : Function.h +// Function : Store quote of the function +// Version : V3.2.0 +// Date : 2022.02.16 +//********************************************************************** + +/***********************user_code_area*********************/ +/**/ +/**/ +/**********************.user_code_area.********************/ + +#ifndef FUNCTION_H + #define FUNCTION_H +#endif +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/Keil_C/User/HeadFiles/SC_itExtern.h b/Keil_C/User/HeadFiles/SC_itExtern.h new file mode 100644 index 0000000..08023e7 --- /dev/null +++ b/Keil_C/User/HeadFiles/SC_itExtern.h @@ -0,0 +1,14 @@ +///**********************************************************************/ +// CopyRight (c) +// File Name : SC_itExtern.h +// Function : store extern var code +// Version : V3.2.0 +// Date : 2022.02.16 +///**********************************************************************/ +#ifndef SC_IT_EXTERN_H + #define SC_IT_EXTERN_H +#include "HeadFiles\SysFunVarDefine.h" +#endif +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/Keil_C/User/HeadFiles/SysFunVarDefine.h b/Keil_C/User/HeadFiles/SysFunVarDefine.h new file mode 100644 index 0000000..9c5cb23 --- /dev/null +++ b/Keil_C/User/HeadFiles/SysFunVarDefine.h @@ -0,0 +1,17 @@ +//********************************************************************** +// CopyRight (c) +// File Name : SysFunVarDefine.h +// Function : Store var control and function control extern +// Version : V3.2.0 +// Date : 2022.02.16 +//********************************************************************** +#ifndef SYS_FUN_VAR_DEFINE + #define SYS_FUN_VAR_DEFINE +#include "HeadFiles\CustomType.h" +#include "HeadFiles\UserExport.h" +#include "HeadFiles\FunctionType.h" +#include "HeadFiles\CompCtrlDefine.h" +#endif +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/Keil_C/User/HeadFiles/UserExport.h b/Keil_C/User/HeadFiles/UserExport.h new file mode 100644 index 0000000..9ed38cc --- /dev/null +++ b/Keil_C/User/HeadFiles/UserExport.h @@ -0,0 +1,21 @@ +//********************************************************************** +// CopyRight (c) +// File Name : UserExport.h +// Function : Store head files +// Version : V3.2.0 +// Date : 2022.02.16 +//********************************************************************** + +/***********************user_code_area*********************/ +/**/ +/**/ +/**********************.user_code_area.********************/ + +#ifndef USER_EXPORT_H + #define USER_EXPORT_H +#endif + +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ + diff --git a/Keil_C/User/SC_Init.c b/Keil_C/User/SC_Init.c new file mode 100644 index 0000000..19ba6d0 --- /dev/null +++ b/Keil_C/User/SC_Init.c @@ -0,0 +1,177 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_Init.c +// Function : Contains the MCU initialization function and its C file +// Instructions : +//************************************************************* + +#include "SC_Init.h" // MCU initialization header file, including all firmware library header files +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SC_itExtern.h" + +#include "motor.h" + +//************************************************************* + + +/***********************user_code_area*********************/ +/**/ +/**/ +/**********************.user_code_area.********************/ + +/***************************************************** +*: SC_Init +*: MCUʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_Init(void) +{ + SC_GPIO_Init(); + SC_OPTION_Init(); + SC_SSI_Init(); + SC_TIM0_Init(); + SC_TIM1_Init(); + //SC_ADC_Init(); + /*write initial function here*/ + //οѹ + ADC_VrefConfig(ADC_VREF_VDD); //ADC_VREF_VDD ADC_VREF_2_4V + EA = 1; + //ݳʼ + motor_data[0] = 0x00;//00 ֱг 01 г + motor_data[1] = 0x00;//00 ֹͣ 01 02 еʼλ 03 еλ + motor_data[2] = 0x00;//00 㶯 01 + motor_data[3] = 0x00;//00 ״̬ 01 ʼ 02 + motor_data[4] = 0x00;//ѹ8λ + motor_data[5] = 0x00;//ѹ8λ + motor_data[6] = 0x00;//ѹ8λ + motor_data[7] = 0x00;//ѹ8λ + motor_data[8] = 0x00;//ȸ8λ + motor_data[9] = 0x00;//ȵ8λ +} + +/***************************************************** +*: SC_OPTION_Init +*: OPTIONóʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_OPTION_Init(void) +{ + /*OPTION_Init write here*/ +} + +/***************************************************** +*: SC_GPIO_Init +*: GPIOʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_GPIO_Init(void) +{ + GPIO_Init(GPIO1, GPIO_PIN_4,GPIO_MODE_IN_HI); + GPIO_Init(GPIO1, GPIO_PIN_5,GPIO_MODE_IN_HI); + GPIO_Init(GPIO1, GPIO_PIN_6,GPIO_MODE_OUT_PP); + GPIO_Init(GPIO1, GPIO_PIN_7,GPIO_MODE_IN_HI); + GPIO_Init(GPIO2, GPIO_PIN_7,GPIO_MODE_OUT_PP); + GPIO_Init(GPIO2, GPIO_PIN_6,GPIO_MODE_OUT_PP); + GPIO_Init(GPIO2, GPIO_PIN_5,GPIO_MODE_OUT_PP); + GPIO_Init(GPIO0, GPIO_PIN_7,GPIO_MODE_OUT_PP); + GPIO_Init(GPIO0, GPIO_PIN_6,GPIO_MODE_OUT_PP); + GPIO_Init(GPIO0, GPIO_PIN_5,GPIO_MODE_IN_HI); + GPIO_Init(GPIO0, GPIO_PIN_4,GPIO_MODE_IN_PU); + GPIO_Init(GPIO0, GPIO_PIN_3,GPIO_MODE_OUT_PP); + GPIO_Init(GPIO0, GPIO_PIN_2,GPIO_MODE_OUT_PP); + GPIO_Init(GPIO0, GPIO_PIN_1,GPIO_MODE_OUT_PP); + GPIO_Init(GPIO0, GPIO_PIN_0,GPIO_MODE_OUT_PP); + /*GPIO_Init write here*/ +} + +/***************************************************** +*: SC_UART0_Init +*: UART0ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_UART0_Init(void) +{ + /*UART0_Init write here*/ +} + +/***************************************************** +*: SC_TIM0_Init +*: TIMER0ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_TIM0_Init(void) +{ + TIM0_TimeBaseInit(TIM0_PRESSEL_FSYS_D12,TIM0_MODE_TIMER); + TIM0_WorkModeConfig(TIM0_WORK_MODE1,55536, 0); + TIM0_ITConfig(ENABLE,LOW); + TIM0_Cmd(ENABLE); + /*TIM0_Init write here*/ +} + +/***************************************************** +*: SC_TIM1_Init +*: TIMER1ʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_TIM1_Init(void) +{ + TIM1_TimeBaseInit(TIM1_PRESSEL_FSYS_D1,TIM1_MODE_TIMER); + TIM1_WorkModeConfig(TIM1_WORK_MODE1,53536); + TIM1_ITConfig(ENABLE,LOW); + TIM1_Cmd(ENABLE); + /*TIM1_Init write here*/ +} + +/***************************************************** +*: SC_ADC_Init +*: ADCʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_ADC_Init(void) +{ + //ADתƵ + ADC_Init(ADC_PRESSEL_FHRC_D32,ADC_Cycle_6Cycle); + //οѹ + ADC_VrefConfig(ADC_VREF_VDD); + /*AIN0ģʽ*/ + //ADC_EAINConfig(ADC_EAIN_0,ENABLE); + + /*AIN2ģʽ*/ + //ADC_EAINConfig(ADC_EAIN_2,ENABLE); + + /*AIN1ģʽ*/ + ADC_EAINConfig(ADC_EAIN_1,ENABLE); + //AD1 ʹ + ADC_ChannelConfig(ADC_CHANNEL_1,ENABLE); + //ADж + ADC_ITConfig(ENABLE,LOW); + //ADʼת + ADC_Cmd(ENABLE); + /*ADC_Init write here*/ + + +} + + +/***************************************************** +*: SC_SSI_Init +*: SSIʼ +*ڲvoid +*ڲvoid +*****************************************************/ +void SC_SSI_Init(void) +{ + GPIO_Init(GPIO2, GPIO_PIN_1,GPIO_MODE_IN_PU); + GPIO_Init(GPIO2, GPIO_PIN_0,GPIO_MODE_IN_PU); + SSI_UART1_Init(12000000,9600,UART1_Mode_10B,UART1_RX_ENABLE); + SSI_ITConfig(ENABLE,LOW); + /*SSI_Init write here*/ +} + diff --git a/Keil_C/User/SC_Init.h b/Keil_C/User/SC_Init.h new file mode 100644 index 0000000..fa36a91 --- /dev/null +++ b/Keil_C/User/SC_Init.h @@ -0,0 +1,64 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_Init.h +// Function : Contains the MCU initialization function and its H file +// Instructions : +//************************************************************* + +/***********************user_code_area*********************/ +/**/ +/**/ +/**********************.user_code_area.********************/ + + +#ifndef _SC_INIT_H_ +#define _SC_INIT_H_ + +#if defined (SC95F8x1x) || defined (SC95F7x1x) || defined (SC95F8x2x) || defined (SC95F7x2x) || defined (SC95F8x3x) || defined (SC95F7x3x) \ + || defined (SC95F8x6x) || defined (SC95F7x6x) || defined (SC95F8x1xB) || defined (SC95F7x1xB) +#include "sc95f_conf.h" +#else +#include "sc92f_conf.h" +#endif + +void SC_Init(void); + +void SC_OPTION_Init(void); +void SC_GPIO_Init(void); +void SC_UART0_Init(void); +void SC_TIM0_Init(void); +void SC_TIM1_Init(void); +void SC_TIM2_Init(void); +void SC_TIM3_Init(void); +void SC_TIM4_Init(void); +void SC_PWM_Init(void); +void SC_PWM0_Init(void); +void SC_PWM1_Init(void); +void SC_INT_Init(void); +void SC_ADC_Init(void); +void SC_IAP_Init(void); +void SC_USCI0_Init(void); +void SC_USCI1_Init(void); +void SC_USCI2_Init(void); +void SC_BTM_Init(void); +void SC_CRC_Init(void); +void SC_WDT_Init(void); +void SC_PWR_Init(void); +void SC_DDIC_Init(void); +void SC_MDU_Init(void); +void SC_ACMP_Init(void); +void SC_USCI3_Init(void); +void SC_USCI4_Init(void); +void SC_USCI5_Init(void); +void SC_PWM2_Init(void); +void SC_PWM3_Init(void); +void SC_PWM4_Init(void); + +void SC_PGA_Init(void); +void SC_SSI_Init(void); +void SC_SSI0_Init(void); +void SC_SSI1_Init(void); +void SC_CHKSUM_Init(void); +void SC_LPD_Init(void); +#endif + diff --git a/Keil_C/User/SC_it.c b/Keil_C/User/SC_it.c new file mode 100644 index 0000000..b508afb --- /dev/null +++ b/Keil_C/User/SC_it.c @@ -0,0 +1,218 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_it.c +// Function : Interrupt Service Routine +// Instructions : +// Date : 2022/03/03 +// Version : V1.0002 +//************************************************************* +/********************Includes************************************************************************/ +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SC_itExtern.h" +#include "uart1.h" +#include "motor.h" +#include "adc.h" + +#define IT_5S_CNT 5000 //5000 +#define IT_2S_CNT 2000 //2000 +#define IT_1S_CNT 1000 //1000 +#define IT_100MS_CNT 100 //100 +#define IT_10MS_CNT 10 //10 +#define IT_1MS_CNT 1 //1 +#define IT_2MS_CNT 2 //2 +#define IT_3MS_CNT 3 //3 +#define IT_4MS_CNT 4 //4 +#define IT_5MS_CNT 5 //5 + +bit it_5s_flag = 0; //5sʱ־ +unsigned int xdata it_5s_cnt = 0; + +bit it_2s_flag = 0; //2sʱ־ +unsigned int xdata it_2s_cnt = 0; + +bit it_1s_flag = 0; //1sʱ־ +unsigned int xdata it_1s_cnt = 0; + +bit it_100ms_flag = 0; //100msʱ־ +unsigned int xdata it_100ms_cnt = 0; + +bit it_10ms_flag = 0; //10msʱ־ +unsigned int xdata it_10ms_cnt = 0; + +bit it_1ms_flag = 0; //1msʱ־ +unsigned int xdata it_1ms_cnt = 0; + +bit it_2ms_flag = 0; //2msʱ־ +unsigned int xdata it_2ms_cnt = 0; + +bit it_3ms_flag = 0; //3msʱ־ +unsigned int xdata it_3ms_cnt = 0; + +bit it_4ms_flag = 0; //4msʱ־ +unsigned int xdata it_4ms_cnt = 0; + +bit it_5ms_flag = 0; //5msʱ־ +unsigned int xdata it_5ms_cnt = 0; +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ + +void Timer0Interrupt() interrupt 1 +{ + /*TIM0_it write here begin*/ + + TH0 = 0xFC;//8λֵ + TL0 = 0x17;//8λֵ + + /*TIM0_it write here*/ + /**/ + /**//*<6>*/ + //Timer0Interrupt + { + /**//*<7>*/ + //5 + it_5s_cnt++; + if(it_5s_cnt >= IT_5S_CNT) + { + it_5s_flag = 1; + it_5s_cnt = 0; + } + + //2 + it_2s_cnt++; + if(it_2s_cnt >= IT_2S_CNT) + { + it_2s_flag = 1; + it_2s_cnt = 0; + } + + // + it_1s_cnt++; + if(it_1s_cnt >= IT_1S_CNT) + { + it_1s_flag = 1; + it_1s_cnt = 0; + } + + //100 + it_100ms_cnt++; + if(it_100ms_cnt >= IT_100MS_CNT) + { + it_100ms_flag = 1; + it_100ms_cnt = 0; + } + + //10 + it_10ms_cnt++; + if(it_10ms_cnt >= IT_10MS_CNT) + { + it_10ms_flag = 1; + it_10ms_cnt = 0; + } + + + /**//*<7>*/ + /**/ + } + /**//*<6>*/ + /**/ + /*Timer0Interrupt Flag Clear begin*/ + /*Timer0Interrupt Flag Clear end*/ +} + + +void Timer1Interrupt() interrupt 3 +{ + /*TIM1_it write here begin*/ + + TIM1_Mode1SetReloadCounter(53536); + + /*TIM1_it write here*/ + /**/ + /**/ + { + /**//*<7>*/ + //1 + it_1ms_cnt++; + if(it_1ms_cnt >= IT_1MS_CNT) + { + it_1ms_flag = 1; + it_1ms_cnt = 0; + } + + //2 + it_2ms_cnt++; + if(it_2ms_cnt >= IT_2MS_CNT) + { + it_2ms_flag = 1; + it_2ms_cnt = 0; + } + + //3 + it_3ms_cnt++; + if(it_3ms_cnt >= IT_3MS_CNT) + { + it_3ms_flag = 1; + it_3ms_cnt = 0; + } + + //4 + it_4ms_cnt++; + if(it_4ms_cnt >= IT_4MS_CNT) + { + it_4ms_flag = 1; + it_4ms_cnt = 0; + } + + //5 + it_5ms_cnt++; + if(it_5ms_cnt >= IT_5MS_CNT) + { + it_5ms_flag = 1; + it_5ms_cnt = 0; + } + /**//*<7>*/ + /**/ + } + /*Timer1Interrupt Flag Clear begin*/ + /*Timer1Interrupt Flag Clear end*/ +} + +void ADCInterrupt() interrupt 6 +{ +// /*ADC_it write here begin*/ + +// /**/ +// /**/ + + + /*ADCInterrupt Flag Clear end*/ + ADC_ClearFlag(); +} +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) \ +|| defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F8003)||defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F83Ax) \ +|| defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F740x) || defined (SC92FWxx) || defined (SC93F743x) || defined (SC93F833x) || defined (SC93F843x)\ +|| defined (SC92F848x) || defined (SC92F748x)|| defined (SC92F859x) || defined (SC92F759x) +extern bit SSI_FLAG; +void SSIInterrupt() interrupt 7 +{ + /*SSI_it write here begin*/ + if(SSI_GetFlagStatus(UART1_FLAG_TI) == SET) //UART1жϱ־λTI + { + SSI_FLAG = 0; + SSI_ClearFlag(UART1_FLAG_TI); + } + + if(SSI_GetFlagStatus(UART1_FLAG_RI) == SET)//UART1жϱ־λRI + { + unsigned char ch = 0; + ch = SSI_UART1_ReceiveData8(); + receive_ttl_data(ch);//Ŵжڣ + SSI_ClearFlag(UART1_FLAG_RI); + } + /*SSIInterrupt Flag Clear end*/ +} + +#endif + diff --git a/Keil_C/User/SC_it.h b/Keil_C/User/SC_it.h new file mode 100644 index 0000000..c1e3d23 --- /dev/null +++ b/Keil_C/User/SC_it.h @@ -0,0 +1,26 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_it.h +// Author : +// Function : Interrupt service program header file +// Local Functions: +// Date : 2022/04/07 +// Version : V1.3 +//************************************************************* + +/***********************user_code_area*********************/ +/**/ +/**/ +/**********************.user_code_area.********************/ + +#ifndef _SC_IT_H_ +#define _SC_IT_H_ + +#if defined (SC95F8x1x) || defined (SC95F7x1x) || defined (SC95F8x2x) || defined (SC95F7x2x) || defined (SC95F8x3x) || defined (SC95F7x3x) \ + || defined (SC95F8x6x) || defined (SC95F7x6x) || defined (SC95F8x1xB) || defined (SC95F7x1xB) +#include "sc95f_conf.h" +#else +#include "sc92f_conf.h" +#endif + +#endif diff --git a/Keil_C/User/SysFunVarDefine.c b/Keil_C/User/SysFunVarDefine.c new file mode 100644 index 0000000..e02a334 --- /dev/null +++ b/Keil_C/User/SysFunVarDefine.c @@ -0,0 +1,14 @@ +//********************************************************************** +// CopyRight (c) +// File Name : SysFunVarDefine.c +// Function : Store var control and function control define +// Version : V2.0 +// Date : 2021.08.04 +//********************************************************************** +#include "SC_Init.h" +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ diff --git a/Keil_C/User/Tmp/SC_it.bak b/Keil_C/User/Tmp/SC_it.bak new file mode 100644 index 0000000..19689e9 --- /dev/null +++ b/Keil_C/User/Tmp/SC_it.bak @@ -0,0 +1,272 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_it.c +// Function : Interrupt Service Routine +// Instructions : +// Date : 2022/03/03 +// Version : V1.0002 +//************************************************************* +/********************Includes************************************************************************/ +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SC_itExtern.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ +void INT0Interrupt() interrupt 0 +{ + TCON &= 0XFD;//Clear interrupt flag bit + /*INT0_it write here begin*/ + /*INT0_it write here*/ +/**/ + +/**/ + /*INT0Interrupt Flag Clear begin*/ + /*INT0Interrupt Flag Clear end*/ +} +void Timer0Interrupt() interrupt 1 +{ + /*TIM0_it write here begin*/ + TIM0_Mode1SetReloadCounter(53536); + /*TIM0_it write here*/ +/**/ + +/**//*<6>*/ + //Timer0Interrupt + { + /**//*<7>*/ + /*****User program*****/ + //<7>/**//*<7>*/ +/**/ + } + //<6>/**//*<6>*/ +/**/ + /*Timer0Interrupt Flag Clear begin*/ + /*Timer0Interrupt Flag Clear end*/ +} +void INT1Interrupt() interrupt 2 +{ + TCON &= 0XF7;//Clear interrupt flag bit + /*INT1_it write here begin*/ + /*INT1_it write here*/ +/**/ + +/**/ + /*INT1Interrupt Flag Clear begin*/ + /*INT1Interrupt Flag Clear end*/ +} +void Timer1Interrupt() interrupt 3 +{ + /*TIM1_it write here begin*/ + /*TIM1_it write here*/ +/**/ + +/**/ + /*Timer1Interrupt Flag Clear begin*/ + /*Timer1Interrupt Flag Clear end*/ +} +#if defined (SC92F742x) || defined (SC92F7490) +void SSI0Interrupt() interrupt 4 +{ + /*SSI0_it write here begin*/ + /*SSI0_it write here*/ +/**/ + +/**/ + /*SSI0Interrupt Flag Clear begin*/ + /*SSI0Interrupt Flag Clear end*/ +} +#else +void UART0Interrupt() interrupt 4 +{ + /*UART0_it write here begin*/ + /*UART0_it write here*/ +/**/ + +/**/ + /*UART0Interrupt Flag Clear begin*/ + /*UART0Interrupt Flag Clear end*/ +} +#endif +void Timer2Interrupt() interrupt 5 +{ + /*TIM2_it write here begin*/ + /*TIM2_it write here*/ +/**/ + +/**/ + /*Timer2Interrupt Flag Clear begin*/ + /*Timer2Interrupt Flag Clear end*/ +} +void ADCInterrupt() interrupt 6 +{ + /*ADC_it write here begin*/ + /*ADC_it write here*/ +/**/ + +/**/ + /*ADCInterrupt Flag Clear begin*/ + ADC_ClearFlag(); + /*ADCInterrupt Flag Clear end*/ +} +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) \ +|| defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F8003)||defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F83Ax) \ +|| defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F740x) || defined (SC92FWxx) || defined (SC93F743x) || defined (SC93F833x) || defined (SC93F843x)\ +|| defined (SC92F848x) || defined (SC92F748x)|| defined (SC92F859x) || defined (SC92F759x) +void SSIInterrupt() interrupt 7 +{ + /*SSI_it write here begin*/ + /*SSI_it write here*/ +/**/ + +/**/ + /*SSIInterrupt Flag Clear begin*/ + SSI_ClearFlag(UART1_FLAG_RI); +SSI_ClearFlag(UART1_FLAG_TI); + /*SSIInterrupt Flag Clear end*/ +} +#elif defined (SC92F742x) || defined (SC92F7490) +void SSI1Interrupt() interrupt 7 +{ + /*SSI1_it write here begin*/ + /*SSI1_it write here*/ +/**/ + +/**/ + /*SSI1Interrupt Flag Clear begin*/ + /*SSI1Interrupt Flag Clear end*/ +} +#else +void USCI0Interrupt() interrupt 7 +{ + /*USCI0_it write here begin*/ + /*USCI0_it write here*/ +/**/ + +/**/ + /*USCI0Interrupt Flag Clear begin*/ + /*USCI0Interrupt Flag Clear end*/ +} +#endif +void PWMInterrupt() interrupt 8 +{ + /*PWM_it write here begin*/ + /*PWM_it write here*/ +/**/ + +/**/ + /*PWMInterrupt Flag Clear begin*/ + /*PWMInterrupt Flag Clear end*/ +} +#if !defined (TK_USE_BTM) +void BTMInterrupt() interrupt 9 +{ + /*BTM_it write here begin*/ + /*BTM_it write here*/ +/**/ + +/**/ + /*BTMInterrupt Flag Clear begin*/ + /*BTMInterrupt Flag Clear end*/ +} +#endif +void INT2Interrupt() interrupt 10 +{ + /*INT2_it write here begin*/ + /*INT2_it write here*/ +/**/ + +/**/ + /*INT2Interrupt Flag Clear begin*/ + /*INT2Interrupt Flag Clear end*/ +} +void ACMPInterrupt() interrupt 12 +{ + /*ACMP_it write here begin*/ + /*ACMP_it write here*/ +/**/ + +/**/ + /*ACMPInterrupt Flag Clear begin*/ + /*ACMPInterrupt Flag Clear end*/ +} +void Timer3Interrupt() interrupt 13 +{ + /*Timer3_it write here begin*/ + /*Timer3_it write here*/ +/**/ + +/**/ + /*Timer3Interrupt Flag Clear begin*/ + /*Timer3Interrupt Flag Clear end*/ +} +void Timer4Interrupt() interrupt 14 +{ + /*Timer4_it write here begin*/ + /*Timer4_it write here*/ +/**/ + +/**/ + /*Timer4Interrupt Flag Clear begin*/ + /*Timer4Interrupt Flag Clear end*/ +} +void USCI1Interrupt() interrupt 15 +{ + /*USCI1_it write here begin*/ + /*USCI1_it write here*/ +/**/ + +/**/ + /*USCI1Interrupt Flag Clear begin*/ + /*USCI1Interrupt Flag Clear end*/ +} +void USCI2Interrupt() interrupt 16 +{ + /*USCI2_it write here begin*/ + /*USCI2_it write here*/ +/**/ + +/**/ + /*USCI2Interrupt Flag Clear begin*/ + /*USCI2Interrupt Flag Clear end*/ +} +void USCI3Interrupt() interrupt 17 +{ + /*USCI3_it write here begin*/ + /*USCI3_it write here*/ +/**/ + +/**/ + /*USCI3Interrupt Flag Clear begin*/ + /*USCI3Interrupt Flag Clear end*/ +} +void USCI4Interrupt() interrupt 18 +{ + /*USCI4_it write here begin*/ + /*USCI4_it write here*/ +/**/ + +/**/ + /*USCI4Interrupt Flag Clear begin*/ + /*USCI4Interrupt Flag Clear end*/ +} +void USCI5Interrupt() interrupt 19 +{ + /*USCI5_it write here begin*/ + /*USCI5_it write here*/ +/**/ + +/**/ + /*USCI5Interrupt Flag Clear begin*/ + /*USCI5Interrupt Flag Clear end*/ +} +void LPDInterrupt() interrupt 22 +{ + /*LPD_it write here begin*/ + /*LPD_it write here*/ +/**/ + +/**/ + /*LPDInterrupt Flag Clear begin*/ + /*LPDInterrupt Flag Clear end*/ +} diff --git a/Keil_C/User/Tmp/SC_it.tmp b/Keil_C/User/Tmp/SC_it.tmp new file mode 100644 index 0000000..eef6936 --- /dev/null +++ b/Keil_C/User/Tmp/SC_it.tmp @@ -0,0 +1,272 @@ +//************************************************************ +// Copyright (c) +// FileName : SC_it.c +// Function : Interrupt Service Routine +// Instructions : +// Date : 2022/03/03 +// Version : V1.0002 +//************************************************************* +/********************Includes************************************************************************/ +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SC_itExtern.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ +void INT0Interrupt() interrupt 0 +{ + TCON &= 0XFD;//Clear interrupt flag bit + /*INT0_it write here begin*/ + /*INT0_it write here*/ +/**/ + +/**/ + /*INT0Interrupt Flag Clear begin*/ + /*INT0Interrupt Flag Clear end*/ +} +void Timer0Interrupt() interrupt 1 +{ + /*TIM0_it write here begin*/ + TIM0_Mode1SetReloadCounter(53536); + /*TIM0_it write here*/ +/**/ + +/**//*<6>*/ + //Timer0Interrupt + { + /**//*<7>*/ + /*****User program*****/ + /**//*<7>*/ +/**/ + } + /**//*<6>*/ +/**/ + /*Timer0Interrupt Flag Clear begin*/ + /*Timer0Interrupt Flag Clear end*/ +} +void INT1Interrupt() interrupt 2 +{ + TCON &= 0XF7;//Clear interrupt flag bit + /*INT1_it write here begin*/ + /*INT1_it write here*/ +/**/ + +/**/ + /*INT1Interrupt Flag Clear begin*/ + /*INT1Interrupt Flag Clear end*/ +} +void Timer1Interrupt() interrupt 3 +{ + /*TIM1_it write here begin*/ + /*TIM1_it write here*/ +/**/ + +/**/ + /*Timer1Interrupt Flag Clear begin*/ + /*Timer1Interrupt Flag Clear end*/ +} +#if defined (SC92F742x) || defined (SC92F7490) +void SSI0Interrupt() interrupt 4 +{ + /*SSI0_it write here begin*/ + /*SSI0_it write here*/ +/**/ + +/**/ + /*SSI0Interrupt Flag Clear begin*/ + /*SSI0Interrupt Flag Clear end*/ +} +#else +void UART0Interrupt() interrupt 4 +{ + /*UART0_it write here begin*/ + /*UART0_it write here*/ +/**/ + +/**/ + /*UART0Interrupt Flag Clear begin*/ + /*UART0Interrupt Flag Clear end*/ +} +#endif +void Timer2Interrupt() interrupt 5 +{ + /*TIM2_it write here begin*/ + /*TIM2_it write here*/ +/**/ + +/**/ + /*Timer2Interrupt Flag Clear begin*/ + /*Timer2Interrupt Flag Clear end*/ +} +void ADCInterrupt() interrupt 6 +{ + /*ADC_it write here begin*/ + /*ADC_it write here*/ +/**/ + +/**/ + /*ADCInterrupt Flag Clear begin*/ + ADC_ClearFlag(); + /*ADCInterrupt Flag Clear end*/ +} +#if defined (SC92F854x) || defined (SC92F754x) ||defined (SC92F844xB) || defined (SC92F744xB)||defined (SC92F84Ax_2) || defined (SC92F74Ax_2)|| defined (SC92F846xB) \ +|| defined (SC92F746xB) || defined (SC92F836xB) || defined (SC92F736xB) || defined (SC92F8003)||defined (SC92F84Ax) || defined (SC92F74Ax) || defined (SC92F83Ax) \ +|| defined (SC92F73Ax) || defined (SC92F7003) || defined (SC92F740x) || defined (SC92FWxx) || defined (SC93F743x) || defined (SC93F833x) || defined (SC93F843x)\ +|| defined (SC92F848x) || defined (SC92F748x)|| defined (SC92F859x) || defined (SC92F759x) +void SSIInterrupt() interrupt 7 +{ + /*SSI_it write here begin*/ + /*SSI_it write here*/ +/**/ + +/**/ + /*SSIInterrupt Flag Clear begin*/ + SSI_ClearFlag(UART1_FLAG_RI); +SSI_ClearFlag(UART1_FLAG_TI); + /*SSIInterrupt Flag Clear end*/ +} +#elif defined (SC92F742x) || defined (SC92F7490) +void SSI1Interrupt() interrupt 7 +{ + /*SSI1_it write here begin*/ + /*SSI1_it write here*/ +/**/ + +/**/ + /*SSI1Interrupt Flag Clear begin*/ + /*SSI1Interrupt Flag Clear end*/ +} +#else +void USCI0Interrupt() interrupt 7 +{ + /*USCI0_it write here begin*/ + /*USCI0_it write here*/ +/**/ + +/**/ + /*USCI0Interrupt Flag Clear begin*/ + /*USCI0Interrupt Flag Clear end*/ +} +#endif +void PWMInterrupt() interrupt 8 +{ + /*PWM_it write here begin*/ + /*PWM_it write here*/ +/**/ + +/**/ + /*PWMInterrupt Flag Clear begin*/ + /*PWMInterrupt Flag Clear end*/ +} +#if !defined (TK_USE_BTM) +void BTMInterrupt() interrupt 9 +{ + /*BTM_it write here begin*/ + /*BTM_it write here*/ +/**/ + +/**/ + /*BTMInterrupt Flag Clear begin*/ + /*BTMInterrupt Flag Clear end*/ +} +#endif +void INT2Interrupt() interrupt 10 +{ + /*INT2_it write here begin*/ + /*INT2_it write here*/ +/**/ + +/**/ + /*INT2Interrupt Flag Clear begin*/ + /*INT2Interrupt Flag Clear end*/ +} +void ACMPInterrupt() interrupt 12 +{ + /*ACMP_it write here begin*/ + /*ACMP_it write here*/ +/**/ + +/**/ + /*ACMPInterrupt Flag Clear begin*/ + /*ACMPInterrupt Flag Clear end*/ +} +void Timer3Interrupt() interrupt 13 +{ + /*Timer3_it write here begin*/ + /*Timer3_it write here*/ +/**/ + +/**/ + /*Timer3Interrupt Flag Clear begin*/ + /*Timer3Interrupt Flag Clear end*/ +} +void Timer4Interrupt() interrupt 14 +{ + /*Timer4_it write here begin*/ + /*Timer4_it write here*/ +/**/ + +/**/ + /*Timer4Interrupt Flag Clear begin*/ + /*Timer4Interrupt Flag Clear end*/ +} +void USCI1Interrupt() interrupt 15 +{ + /*USCI1_it write here begin*/ + /*USCI1_it write here*/ +/**/ + +/**/ + /*USCI1Interrupt Flag Clear begin*/ + /*USCI1Interrupt Flag Clear end*/ +} +void USCI2Interrupt() interrupt 16 +{ + /*USCI2_it write here begin*/ + /*USCI2_it write here*/ +/**/ + +/**/ + /*USCI2Interrupt Flag Clear begin*/ + /*USCI2Interrupt Flag Clear end*/ +} +void USCI3Interrupt() interrupt 17 +{ + /*USCI3_it write here begin*/ + /*USCI3_it write here*/ +/**/ + +/**/ + /*USCI3Interrupt Flag Clear begin*/ + /*USCI3Interrupt Flag Clear end*/ +} +void USCI4Interrupt() interrupt 18 +{ + /*USCI4_it write here begin*/ + /*USCI4_it write here*/ +/**/ + +/**/ + /*USCI4Interrupt Flag Clear begin*/ + /*USCI4Interrupt Flag Clear end*/ +} +void USCI5Interrupt() interrupt 19 +{ + /*USCI5_it write here begin*/ + /*USCI5_it write here*/ +/**/ + +/**/ + /*USCI5Interrupt Flag Clear begin*/ + /*USCI5Interrupt Flag Clear end*/ +} +void LPDInterrupt() interrupt 22 +{ + /*LPD_it write here begin*/ + /*LPD_it write here*/ +/**/ + +/**/ + /*LPDInterrupt Flag Clear begin*/ + /*LPDInterrupt Flag Clear end*/ +} diff --git a/Keil_C/User/Tmp/main.bak b/Keil_C/User/Tmp/main.bak new file mode 100644 index 0000000..fd49fd2 --- /dev/null +++ b/Keil_C/User/Tmp/main.bak @@ -0,0 +1,39 @@ +//************************************************************ +// Copyright (c) +// FileName : main.c +// Module Function : +// Instructions : Contains the MCU initialization function and its H file +//************************************************************ +/********************Includes************************************************************************/ +#include "SC_Init.h" //MCU Init headerInclude all IC resource headers +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ +/***************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +******************************************************************************************************/ +void main(void) +{ + /**/ + +/**//*<3>*/ + SC_Init(); /*** MCU init***/ + //<3>/**//*<3>*/ +/**//*<4>*/ + /*****MainLoop*****/ + while(1) + { + /**//*<5>*/ + /*****User program*****/ + //<5>/**//*<5>*/ +/**/ + } + //<4>/**//*<4>*/ +/**/ +} diff --git a/Keil_C/User/Tmp/main.tmp b/Keil_C/User/Tmp/main.tmp new file mode 100644 index 0000000..ebf2efb --- /dev/null +++ b/Keil_C/User/Tmp/main.tmp @@ -0,0 +1,39 @@ +//************************************************************ +// Copyright (c) +// FileName : main.c +// Module Function : +// Instructions : Contains the MCU initialization function and its H file +//************************************************************ +/********************Includes************************************************************************/ +#include "SC_Init.h" //MCU Init headerInclude all IC resource headers +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" +/**************************************Generated by EasyCodeCube*************************************/ + +/*************************************.Generated by EasyCodeCube.************************************/ +/***************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +******************************************************************************************************/ +void main(void) +{ + /**/ + +/**//*<3>*/ + SC_Init(); /*** MCU init***/ + /**//*<3>*/ +/**//*<4>*/ + /*****MainLoop*****/ + while(1) + { + /**//*<5>*/ + /*****User program*****/ + /**//*<5>*/ +/**/ + } + /**//*<4>*/ +/**/ +} diff --git a/Keil_C/User/main.c b/Keil_C/User/main.c new file mode 100644 index 0000000..71a4a65 --- /dev/null +++ b/Keil_C/User/main.c @@ -0,0 +1,58 @@ +//************************************************************ +// Copyright (c) +// FileName : main.c +// Module Function : +// Instructions : Contains the MCU initialization function and its H file +//************************************************************ +/********************Includes************************************************************************/ +#include "SC_Init.h" //MCU Init headerInclude all IC resource headers +#include "SC_it.h" +#include "..\Drivers\SCDriver_list.h" +#include "HeadFiles\SysFunVarDefine.h" + +#include +#include "test.h" +#include "uart1.h" +#include "motor.h" +#include "adc.h" + +/**************************************Generated by EasyCodeCube*************************************/ + + +/*************************************.Generated by EasyCodeCube.************************************/ +/***************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +******************************************************************************************************/ +void main(void) +{ + SC_Init(); /*** MCU init***/ + InitUart_Data();//ݳʼ + + /*****MainLoop*****/ + while(1) + { + /**//*<5>*/ + //ݽշ(ôѭ) + Deal_Uart_Data_For_Module(); + + //иģʽ + Deal_Motor();//һ1-5 + + //ɼADC + if(it_10ms_flag == 1)//10 + { + it_10ms_flag = 0; + ADC_Multichannel();//ADCݲɼ + } + + //ָʾ + led_test(); + + } +} + + + diff --git a/Keil_C/User/readme.txt b/Keil_C/User/readme.txt new file mode 100644 index 0000000..bbc71df --- /dev/null +++ b/Keil_C/User/readme.txt @@ -0,0 +1,58 @@ +// +1IOڵԣʱʱշݣ +2ֹͣԶѰʼյ㣻 +3㶯Уÿε㶯ڣ㶯ɵڣλף +4ʼƶ㣬ƶ̿ɵڲλףÿһͣʱ䣨λ룩ͣʱڷڣͣһʱԶصʼ㡣ͣʱ趨λ룩 +5ʼ֮ѭƶƶ̿ɵڲλףÿһͣʱ䣨λ룩ͣʱڷڣ +6Թդźȷʼյ㣬ֻеͨդʱװòŻֵᷴ +7˽г̴߼ת̨ٱΪ190Էֱг̻ͬ +8ʼλλк״̬λ״̬ʾ + +//ʹ˵ + УʹúDeal_Uart_Data_For_Module(void)յݣʹúDeal_Motor(void)ƵʹúADC_Multichannel()ɼADCݡ + Ҫʹmotor_start(void)motor_mov(unsigned int speed)ǰţ壬speedɿƵʣرտʹmotor_stop(void) + FWD(void)REV(void)ڸıתҪжϴǰλãҪʹúmotor_seat(void)ʼλÿʹmov_begin(viod)mov_end(void)ôƶʼλλ + void mov_loop1(void)void mov_loop1_ang(void)void mov_loop2(void)void mov_loop2_ang(void)void mov_step(void)void mov_step_ang(void)Ƶģʽ + ڽҪʹreceive_ttl_data(uint8_t rx_data)Ҫʹsend_set_resp(unsigned int OrderNum, unsigned int addr, unsigned char Num, unsigned char sData[]) + +//Э +PC-> + SOF 1ֽ 0x05 ʼֽ + Len 2ֽ + Fou_adr 2ֽ Դַ + Com_adr 2ֽ Ŀַ0ffΪ㲥ַ + Cmd16 2ֽ + Request-data Nֽ + XOR 2ֽ У + END 1ֽ 0x1B ֽ +ݲ + ܣ 00 ֱг 01 г + ƵУ 00 ֹͣ 01 02 еʼλ 03 еλ + ģʽ 00 㶯 01 һ 02 + жȦΪһ 00 00 65535 + мʱ 00 00 65535루ݷʱ䣩 + 㡱ֹͣʱ 00 00 65535 +05 00 14 00 A1 00 B1 F0 01 00 01 01 00 01 03 E8 00 10 CD 40 1B//һ + +->PC + SOF 1ֽ 0x05 ʼֽ + Len 2ֽ + Fou_adr 2ֽ Դַ + Com_adr 2ֽ Ŀַ0ffΪ㲥ַ + Cmd16 2ֽ + Request-data Nֽ + XOR 2ֽ У + END 1ֽ 0x1B ֽ +ݲ + ܣ 00 ֱг 01 г + ƵУ 00 ֹͣ 01 02 еʼλ 03 еλ + ģʽ 00 㶯 01 һ 02 + λ״̬ 00 ״̬ 01 ʼλ 02 λ 03 ͨդ + ѹ 00 00 65535 + ѹ 00 00 65535 + ȣ 00 00 65535 +05 00 14 00 A1 00 B1 F0 01 00 01 01 03 07 03 00 00 00 10 CD 40 1B + +//ֱг̵תһȦˮƽλΪ5mm +//г̵תһȦת4㣻 + diff --git a/magent_test.cgen b/magent_test.cgen new file mode 100644 index 0000000..f5d7aff --- /dev/null +++ b/magent_test.cgen @@ -0,0 +1,89 @@ +[Project] +Project.Name=magent_test +Project.Path=D:\SinOne\file\magent_test +Project.KeilPath=D:\SinOne\file\magent_test\Keil_C\ +Project.CurrentPath=D:\SinOne\file\magent_test\magent_test.cgen +Project.CreationTime=20230203093907 +Project.ModificationTime=20230203093907 +Project.Version=EasyCodeCube 3.2.1 +Project.IsBootloaderProject=false +Project.IsUnifiedVersionProject=True +[/Project] +[WindowStyleSet] +[WindowStyle] +Name=CodeBrowser +Style=DockRightAutoHide +[/WindowStyle] +[WindowStyle] +Name=MainInterface +Style=Document +[/WindowStyle] +[WindowStyle] +Name=Designer +Style=Document +[/WindowStyle] +[/WindowStyleSet] +[Peripheral]GPIO_panel:{X=0,Y=0} +[/Peripheral] +[Peripheral]GPIO[Index]0[/Index] +[Configure][PinNumber]19[/PinNumber][UpperIndex]3[/UpperIndex][Iindex]0[/Iindex][PinName]RX1[/PinName] +[PinNumber]20[/PinNumber][UpperIndex]3[/UpperIndex][Iindex]0[/Iindex][PinName]TX1[/PinName] +[/Configure][/Peripheral] +[Peripheral]OPTION[Index]1[/Index] +[Configure]ϵͳʱFsys=0 +Ƶ(Hz)=[24000000] +Optionʹ=0 +ѡ=0 +ƵʷΧ=0 +οѹѡ=0 +λܽ=0 +LVR ѹѡ=0 +IAPΧ=0 +[/Configure][/Peripheral] +[Peripheral]UART1[Index]4[/Index] +[Configure]Ƶ=[12000000] +UART1=1 +BaudRate=[9600] +ģʽ=0 +ж=0 +ж־λ=True +$19$RX1ģʽ: +$20$TX1ģʽ: +[/Configure][/Peripheral] +[Peripheral]TIM0[Index]10[/Index] +[Configure]ʱ/ģʽ=0 +ʱģʽ=True +ʱ(us)=[1000] +ԤƵѡ=1 +ģʽ=1 +ֵ0=[53536] +ֵ1=[10] +Mode0ֵ=[8000] +Mode1ֵ=[53536] +Mode3ֵL=[100] +Mode3ֵH=[100] +ж=0 +TIM0ʹ=True +[/Configure][/Peripheral] +[Peripheral]ADC[Index]16[/Index] +[Configure]ʱԴԤƵ=0 +ʱ=0 +AIN0=True +AIN1=True +AIN2=True +AIN3=False +AIN4=False +AIN5=False +AIN6=False +AIN7=False +AIN8=False +AIN9=False +ѡ=1 +ж=0 +ADCܿѡ=True +ж־λ=True +$16$AIN2 +$17$AIN1 +$18$AIN0 +[/Configure][/Peripheral] +[PinMode]0[/PinMode] diff --git a/magent_test.fig b/magent_test.fig new file mode 100644 index 0000000..0a2f78d --- /dev/null +++ b/magent_test.fig @@ -0,0 +1 @@ +PMTnXKYzsaGAgOiUN5jCpIOvA3eXqU1velrZs+8nqmhp65mmMNzBHYpnK7Q6kCWWd7NUCuA2BE7rCK7EPl6IEMpaaI6/88MX5fvCHAwKgbd/rYO34aU4VqWXk4k0zyU+zzaqabKExk8utJET3pPvIJbq5IM26yDz6/snXA8ks3D77cFfm+bXFBxP61yj935bxT7SPQI/xKiwFHVG1OaD7R5CAjWug5+pQajnGOdS10GqXua1S7WIzDw40T1zVRfJ5Nk4ssyR1f5Gjx0DvD+v3bJ+mGy3dx42oe2TKo0TV1xMe4dF0RWKix/CVbXeKMD6oVZuc6+dPFPh+VhDLKT8kgJ/SvxwsmznX7wQynKehhKB7M5PGdrfHSJ+GpSAhmXGupSZNqjYy570J3/34jw62YWxo4SerHpXkEuqQltQGImpPTrNF9AjPiZxmt32xKCA7PC80NE0PbfHplsyt6L+bS4DBf0cakeOWtNftUb8ZtAUbUx8jGeJSvmDzXWRRg2+q33NY3eq0dqlA9CCsdtlMfAiKSxzVT3n0SNuTbrVE1ztO7UbowtfjNOQL9Imp67Yd1AGfHLp1jj03ehsuWLLmGZBgHQQ8bL0xGabAncEqbqt9lXxond9R2bwevKBrAFxVaWWtP7wnxZ4OT71pS+lueEQvmG1Mym4sm7p5tRA1KJ0+Fuck7L411t4pouD5o2auuZb6h1RYDXY6Hh1welNsBktmzw6UZw5sK8rxRuxUuswXwuLOKZ5rcgeJeujSsJISQQjo2IJqRvW2q8wqKPVditbp2fdjPbPmvkE7PEWETBJonJjkW5kHUb+ABhz7pMm+j5aqmVJZE6F1T+ycg/weNpgSlAbbZX/npKHrmmZRR8SYflxeJz05Vy6JNshxDCqIcfbI6gAEA6HchFSx77LGmgDoe4IUPWUBRcR0A/bO3bMw4bAaM7cTugpniEBiN3ZjkoNNPsHq6tCnNsSYwJRUpO+xYGRuZUgZrdVALy/Ys8J0l8KOa6ySPQQRzeUDW0R/RKVytvB0rZeGitQBBIjJgNdiSqnI8hvIgSe03DgqQsq/63nGQDan08ATwBRGDkcsQk70/TFbVN/ETzEKJEGmGZIqSFzlYk8vQVreLaTnkWDqgVvCqSc6IyQ/icRzQqPRu51MvnNo/8GOGo1pII5pjXYxkkDX1gHnrOt8crkbYv2LHzVOSOublvFxmPCFfJlGsmDRzXbrk9lgCvknox1CtlNSOphCePMsdmikg2XlvEtPGR9WwlHM8N2X6awMXN1JjmlR8g1mNXZpax6VgkCL23ZYBua1qYQPKmakkd6OBFc8ArshczenuPQd9nGgfbHKHufdwvgC3Mt3Kr4Yag7LNpISV/of6WPAdcuSLLx2iD/H2IV6XScSeplXXzBUgZl9H5eVcFwiLDk6fIMV6GZx/0qya6JZXMLUoyf00kMqfOGoUJGdsTApibYm4DdlNDlfbJsW+/UD4sD1iZaW97VgUV+2q/jEiUZCQ9W/2Cfno46+RsaRR6sbpmGdITBbDVB/XIFTrS8YmwJv5miehbeNzbfjMUjutdD6u/PcS3wBIrejLT0HOLEsWZL1DY3hnwSkhc4eUx4KyMgRkOZG8+b0bWNhqX6wKk/eRRF45rXUBqaufouZaZRC79KZRGVkq/9X0EBStPZMbC4r9W+fQg8YxjjJS/BkdMurjX707wVKMFFnttFAXRzmbhvgGOUGILNkSaKdPeTtfuluU6jizzF3uKHq2hFH+p+1P1YMTDCNhdHoVIo9tBKJKEctI47uSx+PD1Dp23hnfPvVqWUt+pnf1gDoK2XMvOd96KzyY3OmDCgjzz15Y66X+DM3rwGCp66ce3q2SL3oaZi9qkbq6vLE5UlHPFZ62IiF04sZBHcZXVpGXak02qy+cfnR2Fz9SCKm06/nZOnMoGJ1aoPHhbkvHQklQZ2X0IX8NjGC13KfBAAGbC+qriUx4X+DYbOrF+zzn84+mFVv6nq49XRT9yuhRs2ny7s5LBUGSFxj3poAfuth26nD336E14MQ+U/E7lpygtpT9dA++gZuPPWGkg/oO+NC87YIlQdObmQ/9rrIhvEcdRTugEXsfiCp20NwLSBgeVyU4aCyiXFgakZ2+2Cd5piHrgLruhHaBW7u++Em5ORgSvXMYRt/1OWZ7T84t8jPnkmM2bdOUaG2VqjiwoCyPRSc2InkELsz9PXzJIgidWJ1j+d6LUaQcfqeCuIs6wkpkRMaXOvckk5FFQi0/Sy3CkWqQn6JVpd5GyRgtu+FdXFIfQgv/NebZ6Wd7nRTfzshykmsVIVm7qnXJYuQJL9QMNTu3CJUUQ8EPXkEOKFUlzYvGChsNzqBF8Qw0wF0tcQR93zz1IgoLN8tZ59N4scS+Ye8mUGSntXY8QxVVqBcWw16xWyzqjATfgD15kC0YZ9SdvvIdnZL3a9tI9r6680B0umxVLEqJKi7cx8wyWqM7kzKJ+iKOQj9Wb/ccn5okDSS+MFxidUbnHgOMWxRCenm7RTQyTsKHbwMWnvypSfthYIDnN5EbcZJzpM7K2xl/C8Jf9IkaH1F+bt83TTap6CflCjVT2YO3ZuOuH4K4IFjbL/ptz9wXs3pAL4k0moj2rouzvfv5O8txrgP6WxmOalgBu8apv/vhNlTKquMDxZFZT/OKGEbYN56kGjqQJJ4ft6zAUKjnWrYWJq4aTo7Rl0Y1iippA2JsYhSsZMp2FVD8jH7o651TTczUqw9R1KsJvWFavDsPbucRQrTvbl5D2ULMWl0nAlyNerKZnJ/lxwOPGif3gRZmeZqb07HFHtIb9TPZaQiRAzujkF2WEwUy3YuI/6IgEF47nfKdDznHxtIhwVVnU9HllTLDbcAV8gAXeg5MMReKX2G2Q9VodJursBk940oQhUjMOOyilDA9gsdk5G8r5rj3oybJ+UPwaTJrm6u0zxoAEk3pGB4wAR+oaBziW8Q1RoyyySbMpIEUJK8lK34hoTu7Li+owm5ioNc240MWA8otykiM2wif5BCls3KKfmv8RXKGIqqRZSUuImurALjaU9o47eish3O6LBli1LMuxSp+3eXqK6kIe4TT8eJQ/lO8I0OTRnrLhvSrkJ7tmjuR9k1sDu0CXXp8sjwCdfgJkq0pLxAAo+1N94nqiV9RFTz3Pf4/Pz4nxiLZKCy0bJNUW88JPtWtLZTeyBT7p4Fq1qILuvNEm9ClpbhP5JnjepZt6dLX9BAWmido9Nczc8xzHz9E7US69OteggPcDZ4M7Pi6dUEqbh7mhSeVACYWqcHBpvVOQMNC0gYCmYAZboLonE9yV9x43g+JhdcqX1Jx5EcFDRaBxkbBlmae9b01pv+f9lev4yXeQ8wO4sdN64ljf3aqGxUR1ctyD3y7h2b3fNSFoFK5XtKayueOV1rbGQ5BS1NIbYkssmCu5NJnwxM60mUS7KGD1s1cmoC+Aew7dzbs7b2Zdr2tP90hkWnkybJ+TXKL5x98oWr7FigzN9+FPJjBdL3Mu6m104+nOj8prDahFTe1v2foDAhJu/fl9JQnMrKeWb9DLbo+fpmiqkJ8wfXbt81L0Bp2JfYqRLvwnke4mK8O9R1wtofy+vdcn0O9UT676F0QssXL7nC5nSyusz8WBwGqivtMivaWjB3HvI87R46c4ugjIB2TWFcWgMWSY+W2u2YtO6hxXvT2Y+ZVDYRS9Jm75tebmn78J0du0oXL4nK0SXc49S4CE1MkucsFV8VkQ+m9rD3jxMsHZEAE7FihW1Tq+wQ0MlPL1kozJsrT9KirzqnP9k95C9VHtCJNmTGrKpZcENONet7QLTX7AT7H6eWq+lGV6B2javczmQx/xoPFIv5zIVM/jrUnAOEhaq88S8Rsj2/gq3i7Lvcr0E46jxMqS1H+cG5iWjVqnYzIe32V9lTmB3mllMr+fmOk0tu+nb7XxeyXr2vEqUqtLN9JIVDx5zV+6zRlksJ5DH/ZT6QxPd86KMgQLmqHpJDFPmzKuxTNwq+iHG01u32IwyRvX/OjFO51Bc1tbP7w+tkKDOp+YL+AiD0T2+AyKK5hQCgK4WLseHDUhOQRhFNy8v6K1wD6fMM8+K5NUeZCYjXdye5L6k9ng1hwmMM4YgrkU2XiPHbz396bzc3XJz6GAhOxioI9T/Eba2nz7hVsexyXK7/fuOB8E0Y/e98Wvngu9AKoagh73UvA/2JojUm1P+ZDjxog2B4clKYAqGdlb2KidpcDe5TCnTc4P6KL/1++IQfgaBd6AcMcW5Kr/MTiINZHb42fwLlQs3Ddd3NzST9sKL0wc8WQckty/A8Xyr1e8Daz95qNsJqklUGV+6bYTltW0wZHUAqQIlszbdFOwcsBiJiBAfzQpNA5hl4RPKIWCPOPsd6j0AzHfnU2+eXvr73EUYoX0eJwfa/3YyAmjnGmVclEiVwQyq5O9jAjb5A0MhKMtSEUGw41Zt+KPIIw1SV37yznUXmfYefcEc5k23jvyqLKJ2bN2ynKiR51TSxk4b1i2WM4MpulMwATJs0w1AB9kSxhBMosmaR8ghFwEMMlEL7YWoGqh2fIogo6cUw2Yx6BG9XLWdikUwSUtyUZnNcQFLZZD/RsTcRcWKapbFtZFAp3fZiFQZ7Up91YwUvrc8xPfecLSNnpOMK+FnYcxlX38nvJKS8LAIqsLBTO2lhofH9cIx89zWCzvlGu1H11G3ioOojmMY6OF9wjoz0hXOKntj5ia2PX+AMl/Ezb0ELUPMllNJ6KJdHJu8V7zSDaPlXVxEbGC3UwaSpqi45ZJoE/mkIwy+MJFL0mK6vpwGix6I7+IQkME/KCsvA1C5a/lpIExYWmmhvu8mXR9Vc9OCJgkFFyE1rU1q8N/hB9OMqMQnSTbx/QFaQS5tZiAdaNZOAd6XtkOYwqwXzCusD1Mk7U1v+v4f/Acz1wo6/HicEeergaE+lHUVhxWFK2mn6WsBsP65wPEbh0ib0Y/B4tfx9UbXiD2KrFl9QD3XoySs75bkwPUC4PGSNTQ8/zvVcMmgXacSEllgv5g1hRx1oELcanLqfd6We1a6FYzWOgPzVHULC+FNytmyMC2YZf+snuH07+7TkZNkQh2Zgi1PNNdS/rLzBnnSoSUOma3z85/UbcO51RRi8097IV31127Kn15zlcWSQmUuxApPGTOGCmm8yqSMqFlQlibKOx8uPOy3OJjQ5QUDbyGsTeZimbH2NZcKNnqDMrReA0NMs58Canu6TUm58qvcBbP7tzvMQUI5J+wf6Jro0Ob7P2R37ponXhMRAH5MeFlofJl28XLtXt3V3DoFfDaJXZ1c5Pzdx4rkO7DA3hst18JW6xEzh1rMR/gcCGQ25+XPfSMplZAJW2lvopokqVKbKbdpJC0WVWUNajhliFYIABXrVMVN3wWvnROvToVGse0HvexjcUCsSfRMlOHCJzTCYTaJ5wYAI739kwaGHpQWGID5wQm7PMKCeHajEkyUIU6DVjdR4pYnSJQS3zdPRAJhfOeLP5faleXWyoeygitWlFpAEJrCs8A7lS79o4428gz7kDD0AjJOjHG+n0gCdPTgZVaQaC9bdaNOpnPkdnlG+h55x3vhzvpPDsPuM25dt/Cjb0Fk1L7ORfj2nTxLkWai3jTXDpyqLtFGLZhQpumPwkBZf2gZeJ8suZhyLtNrm5nqLDSm07jDudO2vxWc2Ib2cdb7MhyhqTr9cyt7lW7eAGwJq/9aPbCLhw6nNYG+5mkNmJ2wg43gGzlSubyhWB0rohuW3VLMqRcdUz3NKjk+f55+R0hPj/Y+TSZrb9ZcjMcV5wHzfnW2I6CMZWNvQN3QkbKCL2CIyj01ZzKV2juTeSkM6ShMNDaG6I0gMrm/zL2+Pa2899Lt5PBd1L4nou/LYpJsES9SkyMAz5wnBqvJ2GP2Mo6B0Su/XZpoqCiKOlfrJorIkEUZ3UKYV6eMu2EFhgmM7CM+VhoF4DbSWTaeW0YAWDrqAd0tj3a4AFZ0T+nd2P3OZ5qznKzW3XFZKgjDxcYpcBWPvKlTU1AY9EUmwkPqwWhKT6x7hCqy9DjWtIz24hP1X7sBtnv6chAZp7iMSuE/pxLI1nhrqQ6hxzcLt6ZcS7mlw3sIvQH0ksUh0cazW2lqP9cBGpuj0774L4yzlQgn0ujQVYQitiz7H2zQfsAP6TVPGB4Qd3gZr2ZcIYzJZJNpzYJNPnnwoSXmW2uNzFcSoi7l5KxsRre5NquTardirfgJIjqWOzIBYOWgJcTZinKWjxbcOM3QfOGSimMM6eurIvD61xiHIMqwkWwEuYu5GNf14VimztEsarGmzGGBnuI4jxVc4UmTRqtgpuJraBnMQT4EE1YjsiSjZGeAbiU6+DQoY+N4erPYy8OoDnfBEzeoumz1IoIlNkRPx81Q00eP7TtXE7bPUGv53Salon/guyMEV0u18qb91YUgo8cv53+OkF19CvVtu6MQ0b0uIBldxF4gRUBs5n3LN6sEvCFQZlDnDVR3+mmNh/lLu+4zpgVlSgd0P4YPSQjbggEM9zUXGG1mIUWDKPyTiTtLHFtClF8V/qlSseOZnHfsHRZloG0+/frgPkYwMuNv2PemFzg3x+eSd3KjDrTcMbqj4Tu49TkipSGvW24216pBtPvUQvvpX/3x78xyg5qMXYHEAcCZ1EfQi8PKBRDkzp4DuzFuXFlIT5PXz86k0tKamq/9rTG8NuZBdykAnzplOrn+gQ+JmE+5ew825DrgZn5UOsaNroV9td1KJgeppYl2IHjWRm5EOOKewzezdB1bQeWHg/pCGiKVd7Ots6+FVHLsnb61esLuvIwHrAvlD6HRxv7ajqfh8z/+KIwwkgi16xcY/djY9wDaMqFR0iK1Lcu2l9d650BGH55wdznVsFgHncKC/QFwojf1TKLdM9r9RIm+7zvjB2YMZwjkKZY8g9p86/wQhoWuQ0zbJDQjQqLpKHJ4y9KknC2RvYLaO2ivS+Ser6fouq7M0KBGY+dUY9Mj+XlNwD0ie+YJtwsfGyeMuPehNOxTFs5ejoJ3tEF8dguG+PemBGwTTfQ+sBwHa/pHHONxFvLK4UMiVYTYs48ColJz6V7Uvh7QHqnTDrn8nHsu5PvF2VQQOwN77yEtwRsAUnz0B1CPErxJSmacLvgePNYnt+VhNW5fhKsZTTM6v6iPbv/sHB/BUderjoiCQmGorBH01vdTKrOe1x1l2Qw0qkmkaWjSaM65zvnbUACNJjY7ew5TbUVB3ywAW5JPYyHpcQ2jOD5H/K0raHdaSI03FUS6hk/nuWK0ebQHyjM1e+sCV6YDEM3JcR/zYavjtT0hSvClPU8OeLVouFNuzr4XpJaSyuhJVPMbeBGHOy+KEiGKtYsjztoWneRzp3OkZ2YTSdtERDQJtnhAsyg/S9RcfkjkEylcupbbo7K0fcNVOw/fIv/EiPWYmDc5e5r+mT7xjYSs9L+l7eDD4EuVeGO9Ma2qHVXQxTJdq817Qean69y+FOg8qmviIwjfV4YPf6U/fOk17R8HV/dc5X/9QZgEGldCORrIFciNpJgPO+hnk/MjBpzI9vfpDuw7ApJUl+x7ZT0igMXDAVbnX91tQTDXYTCucNQgc/KvOpnbnj0mFYEckBmAqA7/eMVzmyZ6CaxHv/7kaPXtc7yHzgxA/d99jU7PFJtNlWIO9cLH9j4mYEEtc2hvEbhqqBrfGdivuvr3t1HSYOEZwa+tptn0fQmqahLEVrx1Ag3liylAyOB0IuXlUqUKbcnmQLIV8XN6kB7qpxvKq9qbj5pLW9OeRFJ8l0lJ7uatNwC8dF31oMzD9obhThlyjsraVw0dCPiIdYxvPk0/XFBogcbX1W93XG85CcxdT51NLmaw2jiH2wAqMF9b3i3CVykwdcZmqLk1MVUiYLUjpF92Ivi5guey3LPJEMbZG75tabRJ9pI7LLxuzBVpmhAE3Rq1ZIL2bpTMDL3YuTCzTo8f9+H7odK6MGrQGbinlHASfQ7Pzy6MQZ2DbaMH/hmjXaSVhSVebEWxQWGQzN4AL/K4zb0B1v8pCsTKsYmsg/Q+4HSuG4p/I1cKS1tJ7Yp744xP3z5fuxk6KCtrwaRAH5vRLlmzUu0tnyDLQV+pfh/GDPAoD85iK9znklpZZhceXQfHos5I68vcThCUTpzM9YUNKwGCV9JA7jGjB0qiQpI+Vmf7NiWBDJkl/4iwSISjiXzgYDm1dvVBQydnNWTvl3mfIage7yDav81I8aGIF5wU6zwrVFIkdWR78OVYprpMXU047MRCDKZnVVcuBg2N3JB+IEt4mAp6obs7CX+xCBqY8aNSn6HdYNZO7MFyFmfy/Wc5Z/GtTGEjqxBlduW+oINjfSCH4c7Jau8pXVUGKmVqGSmIC0moOw9S9JTL+hgBKl4pICFyugBVhhz2CvOqDePFQErBGVbA8UaCjtYufPk3D80z+MIn0oEmi0G1tfKuzuCsIQ05LskmBU2Bh2YYENGXTXiO4fyDVAiasjNXHAMySx1xsxjfVj8NrIO8kSJO6Eg/T3etDDDYx1g9uKZ62oBwHFkJYd9TanfWfb9HZcmE+qU0nZZXcHRQ8HDNWpW+v+elbqUURinq0ek01UHeAPWUDORI79n6U2cFUVAf8N/i8gNE4sU7zCNsVtZIXGIXwMZyrCoCagLzMgs3vxI5sGEdkEiHttazMBsUntqWyYvZdLbv4GagK8JuPHfpeTbkxMdh2lVI7wP1Ipv3WFXPxUCHV8OCko8tiFSmKRnK/2M37cC+1BeTieYd9/UlP6ulaUE1ERySl6j34uf33NOn+na1ieEWuKWC3sJwFwVifp+yNjw6Kh90keAaQhnQSuhSuNPWFxUKJa8c4jSh/wTRXqgIZft09BmHOuvJDBonkcibbK2uDCe/W2Rm7Ndt1FoWlkc34d2ZkXIH8RR91IHGCHcKlrA0DxlD6x6pfLLsuuT2M4gxx2rSNsCzR4O/zmOiKcJzxzWqNF8wLLwUL4t+wB7BYod+7Z3QPp47+uP5UnU5V0L6nKa2xIQs5moUFlie+ocAXETQypjZoP3zoLHdaLFlsBMLn40lWrYVPBmDar04kV8kcCzP8BgwnRU32qksK8DE//PU0w7M1TMTI5CC+tVqSQ27Bv9W0+EWY4mXfM7r74cHaA7tZ6s2JOqx1JxsUU9xCXPwoMIWxqvT6ipyqvYsk1naZn84dxFyPhawFeBRiLPlm7UCQIJN/t8d1Xcdz9DpBwSk24Q9ZNOOeHkgE+khxgU72zKM8UYL9gcHNbWPGzozXMV7NnGK4LtKszDlWJdBP2PqICbGWMjU+/MhIUNGjLyFammwQaJjIQ+OtzOCGfo4PlKbIN5DaVPnRixSErLtthFhphkbkuDQDhqg4UyCeoe9YkzhJrF/xO992SWmfcw0HUtuhM16emy45P9STkABZCiJ018fmfAiB/7X607ynzPb+moOAFG/nMvVfWxpIAqZAaqZIcJ2JcWP+jsOjuBiXEFwciy09PI7Feu7CJFiE4tNU8Ik+nZmi7v43BD6TMhhYQM8nZ9ouL/bVaPgu4vXdsrRCemo8MkjbcOzA3XaDnzgN+EAIw0i9MYHWXFAYAVDsJXlGW7qzEeroKb2X05AiJdA6bmWCiNZOxIOcULJCb7oQJ15tuPrn/s9IA6VGJz79EGLMjb9VuF135vpMcanwRSeSjoFa2xcEvOX9pIT8ltDTGAOXE9yJx+z0NQE9J+HXvnj8cxc0gsDp0md2q2ayJsplRar5cKizY4E0mhhXXLj3su+5R2fpb1P2sL2n65XZpNqaTcZO7DQNQS0YNgW4/SiOw0R3lVG0/KgUIUznV3e5lp8hhFx+vzeB2EJ3beh1OlDPTkv1YcoF8gS/B4m73TW0sv/im8Asa6Fa02FkBsEJG0MKL2qOpHhJASOfkguI/aEOzJiJWFX/7KzOECF5D7yjitFfV+Y/P7fIvyNcLiAzEBR5V+QHDTKefgVm3vgj/uRONdxzeTpyOZNHb7d2J2knzt3zfGiJBwNxPzbbHgvMXsfRF9WDPU/GmImzatXQWnLqN/RCABRG2HxXM7Chi4pSgTh5jhXzKYFP40oiQn27G55D29Pe08MJvntTUFFroGRVazfRB9ea3RoCtY7+8/LovpthhYTTyHSu6y9EEQnCNiFXifSeAubH7qkWY6K5TRtcK9bGRpbejGxcqU9+LpPnbnDnFtcpRjdjleVbyrEzKQ6lLVOgIZeuElJhhvpXwAcpMCnU20BKo8YBLm7PrLnPfVBXNz82OKOR7vynV8NzCrdu6osoxsT32JhD04u3j3o+raz5fC2Hwm4tLn8S2BIxwm4h5HIzUQZINR1hTWQrPmHI/L0DyaPdvOAHdmllCfwJ8FhczVsT/ETObK1UVtxn21RGasqUMfLwYSzwBY95kScVIjwOcSNtA89lWA+oz1cmm+DrASojENtBktnPFpTbOHt3cXl58H3Vi5ioOZIG5yTPW7sOvjc9BahhZF9dj9WhdvwdNiwk8Q/niZjzrmaYI8f3Av06QjuAEsI9fT/72RT5bxF20lSkgEhWwHpxA6nG9sFiQpoQaHnO9REmXN0tHn9QK3qkvNmnqymJL4j976a9xlJtvjgf2J/f69CZpC1ZxbQkear6IrcwlIl5AiZRUQs/5/cvcwgaAqW70FLn+Uel4oMVklNqzeICuT8iOPSPQkKdP0mfsiV/iGlk5IuBML67V7IPpnvZgUgaj5FetkM8wGYKS0VF5Crk8qpU/W3HqS8vtklFR4OEQa1QPYMDrDdJOSaN9VjPpnhXaVvNHymp7hnXNEzlQxBmuiZQELQVzeyqtrfj0al81CLhwG1l0Rxl9blzhGqrz8aEjrXwj0L5Yk2ByfKk9/N1poxPNZ66fqugRI2lHd+yqDEgVbBJgH2Vq+rnfhatjNYAZZM8Lx8H5TkCSx4RtCw3EjHZcrIhm/xFeVWATLTztp2wZNeW2NL66Lk4TxipEcXyNn7V4fhId/CwAUsGix22SAkeCOTUXc3XNSOS0UPLCUtuouRYjLQm1y2QRID3K6ovNajwh7GYjyr0PW/X76D8OqXIOeaRudM900AAd/AGHt1Quef7HF6h7f9w9EtloUseFlpgoq0DhiP6RaGtLDwQoNb44QeXNy12vhfPRHLF5C+Gohx3dWOdo8p6Qgyj7SwUQGRn4hjtlOgazWQ4RQqYOqLduxGvme042i6fUjlTvTPJRnuVqbaK0CtkfODX3B9RVKJlJWRDCC4Eo+v441dP9Ivf+hjtY3YzOpJEUbXod8C7mvDfdrFhpm5G2tiR2ul6utXfNj4cTYgC46KUwIHmSnf/UrGSC4s3dflDMfAN6JxImNfKCte6JpxCE6pCYu3YwS6JmQkBfH0ch5C6JgGa/MthBHjFv/+/43QJRVCUQrQ0u0TvbyO5FSgYKeyKU0dmre0IkHtc32DoFUknRtxR96OXr06cUZJrwjjKoDHrmEfvg5a5KLRGp3ST7s1k4L96KUhhtmpQETP5XwSx3SkfYyBIUme9PSPPOzFtX9AKv4eNXktxu5M63ZCAfjtPleQQK+922bDG7I1DxGcfZzoD7PIsQW1fCJp+hKxviTr8AhD8e1WQIZKVFyJUQEywEcp4uzEQJ4bhepcrfcnpZMzz6j+22Tt/rhW9w0ZfOl2veaxDs1ptkUnNEJlJWaxqtVdzyfqy3FeB0LgpE94TVLiIZEEmPFMZAv44qFXHMCd9dPHIqMQEnY2PrOHZIdWaC/R9rVmW3jEvLAB0unq81ZWAjlcfqYz+HizelrloyQnAc1qcqJdjgBgQ+n8VZ9J5xE+us0aBYHdqJ8QOwcjK2fnUIu3Vhf1DK0sB2lmYs2ald6OHgfrYJFPtOQx2uCbqk0xyXAolDZhE4073MfqqNf4RxoHWmdF1OV/jSNay/Y7OceqLuIT+6aPiBBaCXxTv642NfRg5jA1X/LF2+wFheY0ZBqO+iNGb5OHYnKfgTS5UCJgEL4Sg+GcSXMErntvcBqTYJSOEDIRwDamhSTW8QnUM77VDmneAVFZvOe9MeJkdhsgz+9IR/uQjlg3psZsg0RGNDM8uxJwMQ9XiFcuWUuDrG5uUzZVOJQjymhVU/+W+iS8EV3vGOBqXfjriXrNNXuUe8O3ZVLk8IYvmyDW1KXKWrryZoahZCmvZqNCs6lTvYEKYFq4UJM3d/I6WyzmjMB+Wr0gGbuYionRohPzkHIEIm/tQMLW4kdJ5rXEfqkKdRXxsZnljZqIwhL3naH36CQjYspFUufwNadcb6b/s3bruPUe6g4K/wt/Kz6ZkrcWrhE9j9YDT8iUIFeYUNSyUjxqQGm8bS03XgSA48Z+wL7fR5TavbZpnAmDK2UbPzoKDYFyI6NQC24TSKxrCuh9vs762zB2mBQecAxMzE7RaGX19/cIDxNu8uhtpOBsl1EECwOHXi6hHB6C/vR3VeKuZxax9XyzScNrO9qoi4H0DtQp1AJ9+xn4itQlx/mJppolwDpiAZbIwqeeHcmLnyfqT1VPltcvVGTA499eMBKFtISudL5n/uvOQ1bnIPGNhsqAyKTWiHhGIoz919PtyGWoH9+ZfIDxR+rh7o+7ImNyjestfV46eA6VBcrhSab19JTb8H4dEjFGwWWGAWRy2yWA5RI06E1ww5yfBCcPM6zopB0Ii+y+2eTyI6sB32/MijA3vlpyd9RGswKuQ2+Yc2uV+V6tO/vCRFTjawrh/Og8wYha1i6SxXGpHqCQs97P98jmFkT81YlKsVK0uaktqPtrjXPoKs7U9iNDpx6I3exV53Wh8W27/EmivBR0cxzdeTVjdfS0Ta6BCYIyebtLYo91KsuRFiO+JeO7Wp4rKT4ZYSpg0jNa3oH5AuYHyC1Ks8Y7lnBm3Yxk3TBUrwLdeBj3P5sLcmVUnvo08dwO0Y+f2qwJH54Q3fhFt4Ll879Wrip8pKPXSVm6tQ5XLJosk8a/8wNAAuz5fMrHo4thW3I+7lq5WHewNjFbt9RAR8RqU8STA3ADOzXmncCa2koMxB08RRXF/5CXODNHQltb1mFY/ztQoqfWlffSQ+ebF3AAbvCg4LYUpd/vWJRbzL2MqNgoamUDmffI/7afzYhGHhFaK5QbS/mF16qxXHQ6wtZZ/06Cqnvxgk9zSiXM8HDcCunmmhyfXNJpwCRLSmpHjw9ShbFF5BNFgzustTPTsJo+0f6VH19t6bYauouap2EFy9J5H4bckvS5Z0W18NZkeuwyaZHULXt57PqXKbT9NIdEYo/3tLajwmWB8h6wS261aLsWc8WKhfFh9En/4NIN+BRovbwmMYPuu7oj1z+ihT6+P54AfQywttWzrzUlrNZbHNI9FJpQvE9Djadn3XV7/JxKwhzpuYy/p8jnf1uP3sedQAGvNQIHN6HRsApWphJ4dNbBG9NClw7YudOP4M1l+aFESPTUT6Z0W9+DtyB0ycvTRBGIOTcdvViZR2BA1aRwBVzaTYvFX/e6mjhyhBlBQ0+DfcHrrIJQjYTYjfdJzL4RR78porasPKZDnPG/ip0mHoxkY52c31yK3QK7z65GUDswx0zei54m4hLxrw+wz1ODdm92gcdcEm1nSG4mR0i4fLc/XGdJG/4Wp7Yc8Np5LHtn6hFq6m5DLey0uXProlueX70b0/QYYAmf3YH86Nmtp+hXF1x9gNKcn7UldnE02js05YSkiLYaeTwpAAw96O+7+gZ8mq+L1O+H5SI6wdmhsQHzg/RVgzj+axirKidFozXvmsCYxKsuqRqzDgO1EkKo6a0QeMqOkpQEDzlkCk5AjZ98UfjWU/ySoq4eFu94tC2VahMF2SJ+pe+GC+3VMIxZrqindpHhO15ejJpb7FYj8G9qS5FCvLy3snWfgeDcBApkIo45I2o3kweM6+weH77+yuOwl+BmN+SUHlFVFenJF8mMx1NeVLcsBd31i49dNPCm9cstp+6oOFCX32Hfm0DDyB3+hsZS5hmudlhR2WUA7Oe+bMWiMGY3rHU1+LitkOdIFV44FHDT4lodOz1apVeTTX6E0jgR8W3bV36oz1EPazLvfJBqAkH5IiemY4MVGAWMPakJp4cbzdbuB66v1xeJ7MKGtcZWJ8/c4/fULYLEP9MGjrFZD8GSdfzWRildlIQWY+QVcaFEKyC0ec71auzalVkvNxqdWfsrvRNH9BjEeqM2ryt2Lo1ee3g9jjNJD7b+J9P+qORSkLxQWjvmueqsc7N4ZcJ7gYtps6hHAUx0CMw9gBMTZCC75PZmXv5e+MhoNapX/TgkwbhgQoE9UzbVIzUrv6ovvLNOcfie3GtCHMAr42Ohh5wdZ7Jwfwdm3ZGfdCMPdt71cRDATiwIDa6GzaJiuhmXh9mvH1+Z4HvEYp4R2GpsyauEwAwp4kEpdygaYh3n5vVxsGegO2HxN1EuP9ZqYoJY52DVIBGNBLGKoJ/f2bFvhYlHb4Ywrr4oZN/Rrgt9PPC4PQZTja6C0H1vw652lG8qHrZT+iFxHqJTYOeYbVgs69jzKq4ba0hJFA8CqoIztIYxkE43j5u2iHukiSj05gzahz6Lzd60PPNybmyPtkjDL+uRsZM3aFpms2ZuJjtp9ymwWzYHuv+i7P5cozZz6emkupDqHUzWbTOsLlRyfl8mblSf98O79XtfFMHjOkFDlhUJYP07P+jCXQIzqqTrd/drP37PofzWw0Xfw7yLjVML46/HXXOLHFjy74mSyE3Nglu8lrtzJOACiIqN0kSmYrzrKbevSePSriqQdCJ483TzO14nVpJDW8GSd0zPcFei6IetsUfoF8qf2Ku3qkdvKZ3QabY4BE4mEI2QEdQSNmAOKf/5rNGVRI8ZE6U2sJbAo49Q/thnp0eyAbIf+f5dFFpf6qHzaA9hJN0qlZwUZouSbWzD8TG74LImhLKXeXdVlNI/eCHkTY53JVbHsUkprYuw5XYYanB+NIYUnVBBpwqV+gc1VTnrMDRcJcL/DRzZqstzcKgV9e/teU5g8TT1SS298F9jtbyGrG9HSXvHVnBab3cakESIKf6XqmOu6Mj2Vsm6vF+2NwiHIdjnhzWv6VSBIY2iMNAJh1HsCOv4jJlGjo+2AyWpwBDHHbA4mNoveneros1xQeU6ARP5KB7HQpR+1CaAEQQZW0dvKK9zUdT0rLbgeiTLYThXwo5onFLpizcseSrefcD5NwFgyrX2JWaHRHWB7CkQH0kovDQKV7cybJQnpWU2d//ntBx4AmbK+Sr7p+7PqjpGgVJ/WMAj5a9ORJOGjbBMPBodH9FSF8dzE9qAARuIFkoxxuMwRELf/i2xVoxC43tLfgaYexFu/HJlxY6xU4sRFGLQM1eL71qr4FLHPucEGH7M6wXlNLHotGBGXU08gIoJ56mcBFjjYQM+CR9/M67nGRM2JCvhjitYZcXAOQA1/aVV3YZjXgXDMMGccpvlWoSow/LF/v39cSePcRte5KfzJPn2u0TOwyt8oNSIIYR11hQs4QVW9l3GHS72uTbIPiFeS5sPga5pwE53I+x7TtGWTk82d1FMWEG5+TCGteV7z02maS/QR6Hl1fTb1VyrDkr5paq1ztM1/aQ2qaSMJSME4OFlR5EiOvldsgCX8hFigQli2u4jraCNdiSMr89vIcGilFFZk8VmDUDJCNm1BVkFNAsk5ltE0dfEF4g4P4GZ3Rd2V1iXxQ3ObMtJJQrzfplBYg28kH9Hbw3V6PCfjfesgu7RMonCL30XNxKfsG1qVd+rBoFuKvJp/9m2OWeJsKg0j6zqk+eo2cQRGUCGgaoOKlMhB/MV5Aoc7lO/IJQB594vH0bxQoKo64SFLZd/PT2kg/tZVNrdYr5Z3/cHmEedNujYcO4HsJDj4Fi+SMkSnIsAZFFnjFdSiFtQ5VJxwRFP0aVT1PeNDWXNZi0Gn9LYvrMtRY4IaQUJg7DtMOCjP5Og+dAdDWoIVA5MVE9YhuLUeRt8oo6Q3Cgi6D8JRLoJkwbvh6meQ5grGP2T3GIpG/X6vtF8tAWOj6stUppC0t916n0dvnLoeBi2JQIzkBjYFjHwt3g9cVQhXgC2MM7tkhWMwm6c5LVDH8JksxA5GjYhgFMbjzroBhSvPvz71BhoRhHsRHNnRHi1PWj67SPnjvxuQbk6qWXadsga2ToXjE0TyQPC0cObFArHMNPsx/aVw+l6kAacrwqq/j+FVbrNl/S1hO8oumyUWrwRrNqsrH/webPNI+Y8XpRo0MWJUuPH1/8IN3w8ZLnUpfsje8boVIlGGuw6MbTcvTCxXQEwzg54KHDBh5x2x/kWIO2vkZfaa81mbYaqDrw9w56sHF9dGewueYwd0sJlhOFVg6CyznOtdwGnVyx1HBOAXsux4lw8AMS/e95o53Cyosc4wNxSyg2fxlq4GBKot++6OJLcxpwm9MdTuxc5dT4ej3t1o3lz4JjkDJEAKQChEtNQhkm42VNgLGlJVaSKrxci4UzNNte2FBt4MztNThPIoZs7GzsqhsOnnTWAeyF+hp8oGS/Ri9DJ8V3QuZRNOlT1YpsAgIoVBB5php9SD3mEPmPSqgXIvnLGs6F4LKBdd92XaFg/fDspn2xyhyw8iOkWaXOgjEELa+OTEd2M6HtKmtE7+5ISOwRtCMRIl3Ef6eNIixCSdVT5iZ3Dlx/KiIcPqaP27ps61AU/U1ZOaegT9h0F2XXSp6CVZML4Fm0HcajlL1TdhjslWrJMsv22aq4u8bXhUPtyZJ2VW32HIxA6LtVoBRLPxyn78FNUu2ECgP1QushR1OnTFtPoagPXLhrG0y4DxsP3DoVcGy38wsjtuq03MR0AIjDoXTIfrCvsJKcQ59Ge1ROoXd6NbLuqq9OOO3YO4c0xwEsdE9Y+YTDmeC+tLhnvjR2uY1fXC8uG20Wh/2anNvBI5VktOUpfJtg0zjGfUrxulanOvX/jIAwHWWM99Utgyu7lOq8ojUmFF2yvXM+1hhf6wlTTIsg8QIRsYsvchoX+rXWbvs2e2PLWBUOP31II79y0/nfzMxbKpfmnOIeI4W6sDl/JnCgFRnLSeRxy2q/+zmVogPS2SxobQDa/YZdluMr2R5grBeI/FTzq9fouyg+az7U5D1xxw3uNsTrNRLaZ7z+Q+EwTcvb8EGOy0sPLDuOyJlU7WQsI5RnsjIKckfuHY2CY6Ho5++P+4fwXZJZtsZYFGSmqQp7F3A8Y+4+gd8qKAPYJSVcbskNx0mVISpF+rlKriJD6tpm9lPFNoBGqMrp4AC+/LEYUSgx15exHSXex5GO2qjJINDnrCQHtjqQ/jNZTxoLhdNulHFKLFC8v4GCYv8YDY5XsiCg96FLu3xpAk/F2CyU3yoO0gNRgmYafGvTsz0OdVD8nBTa7UPivTiMttYzZLM1p39w3QPD/e4tHPJQAZkbB2f3ujBDJTWOIUYK1qZfhLXEA4k8X3cMOeL/v/RT5qoQ9k1yXLc9RuQ4PFr8By7ntD0vfB5TZuzY8LOV2YcakF5qImWYD5do+KEspmtPMjEdoUaDMTcpJq95shWqbeNyQmXHVeVcWaaHqDc8iQ6EpLPH77uhrSSETCZwUvbmDMwBSe3hgu3EMPsjUZIiuseZi43wTP1fETafFLYQO97qX0ECEDZ+XQjAKiz+sJ4WEtt2DGLA1Mx9SRgL4NeQ/K97DLYGzhEl1GAT+VJKdNHu6Eh0ZH6M+U9cuYEjSNl5EpK9yIPotPCmFa7AcL5gJKO+wDqMGCx0y/rQtoajhVDG8ZEEMogI2rqjwA5wDCo+DnKpFLsO/3bInJ1tpE//qT9gJH2yok0nxMxtlBcM0aKYAHMsSImxaTWrOGnIFE9XrKvMzhbecn8U28LJHJRKXRjaSvhIGyH9EQwJI7uz36kE5Jok05oZA5/bL+APuaygFfa5gu8OLHjyJh3z3oYBFf+ES3seAnQEz3HlI2zCZu/2frkODS7LISaWMPgOnpFhMDaoIHI1otVUhiyRN4UEahXtCTeqU5nWMNNODT6o4kzYS2fD1Wdnzau/0ixGmDRUu98yIaKUppYwSRzmxrysdjBM9abgA/PwaXmDIQz4/pRnD/kEHGHZBejbNFl2zuE7OwYcQ6Qk740N45bnvZeBDcu2y3t+86KkaSk2su52RdetIjmfHnLcSjpGx8RYZI6kNmzA/snUFV94/iS7EnoplzoArpusKZxMxX2FiOvcnWNpFg/DYg6xm0hVjNHUVx00FQ8S+rLW4Qia5baiMUTSwU4DuDZzzOyjQRYEsnhk3xoFKrCINEFV2du9ahTXPsUwVdsCNiabB5bhq6kcR5+4Coh5KFfTPQVTYIotssUHEczUwGG63gJaDE7B2rhTg4XGqCLRXOfloOzawjITtNI/HbOVIwn8G6+pr3ayz6BgFL3R0nsFnns+80SENKKUrsTR9/voMSbE42q4Sh/Jq8iYedMBQuFetrFum/r5VqMmNnYMfqYzZF9/20IXoMF0vEl5a5dh05mONM5VD7vyJ2pbuE4dwXjz58vWA77Kl48SyPlohxHk1/Bpj5NeU0yhKg/Zgy0l1ztWXiTc5sSBSRp4CYc3oFHUML/wIP7+GPTOka1PcK8f+n37+GWNp5h3eDjv8R2Sy7BAJUgOHO4EwRdRUWCLuXqvvyAPdjskfFwHldR1Ke2AgoJHipSIRGTpQQ0GMX5f/nwoXSA6OBDIRtYKzP69afJQ1usz+wurxGMiS5Je3PqNnVkwIS8pDq5+vuNrpkawftpIcePFjdirTGlKCd47+QWUei3kXh+hi8vN4PfyAYOgJRJjtFocpFwUFbTv4Nf8rlke3Hpdu74wn5lglM/bSgTZID1Uj0GmEGbW09lvHbmiedUmwf04J2gYedu1rYw0Xr9eP7As0PeNW4W/emgzolcGO1pDCZnuoacOYmc2akb9g7av0k5pf1xtRWtukLQPV01Ed6awihx9X+7iNoE8fHlXd7Cy7wKMw6zmghJzVPHOLIrN9tSPWtx3Cdz7Rbcc8W7w1i/d9hUdkCNDAoo6rpvOdmwy2X3OgkKVlR7K+JLZ3vieaYALkGDrAcQbYD7qCKKaI4nbViLn5UpbLYhxoZq/1LT/SSt3pwdESp5l2fjgTkF9eTJVUOvqF9SQWAUvIgSjS6vMFuPEP63XH3XReeCZGSubqMl+X3EZjgyVhgYvT9uqrTWKlN3wj9qnApb00luCwgSrTDYZNDli97HhJFKg4POjaDFZdo5dAvQcknbCLFBmIJxEab/7Zp5rv9DLB6ys7p3hHmBLKGcySnDZNk0xm082Ly6cUVT/VLCj2I0iWfIuoJ2fFgwL+QBCm45mq/64TsIRHGwjEnQsY1xiFLLLRRVTynMeF9/LlCuJFr/w4Vy+P3Qj3wkXJ0FbjyvFdL/rfewd9VuvtxxE2tn5bWUztfONZlMu2GuaA3Y1rJrcXuPJve3skPv7JypiDu2s4Agce5+5WeqDE0aTIditcX7APgJCZTQ/vxf0k9dXmnqPDl/N8pjR01XvTmWBQeCDiCM5x4OZjYcXTCGEyYlk3wnv8NBMf5pdJmCjeKyW2w14dJetQypPA39Tru9jgm1KXaHTIgsCSgklJ9Vk/wgriwgsAojax8YbN1TZidAjoUh8Ac4tT2m6nmShwz6ysqi8azfP+5NDUXEckBgQSDX1yEehq8RxCKQao3CTTRUfSsY+wD8NzI2G5s+nRm9H3EhD/WAkw9iQ8T3jwyI1kBdNq5i/1c6ugezwsGufNhj7UBOSr1CUe8/2suWSO9tqpt0Z4vmQDXRVoQUNB0k9NOCSBy+dkJqh9dwY7ZAcXNojbj6YKApgLG7BKVQDcfSZ6v9A8ro9TwXnDxvmfI6bO+aP9FZLkQoTnj1aPPzWlsvoGFcljsscSrAlY9pAKDgWebLQPVkt70MmxTvuSmcCyDsNP1QDwWd8dlRo9CQRoS2niNGbc0UCFNTlDna/1OMJE09CUkhPKkh5STNWl7E4eCj46GrscG/SmLXtU5c/b+W40eWoxaIs+/VUyl1bCg3Z2LVJfQZw6d/DvId4zZAvrGOU5gb8x9uEeS0Oq1onqf1cDMohNyT7uqAGUVSoFHwWbnTEZL2LZNTG6aJLSxO4ZKC1PU7+bSutyrNsSPpHjnFwFL16FmsRthlTV1TVXEXlvIQoIRi8qtdK3WDR3f7SrhqPORkPHRZU71I/+HXOZu0XGyxmHW3vMvvgXkY1ny1XHZtLxW1dAm+SAYX4A39ElHBYiOYjnwGmtmoyWGPPXqCbmGg4xFN9hTMMp6Kbjf9pXdAewCLX5O96F/WLJPAlmWrGSMCCkX9uujw9YRJfTNJCEuW+XUhINwFfk7jyU6IU9OsorbGrzOsM6Y/pg2NPSjrkp5sWq4rBhA2GYbzlF+thyhGdjEbbcwAQvBOW4Gy6geMLyeAtusxphWmsAxSskdcTOiz/riP1Z913c/nrRGDvIaQUMdJKyRrWIBRnphXINILZq5fujs9zSVvVZ6Ehrc7fvuX3tS6UfJBet5rn1HTEKeymBtHtWJoI1NfsKNuezz32dvgbPgFaDW7rxYgBDpSXUHf+M7bvTYp23H6M+rWGAdaJOACTndp9DeI23UeDd1XVvYY3Y8tRrN0Qx5aBZ2OHbUKuc6nEfmo8Kb+sApFi8dH54xlAgXSu1hQC3oLXFdGio+oq8m8GYqDJK+/m1JW6SrhRq7jUt49FJ1HIqznskRoFwU5dMJFCE1MSTyRXJyaWRrgy02eScWkM3kfpge5IhEG7p75iWzBTnDPZ/OuJKNAn14U3Zh4dDm657nl2zScr/yivTEoYZeCwa+sjWNVsoGnexGjQYxFN8OZgxPl/+3M3bYt6ak6TW+VsQaz3OJyhyRrMcyN1Jyi0kZwQwZQtXrQfdIIX1oFmU1WH76Nu09zoqqufUgt4f7rRcr8ubokUZHVENLhGk3ewJAe9CQrC67mOLL4fKsSF652vRXXrF0q3sKiDu6J5DEwZmDqXFZvLS3gZ+TtqnjYmSY8vywgcifDJSVv/o8wb8+7/z48+YdIs3u58ycVv7/FoIMiHQ1cvrww3WiniO9FbZQYAcl/Pxg+xtqBmHrnwgpL71TPdE1ljPiSMzFAN/VcO01SfNavkOKu2jqb+5qqgxd30317x4cRn9auErtsjCYeiocrketwaDUly/Eyz4nlQ552dre+5ndMZuO+4PTLRKCYnLvRZM0z7K1v6HTXZLz+nO8kTz3rTM8a51PVobVfgltELsPzAOEoUr1+dGtzGoOzuv7tnwsUxxyg/0K1+W0uU7aBGzXxcn9Cqb2buxduKOPbuJu0KjMXLh5mZgfLNyGOb6L1Us//yCvlbG9d69UfcTThJh0ydwXtdDAwkJtGS30Sdyhb+2dStqVoYHReSVzh5o1Bm/HWaO8gag0y7a/eWagBUQNHKbhHN6bK7ki7xx/zofuNTmVQpKbl1bKUPaKO9p1p3c/FZzAHxa49WqqDtKgA8V6YaGR89PkWA1rPGFkrZsdRVcMc5zSZbBp8mdKPLtaJCgg50Rmehiy9CLjqmacRTYFqkB7BMldLJ6FQ/S1uVyAIb1EVBd3Fh+Ldfe9vGc12osKm+abRxw7niDD70o4jLlTuaPA31CoJSCgRBRMxoa9SBGgF+VMxppvv2nLmbkhYrk5rftlLBeJazAlCWvtCj6xa9IEkF7OrmDYdGUs9ldlH2MoGRKAwLp0u9ST5rOj4e2GjXdTNo0voRh3Aco3loXg7bWZte4z84wV+x5lekrIaCE1AolWFpLYDbYSvYMv6LllzzV5kQYoXYDI9ZjfohWQcpwXI8GPlGc0swaFXY/aEWYqyjhijCBOXceiRZhC1JvvCJKLNyyELcp1HE6qAEC1wzS7lemcYmdLPoBpxHIZTwo9nw7/8ROuNNEeEc8n6TqSXa+AxSmCd13hqVY4LtqK4pHROmKFTMAKZjOzXijA4RuzgNNX76oQKPLtmdWrQTORSb5vTHrQ1A5/hdspNOUvJroXOQTEjVhfutzV4W9eh07QCMeZRVIXZnm27OuOY558vpzzqIMW3j69rQuhJrqnFQk6aCI5WLO+sQ4orBV59KDr41bmOirDqYTqNlCKSKadz2/6J3nc5LmGAWGXVGO7RjZm37A7fRNX8l4Aeo9Ei7hD2NS44jmxmaRbpCN+Vs6Y+aS5bH38/9QVwMAVqQD7WiMJyG3SrAjAQAdvhceen8MBVU9yvu5BAi+U9zvB7kY4W38W0XBMojYh8MGmZvRYPzONX5MyUfW50T2od1+WfSJyT0GVPmRFLxSdQxh3coquDw2uRVGgidRynN1lT8gsikkDixsUsjQBHqZemqnBbALSAr/Id9KxFasF7h+4/ltOWYlcrT9mjrBC46tLkssEfKQt8yaRGMWERkcSWG8NvBX61sCB8b6SG78lzn7G6sIghg/DyAIo1enowSJkpV/mmhCFlHTlHxrRw424+9+w04rBiWi20I2/x9oJWT3NBlUPm9bgmXkU0HhQoamVkJGQX7NIw6nw42z81NvPFG9vjFxQSXaFmDJlY6O9uqv0dRU/fM5geLCZvvsj5QY5hQYPM4mrgB8o7CZwtL8HXSzwxY1zPXzvBYciznETxCyF7rX7Hvgla1XCTXJtwU1Q69ZW6rnzuz4DMQ+t774DoTQ8CbRLAs0yc40hmwGVho0FMgyzVHY1O7zC3mwjTYhSVtgVVh7RsBXcwWrZm5kFXIs/htV8SQzISdkELyY+EelU9hbcazNTipeqNniFJeJAVRa9Cfh+yl3GRDG0Mjg21EAiDDPvnSBUKNVXGxP/yWIdsPyLX9I21GIK0x0GL6299Pcl1Pxn5tHdktpHKoaCq7Ls20D/laTAu21i0mloHjCM4DB12WmUxRPbroff9yYEsBOPNo8qeOy5OlSlYVMCpukG25ewdNpoc+ZYBcesFqsavNYsDwHCS394gyXZ5+UyQ7eXL12XrVcV0NiqkeHdbZkvhQUuHsh5PuzLKR3jKEc3uOUjtS1K+AiAk7ZnH8rUslfgRjn+Jum2UowGGLyWF/oeMDkukSvyoZab2iM1wnloHXZaJ9ZsShogJ0v89kszMqu8CPPVllwcwhrkeRMzhXyiQnKV7xcsqyLjUoRCCSJNjHDxb/IhsOhhT9ylq8w2B3J+mPWw2XsCzzGzxmaTSdQRtBsqzQ7YyS6238dZrkh2FpMx2aO0uRW/KKVyjdTJACK6jswHuhKeb1+ws42fE3uL8qYwQj6nZwxaFQmTrYLMk04PcIyFd1a3Um5oCG4Fvq5vZfqJ853AXBnSOnmAm1zBvNtthH6z7I7q/GU/Fzzv7ybx4TXSLMobNu07wkF8B7GuunMdpJc03N+4EfZ/IAE+LUjw57k05I91fdyc/2dfiIMaIy7SW8R0rAqZkAebDdM8HZvjBCjlwBEVTXgdPkMRVVnQG0oOZgxnzaXlrIzh/sPKKe1zpmf4tT5UxMkxI+qnrnppWkR5knVmzZ6KGomTA4XNMnzjaO8VLuvSjsiCcMs2KkIA7haDL7alpY/5uI4uocYmUBbbsl5sg69mKg6MhUVPiWGWcdkZBW6mn8nL9Ix9nJrMEQbhEVpSYSwcE68UiBN4lA8jc5W9STm/PQ2hm2V+PpO5J+oNA4bIrRWx2mGqJdNcvw20XqH88Xz3AmbA1zrRSbj/XnxUMczMzmTEYuhTLXD4W1oMBB6oqgLYmBHbq+M5xYAUAGWaRLedN7KhjYQ6jfG0DxeWjic6ERLLx1KXGYxE5tHW3D1boO/SgMcw6s61BLK2xVZM5jj16qIU8tgzUGvn0MDiTjeBxmPyDb5s2/QzoKcGHQ4zctJ7a57WV0LOQXcS9NQ/ze/Wc8HS2WdsmlAdED8lp88E74pU+IfD0m6NrMKS42mZ5kXCb5Fa52Jt6x5AsNQLMtjRyu/anHiLkcZJuCrH+HKno7h6BrJiacFHMnUpPdyaBnjrLMFYCplYMGBfYPh34m1BFq96lyyVQhIkcP2b898d0blas0VZnltiAtcGKlEWKHBMn5U0zG88fqYHkT+N3swJEIB3J+KDgyqJX8N2Bk3xi7EOle/rApuPmsaukHZ/huxZ+K8ZHZNQSZU6lC6BARlgzRhacXkiBcFuytmmYQzrT6Hai/8a0Vqn21dSd+pkNVU/N6nkjusBqscYIrt8ZberY/vDd2QYryEpgekRS047GfZzZD/w17FNJjcXXlYeBumSQCXrKdX6sRUy3MkJv57wUFoExxxz9U+4ajQkf7f2+LpTgFs+/jaiTcr+3PthQaTcDk3TTA0C9rhy5Fe+VzgntiGuckCtXbGKlohezP2/wjqv+Lu2j4tkaID2iPbk37/5ZLobZVlS3tcD6s2TnUkCiwLq0XC9OgT6zFnb9tXo8PFVqIUcTbFZduKh37ckLZols8hIMcmevQGXWcCgiJVVj1DSyQn5XNQeOmfLpt13t3qMX2fRZeabShdqt2N0JtztJQkW+OFWBgbzHH4Y+ckzMlzPihew2lmBHOB34gDptUcKB0qK1YDNZSHI2GF+Soz+A/qYADeiBrAurD0mRRCegZumxMepMYHNMgjerPvBcmFH1zqJVcCiXZkYArtr3qBtObD7DZ1Tr67gFsuRWs7sx0/hfYQsWTJ/CyQhlHhGQ02NYFCHYuC/fdOyoI0pzUoqss4LMIQYpbeHCvX2pBp0YeTS/hZrRd2PFCFv/aqCXxjOSnLo/iMBCuK/Zkuk+Geb/v8Yl3sFTyLdvFfWfGH6hxc8IODp4ZC1qjOyd3SQLyGztmT9yy9LXJm2aLwXnoAkNSphwrcrDjnZWRETelV5XOrUHiRxxUtivr+HvDj6jWYIyPP2ifh/sY09xxgoqeMILimDHvFP5kMFeEf4b88qOYLuLKi0FRHLCjjDyF2wNS0iL5VrsweyZqw4LE54PslePwvZetAeuuanZmj1cLIYVmIlc0PUof6o06wvzJD6yAS0nSmvyetX0Yjs5pMnBokCZt8czUhJaN2ZGYbuwGZNz0G77AzW1Jyqcni2aWNcfyS6fdPweSV1u7k6n/W6IYCZcBeNs6yOLo7QZK5Sw8jxlcVa/jdI1yDmKje6CNCzonxv/85O12PCtJlzLY4GIYdiMcp3es1ruBjjhMQ5zJw3WKep4ZK3j5zrnXo+8Z+hWekHkT6mU1R1yg5BXEDx+ib/f4I0Ti6CSGP6remx5pbnPbgf5odyYUx/7DW2rVL8EW5s4tDjTPWCkCJedoL3slm7luZXL0obWFOGWIC9xPciy5161detxmLeThv4fF45s3avgo2ynNDq6JUEAJX7nJ/smvnMRmqv4b6KcmS9ym7ucy8bXdwScEqgGNfMkR9/Dgkc/+fC6Vbp4c0i3hbjqTY3AoDui+sHvJd0oh2c6eIwC4kgvLJcxbxCU5uFfgBsn/wXVLiMaSoM51ZBuwYUqx25GZ/2O1TSwscMC+MO0yiSisJc0iwDuS4iQqMhada1Vf8HVyHvUH1HJgs4YoY7VTaX+KRdPKh+mrJJgNMDVw4o8psAjLGKQkgpw+9BXx9ofz1iWcT+2eyyHkMCgzxtPL08/Z5PmoxtdB9OuaoSwx4ui3EhL64uzc5haBVLMRJJXERLB48kMc3PWmBru2jiBnjU8t6mpTY+WAZikmTATxxsBhf29xmfsvb0oC+FZdeleMSlmnWacexAip73QDUG8tn3aRRhhMczLXSKFntUWSXI3+l1hydQNT7YTQYthSwzfW7LL/7qHYw3PzUMtzRXLf+4Wx5jQGCChdscowj9axIbHwN+re5NA+bhKWqH+SAgWWtQ2pkBqTJTZ0V6KTwuLOjNyVP2ZrEG/O69dqOpKEeqD9StXynrTYjCaHx9QnuCr+skPQjFsGoWRUaUHGoFBQptVlyTyW3Af+A9fDaRtxw5ap2tlvVnJWxZAb/dU0eIxr8NSf4dG6CSqN6I8YfbmxPZjGQb1pdurgXTx1XwQGiu6iHxNPeRzWwa6VTZn9h1HeAPzlcNbwfJ80/gLU+oXieJxspgepeQdff5kKvlQHr/xS9tj6I/drtNjrkZ9X1WHiFuCI8+fbD6LLstGpvV0sXiaG2bA02i3zxD/+1FHCiTSL5BLqJI4UD4mF9ShokHyDFGOubiD8KbUvty2TkS7lTzX/QwabdSVEkKcpu2z88KAYVUtJPKB686udzmlqjbepY8APksH+cg9HiPPM+2MTKzPt2OZDmA3WkR6UvCyCT96TU2cv9TfTVt1UoFYZyPFnNX5JQfd4fxcDXFBOXQAmKZMcfJHlEHisI8njZ63jlTC4LVv9tJBfYOO0L8g/Zb6BBGL+Bj6ML8wCDVp2MxMGMNmehMQVP6sY5LBhr0R2qeDB08hNrtrPfdsJSWXXnjnCIujC0hcEkdWJsEm61dvO5zYemB56kUvOX6FIxJtxXPdxt7kHVrtL/kmdtgRhgKFX0UZ4or+agCpC+Ql5L0pkyBk2AeRGbtjsuE2FwA9krbcCojqKmW07NEGau76uKfQsMFoBi1ewuSqi/PtK9E/Ii3+IrlCUh+pXGEXSXk302Im545nl1/C643jGlfz66wh/00UJIkGQWkL8eYlmUNtEuHf63NFLhE1MH5wk2BNwo1bULUYQ8iu+NQTTUszByPDJD3GocaTBNHYx3eBfIQWCtmiRfd5jBPK1Al537sVspaaEQ/U5MEcBDwBG0UNivUYG4zGnUQ8TR1hFQzDHjhXZLL2I2zgqOkaNDj1HseIp/+Spa/xyQiStmZznuitvVyUSJBwfIpknf4UHVLl3549txRcK6dGF4VI8qE4YZBlEzcHVgtqnUTcIDWbmAaG49L/EPs60LaRGTf15869S89lzTo556OtSm27z4fDm3vCOkhp7gMtbMpAH8LPJtwa1PA5e45ahzEPznvBbDfDtcmW0S27YjZ3e6i1wmbJAhRTU5MHRv02qa29ZhHEJdTraJXFNa496vGHs8EaMmKxLcWxshrEB1nsqDaO9Ud97/7rpxb7hU3OLEjkUSlEtaOLatLLS6Loy0+5ZEbUGCEWwK5W/1KzkChoz4lEowOlycSs+s48bQxhiHfLH5+479SlTfIJaoBEJMbydefpexGEvTULzadR7k71+d4lUQzleHqVIThVhWXPzxUL1oOZb9nHimJjIaxa9OTvUO8QUSpayhRA74LxzMJYoJgu3BD95Su2yuVUfudaDktTb28MMngFJOoJZGKTbTl/g4lNXIICLvaunmnh48R8OOnD8HxWFsVKsVX/6ZC6Q1N6psw+JEvLiu+0PKJ5Thi0o9Y6PwW3MV0K+slOu8xklu6Na+UclZwJAZSFgZiqH1W7Yy0YMvotpRXyc5ks+kvWHsxJDqFs/uYYUHQFdm8cdYjTUYAc2CJdSAdapq+YNzzz7sqiykI/psTdIHWKrToG6ymi1thq9Pw/Ee41lOtWTtA8p4xXM4j1zu5b/vUHArfKVfYKc/ebrWzMnT+UXiiNhbr75G0aoMZn4ur5RM/dmO/3V4WV2HpOE6XVr3jnQtNVpGY7k1fL3chblR4Q5Gh5ki25o89rZNRSWjwE4JG1LNM9p7aFUQebecqyLKbIydUncw1SV8wwODC8vCC+7nEy+Z93BQRZXyWLC1WmjIuDF8YQhwOBi9GAmAjAoOPVsLkwGwXdHW9YN0zUOtzDo0upOEu3UPlinjvb8n5UKbHKnBPGA+HBB3fh/mrOkM5KihQ/5eEGO4G2cU6SzLddhxYDducB+ttMvNLqMQAEtmDXNGwdFiBPEDvDYPDfchzC6OJTneiskUZpFafodTKVY08KSayDYnh2SpZujSuOozyoaKzuMAzMxnJADt8jOV1dnVLFNEbdQS+4W4zCUTbGZC7eOaYaQlQ3qSM70za0XxRG4Ze8tN4MQAiy4oKEC+c7Em2YeqF2vkJGUnuWwTxPj+DnXkbvS2sS3rKPLoQ1q5TismW3PL8sttEau1Sc2XVAhnJZuZo459ZPsLziCxwZ6NYeDulVPB78d/QU4o/PXG+dXS0w2PJUcYg9PNPVi6JL0fNQoNmKpnJyrV/rkQs/REdeipGLIwLrDqK/qIr3FQTdrrBBiMT1f1wvN/O/nz55uyEYh/6RUpiomhztkRfZyPxB7W/szgorKOagcIpdKO/U99B/gxXb/zRk9q8wtCdJr+xJD3vkHczkjmLGJISWbOra7Oqm2slBjg8ckVoUTOkK2ij10gGUkFydyuZkzS/7Yn5CuDduQgTLKGkzB5oRUEanyFEkuDJqoPkYtIJNVOr5JYHRWUDjCn4iPuvVl37fK5Pwq7PKNiXn8HfKFnjnboYZzyFcCiDFONOdKYd4XCEjqHiN8BUg04mbJKxUwM5NnNnl9tSlMlqAD36UjIvKDo2XW9IrCmRbRytbShwJPRM2QiLEPNdeX67tfFrLYxat9gI/NsVbM2yI93v85EFxF6aWl5S4NPtxjhvvfAnPPVLfffgYVJRcXXjuliI7AzA3A0P0YXwduy2nTOu+JHEA/uvKhNKhjVKwzWDgmrhTI9PuHMMQwTHSoFjdakM6Wh76CX70rkwynG3+wREhfWkcjHpWd9weiNOX3BR/gShrjITC8rHPnNk0Y/PFi2v7p63n9XgT0wJY+7G125YA64FV08YXpQiWMCC+/Puv3gNy368Z7GOdG4LICy0LHy3FThu2Q= \ No newline at end of file diff --git a/magent_test_01.fig b/magent_test_01.fig new file mode 100644 index 0000000000000000000000000000000000000000..2d3322c45112297575c7c2ac212dccfee86935c1 GIT binary patch literal 2065 zcmdoj2>@I0Tg;#tS`=PSCO?&>GSAM8~qT50YZ zcAENzmCn9l6}rX9!7MaP3jm=Lj2tXN!=e-ry1>Z6Dn!eSME|6Bgpq?yXvmjtpqOE& KY0S{QhywsxxCsLQ literal 0 HcmV?d00001 diff --git a/readme.txt b/readme.txt new file mode 100644 index 0000000..bbc71df --- /dev/null +++ b/readme.txt @@ -0,0 +1,58 @@ +// +1IOڵԣʱʱշݣ +2ֹͣԶѰʼյ㣻 +3㶯Уÿε㶯ڣ㶯ɵڣλף +4ʼƶ㣬ƶ̿ɵڲλףÿһͣʱ䣨λ룩ͣʱڷڣͣһʱԶصʼ㡣ͣʱ趨λ룩 +5ʼ֮ѭƶƶ̿ɵڲλףÿһͣʱ䣨λ룩ͣʱڷڣ +6Թդźȷʼյ㣬ֻеͨդʱװòŻֵᷴ +7˽г̴߼ת̨ٱΪ190Էֱг̻ͬ +8ʼλλк״̬λ״̬ʾ + +//ʹ˵ + УʹúDeal_Uart_Data_For_Module(void)յݣʹúDeal_Motor(void)ƵʹúADC_Multichannel()ɼADCݡ + Ҫʹmotor_start(void)motor_mov(unsigned int speed)ǰţ壬speedɿƵʣرտʹmotor_stop(void) + FWD(void)REV(void)ڸıתҪжϴǰλãҪʹúmotor_seat(void)ʼλÿʹmov_begin(viod)mov_end(void)ôƶʼλλ + void mov_loop1(void)void mov_loop1_ang(void)void mov_loop2(void)void mov_loop2_ang(void)void mov_step(void)void mov_step_ang(void)Ƶģʽ + ڽҪʹreceive_ttl_data(uint8_t rx_data)Ҫʹsend_set_resp(unsigned int OrderNum, unsigned int addr, unsigned char Num, unsigned char sData[]) + +//Э +PC-> + SOF 1ֽ 0x05 ʼֽ + Len 2ֽ + Fou_adr 2ֽ Դַ + Com_adr 2ֽ Ŀַ0ffΪ㲥ַ + Cmd16 2ֽ + Request-data Nֽ + XOR 2ֽ У + END 1ֽ 0x1B ֽ +ݲ + ܣ 00 ֱг 01 г + ƵУ 00 ֹͣ 01 02 еʼλ 03 еλ + ģʽ 00 㶯 01 һ 02 + жȦΪһ 00 00 65535 + мʱ 00 00 65535루ݷʱ䣩 + 㡱ֹͣʱ 00 00 65535 +05 00 14 00 A1 00 B1 F0 01 00 01 01 00 01 03 E8 00 10 CD 40 1B//һ + +->PC + SOF 1ֽ 0x05 ʼֽ + Len 2ֽ + Fou_adr 2ֽ Դַ + Com_adr 2ֽ Ŀַ0ffΪ㲥ַ + Cmd16 2ֽ + Request-data Nֽ + XOR 2ֽ У + END 1ֽ 0x1B ֽ +ݲ + ܣ 00 ֱг 01 г + ƵУ 00 ֹͣ 01 02 еʼλ 03 еλ + ģʽ 00 㶯 01 һ 02 + λ״̬ 00 ״̬ 01 ʼλ 02 λ 03 ͨդ + ѹ 00 00 65535 + ѹ 00 00 65535 + ȣ 00 00 65535 +05 00 14 00 A1 00 B1 F0 01 00 01 01 03 07 03 00 00 00 10 CD 40 1B + +//ֱг̵תһȦˮƽλΪ5mm +//г̵תһȦת4㣻 +