/*-------------------------------------------------------------------------- SC92F7490_C.H C Header file for SC92F7490 microcontroller. Copyright (c) 2018 Shenzhen SinOne Chip Electronic CO., Ltd. All rights reserved. ÉîÛÚÊÐÈüԪ΢µç×ÓÓÐÏÞ¹«Ë¾ °æ±¾ºÅ: V1.0 ÈÕÆÚ: 2018.07.25 --------------------------------------------------------------------------*/ #ifndef _SC92F7490_H_ #define _SC92F7490_H_ /* ------------------- ×ֽڼĴæÆ÷-------------------- */ ///*CPU*/ sfr ACC = 0xE0; //ÀÛ¼ÓÆ÷£Á sfr B = 0xF0; //ͨÓüĴæÆ÷B sfr PSW = 0xD0; //³ÌÐò״̬×Ö sfr DPH = 0x83; //Êý¾ÝÖ¸Õë¸ß8λ sfr DPL = 0x82; //Êý¾ÝÖ¸ÕëµÍ8λ sfr SP = 0x81; //¶ÑÕ»Ö¸Õë /*system*/ sfr PCON = 0x87; //µçÔ´¹ÜÀí¿ØÖƼĴæÆ÷ /*interrupt*/ sfr IP1 = 0XB9; //ÖжÏÓÅÏȼ¶¿ØÖƼĴæÆ÷1 sfr IP = 0xB8; //ÖжÏÓÅÏÈȨ¿ØÖƼĴæÆ÷ sfr IE = 0xA8; //ÖжϿØÖƼĴæÆ÷ sfr IE1 = 0XA9; //ÖжϿØÖƼĴæÆ÷1 /*PORT*/ sfr P2PH = 0xA2; //P2¿Úģʽ¿ØÖƼĴæÆ÷0 sfr P2CON = 0xA1; //P2¿Úģʽ¿ØÖƼĴæÆ÷1 sfr P2 = 0xA0; //P2¿ÚÊý¾Ý¼Ä´æÆ÷ sfr P1PH = 0x92; //P1¿Úģʽ¿ØÖƼĴæÆ÷0 sfr P1CON = 0x91; //P1¿Úģʽ¿ØÖƼĴæÆ÷1 sfr P1 = 0x90; //P1¿ÚÊý¾Ý¼Ä´æÆ÷ sfr P0PH = 0x9B; //P0¿Úģʽ¿ØÖƼĴæÆ÷1 sfr P0CON = 0x9A; //P0¿Úģʽ¿ØÖƼĴæÆ÷1 sfr P0 = 0x80; //P0¿ÚÊý¾Ý¼Ä´æÆ÷ sfr IOHCON = 0x97; //IOHÉèÖüĴæÆ÷ /*TIMER*/ sfr TMCON = 0x8E; //¶¨Ê±Æ÷ƵÂÊ¿ØÖƼĴæÆ÷ sfr TH1 = 0x8D; //¶¨Ê±Æ÷1¸ß8λ sfr TH0 = 0x8C; //¶¨Ê±Æ÷0¸ß8λ sfr TL1 = 0x8B; //¶¨Ê±Æ÷1µÍ8λ sfr TL0 = 0x8A; //¶¨Ê±Æ÷0µÍ8λ sfr TMOD = 0x89; //¶¨Ê±Æ÷¹¤×÷ģʽ¼Ä´æÆ÷ sfr TCON = 0x88; //¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ sfr T2CON = 0XC8; //¶¨Ê±Æ÷2¿ØÖƼĴæÆ÷ sfr T2MOD = 0XC9; //¶¨Ê±Æ÷2¹¤×÷ģʽ¼Ä´æÆ÷ sfr RCAP2L = 0XCA; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½µÍ8λ sfr RCAP2H = 0XCB; //¶¨Ê±Æ÷2ÖØÔØ/²¶×½¸ß8λ sfr TL2 = 0XCC; //¶¨Ê±Æ÷2µÍ8λ sfr TH2 = 0XCD; //¶¨Ê±Æ÷2¸ß8λ /*ADC*/ sfr ADCCFG0 = 0xAB; //ADCÉèÖüĴæÆ÷0 sfr ADCCFG1 = 0xAC; //ADCÉèÖüĴæÆ÷1 sfr ADCCON = 0XAD; //ADC¿ØÖƼĴæÆ÷ sfr ADCVL = 0xAE; //ADC ½á¹û¼Ä´æÆ÷ sfr ADCVH = 0xAF; //ADC ½á¹û¼Ä´æÆ÷ ///*WatchDog*/ sfr BTMCON = 0XCE; //µÍƵ¶¨Ê±Æ÷¿ØÖƼĴæÆ÷ sfr WDTCON = 0xCF; //WDT¿ØÖƼĴæÆ÷ /*LCD*/ sfr OTCON = 0X8F; //LCDµçѹÊä³ö¿ØÖƼĴæÆ÷ sfr P0VO = 0X9C; //P0 LCD Bais Êä³ö¼Ä´æÆ÷ /*INT*/ sfr INT0F = 0XBA; //INT0 ϽµÑØÖжϿØÖƼĴæÆ÷ sfr INT0R = 0XBB; //INT0 ÉϽµÑØÖжϿØÖƼĴæÆ÷÷ sfr INT2F = 0XC6; //INT2 ϽµÑØÖжϿØÖƼĴæÆ÷ sfr INT2R = 0XC7; //INT2 ÉϽµÑØÖжϿØÖƼĴæÆ÷ /*IAP */ sfr IAPCTL = 0xF6; //IAP¿ØÖƼĴæÆ÷ sfr IAPDAT = 0xF5; //IAPÊý¾Ý¼Ä´æÆ÷ sfr IAPADE = 0xF4; //IAPÀ©Õ¹µØÖ·¼Ä´æÆ÷ sfr IAPADH = 0xF3; //IAPдÈëµØÖ·¸ßλ¼Ä´æÆ÷ sfr IAPADL = 0xF2; //IAPдÈëµØÖ·µÍ8λ¼Ä´æÆ÷ sfr IAPKEY = 0xF1; //IAP±£»¤¼Ä´æÆ÷ /*SSI*/ sfr SS0CON0 = 0XA5; //SSI0¿ØÖƼĴæÆ÷2 sfr SS0CON1 = 0XA6; //SSI0¿ØÖƼĴæÆ÷1 sfr SS0CON2 = 0XA4; //SSI0¿ØÖƼĴæÆ÷0 sfr SS0DAT = 0XA7; //SSI0Êý¾Ý¼Ä´æÆ÷ sfr SS1CON2 = 0X95; //SSI1¿ØÖƼĴæÆ÷2 sfr SS1CON0 = 0X9D; //SSI1¿ØÖƼĴæÆ÷0 sfr SS1CON1 = 0X9E; //SSI1¿ØÖƼĴæÆ÷1 sfr SS1DAT = 0X9F; //SSI1Êý¾Ý¼Ä´æÆ÷ /*CHKSUM*/ sfr OPERCON = 0xEF; //ÔËËã¿ØÖƼĴæÆ÷ sfr CHKSUML = 0xFC; //CHKSUM½á¹û¼Ä´æÆ÷µÍλ sfr CHKSUMH = 0XFD; //CHKSUM½á¹û¼Ä´æÆ÷¸ßλ /*option*/ sfr OPINX = 0XFE; //OptionÖ¸Õë sfr OPREG = 0XFF; //Option¼Ä´æÆ÷ sfr P5PH = 0xDA; sfr P5CON = 0xD9; sfr P5 = 0xD8; ///* ------------------- λ¼Ä´æÆ÷-------------------- */ /*PSW*/ sbit CY = PSW^7; //±ê־λ 0:¼Ó·¨ÔËËã×î¸ßλÎÞ½ø룬»òÕß¼õ·¨ÔËËã×î¸ßλÎÞ½èλʱ 1:¼Ó·¨ÔËËã×î¸ßλÓнø룬»òÕß¼õ·¨ÔËËã×î¸ßλÓнèλʱ sbit AC = PSW^6; //½øλ¸¨Öú±ê־λ 0:ÎÞ½èλ¡¢½øλ 1:¼Ó·¨ÔËËãʱÔÚbit3λÓнø룬»ò¼õ·¨ÔËËãÔÚbit3λÓнèλʱ sbit F0 = PSW^5; //Óû§±ê־λ sbit RS1 = PSW^4; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ sbit RS0 = PSW^3; //¹¤×÷¼Ä´æÆ÷×éÑ¡Ôñλ sbit OV = PSW^2; //Òç³ö±ê־λ sbit F1 = PSW^1; //F1±êÖ¾ sbit P = PSW^0; //Ææż±ê־λ 0:ACCÖÐ1µÄ¸öÊýΪżÊý£¨°üÀ¨0¸ö£© 1:ACCÖÐ1µÄ¸öÊýΪÆæÊý /*T2CON*/ sbit TF2 = T2CON^7; sbit EXF2 = T2CON^6; sbit RCLK = T2CON^5; sbit TCLK = T2CON^4; sbit EXEN2 = T2CON^3; sbit TR2 = T2CON^2; sbit T2 = T2CON^1; sbit CP = T2CON^0; /*IP*/ sbit IPADC = IP^6; //ADCÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 ADCµÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡± sbit IPT2 = IP^5; //Timer2ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer2µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨Timer2µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡± sbit IPSSI0 = IP^4; //SSI0ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨SSI0µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨SSI0µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡± sbit IPT1 = IP^3; //Timer1ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 1µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 1µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡± sbit IPT0 = IP^1; //Timer0ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨 Timer 0µÄÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨 Timer 0µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡± sbit IPINT0 = IP^0; //INT0ÖжÏÓÅÏÈ¿ØÖÆλ 0:É趨INT0ÖжÏÓÅÏÈȨÊÇ ¡°µÍ¡± 1:É趨INT0µÄÖжÏÓÅÏÈȨÊÇ ¡°¸ß¡± /*IE*/ sbit EA = IE^7; //ÖжÏʹÄܵÄ×Ü¿ØÖÆ 0:¹Ø±ÕËùÓеÄÖÐ¶Ï 1:´ò¿ªËùÓеÄÖÐ¶Ï sbit EADC = IE^6; //ADCÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕADCÖÐ¶Ï 1:´ò¿ªADCÖÐ¶Ï sbit ET2 = IE^5; //Timer2ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTimer2ÖÐ¶Ï 1:´ò¿ªTimer2ÖÐ¶Ï sbit ESSI0 = IE^4; //SSI0ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕSSI0ÖÐ¶Ï 1:´ò¿ªSSI0ÖÐ¶Ï sbit ET1 = IE^3; //Timer1ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER1ÖÐ¶Ï 1:´ò¿ªTIMER1ÖÐ¶Ï sbit ET0 = IE^1; //Timer0ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕTIMER0ÖÐ¶Ï 1:´ò¿ªTIMER0ÖÐ¶Ï sbit EINT0 = IE^0; //INT0ÖжÏʹÄÜ¿ØÖÆ 0:¹Ø±ÕINT0ÖÐ¶Ï 1:´ò¿ªINT0ÖÐ¶Ï /*TCON*/ sbit TF1 = TCON^7; //T1Òç³öÖжÏÇëÇó±ê־λ T1²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF1ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPUÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ sbit TR1 = TCON^6; //¶¨Ê±Æ÷T1µÄÔËÐпØÖÆλ 0:Timer1½ûÖ¹¼ÆÊý 1:Timer1¿ªÊ¼¼ÆÊý sbit TF0 = TCON^5; //T0Òç³öÖжÏÇëÇó±ê־λ T0²úÉúÒç³ö£¬·¢ÉúÖжÏʱ£¬Ó²¼þ½«TF0ÖÃΪ¡°1¡±£¬ÉêÇëÖжϣ¬CPUÏìӦʱ£¬Ó²¼þÇå¡°0¡±¡£ sbit TR0 = TCON^4; //¶¨Ê±Æ÷T0µÄÔËÐпØÖÆλ 0:Timer0½ûÖ¹¼ÆÊý 1:Timer0¿ªÊ¼¼ÆÊý /******************* P0 ******************/ sbit P05 = P0^5; /******************* P1 ******************/ sbit P13 = P1^3; sbit P12 = P1^2; sbit P11 = P1^1; /******************* P2 ******************/ sbit P21 = P2^1; sbit P20 = P2^0; /**************************************************************************** *×¢Ò⣺³õʼ»¯IO¿Úºó£¬Ðèµ÷ÓÃÒÔϺꡣ *****************************************************************************/ #define SC92F7490_NIO_Init() {P0CON|=0xDF;P1CON|=0xF1;P2CON|=0xFC;P5CON|=0x03;} #endif