1、SIG16132驱动修正,电阻采集的激励源与4-20mA回采产生了冲突; 2、HART连接模式切换,补充了Vout的控制; |
||
---|---|---|
.vscode | ||
App | ||
Core | ||
Drivers | ||
LVGL | ||
MDK-ARM | ||
Middlewares/Third_Party/FreeRTOS/Source | ||
Utils | ||
.mxproject | ||
signal_generator.ioc |
1、SIG16132驱动修正,电阻采集的激励源与4-20mA回采产生了冲突; 2、HART连接模式切换,补充了Vout的控制; |
||
---|---|---|
.vscode | ||
App | ||
Core | ||
Drivers | ||
LVGL | ||
MDK-ARM | ||
Middlewares/Third_Party/FreeRTOS/Source | ||
Utils | ||
.mxproject | ||
signal_generator.ioc |