备份

Core/Inc/stm32f4xx_it.h

@@ -54,6 +54,7 @@ void UsageFault_Handler(void);
 void DebugMon_Handler(void);
 void EXTI1_IRQHandler(void);
 void EXTI3_IRQHandler(void);
+void DMA1_Stream0_IRQHandler(void);
 void DMA1_Stream1_IRQHandler(void);
 void DMA1_Stream2_IRQHandler(void);
 void DMA1_Stream3_IRQHandler(void);
@@ -62,6 +63,7 @@ void TIM1_UP_TIM10_IRQHandler(void);
 void TIM3_IRQHandler(void);
 void USART2_IRQHandler(void);
 void USART3_IRQHandler(void);
+void DMA1_Stream7_IRQHandler(void);
 void UART4_IRQHandler(void);
 void UART5_IRQHandler(void);
 void DMA2_Stream1_IRQHandler(void);

Core/Src/dma.c

@@ -44,6 +44,9 @@ void MX_DMA_Init(void)
   __HAL_RCC_DMA1_CLK_ENABLE();
 
   /* DMA interrupt init */
+  /* DMA1_Stream0_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
   /* DMA1_Stream1_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
@@ -56,6 +59,9 @@ void MX_DMA_Init(void)
   /* DMA1_Stream4_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
+  /* DMA1_Stream7_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
   /* DMA2_Stream1_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);

Core/Src/freertos.c

@@ -188,7 +188,7 @@ void start_dac_task(void const *argument)
   {
     dac161s997_output(DAC161S997_1, 12.0f);
     dac161s997_output(DAC161S997_2, 12.0f);
-    vTaskDelay(300);
+    vTaskDelay(200);
   }
   /* USER CODE END start_dac_task */
 }

Core/Src/main.c

@@ -120,6 +120,7 @@ int main(void)
   HAL_UARTEx_ReceiveToIdle_DMA(&huart4, lcd_uart4.rx_data_temp, ARRAY_LEN(lcd_uart4.rx_data_temp));
   HAL_UARTEx_ReceiveToIdle_DMA(&huart6, ble1_uart6.rx_data_temp, ARRAY_LEN(ble1_uart6.rx_data_temp));
   HAL_UARTEx_ReceiveToIdle_DMA(&huart3, ble2_uart3.rx_data_temp, ARRAY_LEN(ble2_uart3.rx_data_temp));
+  HAL_UARTEx_ReceiveToIdle_DMA(&huart5, hart1_uart5.rx_data_temp, ARRAY_LEN(hart1_uart5.rx_data_temp));
   hart_ht1200m_reset();                     // 夝佝HT1200M模块
   HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); // 坯动PWM输出，用于驱动HT1200M模块
   /* USER CODE END 2 */
@@ -174,8 +175,7 @@ void SystemClock_Config(void)
 
   /** Initializes the CPU, AHB and APB buses clocks
    */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
@@ -215,8 +215,24 @@ void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
     }
     HAL_UARTEx_ReceiveToIdle_DMA(&huart3, ble2_uart3.rx_data_temp, ARRAY_LEN(ble2_uart3.rx_data_temp));
   }
+  if (huart == &huart5)
+  {
+    __HAL_UNLOCK(huart);
+    hart1_uart5.rx_num = Size;
+    memset(hart1_uart5.rx_data, 0, ARRAY_LEN(hart1_uart5.rx_data));
+    memcpy(hart1_uart5.rx_data, hart1_uart5.rx_data_temp, Size);
+    if (tcp_echo_flags_hart1 == 1)
+    {
+      user_send_data_hart1(hart1_uart5.rx_data, Size);
     }
+    HAL_UARTEx_ReceiveToIdle_DMA(&huart5, hart1_uart5.rx_data_temp, ARRAY_LEN(hart1_uart5.rx_data_temp));
+  }
+}
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
 
+  HART1_RTS_RECEIVE;
+}
 /* USER CODE END 4 */
 
 /**
@@ -232,7 +248,8 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
   /* USER CODE BEGIN Callback 0 */
 
   /* USER CODE END Callback 0 */
-  if (htim->Instance == TIM1) {
+  if (htim->Instance == TIM1)
+  {
     HAL_IncTick();
   }
   /* USER CODE BEGIN Callback 1 */

Core/Src/stm32f4xx_it.c

@@ -25,6 +25,7 @@
 #include "tim.h"
 #include "usart.h"
 #include "tcpserverc.h"
+#include "ht1200m.h"
 /* USER CODE END Includes */
 
 /* Private typedef -----------------------------------------------------------*/
@@ -64,6 +65,8 @@ extern ETH_HandleTypeDef heth;
 extern TIM_HandleTypeDef htim3;
 extern DMA_HandleTypeDef hdma_uart4_rx;
 extern DMA_HandleTypeDef hdma_uart4_tx;
+extern DMA_HandleTypeDef hdma_uart5_tx;
+extern DMA_HandleTypeDef hdma_uart5_rx;
 extern DMA_HandleTypeDef hdma_usart3_rx;
 extern DMA_HandleTypeDef hdma_usart3_tx;
 extern DMA_HandleTypeDef hdma_usart6_rx;
@@ -205,6 +208,20 @@ void EXTI3_IRQHandler(void)
   /* USER CODE END EXTI3_IRQn 1 */
 }
 
+/**
+ * @brief This function handles DMA1 stream0 global interrupt.
+ */
+void DMA1_Stream0_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart5_rx);
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 1 */
+}
+
 /**
  * @brief This function handles DMA1 stream1 global interrupt.
  */
@@ -334,6 +351,28 @@ void USART3_IRQHandler(void)
   /* USER CODE END USART3_IRQn 1 */
 }
 
+/**
+ * @brief This function handles DMA1 stream7 global interrupt.
+ */
+void DMA1_Stream7_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */
+  // if (__HAL_DMA_GET_FLAG(&hdma_uart5_tx, DMA_FLAG_TCIF3_7) != RESET)
+  // {
+  //   uint8_t i = 0;
+  //   for (i = 0; i < 200; i++)
+  //   {
+  //     HART1_RTS_SEND;
+  //   }
+  //   HART1_RTS_RECEIVE;
+  // }
+  /* USER CODE END DMA1_Stream7_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart5_tx);
+  /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream7_IRQn 1 */
+}
+
 /**
  * @brief This function handles UART4 global interrupt.
  */
@@ -353,24 +392,24 @@ void UART4_IRQHandler(void)
 void UART5_IRQHandler(void)
 {
   /* USER CODE BEGIN UART5_IRQn 0 */
-  uint8_t receive_data = 0;
+  // uint8_t receive_data = 0;
-  if (__HAL_UART_GET_FLAG(&huart5, UART_FLAG_RXNE) != RESET)
+  // if (__HAL_UART_GET_FLAG(&huart5, UART_FLAG_RXNE) != RESET)
-  {
+  // {
-    HAL_UART_Receive(&huart5, &receive_data, 1, 1);
+  //   HAL_UART_Receive(&huart5, &receive_data, 1, 1);
-    hart1_uart5.rx_data[hart1_uart5.rx_num] = receive_data;
+  //   hart1_uart5.rx_data[hart1_uart5.rx_num] = receive_data;
-    hart1_uart5.rx_num++;
+  //   hart1_uart5.rx_num++;
-    __HAL_UART_CLEAR_IDLEFLAG(&huart5);
+  //   __HAL_UART_CLEAR_IDLEFLAG(&huart5);
-  }
+  // }
-  // 空闲中断
+  // // 空闲中断
-  if (__HAL_UART_GET_FLAG(&huart5, UART_FLAG_IDLE) != RESET)
+  // if (__HAL_UART_GET_FLAG(&huart5, UART_FLAG_IDLE) != RESET)
-  {
+  // {
-    if (tcp_echo_flags_hart1 == 1)
+  //   if (tcp_echo_flags_hart1 == 1)
-    {
+  //   {
-      user_send_data_hart1(hart1_uart5.rx_data, hart1_uart5.rx_num);
+  //     user_send_data_hart1(hart1_uart5.rx_data, hart1_uart5.rx_num);
-    }
+  //   }
-    hart1_uart5.rx_num = 0;
+  //   hart1_uart5.rx_num = 0;
-    __HAL_UART_CLEAR_IDLEFLAG(&huart5);
+  //   __HAL_UART_CLEAR_IDLEFLAG(&huart5);
-  }
+  // }
   /* USER CODE END UART5_IRQn 0 */
   HAL_UART_IRQHandler(&huart5);
   /* USER CODE BEGIN UART5_IRQn 1 */

Core/Src/usart.c

@@ -31,6 +31,8 @@ UART_HandleTypeDef huart3;
 UART_HandleTypeDef huart6;
 DMA_HandleTypeDef hdma_uart4_rx;
 DMA_HandleTypeDef hdma_uart4_tx;
+DMA_HandleTypeDef hdma_uart5_tx;
+DMA_HandleTypeDef hdma_uart5_rx;
 DMA_HandleTypeDef hdma_usart3_rx;
 DMA_HandleTypeDef hdma_usart3_tx;
 DMA_HandleTypeDef hdma_usart6_rx;
@@ -278,6 +280,43 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
     GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
     HAL_GPIO_Init(HART1_RX_GPIO_Port, &GPIO_InitStruct);
 
+    /* UART5 DMA Init */
+    /* UART5_TX Init */
+    hdma_uart5_tx.Instance = DMA1_Stream7;
+    hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4;
+    hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_uart5_tx.Init.Mode = DMA_NORMAL;
+    hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx);
+
+    /* UART5_RX Init */
+    hdma_uart5_rx.Instance = DMA1_Stream0;
+    hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4;
+    hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_uart5_rx.Init.Mode = DMA_NORMAL;
+    hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx);
+
     /* UART5 interrupt Init */
     HAL_NVIC_SetPriority(UART5_IRQn, 5, 0);
     HAL_NVIC_EnableIRQ(UART5_IRQn);
@@ -485,6 +524,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 
     HAL_GPIO_DeInit(HART1_RX_GPIO_Port, HART1_RX_Pin);
 
+    /* UART5 DMA DeInit */
+    HAL_DMA_DeInit(uartHandle->hdmatx);
+    HAL_DMA_DeInit(uartHandle->hdmarx);
+
     /* UART5 interrupt Deinit */
     HAL_NVIC_DisableIRQ(UART5_IRQn);
   /* USER CODE BEGIN UART5_MspDeInit 1 */

MDK-ARM/TEST2.uvoptx

@@ -148,24 +148,7 @@
           <Name>-UB -O2254 -SF1800 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407VGTx$CMSIS\Flash\STM32F4xx_1024.FLM)</Name>
         </SetRegEntry>
       </TargetDriverDllRegistry>
-      <Breakpoint>
+      <Breakpoint/>
-        <Bp>
-          <Number>0</Number>
-          <Type>0</Type>
-          <LineNumber>289</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>134219030</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>1</BreakIfRCount>
-          <Filename>../Core/Src/stm32f4xx_it.c</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression>\\TEST2\../Core/Src/stm32f4xx_it.c\289</Expression>
-        </Bp>
-      </Breakpoint>
       <WatchWindow1>
         <Ww>
           <count>0</count>

TEST2.ioc

@@ -8,7 +8,9 @@ Dma.Request2=UART4_RX
 Dma.Request3=UART4_TX
 Dma.Request4=USART3_RX
 Dma.Request5=USART3_TX
-Dma.RequestsNb=6
+Dma.Request6=UART5_TX
+Dma.Request7=UART5_RX
+Dma.RequestsNb=8
 Dma.UART4_RX.2.Direction=DMA_PERIPH_TO_MEMORY
 Dma.UART4_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE
 Dma.UART4_RX.2.Instance=DMA1_Stream2
@@ -29,6 +31,26 @@ Dma.UART4_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
 Dma.UART4_TX.3.PeriphInc=DMA_PINC_DISABLE
 Dma.UART4_TX.3.Priority=DMA_PRIORITY_VERY_HIGH
 Dma.UART4_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+Dma.UART5_RX.7.Direction=DMA_PERIPH_TO_MEMORY
+Dma.UART5_RX.7.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.UART5_RX.7.Instance=DMA1_Stream0
+Dma.UART5_RX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UART5_RX.7.MemInc=DMA_MINC_ENABLE
+Dma.UART5_RX.7.Mode=DMA_NORMAL
+Dma.UART5_RX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UART5_RX.7.PeriphInc=DMA_PINC_DISABLE
+Dma.UART5_RX.7.Priority=DMA_PRIORITY_LOW
+Dma.UART5_RX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
+Dma.UART5_TX.6.Direction=DMA_MEMORY_TO_PERIPH
+Dma.UART5_TX.6.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.UART5_TX.6.Instance=DMA1_Stream7
+Dma.UART5_TX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UART5_TX.6.MemInc=DMA_MINC_ENABLE
+Dma.UART5_TX.6.Mode=DMA_NORMAL
+Dma.UART5_TX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UART5_TX.6.PeriphInc=DMA_PINC_DISABLE
+Dma.UART5_TX.6.Priority=DMA_PRIORITY_LOW
+Dma.UART5_TX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
 Dma.USART3_RX.4.Direction=DMA_PERIPH_TO_MEMORY
 Dma.USART3_RX.4.FIFOMode=DMA_FIFOMODE_DISABLE
 Dma.USART3_RX.4.Instance=DMA1_Stream1
@@ -184,10 +206,12 @@ Mcu.UserName=STM32F407VGTx
 MxCube.Version=6.8.0
 MxDb.Version=DB.6.0.80
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.DMA1_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA1_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DMA2_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DMA2_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false

User/application/src/tcpserverc.c

@@ -37,8 +37,8 @@ static err_t tcpecho_recv_hart1(void *arg, struct tcp_pcb *tpcb, struct pbuf *p,
 #if 1
         memcpy(hart1_uart5.tx_data, (int *)p->payload, p->tot_len);
         HART1_RTS_SEND;
-        HAL_UART_Transmit(&huart5, hart1_uart5.tx_data, p->tot_len, 500);
+        dma_usart_send(&huart5, hart1_uart5.tx_data, p->tot_len);      
-        HART1_RTS_RECEIVE;
+        // HART1_RTS_RECEIVE;
 #endif
 #if 0
         memcpy(ble1_uart6.tx_data, (int *)p->payload, p->tot_len);