From aa93ff2508a14ac47b62aac19d9b3ec72fb73d4d Mon Sep 17 00:00:00 2001 From: wangxujie Date: Mon, 10 Feb 2025 18:51:51 +0800 Subject: [PATCH] =?UTF-8?q?=E4=B8=A4=E8=B7=AFHART=E4=BD=BF=E7=94=A8DMA?= =?UTF-8?q?=E5=8F=91=E9=80=81=E5=92=8C=E6=8E=A5=E6=94=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Core/Inc/stm32f4xx_it.h | 2 + Core/Src/dma.c | 6 +++ Core/Src/main.c | 23 ++++++++++- Core/Src/stm32f4xx_it.c | 66 ++++++++++++++++++++++--------- Core/Src/usart.c | 47 +++++++++++++++++++++- TEST2.ioc | 30 ++++++++++++-- User/application/src/tcpserverc.c | 5 +-- 7 files changed, 151 insertions(+), 28 deletions(-) diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h index 0be3aeb..257123a 100644 --- a/Core/Inc/stm32f4xx_it.h +++ b/Core/Inc/stm32f4xx_it.h @@ -59,6 +59,8 @@ void DMA1_Stream1_IRQHandler(void); void DMA1_Stream2_IRQHandler(void); void DMA1_Stream3_IRQHandler(void); void DMA1_Stream4_IRQHandler(void); +void DMA1_Stream5_IRQHandler(void); +void DMA1_Stream6_IRQHandler(void); void TIM1_UP_TIM10_IRQHandler(void); void TIM3_IRQHandler(void); void USART2_IRQHandler(void); diff --git a/Core/Src/dma.c b/Core/Src/dma.c index de2499f..df6eb8e 100644 --- a/Core/Src/dma.c +++ b/Core/Src/dma.c @@ -59,6 +59,12 @@ void MX_DMA_Init(void) /* DMA1_Stream4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); + /* DMA1_Stream5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); + /* DMA1_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); /* DMA1_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); diff --git a/Core/Src/main.c b/Core/Src/main.c index 6990a64..8be7d19 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -121,6 +121,7 @@ int main(void) HAL_UARTEx_ReceiveToIdle_DMA(&huart6, ble1_uart6.rx_data_temp, ARRAY_LEN(ble1_uart6.rx_data_temp)); HAL_UARTEx_ReceiveToIdle_DMA(&huart3, ble2_uart3.rx_data_temp, ARRAY_LEN(ble2_uart3.rx_data_temp)); HAL_UARTEx_ReceiveToIdle_DMA(&huart5, hart1_uart5.rx_data_temp, ARRAY_LEN(hart1_uart5.rx_data_temp)); + HAL_UARTEx_ReceiveToIdle_DMA(&huart2, hart2_uart2.rx_data_temp, ARRAY_LEN(hart2_uart2.rx_data_temp)); hart_ht1200m_reset(); // 夝佝HT1200M模块 HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); // 坯动PWM输出，用于驱动HT1200M模块 /* USER CODE END 2 */ @@ -227,11 +228,29 @@ void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) } HAL_UARTEx_ReceiveToIdle_DMA(&huart5, hart1_uart5.rx_data_temp, ARRAY_LEN(hart1_uart5.rx_data_temp)); } + if (huart == &huart2) + { + __HAL_UNLOCK(huart); + hart2_uart2.rx_num = Size; + memset(hart2_uart2.rx_data, 0, ARRAY_LEN(hart2_uart2.rx_data)); + memcpy(hart2_uart2.rx_data, hart2_uart2.rx_data_temp, Size); + if (tcp_echo_flags_hart2 == 1) + { + user_send_data_hart2(hart2_uart2.rx_data, Size); + } + HAL_UARTEx_ReceiveToIdle_DMA(&huart2, hart2_uart2.rx_data_temp, ARRAY_LEN(hart2_uart2.rx_data_temp)); + } } void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { - - HART1_RTS_RECEIVE; + if (huart == &huart5) + { + HART1_RTS_RECEIVE; + } + if (huart == &huart2) + { + HART2_RTS_RECEIVE; + } } /* USER CODE END 4 */ diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c index 5bac172..bfe6b03 100644 --- a/Core/Src/stm32f4xx_it.c +++ b/Core/Src/stm32f4xx_it.c @@ -67,6 +67,8 @@ extern DMA_HandleTypeDef hdma_uart4_rx; extern DMA_HandleTypeDef hdma_uart4_tx; extern DMA_HandleTypeDef hdma_uart5_tx; extern DMA_HandleTypeDef hdma_uart5_rx; +extern DMA_HandleTypeDef hdma_usart2_rx; +extern DMA_HandleTypeDef hdma_usart2_tx; extern DMA_HandleTypeDef hdma_usart3_rx; extern DMA_HandleTypeDef hdma_usart3_tx; extern DMA_HandleTypeDef hdma_usart6_rx; @@ -278,6 +280,34 @@ void DMA1_Stream4_IRQHandler(void) /* USER CODE END DMA1_Stream4_IRQn 1 */ } +/** + * @brief This function handles DMA1 stream5 global interrupt. + */ +void DMA1_Stream5_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ + + /* USER CODE END DMA1_Stream5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_rx); + /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ + + /* USER CODE END DMA1_Stream5_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream6 global interrupt. + */ +void DMA1_Stream6_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ + + /* USER CODE END DMA1_Stream6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_tx); + /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ + + /* USER CODE END DMA1_Stream6_IRQn 1 */ +} + /** * @brief This function handles TIM1 update interrupt and TIM10 global interrupt. */ @@ -312,24 +342,24 @@ void TIM3_IRQHandler(void) void USART2_IRQHandler(void) { /* USER CODE BEGIN USART2_IRQn 0 */ - uint8_t receive_data = 0; - if (__HAL_UART_GET_FLAG(&huart2, UART_FLAG_RXNE) != RESET) - { - HAL_UART_Receive(&huart2, &receive_data, 1, 10); - hart2_uart2.rx_data[hart2_uart2.rx_num] = receive_data; - hart2_uart2.rx_num++; - __HAL_UART_CLEAR_IDLEFLAG(&huart2); - } - // 空闲中断 - if (__HAL_UART_GET_FLAG(&huart2, UART_FLAG_IDLE) != RESET) - { - if (tcp_echo_flags_hart2 == 1) - { - user_send_data_hart2(hart2_uart2.rx_data, hart2_uart2.rx_num); - } - hart2_uart2.rx_num = 0; - __HAL_UART_CLEAR_IDLEFLAG(&huart2); - } + // uint8_t receive_data = 0; + // if (__HAL_UART_GET_FLAG(&huart2, UART_FLAG_RXNE) != RESET) + // { + // HAL_UART_Receive(&huart2, &receive_data, 1, 10); + // hart2_uart2.rx_data[hart2_uart2.rx_num] = receive_data; + // hart2_uart2.rx_num++; + // __HAL_UART_CLEAR_IDLEFLAG(&huart2); + // } + // // 空闲中断 + // if (__HAL_UART_GET_FLAG(&huart2, UART_FLAG_IDLE) != RESET) + // { + // if (tcp_echo_flags_hart2 == 1) + // { + // user_send_data_hart2(hart2_uart2.rx_data, hart2_uart2.rx_num); + // } + // hart2_uart2.rx_num = 0; + // __HAL_UART_CLEAR_IDLEFLAG(&huart2); + // } /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); /* USER CODE BEGIN USART2_IRQn 1 */ diff --git a/Core/Src/usart.c b/Core/Src/usart.c index d607fa4..a85fa47 100644 --- a/Core/Src/usart.c +++ b/Core/Src/usart.c @@ -33,6 +33,8 @@ DMA_HandleTypeDef hdma_uart4_rx; DMA_HandleTypeDef hdma_uart4_tx; DMA_HandleTypeDef hdma_uart5_tx; DMA_HandleTypeDef hdma_uart5_rx; +DMA_HandleTypeDef hdma_usart2_rx; +DMA_HandleTypeDef hdma_usart2_tx; DMA_HandleTypeDef hdma_usart3_rx; DMA_HandleTypeDef hdma_usart3_tx; DMA_HandleTypeDef hdma_usart6_rx; @@ -290,7 +292,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; hdma_uart5_tx.Init.Mode = DMA_NORMAL; - hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart5_tx.Init.Priority = DMA_PRIORITY_VERY_HIGH; hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK) { @@ -308,7 +310,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; hdma_uart5_rx.Init.Mode = DMA_NORMAL; - hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_uart5_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK) { @@ -344,6 +346,43 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + /* USART2 DMA Init */ + /* USART2_RX Init */ + hdma_usart2_rx.Instance = DMA1_Stream5; + hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; + hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_rx.Init.Mode = DMA_NORMAL; + hdma_usart2_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; + hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); + + /* USART2_TX Init */ + hdma_usart2_tx.Instance = DMA1_Stream6; + hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_VERY_HIGH; + hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); + /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); HAL_NVIC_EnableIRQ(USART2_IRQn); @@ -548,6 +587,10 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) */ HAL_GPIO_DeInit(GPIOD, HART2_TX_Pin|HART2_RX_Pin); + /* USART2 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); + /* USART2 interrupt Deinit */ HAL_NVIC_DisableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspDeInit 1 */ diff --git a/TEST2.ioc b/TEST2.ioc index 9d11aeb..cd7bd74 100644 --- a/TEST2.ioc +++ b/TEST2.ioc @@ -10,7 +10,9 @@ Dma.Request4=USART3_RX Dma.Request5=USART3_TX Dma.Request6=UART5_TX Dma.Request7=UART5_RX -Dma.RequestsNb=8 +Dma.Request8=USART2_RX +Dma.Request9=USART2_TX +Dma.RequestsNb=10 Dma.UART4_RX.2.Direction=DMA_PERIPH_TO_MEMORY Dma.UART4_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE Dma.UART4_RX.2.Instance=DMA1_Stream2 @@ -39,7 +41,7 @@ Dma.UART5_RX.7.MemInc=DMA_MINC_ENABLE Dma.UART5_RX.7.Mode=DMA_NORMAL Dma.UART5_RX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.UART5_RX.7.PeriphInc=DMA_PINC_DISABLE -Dma.UART5_RX.7.Priority=DMA_PRIORITY_LOW +Dma.UART5_RX.7.Priority=DMA_PRIORITY_VERY_HIGH Dma.UART5_RX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode Dma.UART5_TX.6.Direction=DMA_MEMORY_TO_PERIPH Dma.UART5_TX.6.FIFOMode=DMA_FIFOMODE_DISABLE @@ -49,8 +51,28 @@ Dma.UART5_TX.6.MemInc=DMA_MINC_ENABLE Dma.UART5_TX.6.Mode=DMA_NORMAL Dma.UART5_TX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.UART5_TX.6.PeriphInc=DMA_PINC_DISABLE -Dma.UART5_TX.6.Priority=DMA_PRIORITY_LOW +Dma.UART5_TX.6.Priority=DMA_PRIORITY_VERY_HIGH Dma.UART5_TX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.USART2_RX.8.Direction=DMA_PERIPH_TO_MEMORY +Dma.USART2_RX.8.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART2_RX.8.Instance=DMA1_Stream5 +Dma.USART2_RX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_RX.8.MemInc=DMA_MINC_ENABLE +Dma.USART2_RX.8.Mode=DMA_NORMAL +Dma.USART2_RX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_RX.8.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_RX.8.Priority=DMA_PRIORITY_VERY_HIGH +Dma.USART2_RX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.USART2_TX.9.Direction=DMA_MEMORY_TO_PERIPH +Dma.USART2_TX.9.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART2_TX.9.Instance=DMA1_Stream6 +Dma.USART2_TX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_TX.9.MemInc=DMA_MINC_ENABLE +Dma.USART2_TX.9.Mode=DMA_NORMAL +Dma.USART2_TX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_TX.9.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_TX.9.Priority=DMA_PRIORITY_VERY_HIGH +Dma.USART2_TX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode Dma.USART3_RX.4.Direction=DMA_PERIPH_TO_MEMORY Dma.USART3_RX.4.FIFOMode=DMA_FIFOMODE_DISABLE Dma.USART3_RX.4.Instance=DMA1_Stream1 @@ -211,6 +233,8 @@ NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA1_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA1_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA1_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA1_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA2_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA2_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true diff --git a/User/application/src/tcpserverc.c b/User/application/src/tcpserverc.c index bd878b3..8b0a236 100644 --- a/User/application/src/tcpserverc.c +++ b/User/application/src/tcpserverc.c @@ -37,7 +37,7 @@ static err_t tcpecho_recv_hart1(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, #if 1 memcpy(hart1_uart5.tx_data, (int *)p->payload, p->tot_len); HART1_RTS_SEND; - dma_usart_send(&huart5, hart1_uart5.tx_data, p->tot_len); + dma_usart_send(&huart5, hart1_uart5.tx_data, p->tot_len); // HART1_RTS_RECEIVE; #endif #if 0 @@ -73,8 +73,7 @@ static err_t tcpecho_recv_hart2(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, #if 1 memcpy(hart2_uart2.tx_data, (int *)p->payload, p->tot_len); HART2_RTS_SEND; - HAL_UART_Transmit(&huart2, hart2_uart2.tx_data, p->tot_len, 500); - HART2_RTS_RECEIVE; + dma_usart_send(&huart2, hart2_uart2.tx_data, p->tot_len); #endif #if 0 memcpy(hart1_uart5.tx_data, (int *)p->payload, p->tot_len);