/*
 * @Author: shenghao.xu
 * @Date: 2023-04-11 19:44:04
 * @LastEditors: shenghao.xu
 * @LastEditTime: 2023-06-15 13:16:40
 * @Description:继电器模块
 * email:545403892@qq.com
 * Copyright (c) 2023 by shenghao.xu, All Rights Reserved.
 */

#include "relay.h"
#include "tca9555.h"

extern tca9555_register tca9555_reg;

void relay_open_all(void)
{
    for (uint8_t i = 0; i < RELAY_NUM; i++)
    {
        relay_open(i + 1);
    }
}

/**
 * @description: 打开继电器 1-12
 * @param {uint8_t} num
 * @return {*}
 */
void relay_open(uint8_t num)
{
    switch (num)
    {
    case 1:
        tca9555_reg.port.p0.bit.b6 = 1;
        break;
    case 2:
        tca9555_reg.port.p0.bit.b5 = 1;
        break;
    case 3:
        tca9555_reg.port.p0.bit.b4 = 1;
        break;
    case 4:
        tca9555_reg.port.p0.bit.b3 = 1;
        break;
    case 5:
        tca9555_reg.port.p0.bit.b2 = 1;
        break;
    case 6:
        tca9555_reg.port.p0.bit.b1 = 1;
        break;
    case 7:
        tca9555_reg.port.p0.bit.b0 = 1;
        break;
    case 8:
        tca9555_reg.port.p0.bit.b7 = 1;
        break;
    case 9:
        tca9555_reg.port.p1.bit.b5 = 1;
        break;
    case 10:
        tca9555_reg.port.p1.bit.b4 = 1;
        break;
    case 11:
        tca9555_reg.port.p1.bit.b3 = 1;
        break;
    case 12:
        tca9555_reg.port.p1.bit.b2 = 1;
        break;
    case 13:
        tca9555_reg.port.p1.bit.b1 = 1;
        break;
    case 14:
        tca9555_reg.port.p1.bit.b0 = 1;
        break;
    default:
        return;
    }

    tca9555_write_output(&tca9555_reg);
}

/**
 * @description: 关闭继电器 1-12
 * @param {uint8_t} num
 * @return {*}
 */
void relay_close(uint8_t num)
{
    switch (num)
    {
    case 1:
        tca9555_reg.port.p0.bit.b6 = 0;
        break;
    case 2:
        tca9555_reg.port.p0.bit.b5 = 0;
        break;
    case 3:
        tca9555_reg.port.p0.bit.b4 = 0;
        break;
    case 4:
        tca9555_reg.port.p0.bit.b3 = 0;
        break;
    case 5:
        tca9555_reg.port.p0.bit.b2 = 0;
        break;
    case 6:
        tca9555_reg.port.p0.bit.b1 = 0;
        break;
    case 7:
        tca9555_reg.port.p0.bit.b0 = 0;
        break;
    case 8:
        tca9555_reg.port.p0.bit.b7 = 0;
        break;
    case 9:
        tca9555_reg.port.p1.bit.b5 = 0;
        break;
    case 10:
        tca9555_reg.port.p1.bit.b4 = 0;
        break;
    case 11:
        tca9555_reg.port.p1.bit.b3 = 0;
        break;
    case 12:
        tca9555_reg.port.p1.bit.b2 = 0;
        break;
    case 13:
        tca9555_reg.port.p1.bit.b1 = 0;
        break;
    case 14:
        tca9555_reg.port.p1.bit.b0 = 0;
        break;
    default:
        return;
    }

    tca9555_write_output(&tca9555_reg);
}

bool relay_isopen(uint8_t num)
{
    bool ret = false;
    tca9555_read_output(&tca9555_reg);
    switch (num)
    {
    case 1:
        ret = tca9555_reg.port.p0.bit.b6 == 0 ? false : true;
        break;
    case 2:
        ret = tca9555_reg.port.p0.bit.b5 == 0 ? false : true;
        break;
    case 3:
        ret = tca9555_reg.port.p0.bit.b4 == 0 ? false : true;
        break;
    case 4:
        ret = tca9555_reg.port.p0.bit.b3 == 0 ? false : true;
        break;
    case 5:
        ret = tca9555_reg.port.p0.bit.b2 == 0 ? false : true;
        break;
    case 6:
        ret = tca9555_reg.port.p0.bit.b1 == 0 ? false : true;
        break;
    case 7:
        ret = tca9555_reg.port.p0.bit.b0 == 0 ? false : true;
        break;
    case 8:
        ret = tca9555_reg.port.p0.bit.b7 == 0 ? false : true;
        break;
    case 9:
        ret = tca9555_reg.port.p1.bit.b5 == 0 ? false : true;
        break;
    case 10:
        ret = tca9555_reg.port.p1.bit.b4 == 0 ? false : true;
        break;
    case 11:
        ret = tca9555_reg.port.p1.bit.b3 == 0 ? false : true;
        break;
    case 12:
        ret = tca9555_reg.port.p1.bit.b2 == 0 ? false : true;
        break;
    case 13:
        ret = tca9555_reg.port.p1.bit.b1 == 0 ? false : true;
        break;
    case 14:
        ret = tca9555_reg.port.p1.bit.b0 == 0 ? false : true;
        break;
    default:
        break;
    }
    return ret;
}