143 lines
4.8 KiB
C
143 lines
4.8 KiB
C
/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file adc.c
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* @brief This file provides code for the configuration
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* of the ADC instances.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2024 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "adc.h"
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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/* ADC init function */
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void MX_ADC_Init(void)
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{
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/* USER CODE BEGIN ADC_Init 0 */
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/* USER CODE END ADC_Init 0 */
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LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};
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LL_ADC_InitTypeDef ADC_InitStruct = {0};
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LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
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/* Peripheral clock enable */
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC1);
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LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOC);
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LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
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/**ADC GPIO Configuration
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PC0 ------> ADC_IN10
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PC3 ------> ADC_IN13
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PB0 ------> ADC_IN8
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*/
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GPIO_InitStruct.Pin = LL_GPIO_PIN_0;
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GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
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GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
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LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = MG_ADC_IN13_Pin;
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GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
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GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
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LL_GPIO_Init(MG_ADC_IN13_GPIO_Port, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = LL_GPIO_PIN_0;
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GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
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GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
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LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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/* ADC DMA Init */
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/* ADC Init */
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LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMA_REQUEST_0);
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LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
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LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_HIGH);
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LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_CIRCULAR);
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LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PERIPH_NOINCREMENT);
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LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MEMORY_INCREMENT);
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LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_HALFWORD);
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LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_HALFWORD);
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/* USER CODE BEGIN ADC_Init 1 */
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/* USER CODE END ADC_Init 1 */
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/** Configure Regular Channel
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*/
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LL_ADC_REG_SetSequencerChAdd(ADC1, LL_ADC_CHANNEL_8);
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/** Configure Regular Channel
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*/
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LL_ADC_REG_SetSequencerChAdd(ADC1, LL_ADC_CHANNEL_10);
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/** Configure Regular Channel
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*/
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LL_ADC_REG_SetSequencerChAdd(ADC1, LL_ADC_CHANNEL_13);
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/** Common config
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*/
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ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
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ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
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ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_CONTINUOUS;
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ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_UNLIMITED;
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ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_PRESERVED;
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LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
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LL_ADC_SetSamplingTimeCommonChannels(ADC1, LL_ADC_SAMPLINGTIME_160CYCLES_5);
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LL_ADC_SetOverSamplingScope(ADC1, LL_ADC_OVS_DISABLE);
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LL_ADC_REG_SetSequencerScanDirection(ADC1, LL_ADC_REG_SEQ_SCAN_DIR_FORWARD);
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LL_ADC_SetCommonFrequencyMode(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_CLOCK_FREQ_MODE_HIGH);
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LL_ADC_DisableIT_EOC(ADC1);
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LL_ADC_DisableIT_EOS(ADC1);
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ADC_InitStruct.Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
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ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_12B;
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ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
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ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE;
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LL_ADC_Init(ADC1, &ADC_InitStruct);
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/* Enable ADC internal voltage regulator */
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LL_ADC_EnableInternalRegulator(ADC1);
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/* Delay for ADC internal voltage regulator stabilization. */
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/* Compute number of CPU cycles to wait for, from delay in us. */
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/* Note: Variable divided by 2 to compensate partially */
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/* CPU processing cycles (depends on compilation optimization). */
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/* Note: If system core clock frequency is below 200kHz, wait time */
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/* is only a few CPU processing cycles. */
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uint32_t wait_loop_index;
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wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
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while(wait_loop_index != 0)
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{
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wait_loop_index--;
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}
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/* USER CODE BEGIN ADC_Init 2 */
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/* USER CODE END ADC_Init 2 */
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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