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FSMC和CH438读写寄存器

This commit is contained in:
王绪洁 2025-03-11 18:24:55 +08:00
parent 806127b3de
commit 38d45a2b15
23 changed files with 9101 additions and 4659 deletions
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42
.mxproject
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File diff suppressed because one or more lines are too long

5
.vscode/settings.json vendored
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@ -2,6 +2,9 @@
"C_Cpp.errorSquiggles": "disabled",
"files.associations": {
"user_spi.h": "c",
"string.h": "c"
"string.h": "c",
"user_fmsc.h": "c",
"fsmc.h": "c",
"ch438q.h": "c"
}
}

60
Core/Inc/fsmc.h Normal file
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@ -0,0 +1,60 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : FSMC.h
* Description : This file provides code for the configuration
* of the FSMC peripheral.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __FSMC_H
#define __FSMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern SRAM_HandleTypeDef hsram1;
extern SRAM_HandleTypeDef hsram2;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_FSMC_Init(void);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__FSMC_H */
/**
* @}
*/
/**
* @}
*/

40
Core/Inc/main.h
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@ -23,36 +23,35 @@
#define __MAIN_H
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "stdio.h"
#include <string.h>
/* USER CODE END Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
@ -65,19 +64,18 @@ extern "C"
#define HART_CLK_GPIO_Port GPIOA
#define HART_ALL_RST_Pin GPIO_PIN_4
#define HART_ALL_RST_GPIO_Port GPIOA
#define CH438_AMOD_Pin GPIO_PIN_14
#define CH438_AMOD_GPIO_Port GPIOF
#define HART1_RTS_Pin GPIO_PIN_4
#define HART1_RTS_GPIO_Port GPIOG
#define CH438_RST_Pin GPIO_PIN_3
#define CH438_RST_GPIO_Port GPIOD
#define CH438_INT_Pin GPIO_PIN_2
#define CH438_INT_GPIO_Port GPIOD
#define CH438_INT_EXTI_IRQn EXTI2_IRQn
#define DAC1_CS_Pin GPIO_PIN_6
#define DAC1_CS_GPIO_Port GPIOB
/* USER CODE BEGIN Private defines */
#define TRUE 0
#define FAIL -1
/* USER CODE END Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}

2
Core/Inc/stm32f4xx_hal_conf.h
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@ -50,7 +50,7 @@
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_PCCARD_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2C_MODULE_ENABLED */

1
Core/Inc/stm32f4xx_it.h
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@ -52,6 +52,7 @@ void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void DebugMon_Handler(void);
void EXTI2_IRQHandler(void);
void TIM4_IRQHandler(void);
void ETH_IRQHandler(void);
/* USER CODE BEGIN EFP */

26
Core/Src/freertos.c
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@ -26,6 +26,7 @@
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "dac161s997.h"
#include "ch438q.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -49,6 +50,7 @@
/* USER CODE END Variables */
osThreadId lwip_taskHandle;
osThreadId dac_taskHandle;
osThreadId ch438_taskHandle;
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN FunctionPrototypes */
@ -57,6 +59,7 @@ osThreadId dac_taskHandle;
void start_lwip_task(void const *argument);
void start_dac_task(void const *argument);
void start_ch438_task(void const *argument);
extern void MX_LWIP_Init(void);
void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */
@ -113,6 +116,10 @@ void MX_FREERTOS_Init(void)
osThreadDef(dac_task, start_dac_task, osPriorityIdle, 0, 512);
dac_taskHandle = osThreadCreate(osThread(dac_task), NULL);
/* definition and creation of ch438_task */
osThreadDef(ch438_task, start_ch438_task, osPriorityHigh, 0, 512);
ch438_taskHandle = osThreadCreate(osThread(ch438_task), NULL);
/* USER CODE BEGIN RTOS_THREADS */
/* add threads, ... */
/* USER CODE END RTOS_THREADS */
@ -158,6 +165,25 @@ void start_dac_task(void const *argument)
/* USER CODE END start_dac_task */
}
/* USER CODE BEGIN Header_start_ch438_task */
/**
* @brief Function implementing the ch438_task thread.
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_start_ch438_task */
void start_ch438_task(void const *argument)
{
/* USER CODE BEGIN start_ch438_task */
/* Infinite loop */
for (;;)
{
ch438_test();
osDelay(1);
}
/* USER CODE END start_ch438_task */
}
/* Private application code --------------------------------------------------*/
/* USER CODE BEGIN Application */

273
Core/Src/fsmc.c Normal file
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@ -0,0 +1,273 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : FSMC.c
* @file fsmc.c
* of the FSMC peripheral.
******************************************************************************
* @attention
*
* Copyright (c) 2025 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "fsmc.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
SRAM_HandleTypeDef hsram1;
SRAM_HandleTypeDef hsram2;
/* FSMC initialization function */
void MX_FSMC_Init(void)
{
/* USER CODE BEGIN FSMC_Init 0 */
/* USER CODE END FSMC_Init 0 */
FSMC_NORSRAM_TimingTypeDef Timing = {0};
/* USER CODE BEGIN FSMC_Init 1 */
/* USER CODE END FSMC_Init 1 */
/** Perform the SRAM1 memory initialization sequence
*/
hsram1.Instance = FSMC_NORSRAM_DEVICE;
hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
/* hsram1.Init */
hsram1.Init.NSBank = FSMC_NORSRAM_BANK1;
hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
hsram1.Init.PageSize = FSMC_PAGE_SIZE_NONE;
/* Timing */
Timing.AddressSetupTime = 15;
Timing.AddressHoldTime = 15;
Timing.DataSetupTime = 10;
Timing.BusTurnAroundDuration = 15;
Timing.CLKDivision = 16;
Timing.DataLatency = 17;
Timing.AccessMode = FSMC_ACCESS_MODE_A;
/* ExtTiming */
if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
{
Error_Handler();
}
/** Perform the SRAM2 memory initialization sequence
*/
hsram2.Instance = FSMC_NORSRAM_DEVICE;
hsram2.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
/* hsram2.Init */
hsram2.Init.NSBank = FSMC_NORSRAM_BANK2;
hsram2.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
hsram2.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
hsram2.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
hsram2.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
hsram2.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
hsram2.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
hsram2.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
hsram2.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
hsram2.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
hsram2.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
hsram2.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram2.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
hsram2.Init.PageSize = FSMC_PAGE_SIZE_NONE;
/* Timing */
Timing.AddressSetupTime = 15;
Timing.AddressHoldTime = 15;
Timing.DataSetupTime = 10;
Timing.BusTurnAroundDuration = 15;
Timing.CLKDivision = 16;
Timing.DataLatency = 17;
Timing.AccessMode = FSMC_ACCESS_MODE_A;
/* ExtTiming */
if (HAL_SRAM_Init(&hsram2, &Timing, NULL) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN FSMC_Init 2 */
/* USER CODE END FSMC_Init 2 */
}
static uint32_t FSMC_Initialized = 0;
static void HAL_FSMC_MspInit(void)
{
/* USER CODE BEGIN FSMC_MspInit 0 */
/* USER CODE END FSMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct = {0};
if (FSMC_Initialized)
{
return;
}
FSMC_Initialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FSMC_CLK_ENABLE();
/** FSMC GPIO Configuration
PF0 ------> FSMC_A0
PF1 ------> FSMC_A1
PF2 ------> FSMC_A2
PF3 ------> FSMC_A3
PF4 ------> FSMC_A4
PF5 ------> FSMC_A5
PF12 ------> FSMC_A6
PE7 ------> FSMC_D4
PE8 ------> FSMC_D5
PE9 ------> FSMC_D6
PE10 ------> FSMC_D7
PD14 ------> FSMC_D0
PD15 ------> FSMC_D1
PD0 ------> FSMC_D2
PD1 ------> FSMC_D3
PD4 ------> FSMC_NOE
PD5 ------> FSMC_NWE
PD7 ------> FSMC_NE1
PG9 ------> FSMC_NE2
*/
/* GPIO_InitStruct */
GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
/* GPIO_InitStruct */
GPIO_InitStruct.Pin = GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/* GPIO_InitStruct */
GPIO_InitStruct.Pin = GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* GPIO_InitStruct */
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
/* USER CODE BEGIN FSMC_MspInit 1 */
/* USER CODE END FSMC_MspInit 1 */
}
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *sramHandle)
{
/* USER CODE BEGIN SRAM_MspInit 0 */
/* USER CODE END SRAM_MspInit 0 */
HAL_FSMC_MspInit();
/* USER CODE BEGIN SRAM_MspInit 1 */
/* USER CODE END SRAM_MspInit 1 */
}
static uint32_t FSMC_DeInitialized = 0;
static void HAL_FSMC_MspDeInit(void)
{
/* USER CODE BEGIN FSMC_MspDeInit 0 */
/* USER CODE END FSMC_MspDeInit 0 */
if (FSMC_DeInitialized)
{
return;
}
FSMC_DeInitialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FSMC_CLK_DISABLE();
/** FSMC GPIO Configuration
PF0 ------> FSMC_A0
PF1 ------> FSMC_A1
PF2 ------> FSMC_A2
PF3 ------> FSMC_A3
PF4 ------> FSMC_A4
PF5 ------> FSMC_A5
PF12 ------> FSMC_A6
PE7 ------> FSMC_D4
PE8 ------> FSMC_D5
PE9 ------> FSMC_D6
PE10 ------> FSMC_D7
PD14 ------> FSMC_D0
PD15 ------> FSMC_D1
PD0 ------> FSMC_D2
PD1 ------> FSMC_D3
PD4 ------> FSMC_NOE
PD5 ------> FSMC_NWE
PD7 ------> FSMC_NE1
PG9 ------> FSMC_NE2
*/
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_12);
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_9);
/* USER CODE BEGIN FSMC_MspDeInit 1 */
/* USER CODE END FSMC_MspDeInit 1 */
}
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *sramHandle)
{
/* USER CODE BEGIN SRAM_MspDeInit 0 */
/* USER CODE END SRAM_MspDeInit 0 */
HAL_FSMC_MspDeInit();
/* USER CODE BEGIN SRAM_MspDeInit 1 */
/* USER CODE END SRAM_MspDeInit 1 */
}
/**
* @}
*/
/**
* @}
*/

28
Core/Src/gpio.c
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@ -46,13 +46,13 @@ void MX_GPIO_Init(void)
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(PE5_LED_GPIO_Port, PE5_LED_Pin, GPIO_PIN_SET);
@ -60,15 +60,9 @@ void MX_GPIO_Init(void)
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(HART_ALL_RST_GPIO_Port, HART_ALL_RST_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(CH438_AMOD_GPIO_Port, CH438_AMOD_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(HART1_RTS_GPIO_Port, HART1_RTS_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(CH438_RST_GPIO_Port, CH438_RST_Pin, GPIO_PIN_SET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(DAC1_CS_GPIO_Port, DAC1_CS_Pin, GPIO_PIN_SET);
@ -86,13 +80,6 @@ void MX_GPIO_Init(void)
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
HAL_GPIO_Init(HART_ALL_RST_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = CH438_AMOD_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
HAL_GPIO_Init(CH438_AMOD_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = HART1_RTS_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@ -101,11 +88,10 @@ void MX_GPIO_Init(void)
HAL_GPIO_Init(HART1_RTS_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = CH438_RST_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pin = CH438_INT_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
HAL_GPIO_Init(CH438_RST_GPIO_Port, &GPIO_InitStruct);
HAL_GPIO_Init(CH438_INT_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = DAC1_CS_Pin;
@ -114,6 +100,10 @@ void MX_GPIO_Init(void)
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
HAL_GPIO_Init(DAC1_CS_GPIO_Port, &GPIO_InitStruct);
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI2_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(EXTI2_IRQn);
}
/* USER CODE BEGIN 2 */

2
Core/Src/main.c
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@ -23,6 +23,7 @@
#include "spi.h"
#include "tim.h"
#include "gpio.h"
#include "fsmc.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
@ -92,6 +93,7 @@ int main(void)
MX_GPIO_Init();
MX_TIM2_Init();
MX_SPI1_Init();
MX_FSMC_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */

14
Core/Src/stm32f4xx_it.c
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@ -160,6 +160,20 @@ void DebugMon_Handler(void)
/* please refer to the startup file (startup_stm32f4xx.s). */
/******************************************************************************/
/**
* @brief This function handles EXTI line2 interrupt.
*/
void EXTI2_IRQHandler(void)
{
/* USER CODE BEGIN EXTI2_IRQn 0 */
/* USER CODE END EXTI2_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(CH438_INT_Pin);
/* USER CODE BEGIN EXTI2_IRQn 1 */
/* USER CODE END EXTI2_IRQn 1 */
}
/**
* @brief This function handles TIM4 global interrupt.
*/

236
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h Normal file
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@ -0,0 +1,236 @@
/**
******************************************************************************
* @file stm32f4xx_hal_sram.h
* @author MCD Application Team
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F4xx_HAL_SRAM_H
#define STM32F4xx_HAL_SRAM_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FMC_Bank1) || defined(FSMC_Bank1)
/* Includes ------------------------------------------------------------------*/
#if defined(FSMC_Bank1)
#include "stm32f4xx_ll_fsmc.h"
#else
#include "stm32f4xx_ll_fmc.h"
#endif /* FSMC_Bank1 */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup SRAM
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup SRAM_Exported_Types SRAM Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
*/
typedef enum
{
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
} HAL_SRAM_StateTypeDef;
/**
* @brief SRAM handle Structure definition
*/
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
typedef struct __SRAM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
HAL_LockTypeDef Lock; /*!< SRAM locking object */
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
} SRAM_HandleTypeDef;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SRAM Callback ID enumeration definition
*/
typedef enum
{
HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
} HAL_SRAM_CallbackIDTypeDef;
/**
* @brief HAL SRAM Callback pointer definition
*/
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
* @{
*/
/** @brief Reset SRAM handle state
* @param __HANDLE__ SRAM handle
* @retval None
*/
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/* SRAM callback registering/unregistering */
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_DmaCallbackTypeDef pCallback);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
* @{
*/
/* SRAM Control functions ****************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_Bank1 || FSMC_Bank1 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F4xx_HAL_SRAM_H */

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Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h Normal file
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Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c Normal file
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Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c Normal file
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313
MDK-ARM/valve_debugging.uvoptx
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177
MDK-ARM/valve_debugging.uvprojx
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@ -54,7 +54,7 @@
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<CreateHexFile>1</CreateHexFile>
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<HexFormatSelection>1</HexFormatSelection>
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@ -339,7 +339,7 @@
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<Define>USE_HAL_DRIVER,STM32F407xx</Define>
<Undefine></Undefine>
<IncludePath>../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../LWIP/App;../LWIP/Target;../Middlewares/Third_Party/LwIP/src/include;../Middlewares/Third_Party/LwIP/system;../Middlewares/Third_Party/FreeRTOS/Source/include;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F;../Drivers/BSP/Components/lan8742;../Middlewares/Third_Party/LwIP/src/include/netif/ppp;../Middlewares/Third_Party/LwIP/src/include/lwip;../Middlewares/Third_Party/LwIP/src/include/lwip/apps;../Middlewares/Third_Party/LwIP/src/include/lwip/priv;../Middlewares/Third_Party/LwIP/src/include/lwip/prot;../Middlewares/Third_Party/LwIP/src/include/netif;../Middlewares/Third_Party/LwIP/src/include/compat/posix;../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa;../Middlewares/Third_Party/LwIP/src/include/compat/posix/net;../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys;../Middlewares/Third_Party/LwIP/src/include/compat/stdc;../Middlewares/Third_Party/LwIP/system/arch;..\User\driver;..\User\system</IncludePath>
<IncludePath>../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../LWIP/App;../LWIP/Target;../Middlewares/Third_Party/LwIP/src/include;../Middlewares/Third_Party/LwIP/system;../Middlewares/Third_Party/FreeRTOS/Source/include;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F;../Drivers/BSP/Components/lan8742;../Middlewares/Third_Party/LwIP/src/include/netif/ppp;../Middlewares/Third_Party/LwIP/src/include/lwip;../Middlewares/Third_Party/LwIP/src/include/lwip/apps;../Middlewares/Third_Party/LwIP/src/include/lwip/priv;../Middlewares/Third_Party/LwIP/src/include/lwip/prot;../Middlewares/Third_Party/LwIP/src/include/netif;../Middlewares/Third_Party/LwIP/src/include/compat/posix;../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa;../Middlewares/Third_Party/LwIP/src/include/compat/posix/net;../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys;../Middlewares/Third_Party/LwIP/src/include/compat/stdc;../Middlewares/Third_Party/LwIP/system/arch;../User/driver;../User/system</IncludePath>
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@ -459,6 +459,62 @@
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8928
MDK-ARM/valve_debugging/valve_debugging.hex
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User/driver/ch438q.c Normal file
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@ -0,0 +1,59 @@
#include "ch438q.h"
#include "fsmc.h"
const uint8_t offsetadd[] = {
0x00,
0x10,
0x20,
0x30,
0x08,
0x18,
0x28,
0x38,
}; /* 串口号的偏移地址 */
const uint8_t Interruptnum[] = {
0x01,
0x02,
0x04,
0x08,
0x10,
0x20,
0x40,
0x80,
}; /* SSR寄存器中断号对应值 */
// static uint32_t address = 0x68000000;
// uint32_t data = 0;
// uint32_t data1 = 0;
// for(int i = 0;i < 1024;i++,data++)
// {
// HAL_SRAM_Write_32b(&hsram1,&address ,&data,4);
// HAL_SRAM_Read_32b(&hsram1,&address ,&data1,4);
// address = 4*i;
// }
void ch438_write_reg(uint8_t addr, uint8_t data, uint8_t size)
{
uint32_t *address = (uint32_t *)(0x60000000 + addr);
HAL_SRAM_Write_8b(&hsram1, address, &data, size);
}
uint8_t ch438_read_reg(uint8_t addr, uint8_t size)
{
uint8_t data = 0;
uint32_t *address = (uint32_t *)(0x60000000 + addr);
HAL_SRAM_Read_8b(&hsram1, address, &data, size);
return data;
}
void ch438_test(void)
{
uint8_t reg_data[16] = {0};
reg_data[0] = 0xAA;
ch438_write_reg(offsetadd[0] | REG_SCR_ADDR, reg_data[0], 1);
reg_data[1] = ch438_read_reg(offsetadd[0] | REG_SCR_ADDR, 1);
reg_data[2] = ch438_read_reg(offsetadd[0] | REG_IER_ADDR, 1);
reg_data[3] = ch438_read_reg(offsetadd[0] | REG_IIR_ADDR, 1);
reg_data[4] = ch438_read_reg(offsetadd[0] | REG_LSR_ADDR, 1);
}

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User/driver/ch438q.h Normal file
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@ -0,0 +1,106 @@
#ifndef __CH438Q_H__
#define __CH438Q_H__
#include "fsmc.h"
/* CH438串口寄存器地址 */
#define REG_RBR_ADDR 0x00 /* 串口0接收缓冲寄存器地址 */
#define REG_THR_ADDR 0x00 /* 串口0发送保持寄存器地址 */
#define REG_IER_ADDR 0x01 /* 串口0中断使能寄存器地址 */
#define REG_IIR_ADDR 0x02 /* 串口0中断识别寄存器地址 */
#define REG_FCR_ADDR 0x02 /* 串口0FIFO控制寄存器地址 */
#define REG_LCR_ADDR 0x03 /* 串口0线路控制寄存器地址 */
#define REG_MCR_ADDR 0x04 /* 串口0MODEM控制寄存器地址 */
#define REG_LSR_ADDR 0x05 /* 串口0线路状态寄存器地址 */
#define REG_MSR_ADDR 0x06 /* 串口0MODEM状态寄存器地址 */
#define REG_SCR_ADDR 0x07 /* 串口0用户可定义寄存器地址 */
#define REG_DLL_ADDR 0x00 /* 波特率除数锁存器低8位字节地址 */
#define REG_DLM_ADDR 0x01 /* 波特率除数锁存器高8位字节地址 */
/* CH438内部串口0~7 专用状态寄存器 */
#define REG_SSR_ADDR 0x4F /* 专用状态寄存器地址 */
/* IIR寄存器的位 */
#define BIT_IIR_FIFOENS1 0x80
#define BIT_IIR_FIFOENS0 0x40 /* 该2位为1表示起用FIFO */
/* 中断类型：0001没有中断，0110接收线路状态中断，0100接收数据可用中断，1100接收数据超时中断，0010THR寄存器空中断，0000MODEM输入变化中断 */
#define BIT_IIR_IID3 0x08
#define BIT_IIR_IID2 0x04 // 接受数据可用
#define BIT_IIR_IID1 0x02 // THR寄存器空中断
#define BIT_IIR_NOINT 0x01
/* FCR寄存器的位 */
/* 触发点： 00对应1个字节，01对应16个字节，10对应64个字节，11对应112个字节 */
#define BIT_FCR_RECVTG1 0x80 /* 设置FIFO的中断和自动硬件流控制的触发点 */
#define BIT_FCR_RECVTG0 0x40 /* 设置FIFO的中断和自动硬件流控制的触发点 */
#define BIT_FCR_TFIFORST 0x04 /* 该位置1则清空发送FIFO中的数据 */
#define BIT_FCR_RFIFORST 0x02 /* 该位置1则清空接收FIFO中的数据 */
#define BIT_FCR_FIFOEN 0x01 /* 该位置1则起用FIFO,为0则禁用FIFO */
/* LCR寄存器的位 */
#define BIT_LCR_DLAB 0x80 /* 为1才能存取DLL，DLM，为0才能存取RBR/THR/IER */
#define BIT_LCR_BREAKEN 0x40 /* 为1则强制产生BREAK线路间隔*/
/* 设置校验格式：当PAREN为1时，00奇校验，01偶校验，10标志位（MARK，置1)，11空白位（SPACE，清0) */
#define BIT_LCR_PARMODE1 0x20 /* 设置奇偶校验位格式 */
#define BIT_LCR_PARMODE0 0x10 /* 设置奇偶校验位格式 */
#define BIT_LCR_PAREN 0x08 /* 为1则允许发送时产生和接收校验奇偶校验位 */
#define BIT_LCR_STOPBIT 0x04 /* 为1则两个停止位,为0一个停止位 */
/* 设置字长度：00则5个数据位，01则6个数据位，10则7个数据位，11则8个数据位 */
#define BIT_LCR_WORDSZ1 0x02 /* 设置字长长度 */
#define BIT_LCR_WORDSZ0 0x01
/* MCR寄存器的位 */
#define BIT_MCR_AFE 0x20 /* 为1允许CTS和RTS硬件自动流控制 */
#define BIT_MCR_LOOP 0x10 /* 为1使能内部回路的测试模式 */
#define BIT_MCR_OUT2 0x08 /* 为1允许该串口的中断请求输出 */
#define BIT_MCR_OUT1 0x04 /* 为用户定义的MODEM控制位 */
#define BIT_MCR_RTS 0x02 /* 该位为1则RTS引脚输出有效 */
#define BIT_MCR_DTR 0x01 /* 该位为1则DTR引脚输出有效 */
/* LSR寄存器的位 */
#define BIT_LSR_RFIFOERR 0x80 /* 为1表示在接收FIFO中存在至少一个错误 */
#define BIT_LSR_TEMT 0x40 /* 为1表示THR和TSR全空 */
#define BIT_LSR_THRE 0x20 /* 为1表示THR空*/
#define BIT_LSR_BREAKINT 0x10 /* 该位为1表示检测到BREAK线路间隔 */
#define BIT_LSR_FRAMEERR 0x08 /* 该位为1表示读取数据帧错误 */
#define BIT_LSR_PARERR 0x04 /* 该位为1表示奇偶校验错误 */
#define BIT_LSR_OVERR 0x02 /* 为1表示接收FIFO缓冲区溢出 */
#define BIT_LSR_DATARDY 0x01 /* 该位为1表示接收FIFO中有接收到的数据 */
/* MSR寄存器的位 */
#define BIT_MSR_DCD 0x80 /* 该位为1表示DCD引脚有效 */
#define BIT_MSR_RI 0x40 /* 该位为1表示RI引脚有效 */
#define BIT_MSR_DSR 0x20 /* 该位为1表示DSR引脚有效 */
#define BIT_MSR_CTS 0x10 /* 该位为1表示CTS引脚有效 */
#define BIT_MSR_DDCD 0x08 /* 该位为1表示DCD引脚输入状态发生变化过 */
#define BIT_MSR_TERI 0x04 /* 该位为1表示RI引脚输入状态发生变化过 */
#define BIT_MSR_DDSR 0x02 /* 该位为1表示DSR引脚输入状态发生变化过 */
#define BIT_MSR_DCTS 0x01 /* 该位为1表示CTS引脚输入状态发生变化过 */
/* 中断状态码 */
#define INT_NOINT 0x01 /* 没有中断 */
#define INT_THR_EMPTY 0x02 /* THR空中断 */
#define INT_RCV_OVERTIME 0x0C /* 接收超时中断 */
#define INT_RCV_SUCCESS 0x04 /* 接收数据可用中断 */
#define INT_RCV_LINES 0x06 /* 接收线路状态中断 */
#define INT_MODEM_CHANGE 0x00 /* MODEM输入变化中断 */
#define CH438_IIR_FIFOS_ENABLED 0xC0 /* 起用FIFO */
void ch438_write_reg(uint8_t addr, uint8_t data, uint8_t size);
uint8_t ch438_read_reg(uint8_t addr, uint8_t size);
void ch438_test(void);
#endif

0
User/system/user_fmsc.c Normal file
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0
User/system/user_fmsc.h Normal file
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190
valve_debugging.ioc
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@ -9,10 +9,16 @@ ETH.RxBuffLen=1536
ETH.RxMode=ETH_RXINTERRUPT_MODE
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configENABLE_FPU,configMAX_PRIORITIES,configMAX_TASK_NAME_LEN,FootprintOK
FREERTOS.Tasks01=lwip_task,0,512,start_lwip_task,Default,NULL,Dynamic,NULL,NULL;dac_task,-3,512,start_dac_task,Default,NULL,Dynamic,NULL,NULL
FREERTOS.Tasks01=lwip_task,0,512,start_lwip_task,Default,NULL,Dynamic,NULL,NULL;dac_task,-3,512,start_dac_task,Default,NULL,Dynamic,NULL,NULL;ch438_task,2,512,start_ch438_task,Default,NULL,Dynamic,NULL,NULL
FREERTOS.configENABLE_FPU=1
FREERTOS.configMAX_PRIORITIES=32
FREERTOS.configMAX_TASK_NAME_LEN=24
FSMC.DataSetupTime1=10
FSMC.DataSetupTime2=10
FSMC.ExtendedMode1=FSMC_EXTENDED_MODE_DISABLE
FSMC.IPParameters=ExtendedMode1,DataSetupTime2,DataSetupTime1,WriteOperation1,WriteOperation2
FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE
FSMC.WriteOperation2=FSMC_WRITE_OPERATION_ENABLE
File.Version=6
GPIO.groupedBy=Group By Peripherals
KeepUserPlacement=false
@ -37,42 +43,61 @@ Mcu.CPN=STM32F407ZGT6
Mcu.Family=STM32F4
Mcu.IP0=ETH
Mcu.IP1=FREERTOS
Mcu.IP2=LWIP
Mcu.IP3=NVIC
Mcu.IP4=RCC
Mcu.IP5=SPI1
Mcu.IP6=SYS
Mcu.IP7=TIM2
Mcu.IPNb=8
Mcu.IP2=FSMC
Mcu.IP3=LWIP
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=SPI1
Mcu.IP7=SYS
Mcu.IP8=TIM2
Mcu.IPNb=9
Mcu.Name=STM32F407Z(E-G)Tx
Mcu.Package=LQFP144
Mcu.Pin0=PE5
Mcu.Pin1=PH0-OSC_IN
Mcu.Pin10=PC5
Mcu.Pin11=PF14
Mcu.Pin12=PB11
Mcu.Pin13=PB12
Mcu.Pin14=PB13
Mcu.Pin15=PG4
Mcu.Pin16=PA13
Mcu.Pin17=PA14
Mcu.Pin18=PD3
Mcu.Pin19=PB3
Mcu.Pin2=PH1-OSC_OUT
Mcu.Pin20=PB4
Mcu.Pin21=PB5
Mcu.Pin22=PB6
Mcu.Pin23=VP_FREERTOS_VS_CMSIS_V1
Mcu.Pin24=VP_LWIP_VS_Enabled
Mcu.Pin25=VP_SYS_VS_tim4
Mcu.Pin3=PC1
Mcu.Pin4=PA1
Mcu.Pin5=PA2
Mcu.Pin6=PA3
Mcu.Pin7=PA4
Mcu.Pin8=PA7
Mcu.Pin9=PC4
Mcu.PinsNb=26
Mcu.Pin1=PF0
Mcu.Pin10=PA1
Mcu.Pin11=PA2
Mcu.Pin12=PA3
Mcu.Pin13=PA4
Mcu.Pin14=PA7
Mcu.Pin15=PC4
Mcu.Pin16=PC5
Mcu.Pin17=PF12
Mcu.Pin18=PE7
Mcu.Pin19=PE8
Mcu.Pin2=PF1
Mcu.Pin20=PE9
Mcu.Pin21=PE10
Mcu.Pin22=PB11
Mcu.Pin23=PB12
Mcu.Pin24=PB13
Mcu.Pin25=PD14
Mcu.Pin26=PD15
Mcu.Pin27=PG4
Mcu.Pin28=PA13
Mcu.Pin29=PA14
Mcu.Pin3=PF2
Mcu.Pin30=PD0
Mcu.Pin31=PD1
Mcu.Pin32=PD2
Mcu.Pin33=PD4
Mcu.Pin34=PD5
Mcu.Pin35=PD7
Mcu.Pin36=PG9
Mcu.Pin37=PB3
Mcu.Pin38=PB4
Mcu.Pin39=PB5
Mcu.Pin4=PF3
Mcu.Pin40=PB6
Mcu.Pin41=VP_FREERTOS_VS_CMSIS_V1
Mcu.Pin42=VP_LWIP_VS_Enabled
Mcu.Pin43=VP_SYS_VS_tim4
Mcu.Pin5=PF4
Mcu.Pin6=PF5
Mcu.Pin7=PH0-OSC_IN
Mcu.Pin8=PH1-OSC_OUT
Mcu.Pin9=PC1
Mcu.PinsNb=44
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F407ZGTx
@ -81,6 +106,7 @@ MxDb.Version=DB.6.0.80
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.ETH_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.EXTI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
@ -146,13 +172,21 @@ PC4.Mode=RMII
PC4.Signal=ETH_RXD0
PC5.Mode=RMII
PC5.Signal=ETH_RXD1
PD3.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label
PD3.GPIO_Label=CH438_RST
PD3.GPIO_PuPd=GPIO_PULLUP
PD3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PD3.Locked=true
PD3.PinState=GPIO_PIN_SET
PD3.Signal=GPIO_Output
PD0.Signal=FSMC_D2_DA2
PD1.Signal=FSMC_D3_DA3
PD14.Signal=FSMC_D0_DA0
PD15.Signal=FSMC_D1_DA1
PD2.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
PD2.GPIO_Label=CH438_INT
PD2.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
PD2.GPIO_PuPd=GPIO_PULLUP
PD2.Locked=true
PD2.Signal=GPXTI2
PD4.Signal=FSMC_NOE
PD5.Signal=FSMC_NWE
PD7.Mode=NorPsramChipSelect1_1
PD7.Signal=FSMC_NE1
PE10.Signal=FSMC_D7_DA7
PE5.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label
PE5.GPIO_Label=PE5_LED
PE5.GPIO_PuPd=GPIO_PULLUP
@ -160,13 +194,16 @@ PE5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PE5.Locked=true
PE5.PinState=GPIO_PIN_SET
PE5.Signal=GPIO_Output
PF14.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
PF14.GPIO_Label=CH438_AMOD
PF14.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
PF14.GPIO_PuPd=GPIO_PULLDOWN
PF14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PF14.Locked=true
PF14.Signal=GPIO_Output
PE7.Signal=FSMC_D4_DA4
PE8.Signal=FSMC_D5_DA5
PE9.Signal=FSMC_D6_DA6
PF0.Signal=FSMC_A0
PF1.Signal=FSMC_A1
PF12.Signal=FSMC_A6
PF2.Signal=FSMC_A2
PF3.Signal=FSMC_A3
PF4.Signal=FSMC_A4
PF5.Signal=FSMC_A5
PG4.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label
PG4.GPIO_Label=HART1_RTS
PG4.GPIO_PuPd=GPIO_PULLUP
@ -174,6 +211,8 @@ PG4.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PG4.Locked=true
PG4.PinState=GPIO_PIN_SET
PG4.Signal=GPIO_Output
PG9.Mode=NorPsramChipSelect2_2
PG9.Signal=FSMC_NE2
PH0-OSC_IN.Mode=HSE-External-Oscillator
PH0-OSC_IN.Signal=RCC_OSC_IN
PH1-OSC_OUT.Mode=HSE-External-Oscillator
@ -207,7 +246,7 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5.32
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_LWIP_Init-LWIP-false-HAL-false,4-MX_TIM2_Init-TIM2-false-HAL-true
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_LWIP_Init-LWIP-false-HAL-false,4-MX_TIM2_Init-TIM2-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_FSMC_Init-FSMC-false-HAL-true
RCC.48MHZClocksFreq_Value=55296000
RCC.AHBFreq_Value=110592000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
@ -241,6 +280,59 @@ RCC.VCOI2SOutputFreq_Value=353894400
RCC.VCOInputFreq_Value=1843200
RCC.VCOOutputFreq_Value=221184000
RCC.VcooutputI2S=176947200
SH.FSMC_A0.0=FSMC_A0,7b-a1
SH.FSMC_A0.1=FSMC_A0,7b-a2
SH.FSMC_A0.ConfNb=2
SH.FSMC_A1.0=FSMC_A1,7b-a1
SH.FSMC_A1.1=FSMC_A1,7b-a2
SH.FSMC_A1.ConfNb=2
SH.FSMC_A2.0=FSMC_A2,7b-a1
SH.FSMC_A2.1=FSMC_A2,7b-a2
SH.FSMC_A2.ConfNb=2
SH.FSMC_A3.0=FSMC_A3,7b-a1
SH.FSMC_A3.1=FSMC_A3,7b-a2
SH.FSMC_A3.ConfNb=2
SH.FSMC_A4.0=FSMC_A4,7b-a1
SH.FSMC_A4.1=FSMC_A4,7b-a2
SH.FSMC_A4.ConfNb=2
SH.FSMC_A5.0=FSMC_A5,7b-a1
SH.FSMC_A5.1=FSMC_A5,7b-a2
SH.FSMC_A5.ConfNb=2
SH.FSMC_A6.0=FSMC_A6,7b-a1
SH.FSMC_A6.1=FSMC_A6,7b-a2
SH.FSMC_A6.ConfNb=2
SH.FSMC_D0_DA0.0=FSMC_D0,8b-d2
SH.FSMC_D0_DA0.1=FSMC_D0,8b-d1
SH.FSMC_D0_DA0.ConfNb=2
SH.FSMC_D1_DA1.0=FSMC_D1,8b-d2
SH.FSMC_D1_DA1.1=FSMC_D1,8b-d1
SH.FSMC_D1_DA1.ConfNb=2
SH.FSMC_D2_DA2.0=FSMC_D2,8b-d2
SH.FSMC_D2_DA2.1=FSMC_D2,8b-d1
SH.FSMC_D2_DA2.ConfNb=2
SH.FSMC_D3_DA3.0=FSMC_D3,8b-d2
SH.FSMC_D3_DA3.1=FSMC_D3,8b-d1
SH.FSMC_D3_DA3.ConfNb=2
SH.FSMC_D4_DA4.0=FSMC_D4,8b-d2
SH.FSMC_D4_DA4.1=FSMC_D4,8b-d1
SH.FSMC_D4_DA4.ConfNb=2
SH.FSMC_D5_DA5.0=FSMC_D5,8b-d2
SH.FSMC_D5_DA5.1=FSMC_D5,8b-d1
SH.FSMC_D5_DA5.ConfNb=2
SH.FSMC_D6_DA6.0=FSMC_D6,8b-d2
SH.FSMC_D6_DA6.1=FSMC_D6,8b-d1
SH.FSMC_D6_DA6.ConfNb=2
SH.FSMC_D7_DA7.0=FSMC_D7,8b-d2
SH.FSMC_D7_DA7.1=FSMC_D7,8b-d1
SH.FSMC_D7_DA7.ConfNb=2
SH.FSMC_NOE.0=FSMC_NOE,Sram1
SH.FSMC_NOE.1=FSMC_NOE,Sram2
SH.FSMC_NOE.ConfNb=2
SH.FSMC_NWE.0=FSMC_NWE,Sram1
SH.FSMC_NWE.1=FSMC_NWE,Sram2
SH.FSMC_NWE.ConfNb=2
SH.GPXTI2.0=GPIO_EXTI2
SH.GPXTI2.ConfNb=1
SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4
SH.S_TIM2_CH4.ConfNb=1
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_256