diff --git a/.mxproject b/.mxproject
index 5d24f22..f01cf9a 100644
--- a/.mxproject
+++ b/.mxproject
@@ -1,40 +1,42 @@
 [PreviousLibFiles]
-LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_eth.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h;Drivers\BSP\Components\lan8742\lan8742.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ccp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\chap_ms.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\chap-md5.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\chap-new.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\eap.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\eui64.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\fsm.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ipcp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ipv6cp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\lcp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\magic.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\mppe.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ppp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ppp_impl.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ppp_opts.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppapi.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppcrypt.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppdebug.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppoe.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppol2tp.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\pppos.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\upap.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\vj.h;Middlewares\Third_Party\LwIP\src\include\netif\ppp\ecp.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;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 HeaderPath=..\Middlewares\Third_Party\LwIP\src\include;..\Middlewares\Third_Party\LwIP\system;..\Middlewares\Third_Party\LwIP\src\include;..\Middlewares\Third_Party\LwIP\system;..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Middlewares\Third_Party\FreeRTOS\Source\include;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F;..\Drivers\BSP\Components\lan8742;..\Middlewares\Third_Party\LwIP\src\include\netif\ppp;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Middlewares\Third_Party\LwIP\src\include\lwip;..\Middlewares\Third_Party\LwIP\src\include\lwip\apps;..\Middlewares\Third_Party\LwIP\src\include\lwip\priv;..\Middlewares\Third_Party\LwIP\src\include\lwip\prot;..\Middlewares\Third_Party\LwIP\src\include\netif;..\Middlewares\Third_Party\LwIP\src\include\compat\posix;..\Middlewares\Third_Party\LwIP\src\include\compat\posix\arpa;..\Middlewares\Third_Party\LwIP\src\include\compat\posix\net;..\Middlewares\Third_Party\LwIP\src\include\compat\posix\sys;..\Middlewares\Third_Party\LwIP\src\include\compat\stdc;..\Middlewares\Third_Party\LwIP\system\arch;..\Drivers\CMSIS\Include;..\Core\Inc;..\LWIP\App;..\LWIP\Target;
 CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
 
 [PreviousGenFiles]
 AdvancedFolderStructure=true
-HeaderFileListSize=10
+HeaderFileListSize=11
 HeaderFiles#0=..\Core\Inc\gpio.h
 HeaderFiles#1=..\Core\Inc\FreeRTOSConfig.h
-HeaderFiles#2=..\LWIP\App\lwip.h
-HeaderFiles#3=..\LWIP\Target\lwipopts.h
-HeaderFiles#4=..\LWIP\Target\ethernetif.h
-HeaderFiles#5=..\Core\Inc\spi.h
-HeaderFiles#6=..\Core\Inc\tim.h
-HeaderFiles#7=..\Core\Inc\stm32f4xx_it.h
-HeaderFiles#8=..\Core\Inc\stm32f4xx_hal_conf.h
-HeaderFiles#9=..\Core\Inc\main.h
+HeaderFiles#2=..\Core\Inc\fsmc.h
+HeaderFiles#3=..\LWIP\App\lwip.h
+HeaderFiles#4=..\LWIP\Target\lwipopts.h
+HeaderFiles#5=..\LWIP\Target\ethernetif.h
+HeaderFiles#6=..\Core\Inc\spi.h
+HeaderFiles#7=..\Core\Inc\tim.h
+HeaderFiles#8=..\Core\Inc\stm32f4xx_it.h
+HeaderFiles#9=..\Core\Inc\stm32f4xx_hal_conf.h
+HeaderFiles#10=..\Core\Inc\main.h
 HeaderFolderListSize=3
 HeaderPath#0=..\Core\Inc
 HeaderPath#1=..\LWIP\App
 HeaderPath#2=..\LWIP\Target
 HeaderFiles=;
-SourceFileListSize=10
+SourceFileListSize=11
 SourceFiles#0=..\Core\Src\gpio.c
 SourceFiles#1=..\Core\Src\freertos.c
-SourceFiles#2=..\LWIP\App\lwip.c
-SourceFiles#3=..\LWIP\Target\ethernetif.c
-SourceFiles#4=..\Core\Src\spi.c
-SourceFiles#5=..\Core\Src\tim.c
-SourceFiles#6=..\Core\Src\stm32f4xx_it.c
-SourceFiles#7=..\Core\Src\stm32f4xx_hal_msp.c
-SourceFiles#8=..\Core\Src\stm32f4xx_hal_timebase_tim.c
-SourceFiles#9=..\Core\Src\main.c
+SourceFiles#2=..\Core\Src\fsmc.c
+SourceFiles#3=..\LWIP\App\lwip.c
+SourceFiles#4=..\LWIP\Target\ethernetif.c
+SourceFiles#5=..\Core\Src\spi.c
+SourceFiles#6=..\Core\Src\tim.c
+SourceFiles#7=..\Core\Src\stm32f4xx_it.c
+SourceFiles#8=..\Core\Src\stm32f4xx_hal_msp.c
+SourceFiles#9=..\Core\Src\stm32f4xx_hal_timebase_tim.c
+SourceFiles#10=..\Core\Src\main.c
 SourceFolderListSize=3
 SourcePath#0=..\Core\Src
 SourcePath#1=..\LWIP\App
diff --git a/.vscode/settings.json b/.vscode/settings.json
index ed4be88..ffcaf51 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -2,6 +2,9 @@
     "C_Cpp.errorSquiggles": "disabled",
     "files.associations": {
         "user_spi.h": "c",
-        "string.h": "c"
+        "string.h": "c",
+        "user_fmsc.h": "c",
+        "fsmc.h": "c",
+        "ch438q.h": "c"
     }
 }
\ No newline at end of file
diff --git a/Core/Inc/fsmc.h b/Core/Inc/fsmc.h
new file mode 100644
index 0000000..2836016
--- /dev/null
+++ b/Core/Inc/fsmc.h
@@ -0,0 +1,60 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : FSMC.h
+  * Description        : This file provides code for the configuration
+  *                      of the FSMC peripheral.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FSMC_H
+#define __FSMC_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern SRAM_HandleTypeDef hsram1;
+extern SRAM_HandleTypeDef hsram2;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_FSMC_Init(void);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__FSMC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
index 567c06e..0f990b4 100644
--- a/Core/Inc/main.h
+++ b/Core/Inc/main.h
@@ -23,36 +23,35 @@
 #define __MAIN_H
 
 #ifdef __cplusplus
-extern "C"
-{
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f4xx_hal.h"
 
-  /* Private includes ----------------------------------------------------------*/
-  /* USER CODE BEGIN Includes */
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
   #include "stdio.h"
   #include <string.h>
-  /* USER CODE END Includes */
+/* USER CODE END Includes */
 
-  /* Exported types ------------------------------------------------------------*/
-  /* USER CODE BEGIN ET */
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
 
-  /* USER CODE END ET */
+/* USER CODE END ET */
 
-  /* Exported constants --------------------------------------------------------*/
-  /* USER CODE BEGIN EC */
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
 
-  /* USER CODE END EC */
+/* USER CODE END EC */
 
-  /* Exported macro ------------------------------------------------------------*/
-  /* USER CODE BEGIN EM */
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
 
-  /* USER CODE END EM */
+/* USER CODE END EM */
 
-  /* Exported functions prototypes ---------------------------------------------*/
-  void Error_Handler(void);
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
 
 /* USER CODE BEGIN EFP */
 
@@ -65,19 +64,18 @@ extern "C"
 #define HART_CLK_GPIO_Port GPIOA
 #define HART_ALL_RST_Pin GPIO_PIN_4
 #define HART_ALL_RST_GPIO_Port GPIOA
-#define CH438_AMOD_Pin GPIO_PIN_14
-#define CH438_AMOD_GPIO_Port GPIOF
 #define HART1_RTS_Pin GPIO_PIN_4
 #define HART1_RTS_GPIO_Port GPIOG
-#define CH438_RST_Pin GPIO_PIN_3
-#define CH438_RST_GPIO_Port GPIOD
+#define CH438_INT_Pin GPIO_PIN_2
+#define CH438_INT_GPIO_Port GPIOD
+#define CH438_INT_EXTI_IRQn EXTI2_IRQn
 #define DAC1_CS_Pin GPIO_PIN_6
 #define DAC1_CS_GPIO_Port GPIOB
 
 /* USER CODE BEGIN Private defines */
 #define TRUE 0
 #define FAIL -1
-  /* USER CODE END Private defines */
+/* USER CODE END Private defines */
 
 #ifdef __cplusplus
 }
diff --git a/Core/Inc/stm32f4xx_hal_conf.h b/Core/Inc/stm32f4xx_hal_conf.h
index 1c5e075..36853a9 100644
--- a/Core/Inc/stm32f4xx_hal_conf.h
+++ b/Core/Inc/stm32f4xx_hal_conf.h
@@ -50,7 +50,7 @@
 /* #define HAL_NAND_MODULE_ENABLED */
 /* #define HAL_NOR_MODULE_ENABLED */
 /* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
+#define HAL_SRAM_MODULE_ENABLED
 /* #define HAL_SDRAM_MODULE_ENABLED */
 /* #define HAL_HASH_MODULE_ENABLED */
 /* #define HAL_I2C_MODULE_ENABLED */
diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h
index 2edd96e..fe66718 100644
--- a/Core/Inc/stm32f4xx_it.h
+++ b/Core/Inc/stm32f4xx_it.h
@@ -52,6 +52,7 @@ void MemManage_Handler(void);
 void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
+void EXTI2_IRQHandler(void);
 void TIM4_IRQHandler(void);
 void ETH_IRQHandler(void);
 /* USER CODE BEGIN EFP */
diff --git a/Core/Src/freertos.c b/Core/Src/freertos.c
index e3194bd..396fcc9 100644
--- a/Core/Src/freertos.c
+++ b/Core/Src/freertos.c
@@ -26,6 +26,7 @@
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 #include "dac161s997.h"
+#include "ch438q.h"
 /* USER CODE END Includes */
 
 /* Private typedef -----------------------------------------------------------*/
@@ -49,6 +50,7 @@
 /* USER CODE END Variables */
 osThreadId lwip_taskHandle;
 osThreadId dac_taskHandle;
+osThreadId ch438_taskHandle;
 
 /* Private function prototypes -----------------------------------------------*/
 /* USER CODE BEGIN FunctionPrototypes */
@@ -57,6 +59,7 @@ osThreadId dac_taskHandle;
 
 void start_lwip_task(void const *argument);
 void start_dac_task(void const *argument);
+void start_ch438_task(void const *argument);
 
 extern void MX_LWIP_Init(void);
 void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */
@@ -113,6 +116,10 @@ void MX_FREERTOS_Init(void)
   osThreadDef(dac_task, start_dac_task, osPriorityIdle, 0, 512);
   dac_taskHandle = osThreadCreate(osThread(dac_task), NULL);
 
+  /* definition and creation of ch438_task */
+  osThreadDef(ch438_task, start_ch438_task, osPriorityHigh, 0, 512);
+  ch438_taskHandle = osThreadCreate(osThread(ch438_task), NULL);
+
   /* USER CODE BEGIN RTOS_THREADS */
   /* add threads, ... */
   /* USER CODE END RTOS_THREADS */
@@ -158,6 +165,25 @@ void start_dac_task(void const *argument)
   /* USER CODE END start_dac_task */
 }
 
+/* USER CODE BEGIN Header_start_ch438_task */
+/**
+ * @brief Function implementing the ch438_task thread.
+ * @param argument: Not used
+ * @retval None
+ */
+/* USER CODE END Header_start_ch438_task */
+void start_ch438_task(void const *argument)
+{
+  /* USER CODE BEGIN start_ch438_task */
+  /* Infinite loop */
+  for (;;)
+  {
+    ch438_test();
+    osDelay(1);
+  }
+  /* USER CODE END start_ch438_task */
+}
+
 /* Private application code --------------------------------------------------*/
 /* USER CODE BEGIN Application */
 
diff --git a/Core/Src/fsmc.c b/Core/Src/fsmc.c
new file mode 100644
index 0000000..155af55
--- /dev/null
+++ b/Core/Src/fsmc.c
@@ -0,0 +1,273 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * File Name          : FSMC.c
+ * @file fsmc.c
+ *                      of the FSMC peripheral.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fsmc.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+SRAM_HandleTypeDef hsram1;
+SRAM_HandleTypeDef hsram2;
+
+/* FSMC initialization function */
+void MX_FSMC_Init(void)
+{
+  /* USER CODE BEGIN FSMC_Init 0 */
+
+  /* USER CODE END FSMC_Init 0 */
+
+  FSMC_NORSRAM_TimingTypeDef Timing = {0};
+
+  /* USER CODE BEGIN FSMC_Init 1 */
+
+  /* USER CODE END FSMC_Init 1 */
+
+  /** Perform the SRAM1 memory initialization sequence
+   */
+  hsram1.Instance = FSMC_NORSRAM_DEVICE;
+  hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
+  /* hsram1.Init */
+  hsram1.Init.NSBank = FSMC_NORSRAM_BANK1;
+  hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
+  hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
+  hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
+  hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
+  hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
+  hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
+  hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
+  hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
+  hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
+  hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
+  hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
+  hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
+  hsram1.Init.PageSize = FSMC_PAGE_SIZE_NONE;
+  /* Timing */
+  Timing.AddressSetupTime = 15;
+  Timing.AddressHoldTime = 15;
+  Timing.DataSetupTime = 10;
+  Timing.BusTurnAroundDuration = 15;
+  Timing.CLKDivision = 16;
+  Timing.DataLatency = 17;
+  Timing.AccessMode = FSMC_ACCESS_MODE_A;
+  /* ExtTiming */
+
+  if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Perform the SRAM2 memory initialization sequence
+   */
+  hsram2.Instance = FSMC_NORSRAM_DEVICE;
+  hsram2.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
+  /* hsram2.Init */
+  hsram2.Init.NSBank = FSMC_NORSRAM_BANK2;
+  hsram2.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
+  hsram2.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
+  hsram2.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
+  hsram2.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
+  hsram2.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
+  hsram2.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
+  hsram2.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
+  hsram2.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
+  hsram2.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
+  hsram2.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
+  hsram2.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
+  hsram2.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
+  hsram2.Init.PageSize = FSMC_PAGE_SIZE_NONE;
+  /* Timing */
+  Timing.AddressSetupTime = 15;
+  Timing.AddressHoldTime = 15;
+  Timing.DataSetupTime = 10;
+  Timing.BusTurnAroundDuration = 15;
+  Timing.CLKDivision = 16;
+  Timing.DataLatency = 17;
+  Timing.AccessMode = FSMC_ACCESS_MODE_A;
+  /* ExtTiming */
+
+  if (HAL_SRAM_Init(&hsram2, &Timing, NULL) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /* USER CODE BEGIN FSMC_Init 2 */
+
+  /* USER CODE END FSMC_Init 2 */
+}
+
+static uint32_t FSMC_Initialized = 0;
+
+static void HAL_FSMC_MspInit(void)
+{
+  /* USER CODE BEGIN FSMC_MspInit 0 */
+
+  /* USER CODE END FSMC_MspInit 0 */
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if (FSMC_Initialized)
+  {
+    return;
+  }
+  FSMC_Initialized = 1;
+
+  /* Peripheral clock enable */
+  __HAL_RCC_FSMC_CLK_ENABLE();
+
+  /** FSMC GPIO Configuration
+  PF0   ------> FSMC_A0
+  PF1   ------> FSMC_A1
+  PF2   ------> FSMC_A2
+  PF3   ------> FSMC_A3
+  PF4   ------> FSMC_A4
+  PF5   ------> FSMC_A5
+  PF12   ------> FSMC_A6
+  PE7   ------> FSMC_D4
+  PE8   ------> FSMC_D5
+  PE9   ------> FSMC_D6
+  PE10   ------> FSMC_D7
+  PD14   ------> FSMC_D0
+  PD15   ------> FSMC_D1
+  PD0   ------> FSMC_D2
+  PD1   ------> FSMC_D3
+  PD4   ------> FSMC_NOE
+  PD5   ------> FSMC_NWE
+  PD7   ------> FSMC_NE1
+  PG9   ------> FSMC_NE2
+  */
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_12;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
+
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
+
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
+
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* GPIO_InitStruct */
+  GPIO_InitStruct.Pin = GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FSMC;
+
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN FSMC_MspInit 1 */
+
+  /* USER CODE END FSMC_MspInit 1 */
+}
+
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *sramHandle)
+{
+  /* USER CODE BEGIN SRAM_MspInit 0 */
+
+  /* USER CODE END SRAM_MspInit 0 */
+  HAL_FSMC_MspInit();
+  /* USER CODE BEGIN SRAM_MspInit 1 */
+
+  /* USER CODE END SRAM_MspInit 1 */
+}
+
+static uint32_t FSMC_DeInitialized = 0;
+
+static void HAL_FSMC_MspDeInit(void)
+{
+  /* USER CODE BEGIN FSMC_MspDeInit 0 */
+
+  /* USER CODE END FSMC_MspDeInit 0 */
+  if (FSMC_DeInitialized)
+  {
+    return;
+  }
+  FSMC_DeInitialized = 1;
+  /* Peripheral clock enable */
+  __HAL_RCC_FSMC_CLK_DISABLE();
+
+  /** FSMC GPIO Configuration
+  PF0   ------> FSMC_A0
+  PF1   ------> FSMC_A1
+  PF2   ------> FSMC_A2
+  PF3   ------> FSMC_A3
+  PF4   ------> FSMC_A4
+  PF5   ------> FSMC_A5
+  PF12   ------> FSMC_A6
+  PE7   ------> FSMC_D4
+  PE8   ------> FSMC_D5
+  PE9   ------> FSMC_D6
+  PE10   ------> FSMC_D7
+  PD14   ------> FSMC_D0
+  PD15   ------> FSMC_D1
+  PD0   ------> FSMC_D2
+  PD1   ------> FSMC_D3
+  PD4   ------> FSMC_NOE
+  PD5   ------> FSMC_NWE
+  PD7   ------> FSMC_NE1
+  PG9   ------> FSMC_NE2
+  */
+
+  HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_12);
+
+  HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10);
+
+  HAL_GPIO_DeInit(GPIOD, GPIO_PIN_14 | GPIO_PIN_15 | GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_7);
+
+  HAL_GPIO_DeInit(GPIOG, GPIO_PIN_9);
+
+  /* USER CODE BEGIN FSMC_MspDeInit 1 */
+
+  /* USER CODE END FSMC_MspDeInit 1 */
+}
+
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *sramHandle)
+{
+  /* USER CODE BEGIN SRAM_MspDeInit 0 */
+
+  /* USER CODE END SRAM_MspDeInit 0 */
+  HAL_FSMC_MspDeInit();
+  /* USER CODE BEGIN SRAM_MspDeInit 1 */
+
+  /* USER CODE END SRAM_MspDeInit 1 */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c
index 6c8a60e..635eed7 100644
--- a/Core/Src/gpio.c
+++ b/Core/Src/gpio.c
@@ -46,13 +46,13 @@ void MX_GPIO_Init(void)
 
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE();
   __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOF_CLK_ENABLE();
   __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOG_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
 
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(PE5_LED_GPIO_Port, PE5_LED_Pin, GPIO_PIN_SET);
@@ -60,15 +60,9 @@ void MX_GPIO_Init(void)
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(HART_ALL_RST_GPIO_Port, HART_ALL_RST_Pin, GPIO_PIN_SET);
 
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(CH438_AMOD_GPIO_Port, CH438_AMOD_Pin, GPIO_PIN_RESET);
-
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(HART1_RTS_GPIO_Port, HART1_RTS_Pin, GPIO_PIN_SET);
 
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(CH438_RST_GPIO_Port, CH438_RST_Pin, GPIO_PIN_SET);
-
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(DAC1_CS_GPIO_Port, DAC1_CS_Pin, GPIO_PIN_SET);
 
@@ -86,13 +80,6 @@ void MX_GPIO_Init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
   HAL_GPIO_Init(HART_ALL_RST_GPIO_Port, &GPIO_InitStruct);
 
-  /*Configure GPIO pin : PtPin */
-  GPIO_InitStruct.Pin = CH438_AMOD_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  HAL_GPIO_Init(CH438_AMOD_GPIO_Port, &GPIO_InitStruct);
-
   /*Configure GPIO pin : PtPin */
   GPIO_InitStruct.Pin = HART1_RTS_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -101,11 +88,10 @@ void MX_GPIO_Init(void)
   HAL_GPIO_Init(HART1_RTS_GPIO_Port, &GPIO_InitStruct);
 
   /*Configure GPIO pin : PtPin */
-  GPIO_InitStruct.Pin = CH438_RST_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pin = CH438_INT_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
   GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  HAL_GPIO_Init(CH438_RST_GPIO_Port, &GPIO_InitStruct);
+  HAL_GPIO_Init(CH438_INT_GPIO_Port, &GPIO_InitStruct);
 
   /*Configure GPIO pin : PtPin */
   GPIO_InitStruct.Pin = DAC1_CS_Pin;
@@ -114,6 +100,10 @@ void MX_GPIO_Init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
   HAL_GPIO_Init(DAC1_CS_GPIO_Port, &GPIO_InitStruct);
 
+  /* EXTI interrupt init*/
+  HAL_NVIC_SetPriority(EXTI2_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(EXTI2_IRQn);
+
 }
 
 /* USER CODE BEGIN 2 */
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 218e755..41f0fb6 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -23,6 +23,7 @@
 #include "spi.h"
 #include "tim.h"
 #include "gpio.h"
+#include "fsmc.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -92,6 +93,7 @@ int main(void)
   MX_GPIO_Init();
   MX_TIM2_Init();
   MX_SPI1_Init();
+  MX_FSMC_Init();
   /* USER CODE BEGIN 2 */
 
   /* USER CODE END 2 */
diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c
index f818830..69202a3 100644
--- a/Core/Src/stm32f4xx_it.c
+++ b/Core/Src/stm32f4xx_it.c
@@ -160,6 +160,20 @@ void DebugMon_Handler(void)
 /* please refer to the startup file (startup_stm32f4xx.s).                    */
 /******************************************************************************/
 
+/**
+  * @brief This function handles EXTI line2 interrupt.
+  */
+void EXTI2_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI2_IRQn 0 */
+
+  /* USER CODE END EXTI2_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(CH438_INT_Pin);
+  /* USER CODE BEGIN EXTI2_IRQn 1 */
+
+  /* USER CODE END EXTI2_IRQn 1 */
+}
+
 /**
   * @brief This function handles TIM4 global interrupt.
   */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h
new file mode 100644
index 0000000..e135aa1
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h
@@ -0,0 +1,236 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sram.h
+  * @author  MCD Application Team
+  * @brief   Header file of SRAM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_SRAM_H
+#define STM32F4xx_HAL_SRAM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(FMC_Bank1) || defined(FSMC_Bank1)
+
+/* Includes ------------------------------------------------------------------*/
+#if defined(FSMC_Bank1)
+#include "stm32f4xx_ll_fsmc.h"
+#else
+#include "stm32f4xx_ll_fmc.h"
+#endif /* FSMC_Bank1 */
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+/** @addtogroup SRAM
+  * @{
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Types SRAM Exported Types
+  * @{
+  */
+/**
+  * @brief  HAL SRAM State structures definition
+  */
+typedef enum
+{
+  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
+  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
+  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
+  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
+  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
+
+} HAL_SRAM_StateTypeDef;
+
+/**
+  * @brief  SRAM handle Structure definition
+  */
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SRAM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+{
+  FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
+
+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
+
+  FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
+
+  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
+
+  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
+
+  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram);               /*!< SRAM Msp Init callback              */
+  void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram);             /*!< SRAM Msp DeInit callback            */
+  void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma);                      /*!< SRAM DMA Xfer Complete callback     */
+  void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma);                     /*!< SRAM DMA Xfer Error callback        */
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+} SRAM_HandleTypeDef;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL SRAM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
+  HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
+  HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
+  HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
+} HAL_SRAM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SRAM Callback pointer definition
+  */
+typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
+typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
+  * @{
+  */
+
+/** @brief Reset SRAM handle state
+  * @param  __HANDLE__ SRAM handle
+  * @retval None
+  */
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
+                                                               (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
+  * @{
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+                                FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+  * @{
+  */
+
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+                                   uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                     uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                    uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                     uint32_t BufferSize);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/* SRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+                                            pSRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+                                               pSRAM_DmaCallbackTypeDef pCallback);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
+  * @{
+  */
+
+/* SRAM Control functions  ****************************************************/
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+
+/* SRAM  State functions ******************************************************/
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* FMC_Bank1 || FSMC_Bank1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_SRAM_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h
new file mode 100644
index 0000000..8b0ceb7
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h
@@ -0,0 +1,1086 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_fsmc.h
+  * @author  MCD Application Team
+  * @brief   Header file of FSMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_LL_FSMC_H
+#define STM32F4xx_LL_FSMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FSMC_LL
+  * @{
+  */
+
+/** @addtogroup FSMC_LL_Private_Macros
+  * @{
+  */
+#if defined(FSMC_Bank1)
+
+#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
+                                       ((__BANK__) == FSMC_NORSRAM_BANK2) || \
+                                       ((__BANK__) == FSMC_NORSRAM_BANK3) || \
+                                       ((__BANK__) == FSMC_NORSRAM_BANK4))
+#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+                             ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
+                                   ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
+                                   ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
+                                                ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+                                                ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
+                                   ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
+                                   ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
+                                   ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
+                                   ((__SIZE__) == FSMC_PAGE_SIZE_1024))
+#if defined(FSMC_BCR1_WFDIS)
+#define IS_FSMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FSMC_WRITE_FIFO_DISABLE) || \
+                                     ((__FIFO__) == FSMC_WRITE_FIFO_ENABLE))
+#endif /* FSMC_BCR1_WFDIS */
+#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
+                                      ((__MODE__) == FSMC_ACCESS_MODE_B) || \
+                                      ((__MODE__) == FSMC_ACCESS_MODE_C) || \
+                                      ((__MODE__) == FSMC_ACCESS_MODE_D))
+#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+                                     ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
+#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+                                            ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
+                                             ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+                                               ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
+#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
+                                               ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
+#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
+                                         ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
+#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
+                                        ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
+#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+                                    ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
+#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
+                                       ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
+#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+                                            ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
+#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
+#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
+#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
+#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
+
+#endif /* FSMC_Bank1 */
+#if  defined(FSMC_Bank2_3)
+
+#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
+                                            ((__BANK__) == FSMC_NAND_BANK3))
+#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+                                                   ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+                                                      ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
+                                     ((__STATE__) == FSMC_NAND_ECC_ENABLE))
+
+#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
+
+#endif /* FSMC_Bank2_3 */
+#if defined(FSMC_Bank4)
+#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
+
+#endif /* FSMC_Bank4 */
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
+  * @{
+  */
+
+#if defined(FSMC_Bank1)
+#define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
+#endif /* FSMC_Bank1 */
+#if defined(FSMC_Bank2_3)
+#define FSMC_NAND_TypeDef               FSMC_Bank2_3_TypeDef
+#endif /* FSMC_Bank2_3 */
+#if defined(FSMC_Bank4)
+#define FSMC_PCCARD_TypeDef             FSMC_Bank4_TypeDef
+#endif /* FSMC_Bank4 */
+
+#if defined(FSMC_Bank1)
+#define FSMC_NORSRAM_DEVICE             FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
+#endif /* FSMC_Bank1 */
+#if defined(FSMC_Bank2_3)
+#define FSMC_NAND_DEVICE                FSMC_Bank2_3
+#endif /* FSMC_Bank2_3 */
+#if defined(FSMC_Bank4)
+#define FSMC_PCCARD_DEVICE              FSMC_Bank4
+#endif /* FSMC_Bank4 */
+
+#if defined(FSMC_Bank1)
+/**
+  * @brief  FSMC NORSRAM Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
+                                              This parameter can be a value of @ref FSMC_NORSRAM_Bank                  */
+
+  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
+                                              multiplexed on the data bus or not.
+                                              This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
+                                              the corresponding memory device.
+                                              This parameter can be a value of @ref FSMC_Memory_Type                   */
+
+  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
+                                              This parameter can be a value of @ref FSMC_NORSRAM_Data_Width            */
+
+  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
+                                              valid only with synchronous burst Flash memories.
+                                              This parameter can be a value of @ref FSMC_Burst_Access_Mode             */
+
+  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
+                                              the Flash memory in burst mode.
+                                              This parameter can be a value of @ref FSMC_Wait_Signal_Polarity          */
+
+  uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
+                                              memory, valid only when accessing Flash memories in burst mode.
+                                              This parameter can be a value of @ref FSMC_Wrap_Mode
+                                              This mode is available only for the STM32F405/407/4015/417xx devices             */
+
+  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
+                                              clock cycle before the wait state or during the wait state,
+                                              valid only when accessing memories in burst mode.
+                                              This parameter can be a value of @ref FSMC_Wait_Timing                   */
+
+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
+                                              This parameter can be a value of @ref FSMC_Write_Operation               */
+
+  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
+                                              signal, valid for Flash memory access in burst mode.
+                                              This parameter can be a value of @ref FSMC_Wait_Signal                   */
+
+  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
+                                              This parameter can be a value of @ref FSMC_Extended_Mode                 */
+
+  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
+                                              valid only with asynchronous Flash memories.
+                                              This parameter can be a value of @ref FSMC_AsynchronousWait              */
+
+  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
+                                              This parameter can be a value of @ref FSMC_Write_Burst                   */
+
+  uint32_t ContinuousClock;              /*!< Enables or disables the FSMC clock output to external memory devices.
+                                              This parameter is only enabled through the FSMC_BCR1 register,
+                                              and don't care through FSMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FSMC_Continous_Clock
+                                              This mode is available only for the STM32F412Vx/Zx/Rx devices           */
+
+  uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FSMC controller.
+                                              This parameter is only enabled through the FSMC_BCR1 register,
+                                              and don't care through FSMC_BCR2..4 registers.
+                                              This parameter can be a value of @ref FSMC_Write_FIFO
+                                              This mode is available only for the STM32F412Vx/Vx devices              */
+
+  uint32_t PageSize;                     /*!< Specifies the memory page size.
+                                              This parameter can be a value of @ref FSMC_Page_Size                     */
+} FSMC_NORSRAM_InitTypeDef;
+
+/**
+  * @brief  FSMC NORSRAM Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address setup time.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.   */
+
+  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the address hold time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+                                              @note This parameter is not used with synchronous NOR Flash memories.   */
+
+  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the data setup time.
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+                                              NOR Flash memories.                                                     */
+
+  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
+                                              the duration of the bus turnaround.
+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
+                                              @note This parameter is only used for multiplexed NOR Flash memories.   */
+
+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
+                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and
+                                              Max_Data = 16.
+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+                                              accesses.                                                               */
+
+  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
+                                              to the memory before getting the first data.
+                                              The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between Min_Data = 2 and Max_Data = 17
+                                                in NOR Flash memories with synchronous burst mode enable              */
+
+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
+                                              This parameter can be a value of @ref FSMC_Access_Mode                   */
+} FSMC_NORSRAM_TimingTypeDef;
+#endif /* FSMC_Bank1 */
+
+#if defined(FSMC_Bank2_3)
+/**
+  * @brief  FSMC NAND Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
+                                        This parameter can be a value of @ref FSMC_NAND_Bank                  */
+
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
+                                        This parameter can be any value of @ref FSMC_Wait_feature             */
+
+  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
+                                        This parameter can be any value of @ref FSMC_NAND_Data_Width          */
+
+  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
+                                        This parameter can be any value of @ref FSMC_ECC                      */
+
+  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
+                                        This parameter can be any value of @ref FSMC_ECC_Page_Size            */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+} FSMC_NAND_InitTypeDef;
+#endif
+
+#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
+/**
+  * @brief  FSMC NAND Timing parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
+                                      the command assertion for NAND-Flash read or write access
+                                      to common/Attribute or I/O memory space (depending on
+                                      the memory space timing to be configured).
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 254    */
+
+  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
+                                      command for NAND-Flash read or write access to
+                                      common/Attribute or I/O memory space (depending on the
+                                      memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
+
+  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
+                                      (and data for write access) after the command de-assertion
+                                      for NAND-Flash read or write access to common/Attribute
+                                      or I/O memory space (depending on the memory space timing
+                                      to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
+
+  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
+                                      data bus is kept in HiZ after the start of a NAND-Flash
+                                      write access to common/Attribute or I/O memory space (depending
+                                      on the memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
+} FSMC_NAND_PCC_TimingTypeDef;
+#endif /* FSMC_Bank2_3 */
+
+#if defined(FSMC_Bank4)
+/**
+  * @brief FSMC PCCARD Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
+                                        This parameter can be any value of @ref FSMC_Wait_feature      */
+
+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
+                                        delay between CLE low and RE low.
+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
+
+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
+                                        delay between ALE low and RE low.
+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FSMC_PCCARD_InitTypeDef;
+#endif /* FSMC_Bank4 */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
+  * @{
+  */
+#if defined(FSMC_Bank1)
+
+/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
+  * @{
+  */
+
+/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
+  * @{
+  */
+#define FSMC_NORSRAM_BANK1                       (0x00000000U)
+#define FSMC_NORSRAM_BANK2                       (0x00000002U)
+#define FSMC_NORSRAM_BANK3                       (0x00000004U)
+#define FSMC_NORSRAM_BANK4                       (0x00000006U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
+  * @{
+  */
+#define FSMC_DATA_ADDRESS_MUX_DISABLE            (0x00000000U)
+#define FSMC_DATA_ADDRESS_MUX_ENABLE             (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Memory_Type FSMC Memory Type
+  * @{
+  */
+#define FSMC_MEMORY_TYPE_SRAM                    (0x00000000U)
+#define FSMC_MEMORY_TYPE_PSRAM                   (0x00000004U)
+#define FSMC_MEMORY_TYPE_NOR                     (0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
+  * @{
+  */
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_8             (0x00000000U)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_16            (0x00000010U)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_32            (0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
+  * @{
+  */
+#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         (0x00000040U)
+#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
+  * @{
+  */
+#define FSMC_BURST_ACCESS_MODE_DISABLE           (0x00000000U)
+#define FSMC_BURST_ACCESS_MODE_ENABLE            (0x00000100U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
+  * @{
+  */
+#define FSMC_WAIT_SIGNAL_POLARITY_LOW            (0x00000000U)
+#define FSMC_WAIT_SIGNAL_POLARITY_HIGH           (0x00000200U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
+  * @note  These values are available only for the STM32F405/415/407/417xx devices.
+  * @{
+  */
+#define FSMC_WRAP_MODE_DISABLE                   (0x00000000U)
+#define FSMC_WRAP_MODE_ENABLE                    (0x00000400U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
+  * @{
+  */
+#define FSMC_WAIT_TIMING_BEFORE_WS               (0x00000000U)
+#define FSMC_WAIT_TIMING_DURING_WS               (0x00000800U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Operation FSMC Write Operation
+  * @{
+  */
+#define FSMC_WRITE_OPERATION_DISABLE             (0x00000000U)
+#define FSMC_WRITE_OPERATION_ENABLE              (0x00001000U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
+  * @{
+  */
+#define FSMC_WAIT_SIGNAL_DISABLE                 (0x00000000U)
+#define FSMC_WAIT_SIGNAL_ENABLE                  (0x00002000U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
+  * @{
+  */
+#define FSMC_EXTENDED_MODE_DISABLE               (0x00000000U)
+#define FSMC_EXTENDED_MODE_ENABLE                (0x00004000U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
+  * @{
+  */
+#define FSMC_ASYNCHRONOUS_WAIT_DISABLE           (0x00000000U)
+#define FSMC_ASYNCHRONOUS_WAIT_ENABLE            (0x00008000U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Page_Size FSMC Page Size
+  * @{
+  */
+#define FSMC_PAGE_SIZE_NONE                      (0x00000000U)
+#define FSMC_PAGE_SIZE_128                       FSMC_BCR1_CPSIZE_0
+#define FSMC_PAGE_SIZE_256                       FSMC_BCR1_CPSIZE_1
+#define FSMC_PAGE_SIZE_512                       (FSMC_BCR1_CPSIZE_0\
+                                                 | FSMC_BCR1_CPSIZE_1)
+#define FSMC_PAGE_SIZE_1024                      FSMC_BCR1_CPSIZE_2
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Burst FSMC Write Burst
+  * @{
+  */
+#define FSMC_WRITE_BURST_DISABLE                 (0x00000000U)
+#define FSMC_WRITE_BURST_ENABLE                  (0x00080000U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
+  * @note  These values are available only for the STM32F412Vx/Zx/Rx devices.
+  * @{
+  */
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY          (0x00000000U)
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC         (0x00100000U)
+/**
+  * @}
+  */
+
+#if defined(FSMC_BCR1_WFDIS)
+/** @defgroup FSMC_Write_FIFO FSMC Write FIFO
+  * @note  These values are available only for the STM32F412Vx/Zx/Rx devices.
+  * @{
+  */
+#define FSMC_WRITE_FIFO_DISABLE                  FSMC_BCR1_WFDIS
+#define FSMC_WRITE_FIFO_ENABLE                   (0x00000000U)
+#endif /* FSMC_BCR1_WFDIS */
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Access_Mode FSMC Access Mode
+  * @{
+  */
+#define FSMC_ACCESS_MODE_A                       (0x00000000U)
+#define FSMC_ACCESS_MODE_B                       (0x10000000U)
+#define FSMC_ACCESS_MODE_C                       (0x20000000U)
+#define FSMC_ACCESS_MODE_D                       (0x30000000U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* FSMC_Bank1 */
+
+#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
+
+/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
+  * @{
+  */
+/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
+  * @{
+  */
+#if defined(FSMC_Bank2_3)
+#define FSMC_NAND_BANK2                          (0x00000010U)
+#endif
+#define FSMC_NAND_BANK3                          (0x00000100U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_feature FSMC Wait feature
+  * @{
+  */
+#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE       (0x00000000U)
+#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
+  * @{
+  */
+#if defined(FSMC_Bank4)
+#define FSMC_PCR_MEMORY_TYPE_PCCARD              (0x00000000U)
+#endif /* FSMC_Bank4 */
+#define FSMC_PCR_MEMORY_TYPE_NAND                (0x00000008U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
+  * @{
+  */
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8            (0x00000000U)
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16           (0x00000010U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC FSMC ECC
+  * @{
+  */
+#define FSMC_NAND_ECC_DISABLE                    (0x00000000U)
+#define FSMC_NAND_ECC_ENABLE                     (0x00000040U)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
+  * @{
+  */
+#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE          (0x00000000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE          (0x00020000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE         (0x00040000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE         (0x00060000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE         (0x00080000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE         (0x000A0000U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* FSMC_Bank2_3 || FSMC_Bank4 */
+
+
+/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
+  * @{
+  */
+#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
+#define FSMC_IT_RISING_EDGE                      (0x00000008U)
+#define FSMC_IT_LEVEL                            (0x00000010U)
+#define FSMC_IT_FALLING_EDGE                     (0x00000020U)
+#endif /* FSMC_Bank2_3 || FSMC_Bank4 */
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
+  * @{
+  */
+#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
+#define FSMC_FLAG_RISING_EDGE                    (0x00000001U)
+#define FSMC_FLAG_LEVEL                          (0x00000002U)
+#define FSMC_FLAG_FALLING_EDGE                   (0x00000004U)
+#define FSMC_FLAG_FEMPT                          (0x00000040U)
+#endif /* FSMC_Bank2_3 || FSMC_Bank4 */
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_LL_Alias_definition  FSMC Alias definition
+  * @{
+  */
+#define FMC_WRITE_OPERATION_DISABLE          FSMC_WRITE_OPERATION_DISABLE
+#define FMC_WRITE_OPERATION_ENABLE           FSMC_WRITE_OPERATION_ENABLE
+
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8           FSMC_NORSRAM_MEM_BUS_WIDTH_8
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16          FSMC_NORSRAM_MEM_BUS_WIDTH_16
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32          FSMC_NORSRAM_MEM_BUS_WIDTH_32
+
+#define FMC_NORSRAM_TypeDef                   FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef          FSMC_NORSRAM_EXTENDED_TypeDef
+#define FMC_NORSRAM_InitTypeDef               FSMC_NORSRAM_InitTypeDef
+#define FMC_NORSRAM_TimingTypeDef             FSMC_NORSRAM_TimingTypeDef
+
+#define FMC_NORSRAM_Init                      FSMC_NORSRAM_Init
+#define FMC_NORSRAM_Timing_Init               FSMC_NORSRAM_Timing_Init
+#define FMC_NORSRAM_Extended_Timing_Init      FSMC_NORSRAM_Extended_Timing_Init
+#define FMC_NORSRAM_DeInit                    FSMC_NORSRAM_DeInit
+#define FMC_NORSRAM_WriteOperation_Enable     FSMC_NORSRAM_WriteOperation_Enable
+#define FMC_NORSRAM_WriteOperation_Disable    FSMC_NORSRAM_WriteOperation_Disable
+
+#define __FMC_NORSRAM_ENABLE                  __FSMC_NORSRAM_ENABLE
+#define __FMC_NORSRAM_DISABLE                 __FSMC_NORSRAM_DISABLE
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FMC_NAND_InitTypeDef                  FSMC_NAND_InitTypeDef
+#define FMC_PCCARD_InitTypeDef                FSMC_PCCARD_InitTypeDef
+#define FMC_NAND_PCC_TimingTypeDef            FSMC_NAND_PCC_TimingTypeDef
+
+#define FMC_NAND_Init                         FSMC_NAND_Init
+#define FMC_NAND_CommonSpace_Timing_Init      FSMC_NAND_CommonSpace_Timing_Init
+#define FMC_NAND_AttributeSpace_Timing_Init   FSMC_NAND_AttributeSpace_Timing_Init
+#define FMC_NAND_DeInit                       FSMC_NAND_DeInit
+#define FMC_NAND_ECC_Enable                   FSMC_NAND_ECC_Enable
+#define FMC_NAND_ECC_Disable                  FSMC_NAND_ECC_Disable
+#define FMC_NAND_GetECC                       FSMC_NAND_GetECC
+#define FMC_PCCARD_Init                       FSMC_PCCARD_Init
+#define FMC_PCCARD_CommonSpace_Timing_Init    FSMC_PCCARD_CommonSpace_Timing_Init
+#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
+#define FMC_PCCARD_IOSpace_Timing_Init        FSMC_PCCARD_IOSpace_Timing_Init
+#define FMC_PCCARD_DeInit                     FSMC_PCCARD_DeInit
+
+#define __FMC_NAND_ENABLE                     __FSMC_NAND_ENABLE
+#define __FMC_NAND_DISABLE                    __FSMC_NAND_DISABLE
+#define __FMC_PCCARD_ENABLE                   __FSMC_PCCARD_ENABLE
+#define __FMC_PCCARD_DISABLE                  __FSMC_PCCARD_DISABLE
+#define __FMC_NAND_ENABLE_IT                  __FSMC_NAND_ENABLE_IT
+#define __FMC_NAND_DISABLE_IT                 __FSMC_NAND_DISABLE_IT
+#define __FMC_NAND_GET_FLAG                   __FSMC_NAND_GET_FLAG
+#define __FMC_NAND_CLEAR_FLAG                 __FSMC_NAND_CLEAR_FLAG
+#define __FMC_PCCARD_ENABLE_IT                __FSMC_PCCARD_ENABLE_IT
+#define __FMC_PCCARD_DISABLE_IT               __FSMC_PCCARD_DISABLE_IT
+#define __FMC_PCCARD_GET_FLAG                 __FSMC_PCCARD_GET_FLAG
+#define __FMC_PCCARD_CLEAR_FLAG               __FSMC_PCCARD_CLEAR_FLAG
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#define FMC_NORSRAM_TypeDef                   FSMC_NORSRAM_TypeDef
+#define FMC_NORSRAM_EXTENDED_TypeDef          FSMC_NORSRAM_EXTENDED_TypeDef
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FMC_NAND_TypeDef                      FSMC_NAND_TypeDef
+#define FMC_PCCARD_TypeDef                    FSMC_PCCARD_TypeDef
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#define FMC_NORSRAM_DEVICE                    FSMC_NORSRAM_DEVICE
+#define FMC_NORSRAM_EXTENDED_DEVICE           FSMC_NORSRAM_EXTENDED_DEVICE
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define FMC_NAND_DEVICE                       FSMC_NAND_DEVICE
+#define FMC_PCCARD_DEVICE                     FSMC_PCCARD_DEVICE
+
+#define FMC_NAND_BANK2                        FSMC_NAND_BANK2
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#define FMC_NORSRAM_BANK1                     FSMC_NORSRAM_BANK1
+#define FMC_NORSRAM_BANK2                     FSMC_NORSRAM_BANK2
+#define FMC_NORSRAM_BANK3                     FSMC_NORSRAM_BANK3
+
+#define FMC_IT_RISING_EDGE                    FSMC_IT_RISING_EDGE
+#define FMC_IT_LEVEL                          FSMC_IT_LEVEL
+#define FMC_IT_FALLING_EDGE                   FSMC_IT_FALLING_EDGE
+#define FMC_IT_REFRESH_ERROR                  FSMC_IT_REFRESH_ERROR
+
+#define FMC_FLAG_RISING_EDGE                  FSMC_FLAG_RISING_EDGE
+#define FMC_FLAG_LEVEL                        FSMC_FLAG_LEVEL
+#define FMC_FLAG_FALLING_EDGE                 FSMC_FLAG_FALLING_EDGE
+#define FMC_FLAG_FEMPT                        FSMC_FLAG_FEMPT
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Macros FSMC_LL  Private Macros
+  * @{
+  */
+#if defined(FSMC_Bank1)
+/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
+  * @brief macros to handle NOR device enable/disable and read/write operations
+  * @{
+  */
+
+/**
+  * @brief  Enable the NORSRAM device access.
+  * @param  __INSTANCE__ FSMC_NORSRAM Instance
+  * @param  __BANK__ FSMC_NORSRAM Bank
+  * @retval None
+  */
+#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)]\
+                                                       |= FSMC_BCR1_MBKEN)
+
+/**
+  * @brief  Disable the NORSRAM device access.
+  * @param  __INSTANCE__ FSMC_NORSRAM Instance
+  * @param  __BANK__ FSMC_NORSRAM Bank
+  * @retval None
+  */
+#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+                                                       &= ~FSMC_BCR1_MBKEN)
+
+/**
+  * @}
+  */
+#endif /* FSMC_Bank1 */
+
+#if defined(FSMC_Bank2_3)
+/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
+  *  @brief macros to handle NAND device enable/disable
+  *  @{
+  */
+
+/**
+  * @brief  Enable the NAND device access.
+  * @param  __INSTANCE__ FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @retval None
+  */
+#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
+                                                             ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
+
+/**
+  * @brief  Disable the NAND device access.
+  * @param  __INSTANCE__ FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @retval None
+  */
+#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \
+                                                             CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN))
+
+/**
+  * @}
+  */
+#endif /* FSMC_Bank2_3 */
+
+#if defined(FSMC_Bank4)
+/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
+  *  @brief macros to handle PCCARD read/write operations
+  *  @{
+  */
+/**
+  * @brief  Enable the PCCARD device access.
+  * @param  __INSTANCE__ FSMC_PCCARD Instance
+  * @retval None
+  */
+#define __FSMC_PCCARD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
+
+/**
+  * @brief  Disable the PCCARD device access.
+  * @param  __INSTANCE__ FSMC_PCCARD Instance
+  * @retval None
+  */
+#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
+/**
+  * @}
+  */
+
+#endif
+#if defined(FSMC_Bank2_3)
+/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
+  * @brief macros to handle NAND interrupts
+  * @{
+  */
+
+/**
+  * @brief  Enable the NAND device interrupt.
+  * @param  __INSTANCE__  FSMC_NAND instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @param  __INTERRUPT__ FSMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FSMC_IT_LEVEL: Interrupt level.
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
+                                                                               ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+
+/**
+  * @brief  Disable the NAND device interrupt.
+  * @param  __INSTANCE__  FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @param  __INTERRUPT__ FSMC_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FSMC_IT_LEVEL: Interrupt level.
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
+                                                                                ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+
+/**
+  * @brief  Get flag status of the NAND device.
+  * @param  __INSTANCE__ FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @param  __FLAG__     FSMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
+                                                                         (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+
+/**
+  * @brief  Clear flag status of the NAND device.
+  * @param  __INSTANCE__ FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @param  __FLAG__     FSMC_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval None
+  */
+#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
+                                                                           ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+
+/**
+  * @}
+  */
+#endif /* FSMC_Bank2_3 */
+
+#if defined(FSMC_Bank4)
+/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
+  * @brief macros to handle PCCARD interrupts
+  * @{
+  */
+
+/**
+  * @brief  Enable the PCCARD device interrupt.
+  * @param  __INSTANCE__ FSMC_PCCARD instance
+  * @param  __INTERRUPT__ FSMC_PCCARD interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FSMC_IT_LEVEL: Interrupt level.
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the PCCARD device interrupt.
+  * @param  __INSTANCE__ FSMC_PCCARD instance
+  * @param  __INTERRUPT__ FSMC_PCCARD interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg FSMC_IT_LEVEL: Interrupt level.
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Get flag status of the PCCARD device.
+  * @param  __INSTANCE__ FSMC_PCCARD instance
+  * @param  __FLAG__ FSMC_PCCARD flag
+  *         This parameter can be any combination of the following values:
+  *            @arg  FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg  FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg  FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg  FSMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief  Clear flag status of the PCCARD device.
+  * @param  __INSTANCE__ FSMC_PCCARD instance
+  * @param  __FLAG__ FSMC_PCCARD flag
+  *         This parameter can be any combination of the following values:
+  *            @arg  FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg  FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg  FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg  FSMC_FLAG_FEMPT: FIFO empty flag.
+  * @retval None
+  */
+#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+
+/**
+  * @}
+  */
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
+  *  @{
+  */
+
+#if defined(FSMC_Bank1)
+/** @defgroup FSMC_LL_NORSRAM  NOR SRAM
+  *  @{
+  */
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
+                                    FSMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
+                                           FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
+                                                    FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+                                                    uint32_t ExtendedMode);
+HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
+                                      FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
+  *  @{
+  */
+HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* FSMC_Bank1 */
+
+#if defined(FSMC_Bank2_3)
+/** @defgroup FSMC_LL_NAND NAND
+  *  @{
+  */
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
+HAL_StatusTypeDef  FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
+                                                    FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
+                                                       FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
+  *  @{
+  */
+HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+                                   uint32_t Timeout);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* FSMC_Bank2_3 */
+
+#if defined(FSMC_Bank4)
+/** @defgroup FSMC_LL_PCCARD PCCARD
+  *  @{
+  */
+/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
+  *  @{
+  */
+HAL_StatusTypeDef  FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
+HAL_StatusTypeDef  FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
+                                                               FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
+                                                                  FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
+                                                           FSMC_NAND_PCC_TimingTypeDef *Timing);
+HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* FSMC_Bank4 */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_LL_FSMC_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c
new file mode 100644
index 0000000..ef2eaf0
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c
@@ -0,0 +1,1110 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_sram.c
+  * @author  MCD Application Team
+  * @brief   SRAM HAL module driver.
+  *          This file provides a generic firmware to drive SRAM memories
+  *          mounted as external device.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                          ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    This driver is a generic layered driver which contains a set of APIs used to
+    control SRAM memories. It uses the FMC layer functions to interface
+    with SRAM devices.
+    The following sequence should be followed to configure the FMC/FSMC to interface
+    with SRAM/PSRAM memories:
+
+   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
+          SRAM_HandleTypeDef  hsram; and:
+
+       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
+            values of the structure member.
+
+       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
+            base register instance for NOR or SRAM device
+
+       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
+            base register instance for NOR or SRAM extended mode
+
+   (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
+       mode timings; for example:
+          FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
+      and fill its fields with the allowed values of the structure member.
+
+   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
+       performs the following sequence:
+
+       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
+       (##) Control register configuration using the FMC NORSRAM interface function
+            FMC_NORSRAM_Init()
+       (##) Timing register configuration using the FMC NORSRAM interface function
+            FMC_NORSRAM_Timing_Init()
+       (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
+            FMC_NORSRAM_Extended_Timing_Init()
+       (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
+
+   (#) At this stage you can perform read/write accesses from/to the memory connected
+       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
+       following APIs:
+       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
+       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
+
+   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
+       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
+
+   (#) You can continuously monitor the SRAM device HAL state by calling the function
+       HAL_SRAM_GetState()
+
+       *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : SRAM MspInit.
+        (+) MspDeInitCallback  : SRAM MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : SRAM MspInit.
+        (+) MspDeInitCallback  : SRAM MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
+      and  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
+      or HAL_SRAM_Init function.
+
+      When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+#if defined(FMC_Bank1) || defined(FSMC_Bank1)
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+
+/** @defgroup SRAM SRAM
+  * @brief SRAM driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
+static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
+static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
+  * @{
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions.
+  *
+  @verbatim
+  ==============================================================================
+           ##### SRAM Initialization and de_initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to initialize/de-initialize
+          the SRAM memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Performs the SRAM device initialization sequence
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  Timing Pointer to SRAM control timing structure
+  * @param  ExtTiming Pointer to SRAM extended mode timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+                                FMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+  /* Check the SRAM handle parameter */
+  if (hsram == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hsram->State == HAL_SRAM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsram->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+    if (hsram->MspInitCallback == NULL)
+    {
+      hsram->MspInitCallback = HAL_SRAM_MspInit;
+    }
+    hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+    hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+    /* Init the low level hardware */
+    hsram->MspInitCallback(hsram);
+#else
+    /* Initialize the low level hardware (MSP) */
+    HAL_SRAM_MspInit(hsram);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+  }
+
+  /* Initialize SRAM control Interface */
+  (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+
+  /* Initialize SRAM timing Interface */
+  (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
+
+  /* Initialize SRAM extended mode timing Interface */
+  (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
+                                         hsram->Init.ExtendedMode);
+
+  /* Enable the NORSRAM device */
+  __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
+
+  /* Initialize the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Performs the SRAM device De-initialization sequence.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  if (hsram->MspDeInitCallback == NULL)
+  {
+    hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsram->MspDeInitCallback(hsram);
+#else
+  /* De-Initialize the low level hardware (MSP) */
+  HAL_SRAM_MspDeInit(hsram);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+
+  /* Configure the SRAM registers with their reset values */
+  (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+
+  /* Reset the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  SRAM MSP Init.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  SRAM MSP DeInit.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA transfer complete error callback.
+  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval None
+  */
+__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+  * @brief    Input Output and memory control functions
+  *
+  @verbatim
+  ==============================================================================
+                  ##### SRAM Input and Output functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to use and control the SRAM memory
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads 8-bit buffer from SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+                                   uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
+  uint8_t *pdestbuff = pDstBuffer;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Read data from memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *psramaddress;
+      pdestbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 8-bit buffer to SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+                                    uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
+  uint8_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *psramaddress = *psrcbuff;
+      psrcbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads 16-bit buffer from SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+                                    uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint16_t *pdestbuff = pDstBuffer;
+  uint8_t limit;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Check if the size is a 32-bits multiple */
+    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
+
+    /* Read data from memory */
+    for (size = BufferSize; size != limit; size -= 2U)
+    {
+      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
+      pdestbuff++;
+      *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
+      pdestbuff++;
+      psramaddress++;
+    }
+
+    /* Read last 16-bits if size is not 32-bits multiple */
+    if (limit != 0U)
+    {
+      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 16-bit buffer to SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint16_t *psrcbuff = pSrcBuffer;
+  uint8_t limit;
+
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Check if the size is a 32-bits multiple */
+    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
+
+    /* Write data to memory */
+    for (size = BufferSize; size != limit; size -= 2U)
+    {
+      *psramaddress = (uint32_t)(*psrcbuff);
+      psrcbuff++;
+      *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
+      psrcbuff++;
+      psramaddress++;
+    }
+
+    /* Write last 16-bits if size is not 32-bits multiple */
+    if (limit != 0U)
+    {
+      *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads 32-bit buffer from SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                    uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint32_t *pdestbuff = pDstBuffer;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Read data from memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *psramaddress;
+      pdestbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Writes 32-bit buffer to SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                     uint32_t BufferSize)
+{
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint32_t *psrcbuff = pSrcBuffer;
+
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *psramaddress = *psrcbuff;
+      psrcbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reads a Words data from the SRAM memory using DMA transfer.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+                                    uint32_t BufferSize)
+{
+  HAL_StatusTypeDef status;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    if (state == HAL_SRAM_STATE_READY)
+    {
+      hsram->hdma->XferCpltCallback = SRAM_DMACplt;
+    }
+    else
+    {
+      hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
+    }
+    hsram->hdma->XferErrorCallback = SRAM_DMAError;
+
+    /* Enable the DMA Stream */
+    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+                                     uint32_t BufferSize)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    hsram->hdma->XferCpltCallback = SRAM_DMACplt;
+    hsram->hdma->XferErrorCallback = SRAM_DMAError;
+
+    /* Enable the DMA Stream */
+    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User SRAM Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsram : SRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
+  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+                                            pSRAM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SRAM_StateTypeDef state;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsram);
+
+  state = hsram->State;
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SRAM_MSP_INIT_CB_ID :
+        hsram->MspInitCallback = pCallback;
+        break;
+      case HAL_SRAM_MSP_DEINIT_CB_ID :
+        hsram->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SRAM Callback
+  *         SRAM Callback is redirected to the weak (surcharged) predefined callback
+  * @param hsram : SRAM handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
+  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
+  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SRAM_StateTypeDef state;
+
+  /* Process locked */
+  __HAL_LOCK(hsram);
+
+  state = hsram->State;
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SRAM_MSP_INIT_CB_ID :
+        hsram->MspInitCallback = HAL_SRAM_MspInit;
+        break;
+      case HAL_SRAM_MSP_DEINIT_CB_ID :
+        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+        break;
+      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+        hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+        break;
+      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+        hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (state == HAL_SRAM_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+      case HAL_SRAM_MSP_INIT_CB_ID :
+        hsram->MspInitCallback = HAL_SRAM_MspInit;
+        break;
+      case HAL_SRAM_MSP_DEINIT_CB_ID :
+        hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+  return status;
+}
+
+/**
+  * @brief  Register a User SRAM Callback for DMA transfers
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsram : SRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+                                               pSRAM_DmaCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SRAM_StateTypeDef state;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsram);
+
+  state = hsram->State;
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+        hsram->DmaXferCpltCallback = pCallback;
+        break;
+      case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+        hsram->DmaXferErrorCallback = pCallback;
+        break;
+      default :
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+  return status;
+}
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
+  *  @brief   Control functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### SRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the SRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically SRAM write operation.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
+{
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Enable write operation */
+    (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically SRAM write operation.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
+{
+  /* Check the SRAM controller state */
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Disable write operation */
+    (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### SRAM State functions #####
+  ==============================================================================
+  [..]
+    This subsection permits to get in run-time the status of the SRAM controller
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the SRAM controller state
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
+  *                the configuration information for SRAM module.
+  * @retval HAL state
+  */
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+{
+  return hsram->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA SRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
+{
+  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  hsram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
+{
+  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  hsram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SRAM_DMA_XferCpltCallback(hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SRAM error callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_ERROR;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  hsram->DmaXferErrorCallback(hdma);
+#else
+  HAL_SRAM_DMA_XferErrorCallback(hdma);
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* FMC_Bank1 || FSMC_Bank1 */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c
new file mode 100644
index 0000000..8172871
--- /dev/null
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c
@@ -0,0 +1,1062 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_fsmc.c
+  * @author  MCD Application Team
+  * @brief   FSMC Low Layer HAL module driver.
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### FSMC peripheral features #####
+  ==============================================================================
+  [..] The Flexible memory controller (FSMC) includes following memory controllers:
+       (+) The NOR/PSRAM memory controller
+       (+) The NAND/PC Card memory controller
+
+  [..] The FSMC functional block makes the interface with synchronous and asynchronous static
+       memories and 16-bit PC memory cards. Its main purposes are:
+       (+) to translate AHB transactions into the appropriate external device protocol
+       (+) to meet the access time requirements of the external memory devices
+
+  [..] All external memories share the addresses, data and control signals with the controller.
+       Each external device is accessed by means of a unique Chip Select. The FSMC performs
+       only one access at a time to an external device.
+       The main features of the FSMC controller are the following:
+        (+) Interface with static-memory mapped devices including:
+           (++) Static random access memory (SRAM)
+           (++) Read-only memory (ROM)
+           (++) NOR Flash memory/OneNAND Flash memory
+           (++) PSRAM (4 memory banks)
+           (++) 16-bit PC Card compatible devices
+           (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+                data
+        (+) Independent Chip Select control for each memory bank
+        (+) Independent configuration for each memory bank
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
+
+/** @defgroup FSMC_LL  FSMC Low Layer
+  * @brief FSMC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
+  * @{
+  */
+
+/* ----------------------- FSMC registers bit mask --------------------------- */
+
+#if defined(FSMC_Bank1)
+/* --- BCR Register ---*/
+/* BCR register clear mask */
+
+/* --- BTR Register ---*/
+/* BTR register clear mask */
+#define BTR_CLEAR_MASK    ((uint32_t)(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD  |\
+                                      FSMC_BTR1_DATAST | FSMC_BTR1_BUSTURN |\
+                                      FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT  |\
+                                      FSMC_BTR1_ACCMOD))
+
+/* --- BWTR Register ---*/
+/* BWTR register clear mask */
+#define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD  |\
+                                      FSMC_BWTR1_DATAST | FSMC_BWTR1_BUSTURN |\
+                                      FSMC_BWTR1_ACCMOD))
+#endif /* FSMC_Bank1 */
+#if defined(FSMC_Bank2_3)
+
+#if defined (FSMC_PCR_PWAITEN)
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCR_PWAITEN | FSMC_PCR_PBKEN  | \
+                                      FSMC_PCR_PTYP    | FSMC_PCR_PWID   | \
+                                      FSMC_PCR_ECCEN   | FSMC_PCR_TCLR   | \
+                                      FSMC_PCR_TAR     | FSMC_PCR_ECCPS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEM_MEMSET2  | FSMC_PMEM_MEMWAIT2 |\
+                                      FSMC_PMEM_MEMHOLD2 | FSMC_PMEM_MEMHIZ2))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATT_ATTSET2  | FSMC_PATT_ATTWAIT2 |\
+                                      FSMC_PATT_ATTHOLD2 | FSMC_PATT_ATTHIZ2))
+#else
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN  | \
+                                      FSMC_PCR2_PTYP    | FSMC_PCR2_PWID   | \
+                                      FSMC_PCR2_ECCEN   | FSMC_PCR2_TCLR   | \
+                                      FSMC_PCR2_TAR     | FSMC_PCR2_ECCPS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEM2_MEMSET2  | FSMC_PMEM2_MEMWAIT2 |\
+                                      FSMC_PMEM2_MEMHOLD2 | FSMC_PMEM2_MEMHIZ2))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATT2_ATTSET2  | FSMC_PATT2_ATTWAIT2 |\
+                                      FSMC_PATT2_ATTHOLD2 | FSMC_PATT2_ATTHIZ2))
+
+#endif /* FSMC_PCR_PWAITEN */
+#endif /* FSMC_Bank2_3 */
+#if defined(FSMC_Bank4)
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR4_CLEAR_MASK   ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN  | \
+                                      FSMC_PCR4_PTYP    | FSMC_PCR4_PWID   | \
+                                      FSMC_PCR4_ECCEN   | FSMC_PCR4_TCLR   | \
+                                      FSMC_PCR4_TAR     | FSMC_PCR4_ECCPS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM4_CLEAR_MASK  ((uint32_t)(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 |\
+                                      FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT4_CLEAR_MASK  ((uint32_t)(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 |\
+                                      FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
+
+/* --- PIO4 Register ---*/
+/* PIO4 register clear mask */
+#define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | \
+                                      FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
+
+#endif /* FSMC_Bank4 */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
+  * @{
+  */
+
+#if defined(FSMC_Bank1)
+
+/** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
+  * @brief  NORSRAM Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                   ##### How to use NORSRAM device driver #####
+  ==============================================================================
+
+  [..]
+    This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
+    to run the NORSRAM external devices.
+
+    (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
+    (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
+    (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
+    (+) FSMC NORSRAM bank extended timing configuration using the function
+        FSMC_NORSRAM_Extended_Timing_Init()
+    (+) FSMC NORSRAM bank enable/disable write operation using the functions
+        FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
+
+@endverbatim
+  * @{
+  */
+
+/** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+  @verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FSMC NORSRAM interface
+    (+) De-initialize the FSMC NORSRAM interface
+    (+) Configure the FSMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the FSMC_NORSRAM device according to the specified
+  *         control parameters in the FSMC_NORSRAM_InitTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Init Pointer to NORSRAM Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
+                                    FSMC_NORSRAM_InitTypeDef *Init)
+{
+  uint32_t flashaccess;
+  uint32_t btcr_reg;
+  uint32_t mask;
+
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
+  assert_param(IS_FSMC_MUX(Init->DataAddressMux));
+  assert_param(IS_FSMC_MEMORY(Init->MemoryType));
+  assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
+  assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
+#if defined(FSMC_BCR1_WRAPMOD)
+  assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
+#endif /* FSMC_BCR1_WRAPMOD */
+  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
+  assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
+  assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
+  assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
+  assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
+  assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
+#if defined(FSMC_BCR1_CCLKEN)
+  assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+#endif
+#if defined(FSMC_BCR1_WFDIS)
+  assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
+#endif /* FSMC_BCR1_WFDIS */
+  assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
+
+  /* Disable NORSRAM Device */
+  __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
+
+  /* Set NORSRAM device control parameters */
+  if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
+  {
+    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
+  }
+  else
+  {
+    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
+  }
+
+  btcr_reg = (flashaccess                   | \
+              Init->DataAddressMux          | \
+              Init->MemoryType              | \
+              Init->MemoryDataWidth         | \
+              Init->BurstAccessMode         | \
+              Init->WaitSignalPolarity      | \
+              Init->WaitSignalActive        | \
+              Init->WriteOperation          | \
+              Init->WaitSignal              | \
+              Init->ExtendedMode            | \
+              Init->AsynchronousWait        | \
+              Init->WriteBurst);
+
+#if defined(FSMC_BCR1_WRAPMOD)
+  btcr_reg |= Init->WrapMode;
+#endif /* FSMC_BCR1_WRAPMOD */
+#if defined(FSMC_BCR1_CCLKEN)
+  btcr_reg |= Init->ContinuousClock;
+#endif /* FSMC_BCR1_CCLKEN */
+#if defined(FSMC_BCR1_WFDIS)
+  btcr_reg |= Init->WriteFifo;
+#endif /* FSMC_BCR1_WFDIS */
+  btcr_reg |= Init->PageSize;
+
+  mask = (FSMC_BCR1_MBKEN                |
+          FSMC_BCR1_MUXEN                |
+          FSMC_BCR1_MTYP                 |
+          FSMC_BCR1_MWID                 |
+          FSMC_BCR1_FACCEN               |
+          FSMC_BCR1_BURSTEN              |
+          FSMC_BCR1_WAITPOL              |
+          FSMC_BCR1_WAITCFG              |
+          FSMC_BCR1_WREN                 |
+          FSMC_BCR1_WAITEN               |
+          FSMC_BCR1_EXTMOD               |
+          FSMC_BCR1_ASYNCWAIT            |
+          FSMC_BCR1_CBURSTRW);
+
+#if defined(FSMC_BCR1_WRAPMOD)
+  mask |= FSMC_BCR1_WRAPMOD;
+#endif /* FSMC_BCR1_WRAPMOD */
+#if defined(FSMC_BCR1_CCLKEN)
+  mask |= FSMC_BCR1_CCLKEN;
+#endif
+#if defined(FSMC_BCR1_WFDIS)
+  mask |= FSMC_BCR1_WFDIS;
+#endif /* FSMC_BCR1_WFDIS */
+  mask |= FSMC_BCR1_CPSIZE;
+
+  MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
+
+#if defined(FSMC_BCR1_CCLKEN)
+  /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
+  if ((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
+  {
+    MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock);
+  }
+#endif
+#if defined(FSMC_BCR1_WFDIS)
+
+  if (Init->NSBank != FSMC_NORSRAM_BANK1)
+  {
+    /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
+    SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
+  }
+#endif /* FSMC_BCR1_WFDIS */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the FSMC_NORSRAM peripheral
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  ExDevice Pointer to NORSRAM extended mode device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
+                                     FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+  /* Disable the FSMC_NORSRAM device */
+  __FSMC_NORSRAM_DISABLE(Device, Bank);
+
+  /* De-initialize the FSMC_NORSRAM device */
+  /* FSMC_NORSRAM_BANK1 */
+  if (Bank == FSMC_NORSRAM_BANK1)
+  {
+    Device->BTCR[Bank] = 0x000030DBU;
+  }
+  /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
+  else
+  {
+    Device->BTCR[Bank] = 0x000030D2U;
+  }
+
+  Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
+  ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
+  *         parameters in the FSMC_NORSRAM_TimingTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
+                                          FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+{
+#if defined(FSMC_BCR1_CCLKEN)
+  uint32_t tmpr;
+#endif
+
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+  assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
+  assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+  assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
+  assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
+  assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
+  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+  /* Set FSMC_NORSRAM device timing parameters */
+  MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
+                                                       ((Timing->AddressHoldTime)        << FSMC_BTR1_ADDHLD_Pos)  |
+                                                       ((Timing->DataSetupTime)          << FSMC_BTR1_DATAST_Pos)  |
+                                                       ((Timing->BusTurnAroundDuration)  << FSMC_BTR1_BUSTURN_Pos) |
+                                                       (((Timing->CLKDivision) - 1U)     << FSMC_BTR1_CLKDIV_Pos)  |
+                                                       (((Timing->DataLatency) - 2U)     << FSMC_BTR1_DATLAT_Pos)  |
+                                                       (Timing->AccessMode)));
+
+#if defined(FSMC_BCR1_CCLKEN)
+  /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
+  if (HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
+  {
+    tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FSMC_BTR1_CLKDIV_Pos));
+    tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos);
+    MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U], FSMC_BTR1_CLKDIV, tmpr);
+  }
+
+#endif
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
+  *         parameters in the FSMC_NORSRAM_TimingTypeDef
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
+  * @param  ExtendedMode FSMC Extended Mode
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_EXTENDED_MODE_DISABLE
+  *            @arg FSMC_EXTENDED_MODE_ENABLE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
+                                                   FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
+                                                   uint32_t ExtendedMode)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
+
+  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+  if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
+  {
+    /* Check the parameters */
+    assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
+    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
+    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
+    assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
+    assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
+    assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
+    assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+    /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
+                                                     ((Timing->AddressHoldTime)        << FSMC_BWTR1_ADDHLD_Pos)  |
+                                                     ((Timing->DataSetupTime)          << FSMC_BWTR1_DATAST_Pos)  |
+                                                     Timing->AccessMode                                          |
+                                                     ((Timing->BusTurnAroundDuration)  << FSMC_BWTR1_BUSTURN_Pos)));
+  }
+  else
+  {
+    Device->BWTR[Bank] = 0x0FFFFFFFU;
+  }
+
+  return HAL_OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### FSMC_NORSRAM Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FSMC NORSRAM interface.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables dynamically FSMC_NORSRAM write operation.
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+  /* Enable write operation */
+  SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FSMC_NORSRAM write operation.
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+  /* Disable write operation */
+  CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* FSMC_Bank1 */
+
+#if defined(FSMC_Bank2_3)
+
+/** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
+  * @brief    NAND Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use NAND device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FSMC NAND banks in order
+    to run the NAND external devices.
+
+    (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
+    (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
+    (+) FSMC NAND bank common space timing configuration using the function
+        FSMC_NAND_CommonSpace_Timing_Init()
+    (+) FSMC NAND bank attribute space timing configuration using the function
+        FSMC_NAND_AttributeSpace_Timing_Init()
+    (+) FSMC NAND bank enable/disable ECC correction feature using the functions
+        FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
+    (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
+
+@endverbatim
+  * @{
+  */
+
+/** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FSMC NAND interface
+    (+) De-initialize the FSMC NAND interface
+    (+) Configure the FSMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FSMC_NAND device according to the specified
+  *         control parameters in the FSMC_NAND_HandleTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Init Pointer to NAND Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
+  assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
+  assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
+  assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
+  assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
+
+  /* Set NAND device control parameters */
+  if (Init->NandBank == FSMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
+                                              FSMC_PCR_MEMORY_TYPE_NAND                               |
+                                              Init->MemoryDataWidth                                  |
+                                              Init->EccComputation                                   |
+                                              Init->ECCPageSize                                      |
+                                              ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) |
+                                              ((Init->TARSetupTime)  << FSMC_PCR2_TAR_Pos)));
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
+                                              FSMC_PCR_MEMORY_TYPE_NAND                               |
+                                              Init->MemoryDataWidth                                  |
+                                              Init->EccComputation                                   |
+                                              Init->ECCPageSize                                      |
+                                              ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos)  |
+                                              ((Init->TARSetupTime)  << FSMC_PCR2_TAR_Pos)));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
+                                                   FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
+  /* Set FSMC_NAND device timing parameters */
+  if (Bank == FSMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) |
+                                                ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) |
+                                                ((Timing->HiZSetupTime)  << FSMC_PMEM2_MEMHIZ2_Pos)));
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) |
+                                                ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) |
+                                                ((Timing->HiZSetupTime)  << FSMC_PMEM2_MEMHIZ2_Pos)));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
+                                                      FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
+  /* Set FSMC_NAND device timing parameters */
+  if (Bank == FSMC_NAND_BANK2)
+  {
+    /* NAND bank 2 registers configuration */
+    MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) |
+                                                ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) |
+                                                ((Timing->HiZSetupTime)  << FSMC_PATT2_ATTHIZ2_Pos)));
+  }
+  else
+  {
+    /* NAND bank 3 registers configuration */
+    MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) |
+                                                ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) |
+                                                ((Timing->HiZSetupTime)  << FSMC_PATT2_ATTHIZ2_Pos)));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the FSMC_NAND device
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
+  /* Disable the NAND Bank */
+  __FSMC_NAND_DISABLE(Device, Bank);
+
+  /* De-initialize the NAND Bank */
+  if (Bank == FSMC_NAND_BANK2)
+  {
+    /* Set the FSMC_NAND_BANK2 registers to their reset values */
+    WRITE_REG(Device->PCR2,  0x00000018U);
+    WRITE_REG(Device->SR2,   0x00000040U);
+    WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
+    WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
+  }
+  /* FSMC_Bank3_NAND */
+  else
+  {
+    /* Set the FSMC_NAND_BANK3 registers to their reset values */
+    WRITE_REG(Device->PCR3,  0x00000018U);
+    WRITE_REG(Device->SR3,   0x00000040U);
+    WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
+    WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
+  *  @brief   management functions
+  *
+@verbatim
+  ==============================================================================
+                       ##### FSMC_NAND Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control dynamically
+    the FSMC NAND interface.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Enables dynamically FSMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
+  /* Enable ECC feature */
+  if (Bank == FSMC_NAND_BANK2)
+  {
+    SET_BIT(Device->PCR2, FSMC_PCR2_ECCEN);
+  }
+  else
+  {
+    SET_BIT(Device->PCR3, FSMC_PCR2_ECCEN);
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Disables dynamically FSMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
+  /* Disable ECC feature */
+  if (Bank == FSMC_NAND_BANK2)
+  {
+    CLEAR_BIT(Device->PCR2, FSMC_PCR2_ECCEN);
+  }
+  else
+  {
+    CLEAR_BIT(Device->PCR3, FSMC_PCR2_ECCEN);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables dynamically FSMC_NAND ECC feature.
+  * @param  Device Pointer to NAND device instance
+  * @param  ECCval Pointer to ECC value
+  * @param  Bank NAND bank number
+  * @param  Timeout Timeout wait value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+                                  uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait until FIFO is empty */
+  while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  if (Bank == FSMC_NAND_BANK2)
+  {
+    /* Get the ECCR2 register value */
+    *ECCval = (uint32_t)Device->ECCR2;
+  }
+  else
+  {
+    /* Get the ECCR3 register value */
+    *ECCval = (uint32_t)Device->ECCR3;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+#endif /* FSMC_Bank2_3 */
+
+#if defined(FSMC_Bank4)
+
+/** @addtogroup FSMC_LL_PCCARD
+  * @brief    PCCARD Controller functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### How to use PCCARD device driver #####
+  ==============================================================================
+  [..]
+    This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
+    to run the PCCARD/compact flash external devices.
+
+    (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
+    (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
+    (+) FSMC PCCARD bank common space timing configuration using the function
+        FSMC_PCCARD_CommonSpace_Timing_Init()
+    (+) FSMC PCCARD bank attribute space timing configuration using the function
+        FSMC_PCCARD_AttributeSpace_Timing_Init()
+    (+) FSMC PCCARD bank IO space timing configuration using the function
+        FSMC_PCCARD_IOSpace_Timing_Init()
+@endverbatim
+  * @{
+  */
+
+/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de_initialization functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the FSMC PCCARD interface
+    (+) De-initialize the FSMC PCCARD interface
+    (+) Configure the FSMC clock and associated GPIOs
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the FSMC_PCCARD device according to the specified
+  *         control parameters in the FSMC_PCCARD_HandleTypeDef
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Init Pointer to PCCARD Initialization structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
+#if defined(FSMC_Bank2_3)
+  assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
+  assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
+  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
+#endif /* FSMC_Bank2_3 */
+
+  /* Set FSMC_PCCARD device control parameters */
+  MODIFY_REG(Device->PCR4,
+             (FSMC_PCR4_PTYP                                          |
+              FSMC_PCR4_PWAITEN                                       |
+              FSMC_PCR4_PWID                                          |
+              FSMC_PCR4_TCLR                                          |
+              FSMC_PCR4_TAR),
+             (FSMC_PCR_MEMORY_TYPE_PCCARD                             |
+              Init->Waitfeature                                      |
+              FSMC_NAND_PCC_MEM_BUS_WIDTH_16                          |
+              (Init->TCLRSetupTime << FSMC_PCR4_TCLR_Pos)   |
+              (Init->TARSetupTime  << FSMC_PCR4_TAR_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Timing Pointer to PCCARD timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
+                                                              FSMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
+#if defined(FSMC_Bank2_3)
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+#endif /* FSMC_Bank2_3 */
+
+  /* Set PCCARD timing parameters */
+  MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,
+             (Timing->SetupTime                                              |
+              ((Timing->WaitSetupTime) << FSMC_PMEM4_MEMWAIT4_Pos)  |
+              ((Timing->HoldSetupTime) << FSMC_PMEM4_MEMHOLD4_Pos)  |
+              ((Timing->HiZSetupTime)  << FSMC_PMEM4_MEMHIZ4_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Timing Pointer to PCCARD timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
+                                                                 FSMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
+#if defined(FSMC_Bank2_3)
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+#endif /* FSMC_Bank2_3 */
+
+  /* Set PCCARD timing parameters */
+  MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,
+             (Timing->SetupTime                                              |
+              ((Timing->WaitSetupTime) << FSMC_PATT4_ATTWAIT4_Pos)  |
+              ((Timing->HoldSetupTime) << FSMC_PATT4_ATTHOLD4_Pos)  |
+              ((Timing->HiZSetupTime)  << FSMC_PATT4_ATTHIZ4_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
+  *         parameters in the FSMC_NAND_PCC_TimingTypeDef
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Timing Pointer to PCCARD timing structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
+                                                          FSMC_NAND_PCC_TimingTypeDef *Timing)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
+#if defined(FSMC_Bank2_3)
+  assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
+#endif /* FSMC_Bank2_3 */
+
+  /* Set FSMC_PCCARD device timing parameters */
+  MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
+             (Timing->SetupTime                                           |
+              (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) |
+              (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) |
+              (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the FSMC_PCCARD device
+  * @param  Device Pointer to PCCARD device instance
+  * @retval HAL status
+  */
+HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
+
+  /* Disable the FSMC_PCCARD device */
+  __FSMC_PCCARD_DISABLE(Device);
+
+  /* De-initialize the FSMC_PCCARD device */
+  Device->PCR4    = 0x00000018U;
+  Device->SR4     = 0x00000040U;
+  Device->PMEM4   = 0xFCFCFCFCU;
+  Device->PATT4   = 0xFCFCFCFCU;
+  Device->PIO4    = 0xFCFCFCFCU;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+#endif /* FSMC_Bank4 */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_NOR_MODULE_ENABLED */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
diff --git a/MDK-ARM/valve_debugging.uvoptx b/MDK-ARM/valve_debugging.uvoptx
index 305ceac..0cf10b8 100644
--- a/MDK-ARM/valve_debugging.uvoptx
+++ b/MDK-ARM/valve_debugging.uvoptx
@@ -149,6 +149,29 @@
         </SetRegEntry>
       </TargetDriverDllRegistry>
       <Breakpoint/>
+      <WatchWindow1>
+        <Ww>
+          <count>0</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>reg_data</ItemText>
+        </Ww>
+      </WatchWindow1>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>0x60000000</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow1>
+      <MemoryWindow2>
+        <Mm>
+          <WinNumber>2</WinNumber>
+          <SubType>0</SubType>
+          <ItemText>pAddress</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow2>
       <Tracepoint>
         <THDelay>0</THDelay>
       </Tracepoint>
@@ -157,7 +180,7 @@
         <periodic>1</periodic>
         <aLwin>1</aLwin>
         <aCover>0</aCover>
-        <aSer1>0</aSer1>
+        <aSer1>1</aSer1>
         <aSer2>0</aSer2>
         <aPa>0</aPa>
         <viewmode>1</viewmode>
@@ -270,6 +293,18 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
+      <PathWithFileName>../Core/Src/fsmc.c</PathWithFileName>
+      <FilenameWithoutPath>fsmc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
       <PathWithFileName>../Core/Src/spi.c</PathWithFileName>
       <FilenameWithoutPath>spi.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
@@ -277,7 +312,7 @@
     </File>
     <File>
       <GroupNumber>2</GroupNumber>
-      <FileNumber>6</FileNumber>
+      <FileNumber>7</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -289,7 +324,7 @@
     </File>
     <File>
       <GroupNumber>2</GroupNumber>
-      <FileNumber>7</FileNumber>
+      <FileNumber>8</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -301,7 +336,7 @@
     </File>
     <File>
       <GroupNumber>2</GroupNumber>
-      <FileNumber>8</FileNumber>
+      <FileNumber>9</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -313,7 +348,7 @@
     </File>
     <File>
       <GroupNumber>2</GroupNumber>
-      <FileNumber>9</FileNumber>
+      <FileNumber>10</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -333,7 +368,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>10</FileNumber>
+      <FileNumber>11</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -345,7 +380,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>11</FileNumber>
+      <FileNumber>12</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -357,7 +392,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>12</FileNumber>
+      <FileNumber>13</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -369,7 +404,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>13</FileNumber>
+      <FileNumber>14</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -381,7 +416,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>14</FileNumber>
+      <FileNumber>15</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -393,7 +428,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>15</FileNumber>
+      <FileNumber>16</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -405,7 +440,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>16</FileNumber>
+      <FileNumber>17</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -417,7 +452,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>17</FileNumber>
+      <FileNumber>18</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -429,7 +464,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>18</FileNumber>
+      <FileNumber>19</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -441,7 +476,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>19</FileNumber>
+      <FileNumber>20</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -453,7 +488,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>20</FileNumber>
+      <FileNumber>21</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -465,7 +500,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>21</FileNumber>
+      <FileNumber>22</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -477,7 +512,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>22</FileNumber>
+      <FileNumber>23</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -489,7 +524,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>23</FileNumber>
+      <FileNumber>24</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -501,7 +536,31 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>24</FileNumber>
+      <FileNumber>25</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c</PathWithFileName>
+      <FilenameWithoutPath>stm32f4xx_ll_fsmc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>26</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c</PathWithFileName>
+      <FilenameWithoutPath>stm32f4xx_hal_sram.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>27</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -513,7 +572,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>25</FileNumber>
+      <FileNumber>28</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -525,7 +584,7 @@
     </File>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>26</FileNumber>
+      <FileNumber>29</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -545,7 +604,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>4</GroupNumber>
-      <FileNumber>27</FileNumber>
+      <FileNumber>30</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -565,7 +624,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>28</FileNumber>
+      <FileNumber>31</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -585,7 +644,7 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>29</FileNumber>
+      <FileNumber>32</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
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@@ -605,7 +664,7 @@
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+      <FileNumber>33</FileNumber>
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       <tvExpOptDlg>0</tvExpOptDlg>
@@ -625,7 +684,7 @@
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+      <FileNumber>34</FileNumber>
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@@ -637,7 +696,7 @@
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@@ -649,7 +708,7 @@
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@@ -661,7 +720,7 @@
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@@ -673,7 +732,7 @@
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@@ -685,7 +744,7 @@
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@@ -697,7 +756,7 @@
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@@ -709,7 +768,7 @@
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@@ -721,7 +780,7 @@
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@@ -733,7 +792,7 @@
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@@ -753,7 +812,7 @@
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@@ -765,7 +824,7 @@
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@@ -777,7 +836,7 @@
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@@ -789,7 +848,7 @@
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@@ -801,7 +860,7 @@
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@@ -813,7 +872,7 @@
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@@ -825,7 +884,7 @@
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@@ -837,7 +896,7 @@
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@@ -849,7 +908,7 @@
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@@ -861,7 +920,7 @@
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@@ -873,7 +932,7 @@
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@@ -885,7 +944,7 @@
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@@ -897,7 +956,7 @@
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@@ -909,7 +968,7 @@
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@@ -921,7 +980,7 @@
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@@ -933,7 +992,7 @@
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@@ -945,7 +1004,7 @@
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@@ -957,7 +1016,7 @@
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@@ -969,7 +1028,7 @@
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@@ -981,7 +1040,7 @@
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@@ -993,7 +1052,7 @@
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@@ -1005,7 +1064,7 @@
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@@ -1017,7 +1076,7 @@
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@@ -1029,7 +1088,7 @@
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@@ -1041,7 +1100,7 @@
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@@ -1065,7 +1124,7 @@
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@@ -1125,7 +1184,7 @@
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@@ -1149,7 +1208,7 @@
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@@ -1161,7 +1220,7 @@
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@@ -1425,7 +1484,7 @@
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@@ -1437,7 +1496,7 @@
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@@ -1509,7 +1568,7 @@
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@@ -1533,7 +1592,7 @@
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+      <FileNumber>111</FileNumber>
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       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1569,7 +1628,7 @@
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     <File>
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-      <FileNumber>109</FileNumber>
+      <FileNumber>112</FileNumber>
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       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1581,7 +1640,7 @@
     </File>
     <File>
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-      <FileNumber>110</FileNumber>
+      <FileNumber>113</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1593,7 +1652,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>111</FileNumber>
+      <FileNumber>114</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1605,7 +1664,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>112</FileNumber>
+      <FileNumber>115</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1617,7 +1676,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>113</FileNumber>
+      <FileNumber>116</FileNumber>
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       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1629,7 +1688,7 @@
     </File>
     <File>
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-      <FileNumber>114</FileNumber>
+      <FileNumber>117</FileNumber>
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       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1641,7 +1700,7 @@
     </File>
     <File>
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-      <FileNumber>115</FileNumber>
+      <FileNumber>118</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1653,7 +1712,7 @@
     </File>
     <File>
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-      <FileNumber>116</FileNumber>
+      <FileNumber>119</FileNumber>
       <FileType>1</FileType>
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       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1665,7 +1724,7 @@
     </File>
     <File>
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-      <FileNumber>117</FileNumber>
+      <FileNumber>120</FileNumber>
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       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1677,7 +1736,7 @@
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     <File>
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-      <FileNumber>118</FileNumber>
+      <FileNumber>121</FileNumber>
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@@ -1689,7 +1748,7 @@
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     <File>
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+      <FileNumber>122</FileNumber>
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       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1701,7 +1760,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>120</FileNumber>
+      <FileNumber>123</FileNumber>
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       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1713,7 +1772,7 @@
     </File>
     <File>
       <GroupNumber>9</GroupNumber>
-      <FileNumber>121</FileNumber>
+      <FileNumber>124</FileNumber>
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       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1733,9 +1792,9 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>10</GroupNumber>
-      <FileNumber>122</FileNumber>
+      <FileNumber>125</FileNumber>
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-      <tvExp>1</tvExp>
+      <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
       <PathWithFileName>..\User\driver\dac161s997.c</PathWithFileName>
@@ -1743,6 +1802,18 @@
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
+    <File>
+      <GroupNumber>10</GroupNumber>
+      <FileNumber>126</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>1</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\User\driver\ch438q.c</PathWithFileName>
+      <FilenameWithoutPath>ch438q.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
   </Group>
 
   <Group>
@@ -1753,9 +1824,9 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>11</GroupNumber>
-      <FileNumber>123</FileNumber>
+      <FileNumber>127</FileNumber>
       <FileType>1</FileType>
-      <tvExp>1</tvExp>
+      <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
       <PathWithFileName>..\User\system\user_spi.c</PathWithFileName>
diff --git a/MDK-ARM/valve_debugging.uvprojx b/MDK-ARM/valve_debugging.uvprojx
index aef13af..6fc3d79 100644
--- a/MDK-ARM/valve_debugging.uvprojx
+++ b/MDK-ARM/valve_debugging.uvprojx
@@ -54,7 +54,7 @@
           <CreateLib>0</CreateLib>
           <CreateHexFile>1</CreateHexFile>
           <DebugInformation>1</DebugInformation>
-          <BrowseInformation>0</BrowseInformation>
+          <BrowseInformation>1</BrowseInformation>
           <ListingPath></ListingPath>
           <HexFormatSelection>1</HexFormatSelection>
           <Merge32K>0</Merge32K>
@@ -339,7 +339,7 @@
               <MiscControls></MiscControls>
               <Define>USE_HAL_DRIVER,STM32F407xx</Define>
               <Undefine></Undefine>
-              <IncludePath>../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../LWIP/App;../LWIP/Target;../Middlewares/Third_Party/LwIP/src/include;../Middlewares/Third_Party/LwIP/system;../Middlewares/Third_Party/FreeRTOS/Source/include;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F;../Drivers/BSP/Components/lan8742;../Middlewares/Third_Party/LwIP/src/include/netif/ppp;../Middlewares/Third_Party/LwIP/src/include/lwip;../Middlewares/Third_Party/LwIP/src/include/lwip/apps;../Middlewares/Third_Party/LwIP/src/include/lwip/priv;../Middlewares/Third_Party/LwIP/src/include/lwip/prot;../Middlewares/Third_Party/LwIP/src/include/netif;../Middlewares/Third_Party/LwIP/src/include/compat/posix;../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa;../Middlewares/Third_Party/LwIP/src/include/compat/posix/net;../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys;../Middlewares/Third_Party/LwIP/src/include/compat/stdc;../Middlewares/Third_Party/LwIP/system/arch;..\User\driver;..\User\system</IncludePath>
+              <IncludePath>../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../LWIP/App;../LWIP/Target;../Middlewares/Third_Party/LwIP/src/include;../Middlewares/Third_Party/LwIP/system;../Middlewares/Third_Party/FreeRTOS/Source/include;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS;../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F;../Drivers/BSP/Components/lan8742;../Middlewares/Third_Party/LwIP/src/include/netif/ppp;../Middlewares/Third_Party/LwIP/src/include/lwip;../Middlewares/Third_Party/LwIP/src/include/lwip/apps;../Middlewares/Third_Party/LwIP/src/include/lwip/priv;../Middlewares/Third_Party/LwIP/src/include/lwip/prot;../Middlewares/Third_Party/LwIP/src/include/netif;../Middlewares/Third_Party/LwIP/src/include/compat/posix;../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa;../Middlewares/Third_Party/LwIP/src/include/compat/posix/net;../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys;../Middlewares/Third_Party/LwIP/src/include/compat/stdc;../Middlewares/Third_Party/LwIP/system/arch;../User/driver;../User/system</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -459,6 +459,62 @@
                 </FileArmAds>
               </FileOption>
             </File>
+            <File>
+              <FileName>fsmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Core/Src/fsmc.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
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+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
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+                  <ComprImg>1</ComprImg>
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             <File>
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               <FileType>1</FileType>
@@ -712,6 +768,118 @@
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+              <FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c</FilePath>
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+              <FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c</FilePath>
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             <File>
               <FileName>stm32f4xx_hal_spi.c</FileName>
               <FileType>1</FileType>
@@ -6432,6 +6600,11 @@
               <FileType>1</FileType>
               <FilePath>..\User\driver\dac161s997.c</FilePath>
             </File>
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+              <FileType>1</FileType>
+              <FilePath>..\User\driver\ch438q.c</FilePath>
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           </Files>
         </Group>
         <Group>
diff --git a/MDK-ARM/valve_debugging/valve_debugging.hex b/MDK-ARM/valve_debugging/valve_debugging.hex
index bf95e10..a3f3429 100644
--- a/MDK-ARM/valve_debugging/valve_debugging.hex
+++ b/MDK-ARM/valve_debugging/valve_debugging.hex
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diff --git a/User/driver/ch438q.c b/User/driver/ch438q.c
new file mode 100644
index 0000000..8af2a31
--- /dev/null
+++ b/User/driver/ch438q.c
@@ -0,0 +1,59 @@
+#include "ch438q.h"
+#include "fsmc.h"
+
+const uint8_t offsetadd[] = {
+    0x00,
+    0x10,
+    0x20,
+    0x30,
+    0x08,
+    0x18,
+    0x28,
+    0x38,
+}; /* 串口号的偏移地址 */
+const uint8_t Interruptnum[] = {
+    0x01,
+    0x02,
+    0x04,
+    0x08,
+    0x10,
+    0x20,
+    0x40,
+    0x80,
+}; /* SSR寄存器中断号对应值 */
+// static uint32_t address = 0x68000000;
+// uint32_t data = 0;
+// uint32_t data1 = 0;
+// for(int i = 0;i < 1024;i++,data++)
+// {
+//     HAL_SRAM_Write_32b(&hsram1,&address ,&data,4);
+//     HAL_SRAM_Read_32b(&hsram1,&address ,&data1,4);
+//     address = 4*i;
+// }
+
+void ch438_write_reg(uint8_t addr, uint8_t data, uint8_t size)
+{
+    uint32_t *address = (uint32_t *)(0x60000000 + addr);
+    HAL_SRAM_Write_8b(&hsram1, address, &data, size);
+}
+
+uint8_t ch438_read_reg(uint8_t addr, uint8_t size)
+{
+    uint8_t data = 0;
+    uint32_t *address = (uint32_t *)(0x60000000 + addr);
+    HAL_SRAM_Read_8b(&hsram1, address, &data, size);
+    return data;
+}
+
+void ch438_test(void)
+{
+    uint8_t reg_data[16] = {0};
+    reg_data[0] = 0xAA;
+    ch438_write_reg(offsetadd[0] | REG_SCR_ADDR, reg_data[0], 1);
+
+    reg_data[1] = ch438_read_reg(offsetadd[0] | REG_SCR_ADDR, 1);
+
+    reg_data[2] = ch438_read_reg(offsetadd[0] | REG_IER_ADDR, 1);
+    reg_data[3] = ch438_read_reg(offsetadd[0] | REG_IIR_ADDR, 1);
+    reg_data[4] = ch438_read_reg(offsetadd[0] | REG_LSR_ADDR, 1);
+}
diff --git a/User/driver/ch438q.h b/User/driver/ch438q.h
new file mode 100644
index 0000000..07a250e
--- /dev/null
+++ b/User/driver/ch438q.h
@@ -0,0 +1,106 @@
+#ifndef __CH438Q_H__
+#define __CH438Q_H__
+
+#include "fsmc.h"
+
+/* CH438串口寄存器地址 */
+#define REG_RBR_ADDR 0x00 /* 串口0接收缓冲寄存器地址 */
+#define REG_THR_ADDR 0x00 /* 串口0发送保持寄存器地址 */
+#define REG_IER_ADDR 0x01 /* 串口0中断使能寄存器地址 */
+#define REG_IIR_ADDR 0x02 /* 串口0中断识别寄存器地址 */
+#define REG_FCR_ADDR 0x02 /* 串口0FIFO控制寄存器地址 */
+#define REG_LCR_ADDR 0x03 /* 串口0线路控制寄存器地址 */
+#define REG_MCR_ADDR 0x04 /* 串口0MODEM控制寄存器地址 */
+#define REG_LSR_ADDR 0x05 /* 串口0线路状态寄存器地址 */
+#define REG_MSR_ADDR 0x06 /* 串口0MODEM状态寄存器地址 */
+#define REG_SCR_ADDR 0x07 /* 串口0用户可定义寄存器地址 */
+#define REG_DLL_ADDR 0x00 /* 波特率除数锁存器低8位字节地址 */
+#define REG_DLM_ADDR 0x01 /* 波特率除数锁存器高8位字节地址 */
+
+/* CH438内部串口0~7 专用状态寄存器 */
+#define REG_SSR_ADDR 0x4F /* 专用状态寄存器地址 */
+
+/* IIR寄存器的位 */
+
+#define BIT_IIR_FIFOENS1 0x80
+#define BIT_IIR_FIFOENS0 0x40 /* 该2位为1表示起用FIFO */
+
+/* 中断类型：0001没有中断，0110接收线路状态中断，0100接收数据可用中断，1100接收数据超时中断，0010THR寄存器空中断，0000MODEM输入变化中断 */
+#define BIT_IIR_IID3 0x08
+#define BIT_IIR_IID2 0x04 // 接受数据可用
+#define BIT_IIR_IID1 0x02 // THR寄存器空中断
+#define BIT_IIR_NOINT 0x01
+
+/* FCR寄存器的位 */
+
+/* 触发点： 00对应1个字节，01对应16个字节，10对应64个字节，11对应112个字节 */
+#define BIT_FCR_RECVTG1 0x80 /* 设置FIFO的中断和自动硬件流控制的触发点 */
+#define BIT_FCR_RECVTG0 0x40 /* 设置FIFO的中断和自动硬件流控制的触发点 */
+
+#define BIT_FCR_TFIFORST 0x04 /* 该位置1则清空发送FIFO中的数据 */
+#define BIT_FCR_RFIFORST 0x02 /* 该位置1则清空接收FIFO中的数据 */
+#define BIT_FCR_FIFOEN 0x01   /* 该位置1则起用FIFO,为0则禁用FIFO */
+
+/* LCR寄存器的位 */
+
+#define BIT_LCR_DLAB 0x80    /* 为1才能存取DLL，DLM，为0才能存取RBR/THR/IER */
+#define BIT_LCR_BREAKEN 0x40 /* 为1则强制产生BREAK线路间隔*/
+
+/* 设置校验格式：当PAREN为1时，00奇校验，01偶校验，10标志位（MARK，置1)，11空白位（SPACE，清0) */
+#define BIT_LCR_PARMODE1 0x20 /* 设置奇偶校验位格式 */
+#define BIT_LCR_PARMODE0 0x10 /* 设置奇偶校验位格式 */
+
+#define BIT_LCR_PAREN 0x08   /* 为1则允许发送时产生和接收校验奇偶校验位 */
+#define BIT_LCR_STOPBIT 0x04 /* 为1则两个停止位,为0一个停止位 */
+
+/* 设置字长度：00则5个数据位，01则6个数据位，10则7个数据位，11则8个数据位 */
+#define BIT_LCR_WORDSZ1 0x02 /* 设置字长长度 */
+#define BIT_LCR_WORDSZ0 0x01
+
+/* MCR寄存器的位 */
+
+#define BIT_MCR_AFE 0x20  /* 为1允许CTS和RTS硬件自动流控制 */
+#define BIT_MCR_LOOP 0x10 /* 为1使能内部回路的测试模式 */
+#define BIT_MCR_OUT2 0x08 /* 为1允许该串口的中断请求输出 */
+#define BIT_MCR_OUT1 0x04 /* 为用户定义的MODEM控制位 */
+#define BIT_MCR_RTS 0x02  /* 该位为1则RTS引脚输出有效 */
+#define BIT_MCR_DTR 0x01  /* 该位为1则DTR引脚输出有效 */
+
+/* LSR寄存器的位 */
+
+#define BIT_LSR_RFIFOERR 0x80 /* 为1表示在接收FIFO中存在至少一个错误 */
+#define BIT_LSR_TEMT 0x40     /* 为1表示THR和TSR全空 */
+#define BIT_LSR_THRE 0x20     /* 为1表示THR空*/
+#define BIT_LSR_BREAKINT 0x10 /* 该位为1表示检测到BREAK线路间隔 */
+#define BIT_LSR_FRAMEERR 0x08 /* 该位为1表示读取数据帧错误 */
+#define BIT_LSR_PARERR 0x04   /* 该位为1表示奇偶校验错误 */
+#define BIT_LSR_OVERR 0x02    /* 为1表示接收FIFO缓冲区溢出 */
+#define BIT_LSR_DATARDY 0x01  /* 该位为1表示接收FIFO中有接收到的数据 */
+
+/* MSR寄存器的位 */
+
+#define BIT_MSR_DCD 0x80  /* 该位为1表示DCD引脚有效 */
+#define BIT_MSR_RI 0x40   /* 该位为1表示RI引脚有效 */
+#define BIT_MSR_DSR 0x20  /* 该位为1表示DSR引脚有效 */
+#define BIT_MSR_CTS 0x10  /* 该位为1表示CTS引脚有效 */
+#define BIT_MSR_DDCD 0x08 /* 该位为1表示DCD引脚输入状态发生变化过 */
+#define BIT_MSR_TERI 0x04 /* 该位为1表示RI引脚输入状态发生变化过 */
+#define BIT_MSR_DDSR 0x02 /* 该位为1表示DSR引脚输入状态发生变化过 */
+#define BIT_MSR_DCTS 0x01 /* 该位为1表示CTS引脚输入状态发生变化过 */
+
+/* 中断状态码 */
+
+#define INT_NOINT 0x01        /* 没有中断 */
+#define INT_THR_EMPTY 0x02    /* THR空中断 */
+#define INT_RCV_OVERTIME 0x0C /* 接收超时中断 */
+#define INT_RCV_SUCCESS 0x04  /* 接收数据可用中断 */
+#define INT_RCV_LINES 0x06    /* 接收线路状态中断 */
+#define INT_MODEM_CHANGE 0x00 /* MODEM输入变化中断 */
+
+#define CH438_IIR_FIFOS_ENABLED 0xC0 /* 起用FIFO */
+
+void ch438_write_reg(uint8_t addr, uint8_t data, uint8_t size);
+uint8_t ch438_read_reg(uint8_t addr, uint8_t size);
+void ch438_test(void);
+
+#endif
diff --git a/User/system/user_fmsc.c b/User/system/user_fmsc.c
new file mode 100644
index 0000000..e69de29
diff --git a/User/system/user_fmsc.h b/User/system/user_fmsc.h
new file mode 100644
index 0000000..e69de29
diff --git a/valve_debugging.ioc b/valve_debugging.ioc
index 44eaca3..ba57119 100644
--- a/valve_debugging.ioc
+++ b/valve_debugging.ioc
@@ -9,10 +9,16 @@ ETH.RxBuffLen=1536
 ETH.RxMode=ETH_RXINTERRUPT_MODE
 FREERTOS.FootprintOK=true
 FREERTOS.IPParameters=Tasks01,configENABLE_FPU,configMAX_PRIORITIES,configMAX_TASK_NAME_LEN,FootprintOK
-FREERTOS.Tasks01=lwip_task,0,512,start_lwip_task,Default,NULL,Dynamic,NULL,NULL;dac_task,-3,512,start_dac_task,Default,NULL,Dynamic,NULL,NULL
+FREERTOS.Tasks01=lwip_task,0,512,start_lwip_task,Default,NULL,Dynamic,NULL,NULL;dac_task,-3,512,start_dac_task,Default,NULL,Dynamic,NULL,NULL;ch438_task,2,512,start_ch438_task,Default,NULL,Dynamic,NULL,NULL
 FREERTOS.configENABLE_FPU=1
 FREERTOS.configMAX_PRIORITIES=32
 FREERTOS.configMAX_TASK_NAME_LEN=24
+FSMC.DataSetupTime1=10
+FSMC.DataSetupTime2=10
+FSMC.ExtendedMode1=FSMC_EXTENDED_MODE_DISABLE
+FSMC.IPParameters=ExtendedMode1,DataSetupTime2,DataSetupTime1,WriteOperation1,WriteOperation2
+FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE
+FSMC.WriteOperation2=FSMC_WRITE_OPERATION_ENABLE
 File.Version=6
 GPIO.groupedBy=Group By Peripherals
 KeepUserPlacement=false
@@ -37,42 +43,61 @@ Mcu.CPN=STM32F407ZGT6
 Mcu.Family=STM32F4
 Mcu.IP0=ETH
 Mcu.IP1=FREERTOS
-Mcu.IP2=LWIP
-Mcu.IP3=NVIC
-Mcu.IP4=RCC
-Mcu.IP5=SPI1
-Mcu.IP6=SYS
-Mcu.IP7=TIM2
-Mcu.IPNb=8
+Mcu.IP2=FSMC
+Mcu.IP3=LWIP
+Mcu.IP4=NVIC
+Mcu.IP5=RCC
+Mcu.IP6=SPI1
+Mcu.IP7=SYS
+Mcu.IP8=TIM2
+Mcu.IPNb=9
 Mcu.Name=STM32F407Z(E-G)Tx
 Mcu.Package=LQFP144
 Mcu.Pin0=PE5
-Mcu.Pin1=PH0-OSC_IN
-Mcu.Pin10=PC5
-Mcu.Pin11=PF14
-Mcu.Pin12=PB11
-Mcu.Pin13=PB12
-Mcu.Pin14=PB13
-Mcu.Pin15=PG4
-Mcu.Pin16=PA13
-Mcu.Pin17=PA14
-Mcu.Pin18=PD3
-Mcu.Pin19=PB3
-Mcu.Pin2=PH1-OSC_OUT
-Mcu.Pin20=PB4
-Mcu.Pin21=PB5
-Mcu.Pin22=PB6
-Mcu.Pin23=VP_FREERTOS_VS_CMSIS_V1
-Mcu.Pin24=VP_LWIP_VS_Enabled
-Mcu.Pin25=VP_SYS_VS_tim4
-Mcu.Pin3=PC1
-Mcu.Pin4=PA1
-Mcu.Pin5=PA2
-Mcu.Pin6=PA3
-Mcu.Pin7=PA4
-Mcu.Pin8=PA7
-Mcu.Pin9=PC4
-Mcu.PinsNb=26
+Mcu.Pin1=PF0
+Mcu.Pin10=PA1
+Mcu.Pin11=PA2
+Mcu.Pin12=PA3
+Mcu.Pin13=PA4
+Mcu.Pin14=PA7
+Mcu.Pin15=PC4
+Mcu.Pin16=PC5
+Mcu.Pin17=PF12
+Mcu.Pin18=PE7
+Mcu.Pin19=PE8
+Mcu.Pin2=PF1
+Mcu.Pin20=PE9
+Mcu.Pin21=PE10
+Mcu.Pin22=PB11
+Mcu.Pin23=PB12
+Mcu.Pin24=PB13
+Mcu.Pin25=PD14
+Mcu.Pin26=PD15
+Mcu.Pin27=PG4
+Mcu.Pin28=PA13
+Mcu.Pin29=PA14
+Mcu.Pin3=PF2
+Mcu.Pin30=PD0
+Mcu.Pin31=PD1
+Mcu.Pin32=PD2
+Mcu.Pin33=PD4
+Mcu.Pin34=PD5
+Mcu.Pin35=PD7
+Mcu.Pin36=PG9
+Mcu.Pin37=PB3
+Mcu.Pin38=PB4
+Mcu.Pin39=PB5
+Mcu.Pin4=PF3
+Mcu.Pin40=PB6
+Mcu.Pin41=VP_FREERTOS_VS_CMSIS_V1
+Mcu.Pin42=VP_LWIP_VS_Enabled
+Mcu.Pin43=VP_SYS_VS_tim4
+Mcu.Pin5=PF4
+Mcu.Pin6=PF5
+Mcu.Pin7=PH0-OSC_IN
+Mcu.Pin8=PH1-OSC_OUT
+Mcu.Pin9=PC1
+Mcu.PinsNb=44
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F407ZGTx
@@ -81,6 +106,7 @@ MxDb.Version=DB.6.0.80
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
 NVIC.ETH_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.EXTI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
 NVIC.ForceEnableDMAVector=true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
@@ -146,13 +172,21 @@ PC4.Mode=RMII
 PC4.Signal=ETH_RXD0
 PC5.Mode=RMII
 PC5.Signal=ETH_RXD1
-PD3.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label
-PD3.GPIO_Label=CH438_RST
-PD3.GPIO_PuPd=GPIO_PULLUP
-PD3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PD3.Locked=true
-PD3.PinState=GPIO_PIN_SET
-PD3.Signal=GPIO_Output
+PD0.Signal=FSMC_D2_DA2
+PD1.Signal=FSMC_D3_DA3
+PD14.Signal=FSMC_D0_DA0
+PD15.Signal=FSMC_D1_DA1
+PD2.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
+PD2.GPIO_Label=CH438_INT
+PD2.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
+PD2.GPIO_PuPd=GPIO_PULLUP
+PD2.Locked=true
+PD2.Signal=GPXTI2
+PD4.Signal=FSMC_NOE
+PD5.Signal=FSMC_NWE
+PD7.Mode=NorPsramChipSelect1_1
+PD7.Signal=FSMC_NE1
+PE10.Signal=FSMC_D7_DA7
 PE5.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label
 PE5.GPIO_Label=PE5_LED
 PE5.GPIO_PuPd=GPIO_PULLUP
@@ -160,13 +194,16 @@ PE5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
 PE5.Locked=true
 PE5.PinState=GPIO_PIN_SET
 PE5.Signal=GPIO_Output
-PF14.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
-PF14.GPIO_Label=CH438_AMOD
-PF14.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP
-PF14.GPIO_PuPd=GPIO_PULLDOWN
-PF14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
-PF14.Locked=true
-PF14.Signal=GPIO_Output
+PE7.Signal=FSMC_D4_DA4
+PE8.Signal=FSMC_D5_DA5
+PE9.Signal=FSMC_D6_DA6
+PF0.Signal=FSMC_A0
+PF1.Signal=FSMC_A1
+PF12.Signal=FSMC_A6
+PF2.Signal=FSMC_A2
+PF3.Signal=FSMC_A3
+PF4.Signal=FSMC_A4
+PF5.Signal=FSMC_A5
 PG4.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label
 PG4.GPIO_Label=HART1_RTS
 PG4.GPIO_PuPd=GPIO_PULLUP
@@ -174,6 +211,8 @@ PG4.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
 PG4.Locked=true
 PG4.PinState=GPIO_PIN_SET
 PG4.Signal=GPIO_Output
+PG9.Mode=NorPsramChipSelect2_2
+PG9.Signal=FSMC_NE2
 PH0-OSC_IN.Mode=HSE-External-Oscillator
 PH0-OSC_IN.Signal=RCC_OSC_IN
 PH1-OSC_OUT.Mode=HSE-External-Oscillator
@@ -207,7 +246,7 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=MDK-ARM V5.32
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_LWIP_Init-LWIP-false-HAL-false,4-MX_TIM2_Init-TIM2-false-HAL-true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_LWIP_Init-LWIP-false-HAL-false,4-MX_TIM2_Init-TIM2-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_FSMC_Init-FSMC-false-HAL-true
 RCC.48MHZClocksFreq_Value=55296000
 RCC.AHBFreq_Value=110592000
 RCC.APB1CLKDivider=RCC_HCLK_DIV4
@@ -241,6 +280,59 @@ RCC.VCOI2SOutputFreq_Value=353894400
 RCC.VCOInputFreq_Value=1843200
 RCC.VCOOutputFreq_Value=221184000
 RCC.VcooutputI2S=176947200
+SH.FSMC_A0.0=FSMC_A0,7b-a1
+SH.FSMC_A0.1=FSMC_A0,7b-a2
+SH.FSMC_A0.ConfNb=2
+SH.FSMC_A1.0=FSMC_A1,7b-a1
+SH.FSMC_A1.1=FSMC_A1,7b-a2
+SH.FSMC_A1.ConfNb=2
+SH.FSMC_A2.0=FSMC_A2,7b-a1
+SH.FSMC_A2.1=FSMC_A2,7b-a2
+SH.FSMC_A2.ConfNb=2
+SH.FSMC_A3.0=FSMC_A3,7b-a1
+SH.FSMC_A3.1=FSMC_A3,7b-a2
+SH.FSMC_A3.ConfNb=2
+SH.FSMC_A4.0=FSMC_A4,7b-a1
+SH.FSMC_A4.1=FSMC_A4,7b-a2
+SH.FSMC_A4.ConfNb=2
+SH.FSMC_A5.0=FSMC_A5,7b-a1
+SH.FSMC_A5.1=FSMC_A5,7b-a2
+SH.FSMC_A5.ConfNb=2
+SH.FSMC_A6.0=FSMC_A6,7b-a1
+SH.FSMC_A6.1=FSMC_A6,7b-a2
+SH.FSMC_A6.ConfNb=2
+SH.FSMC_D0_DA0.0=FSMC_D0,8b-d2
+SH.FSMC_D0_DA0.1=FSMC_D0,8b-d1
+SH.FSMC_D0_DA0.ConfNb=2
+SH.FSMC_D1_DA1.0=FSMC_D1,8b-d2
+SH.FSMC_D1_DA1.1=FSMC_D1,8b-d1
+SH.FSMC_D1_DA1.ConfNb=2
+SH.FSMC_D2_DA2.0=FSMC_D2,8b-d2
+SH.FSMC_D2_DA2.1=FSMC_D2,8b-d1
+SH.FSMC_D2_DA2.ConfNb=2
+SH.FSMC_D3_DA3.0=FSMC_D3,8b-d2
+SH.FSMC_D3_DA3.1=FSMC_D3,8b-d1
+SH.FSMC_D3_DA3.ConfNb=2
+SH.FSMC_D4_DA4.0=FSMC_D4,8b-d2
+SH.FSMC_D4_DA4.1=FSMC_D4,8b-d1
+SH.FSMC_D4_DA4.ConfNb=2
+SH.FSMC_D5_DA5.0=FSMC_D5,8b-d2
+SH.FSMC_D5_DA5.1=FSMC_D5,8b-d1
+SH.FSMC_D5_DA5.ConfNb=2
+SH.FSMC_D6_DA6.0=FSMC_D6,8b-d2
+SH.FSMC_D6_DA6.1=FSMC_D6,8b-d1
+SH.FSMC_D6_DA6.ConfNb=2
+SH.FSMC_D7_DA7.0=FSMC_D7,8b-d2
+SH.FSMC_D7_DA7.1=FSMC_D7,8b-d1
+SH.FSMC_D7_DA7.ConfNb=2
+SH.FSMC_NOE.0=FSMC_NOE,Sram1
+SH.FSMC_NOE.1=FSMC_NOE,Sram2
+SH.FSMC_NOE.ConfNb=2
+SH.FSMC_NWE.0=FSMC_NWE,Sram1
+SH.FSMC_NWE.1=FSMC_NWE,Sram2
+SH.FSMC_NWE.ConfNb=2
+SH.GPXTI2.0=GPIO_EXTI2
+SH.GPXTI2.ConfNb=1
 SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4
 SH.S_TIM2_CH4.ConfNb=1
 SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_256