83 lines
3.8 KiB
Plaintext
83 lines
3.8 KiB
Plaintext
// File: STM32L4x5_4x6.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32L4x5 and STM32L4x6 Reference manual (RM0351)
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// refer to STM32L475xx STM32L476xx STM32L486xx STM32L496xx STM32L4A6xx datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug Standby mode
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// <o.1> DBG_STOP <i> Debug Stop mode
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// <o.0> DBG_SLEEP <i> Debug Sleep mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <h> Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
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// <i> Reserved bits must be kept at reset value
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// <o.31> DBG_LPTIM1_STOP <i> LPTIM1 counter stopped when core is halted
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// <o.26> DBG_CAN2_STOP <i> bxCAN2 stopped when core is halted
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// <o.25> DBG_CAN1_STOP <i> bxCAN1 stopped when core is halted
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// <o.23> DBG_I2C3_STOP <i> I2C3 SMBUS timeout counter stopped when core is halted
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// <o.22> DBG_I2C2_STOP <i> I2C2 SMBUS timeout counter stopped when core is halted
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// <o.21> DBG_I2C1_STOP <i> I2C1 SMBUS timeout counter stopped when core is halted
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// <o.12> DBG_IWDG_STOP <i> Independent watchdog counter stopped when core is halted
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// <o.11> DBG_WWDG_STOP <i> Window watchdog counter stopped when core is halted
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// <o.10> DBG_RTC_STOP <i> RTC counter stopped when core is halted
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// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// </h>
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DbgMCU_APB1_Fz1 = 0x00000000;
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// <h> Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
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// <i> Reserved bits must be kept at reset value
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// <o.5> DBG_LPTIM2_STOP <i> LPTIM2 counter stopped when core is halted
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// <o.1> DBG_I2C4_STOP <i> I2C4 SMBUS timeout counter stopped when core is halted
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// </h>
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DbgMCU_APB1_Fz2 = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM17_STOP <i> TIM17 counter stopped when core is halted
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// <o.17> DBG_TIM16_STOP <i> TIM16 counter stopped when core is halted
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// <o.16> DBG_TIM15_STOP <i> TIM15 counter stopped when core is halted
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// <o.13> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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// <o.11> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
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// <i> TRACECLK: Pin PE2
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// <o1> TRACED0
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// <i> ETM Trace Data 0
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// <0x00040003=> Pin PE3
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// <0x00020001=> Pin PC1
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// <o2> TRACED1
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// <i> ETM Trace Data 1
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// <0x00040004=> Pin PE4
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// <0x0002000A=> Pin PC10
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// <o3> TRACED2
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// <i> ETM Trace Data 2
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// <0x00040005=> Pin PE5
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// <0x00030002=> Pin PD2
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// <o4> TRACED3
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// <i> ETM Trace Data 3
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// <0x00040006=> Pin PE6
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// <0x0002000C=> Pin PC12
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// </h>
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TraceClk_Pin = 0x00040002;
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TraceD0_Pin = 0x00040003;
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TraceD1_Pin = 0x00040004;
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TraceD2_Pin = 0x00040005;
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TraceD3_Pin = 0x00040006;
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// <h> Flash Download Options
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// <o.0> Option Byte Loading <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
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// </h>
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DoOptionByteLoading = 0x00000000;
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// <<< end of configuration section >>>
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