diff --git a/Core/Src/main.c b/Core/Src/main.c
index 1b81630..a783f95 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -72,9 +72,9 @@ void PeriphCommonClock_Config(void);
/* USER CODE END 0 */
/**
- * @brief The application entry point.
- * @retval int
- */
+ * @brief The application entry point.
+ * @retval int
+ */
int main(void)
{
/* USER CODE BEGIN 1 */
@@ -91,7 +91,7 @@ int main(void)
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* SysTick_IRQn interrupt configuration */
- NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));
+ NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),15, 0));
/* USER CODE BEGIN Init */
/* USER CODE END Init */
@@ -99,7 +99,7 @@ int main(void)
/* Configure the system clock */
SystemClock_Config();
- /* Configure the peripherals common clocks */
+/* Configure the peripherals common clocks */
PeriphCommonClock_Config();
/* USER CODE BEGIN SysInit */
@@ -147,13 +147,13 @@ int main(void)
}
/**
- * @brief System Clock Configuration
- * @retval None
- */
+ * @brief System Clock Configuration
+ * @retval None
+ */
void SystemClock_Config(void)
{
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
- while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_0)
+ while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_0)
{
}
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
@@ -162,23 +162,26 @@ void SystemClock_Config(void)
}
LL_RCC_HSE_Enable();
- /* Wait till HSE is ready */
- while (LL_RCC_HSE_IsReady() != 1)
+ /* Wait till HSE is ready */
+ while(LL_RCC_HSE_IsReady() != 1)
{
+
}
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_1, 8, LL_RCC_PLLR_DIV_2);
LL_RCC_PLL_EnableDomain_SYS();
LL_RCC_PLL_Enable();
- /* Wait till PLL is ready */
- while (LL_RCC_PLL_IsReady() != 1)
+ /* Wait till PLL is ready */
+ while(LL_RCC_PLL_IsReady() != 1)
{
+
}
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- /* Wait till System clock is ready */
- while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ /* Wait till System clock is ready */
+ while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
{
+
}
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_8);
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
@@ -190,18 +193,19 @@ void SystemClock_Config(void)
}
/**
- * @brief Peripherals Common Clock Configuration
- * @retval None
- */
+ * @brief Peripherals Common Clock Configuration
+ * @retval None
+ */
void PeriphCommonClock_Config(void)
{
LL_RCC_PLLSAI1_ConfigDomain_ADC(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_1, 8, LL_RCC_PLLSAI1R_DIV_2);
LL_RCC_PLLSAI1_EnableDomain_ADC();
LL_RCC_PLLSAI1_Enable();
- /* Wait till PLLSAI1 is ready */
- while (LL_RCC_PLLSAI1_IsReady() != 1)
+ /* Wait till PLLSAI1 is ready */
+ while(LL_RCC_PLLSAI1_IsReady() != 1)
{
+
}
}
@@ -210,9 +214,9 @@ void PeriphCommonClock_Config(void)
/* USER CODE END 4 */
/**
- * @brief This function is executed in case of error occurrence.
- * @retval None
- */
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
@@ -224,14 +228,14 @@ void Error_Handler(void)
/* USER CODE END Error_Handler_Debug */
}
-#ifdef USE_FULL_ASSERT
+#ifdef USE_FULL_ASSERT
/**
- * @brief Reports the name of the source file and the source line number
- * where the assert_param error has occurred.
- * @param file: pointer to the source file name
- * @param line: assert_param error line source number
- * @retval None
- */
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
diff --git a/Core/Src/tim.c b/Core/Src/tim.c
index 5e6f948..1d7a688 100644
--- a/Core/Src/tim.c
+++ b/Core/Src/tim.c
@@ -186,7 +186,7 @@ void MX_TIM7_Init(void)
/* USER CODE END TIM7_Init 1 */
TIM_InitStruct.Prescaler = 399;
TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
- TIM_InitStruct.Autoreload = 99;
+ TIM_InitStruct.Autoreload = 499;
LL_TIM_Init(TIM7, &TIM_InitStruct);
LL_TIM_EnableARRPreload(TIM7);
LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_RESET);
diff --git a/MDK-ARM/controller-v2.uvoptx b/MDK-ARM/controller-v2.uvoptx
index f31b880..707886d 100644
--- a/MDK-ARM/controller-v2.uvoptx
+++ b/MDK-ARM/controller-v2.uvoptx
@@ -1500,6 +1500,14 @@
+
+ ::CMSIS
+ 0
+ 0
+ 0
+ 1
+
+
Middlewares/Library/DSP Library/DSP Library
0
@@ -1507,7 +1515,7 @@
0
0
- 16
+ 17
91
4
0
@@ -1520,12 +1528,4 @@
-
- ::CMSIS
- 0
- 0
- 0
- 1
-
-
diff --git a/MDK-ARM/controller-v2.uvprojx b/MDK-ARM/controller-v2.uvprojx
index c806e9a..e6b7aa4 100644
--- a/MDK-ARM/controller-v2.uvprojx
+++ b/MDK-ARM/controller-v2.uvprojx
@@ -83,7 +83,7 @@
1
1
fromelf --bin --output=@L.bin !L
- output-controller-v24.bat
+
0
0
0
@@ -1278,6 +1278,9 @@
+
+ ::CMSIS
+
Middlewares/Library/DSP Library/DSP Library
@@ -1376,9 +1379,6 @@
-
- ::CMSIS
-
diff --git a/User/application/mode/mode.c b/User/application/mode/mode.c
index d3c7d5b..4617ffa 100644
--- a/User/application/mode/mode.c
+++ b/User/application/mode/mode.c
@@ -295,6 +295,7 @@ void mode_init(void)
break;
case MODE_FREQUENCY_DOMAIN_CONTROL_ALGORITHM:
pdctrl_init(PDCTRL_PWMP);
+ //pdctrl_init(PDCTRL_DAC);
mode_pwmp_hd_init(&mode_get()->interface_req, mode_get()->positioner_model, &mode_params.mode_pwmp_hd_params,
mode_params_save_cb);
break;
diff --git a/controller-v2.ioc b/controller-v2.ioc
index c7cf81c..f4ebcdb 100644
--- a/controller-v2.ioc
+++ b/controller-v2.ioc
@@ -267,8 +267,8 @@ Mcu.ThirdParty0=STMicroelectronics.X-CUBE-ALGOBUILD.1.3.0
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32L476VGTx
-MxCube.Version=6.9.2
-MxDb.Version=DB.6.0.92
+MxCube.Version=6.10.0
+MxDb.Version=DB.6.0.100
NVIC.ADC1_2_IRQn=true\:14\:0\:true\:false\:true\:true\:true\:true
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DMA1_Channel1_IRQn=true\:14\:0\:true\:false\:true\:false\:true\:true
@@ -710,7 +710,7 @@ TIM6.Period=99
TIM6.Prescaler=399
TIM7.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
TIM7.IPParameters=Prescaler,Period,AutoReloadPreload
-TIM7.Period=99
+TIM7.Period=499
TIM7.Prescaler=399
UART5.BaudRate=9600
UART5.IPParameters=BaudRate