// File: STM32L4x5_4x6.dbgconf // Version: 1.0.0 // Note: refer to STM32L4x5 and STM32L4x6 Reference manual (RM0351) // refer to STM32L475xx STM32L476xx STM32L486xx STM32L496xx STM32L4A6xx datasheets // <<< Use Configuration Wizard in Context Menu >>> // Debug MCU configuration register (DBGMCU_CR) // DBG_STANDBY Debug Standby mode // DBG_STOP Debug Stop mode // DBG_SLEEP Debug Sleep mode // DbgMCU_CR = 0x00000007; // Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1) // Reserved bits must be kept at reset value // DBG_LPTIM1_STOP LPTIM1 counter stopped when core is halted // DBG_CAN2_STOP bxCAN2 stopped when core is halted // DBG_CAN1_STOP bxCAN1 stopped when core is halted // DBG_I2C3_STOP I2C3 SMBUS timeout counter stopped when core is halted // DBG_I2C2_STOP I2C2 SMBUS timeout counter stopped when core is halted // DBG_I2C1_STOP I2C1 SMBUS timeout counter stopped when core is halted // DBG_IWDG_STOP Independent watchdog counter stopped when core is halted // DBG_WWDG_STOP Window watchdog counter stopped when core is halted // DBG_RTC_STOP RTC counter stopped when core is halted // DBG_TIM7_STOP TIM7 counter stopped when core is halted // DBG_TIM6_STOP TIM6 counter stopped when core is halted // DBG_TIM5_STOP TIM5 counter stopped when core is halted // DBG_TIM4_STOP TIM4 counter stopped when core is halted // DBG_TIM3_STOP TIM3 counter stopped when core is halted // DBG_TIM2_STOP TIM2 counter stopped when core is halted // DbgMCU_APB1_Fz1 = 0x00000000; // Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) // Reserved bits must be kept at reset value // DBG_LPTIM2_STOP LPTIM2 counter stopped when core is halted // DBG_I2C4_STOP I2C4 SMBUS timeout counter stopped when core is halted // DbgMCU_APB1_Fz2 = 0x00000000; // Debug MCU APB2 freeze register (DBGMCU_APB2FZR) // Reserved bits must be kept at reset value // DBG_TIM17_STOP TIM17 counter stopped when core is halted // DBG_TIM16_STOP TIM16 counter stopped when core is halted // DBG_TIM15_STOP TIM15 counter stopped when core is halted // DBG_TIM8_STOP TIM8 counter stopped when core is halted // DBG_TIM1_STOP TIM1 counter stopped when core is halted // DbgMCU_APB2_Fz = 0x00000000; // TPIU Pin Routing (TRACECLK fixed on Pin PE2) // TRACECLK: Pin PE2 // TRACED0 // ETM Trace Data 0 // <0x00040003=> Pin PE3 // <0x00020001=> Pin PC1 // TRACED1 // ETM Trace Data 1 // <0x00040004=> Pin PE4 // <0x0002000A=> Pin PC10 // TRACED2 // ETM Trace Data 2 // <0x00040005=> Pin PE5 // <0x00030002=> Pin PD2 // TRACED3 // ETM Trace Data 3 // <0x00040006=> Pin PE6 // <0x0002000C=> Pin PC12 // TraceClk_Pin = 0x00040002; TraceD0_Pin = 0x00040003; TraceD1_Pin = 0x00040004; TraceD2_Pin = 0x00040005; TraceD3_Pin = 0x00040006; // <<< end of configuration section >>>