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controller-hd/Core/Src/stm32l4xx_it.c

452 lines
11 KiB
C

/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32l4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "flow.h"
#include "board.h"
#include "bsp.h"
#include "sys.h"
#include "app.h"
#include "diagnosis.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
extern uart_t *uarts[APP_UART_MAX];
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
leds_off_all();
leds_on(LEDS_RED);
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
DBG_ASSERT(FALSE __DBG_LINE);
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32L4xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32l4xx.s). */
/******************************************************************************/
/**
* @brief This function handles EXTI line0 interrupt.
*/
void EXTI0_IRQHandler(void)
{
/* USER CODE BEGIN EXTI0_IRQn 0 */
/* USER CODE END EXTI0_IRQn 0 */
if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_0) != RESET)
{
LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
/* USER CODE BEGIN LL_EXTI_LINE_0 */
uart_rx_cd_callback(uarts[APP_UART_1]); // HART CD
LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_0);
/* USER CODE END LL_EXTI_LINE_0 */
}
/* USER CODE BEGIN EXTI0_IRQn 1 */
/* USER CODE END EXTI0_IRQn 1 */
}
/**
* @brief This function handles DMA1 channel1 global interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
adc_dma_callback(ADCS_1);
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
/**
* @brief This function handles DMA1 channel5 global interrupt.
*/
void DMA1_Channel5_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Channel5_IRQn 0 */
/* USER CODE END DMA1_Channel5_IRQn 0 */
/* USER CODE BEGIN DMA1_Channel5_IRQn 1 */
lcd->info.spi->interface.spi_dma_callback(lcd->info.spi);
/* USER CODE END DMA1_Channel5_IRQn 1 */
}
/**
* @brief This function handles ADC1 and ADC2 interrupts.
*/
void ADC1_2_IRQHandler(void)
{
/* USER CODE BEGIN ADC1_2_IRQn 0 */
/* USER CODE END ADC1_2_IRQn 0 */
/* USER CODE BEGIN ADC1_2_IRQn 1 */
adc_env_callback(ADCS_1);
/* USER CODE END ADC1_2_IRQn 1 */
}
/**
* @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
*/
void TIM1_UP_TIM16_IRQHandler(void)
{
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
/* USER CODE END TIM1_UP_TIM16_IRQn 0 */
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
if (IS_TIM_IT_FLAG(HART_TIM))
{
TIM_IRQ_HANDLER(HART_TIM);
hart_timer_interupt_cb();
}
/* USER CODE END TIM1_UP_TIM16_IRQn 1 */
}
/**
* @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
*/
void TIM1_TRG_COM_TIM17_IRQHandler(void)
{
/* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
/* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
/* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
if (IS_TIM_IT_FLAG(MODE_GATHE_TIM))
{
TIM_IRQ_HANDLER(MODE_GATHE_TIM);
mode_ctrl_gather();
mode_ctrl_output();
if (rt_data.flag.bits.app_init_over == TRUE)
{
scheduler_time_1s_irqhandler(100);
}
}
/* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
}
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
/* USER CODE BEGIN USART1_IRQn 1 */
uart_reception_callback(uarts[APP_UART_1]);
if (uarts[APP_UART_1]->rx_index > 1)
{
if (hart_timeout_compare() == FALSE)
{
uart_data_storage_reset(uarts[APP_UART_1]);
}
}
hart_timer_start(HART_BYTE_INTERVAL_TIME);
/* USER CODE END USART1_IRQn 1 */
}
/**
* @brief This function handles UART5 global interrupt.
*/
void UART5_IRQHandler(void)
{
/* USER CODE BEGIN UART5_IRQn 0 */
/* USER CODE END UART5_IRQn 0 */
/* USER CODE BEGIN UART5_IRQn 1 */
uart_reception_callback(uarts[APP_UART_2]);
/* USER CODE END UART5_IRQn 1 */
}
/**
* @brief This function handles TIM6 global interrupt, DAC channel1 and channel2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
if (IS_TIM_IT_FLAG(TASK_TIM))
{
TIM_IRQ_HANDLER(TASK_TIM);
LL_IncTick();
if (rt_data.flag.bits.app_init_over == TRUE)
{
FLOW_TICK_UPDATE();
#if HART_SOFTWARE_TEST_ENABLE == FALSE
button_ticks();
#endif
}
}
/* USER CODE END TIM6_DAC_IRQn 1 */
}
/**
* @brief This function handles TIM7 global interrupt.
*/
void TIM7_IRQHandler(void)
{
/* USER CODE BEGIN TIM7_IRQn 0 */
/* USER CODE END TIM7_IRQn 0 */
/* USER CODE BEGIN TIM7_IRQn 1 */
if (IS_TIM_IT_FLAG(MODE_TIM))
{
TIM_IRQ_HANDLER(MODE_TIM);
if (rt_data.flag.bits.app_init_over == TRUE)
{
mode_ctrl_process();
}
}
/* USER CODE END TIM7_IRQn 1 */
}
/**
* @brief This function handles DMA2 channel1 global interrupt.
*/
void DMA2_Channel1_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Channel1_IRQn 0 */
/* USER CODE END DMA2_Channel1_IRQn 0 */
/* USER CODE BEGIN DMA2_Channel1_IRQn 1 */
uart_dma_reception_callback(uarts[APP_UART_2]);
/* USER CODE END DMA2_Channel1_IRQn 1 */
}
/**
* @brief This function handles DMA2 channel2 global interrupt.
*/
void DMA2_Channel2_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Channel2_IRQn 0 */
/* USER CODE END DMA2_Channel2_IRQn 0 */
/* USER CODE BEGIN DMA2_Channel2_IRQn 1 */
uart_dma_reception_callback(uarts[APP_UART_2]);
/* USER CODE END DMA2_Channel2_IRQn 1 */
}
/**
* @brief This function handles DMA2 channel6 global interrupt.
*/
void DMA2_Channel6_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Channel6_IRQn 0 */
/* USER CODE END DMA2_Channel6_IRQn 0 */
/* USER CODE BEGIN DMA2_Channel6_IRQn 1 */
uart_dma_reception_callback(uarts[APP_UART_1]);
/* USER CODE END DMA2_Channel6_IRQn 1 */
}
/**
* @brief This function handles DMA2 channel7 global interrupt.
*/
void DMA2_Channel7_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Channel7_IRQn 0 */
/* USER CODE END DMA2_Channel7_IRQn 0 */
/* USER CODE BEGIN DMA2_Channel7_IRQn 1 */
uart_dma_reception_callback(uarts[APP_UART_1]);
/* USER CODE END DMA2_Channel7_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */