#ifndef __AD7124_H #define __AD7124_H /******************************************************************************/ /***************************** Include Files **********************************/ /******************************************************************************/ #include "main.h" #include "user_spi.h" /******************************************************************************/ /******************* Register map and register definitions ********************/ /******************************************************************************/ // 常量定义 #define AD7124_CRC8_POLYNOMIAL_REPRESENTATION 0x07 /* x8 + x2 + x + 1 */ #define AD7124_DISABLE_CRC 0 #define AD7124_USE_CRC 1 #define AD7124_RDY 10000 #define AD7124_RES 100 #define VREF 2.5f #define GAIN 1 #define AD_CODE 0XFFFFFF /* Communication Register bits */ #define AD7124_COMM_REG_WEN (0 << 7) #define AD7124_COMM_REG_WR (0 << 6) #define AD7124_COMM_REG_RD (1 << 6) //0x40 #define AD7124_COMM_REG_RA(x) ((x) & 0x3F) /* Status Register bits */ #define AD7124_STATUS_REG_RDY (1 << 7) #define AD7124_STATUS_REG_ERROR_FLAG (1 << 6) #define AD7124_STATUS_REG_POR_FLAG (1 << 4) #define AD7124_STATUS_REG_CH_ACTIVE(x) ((x) & 0xF) /* ADC_Control Register bits */ #define AD7124_ADC_CTRL_REG_DOUT_RDY_DEL (1 << 12) #define AD7124_ADC_CTRL_REG_CONT_READ (1 << 11) #define AD7124_ADC_CTRL_REG_DATA_STATUS (1 << 10) #define AD7124_ADC_CTRL_REG_CS_EN (1 << 9) #define AD7124_ADC_CTRL_REG_REF_EN (1 << 8) #define AD7124_ADC_CTRL_REG_POWER_MODE(x) (((x) & 0x3) << 6) #define AD7124_ADC_CTRL_REG_MODE(x) (((x) & 0xF) << 2) #define AD7124_ADC_CTRL_REG_CLK_SEL(x) (((x) & 0x3) << 0) /* IO_Control_1 Register bits */ #define AD7124_IO_CTRL1_REG_GPIO_DAT2 (1 << 23) #define AD7124_IO_CTRL1_REG_GPIO_DAT1 (1 << 22) #define AD7124_IO_CTRL1_REG_GPIO_CTRL2 (1 << 19) #define AD7124_IO_CTRL1_REG_GPIO_CTRL1 (1 << 18) #define AD7124_IO_CTRL1_REG_PDSW (1 << 15) #define AD7124_IO_CTRL1_REG_IOUT1(x) (((x) & 0x7) << 11) #define AD7124_IO_CTRL1_REG_IOUT0(x) (((x) & 0x7) << 8) #define AD7124_IO_CTRL1_REG_IOUT_CH1(x) (((x) & 0xF) << 4) #define AD7124_IO_CTRL1_REG_IOUT_CH0(x) (((x) & 0xF) << 0) /* IO_Control_1 AD7124-8 specific bits */ #define AD7124_8_IO_CTRL1_REG_GPIO_DAT4 (1 << 23) #define AD7124_8_IO_CTRL1_REG_GPIO_DAT3 (1 << 22) #define AD7124_8_IO_CTRL1_REG_GPIO_DAT2 (1 << 21) #define AD7124_8_IO_CTRL1_REG_GPIO_DAT1 (1 << 20) #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL4 (1 << 19) #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL3 (1 << 18) #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL2 (1 << 17) #define AD7124_8_IO_CTRL1_REG_GPIO_CTRL1 (1 << 16) /* IO_Control_2 Register bits */ #define AD7124_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 15) #define AD7124_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 14) #define AD7124_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 11) #define AD7124_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 10) #define AD7124_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 5) #define AD7124_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 4) #define AD7124_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1) #define AD7124_IO_CTRL2_REG_GPIO_VBIAS0 (1 << 0) /* IO_Control_2 AD7124-8 specific bits */ #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS15 (1 << 15) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS14 (1 << 14) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS13 (1 << 13) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS12 (1 << 12) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS11 (1 << 11) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS10 (1 << 10) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS9 (1 << 9) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS8 (1 << 8) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS7 (1 << 7) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS6 (1 << 6) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS5 (1 << 5) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS4 (1 << 4) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS3 (1 << 3) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS2 (1 << 2) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS1 (1 << 1) #define AD7124_8_IO_CTRL2_REG_GPIO_VBIAS0 (1 << 0) /* ID Register bits */ #define AD7124_ID_REG_DEVICE_ID(x) (((x) & 0xF) << 4) #define AD7124_ID_REG_SILICON_REV(x) (((x) & 0xF) << 0) /* Error Register bits */ #define AD7124_ERR_REG_LDO_CAP_ERR (1 << 19) #define AD7124_ERR_REG_ADC_CAL_ERR (1 << 18) #define AD7124_ERR_REG_ADC_CONV_ERR (1 << 17) #define AD7124_ERR_REG_ADC_SAT_ERR (1 << 16) #define AD7124_ERR_REG_AINP_OV_ERR (1 << 15) #define AD7124_ERR_REG_AINP_UV_ERR (1 << 14) #define AD7124_ERR_REG_AINM_OV_ERR (1 << 13) #define AD7124_ERR_REG_AINM_UV_ERR (1 << 12) #define AD7124_ERR_REG_REF_DET_ERR (1 << 11) #define AD7124_ERR_REG_DLDO_PSM_ERR (1 << 9) #define AD7124_ERR_REG_ALDO_PSM_ERR (1 << 7) #define AD7124_ERR_REG_SPI_IGNORE_ERR (1 << 6) #define AD7124_ERR_REG_SPI_SLCK_CNT_ERR (1 << 5) #define AD7124_ERR_REG_SPI_READ_ERR (1 << 4) #define AD7124_ERR_REG_SPI_WRITE_ERR (1 << 3) #define AD7124_ERR_REG_SPI_CRC_ERR (1 << 2) #define AD7124_ERR_REG_MM_CRC_ERR (1 << 1) #define AD7124_ERR_REG_ROM_CRC_ERR (1 << 0) /* Error_En Register bits */ #define AD7124_ERREN_REG_MCLK_CNT_EN (1 << 22) #define AD7124_ERREN_REG_LDO_CAP_CHK_TEST_EN (1 << 21) #define AD7124_ERREN_REG_LDO_CAP_CHK(x) (((x) & 0x3) << 19) #define AD7124_ERREN_REG_ADC_CAL_ERR_EN (1 << 18) #define AD7124_ERREN_REG_ADC_CONV_ERR_EN (1 << 17) #define AD7124_ERREN_REG_ADC_SAT_ERR_EN (1 << 16) #define AD7124_ERREN_REG_AINP_OV_ERR_EN (1 << 15) #define AD7124_ERREN_REG_AINP_UV_ERR_EN (1 << 14) #define AD7124_ERREN_REG_AINM_OV_ERR_EN (1 << 13) #define AD7124_ERREN_REG_AINM_UV_ERR_EN (1 << 12) #define AD7124_ERREN_REG_REF_DET_ERR_EN (1 << 11) #define AD7124_ERREN_REG_DLDO_PSM_TRIP_TEST_EN (1 << 10) #define AD7124_ERREN_REG_DLDO_PSM_ERR_ERR (1 << 9) #define AD7124_ERREN_REG_ALDO_PSM_TRIP_TEST_EN (1 << 8) #define AD7124_ERREN_REG_ALDO_PSM_ERR_EN (1 << 7) #define AD7124_ERREN_REG_SPI_IGNORE_ERR_EN (1 << 6) #define AD7124_ERREN_REG_SPI_SCLK_CNT_ERR_EN (1 << 5) #define AD7124_ERREN_REG_SPI_READ_ERR_EN (1 << 4) #define AD7124_ERREN_REG_SPI_WRITE_ERR_EN (1 << 3) #define AD7124_ERREN_REG_SPI_CRC_ERR_EN (1 << 2) #define AD7124_ERREN_REG_MM_CRC_ERR_EN (1 << 1) #define AD7124_ERREN_REG_ROM_CRC_ERR_EN (1 << 0) /* Channel Registers 0-15 bits */ #define AD7124_CH_MAP_REG_CH_ENABLE (1 << 15) #define AD7124_CH_MAP_REG_SETUP(x) (((x) & 0x7) << 12) #define AD7124_CH_MAP_REG_AINP(x) (((x) & 0x1F) << 5) #define AD7124_CH_MAP_REG_AINM(x) (((x) & 0x1F) << 0) /* Configuration Registers 0-7 bits */ #define AD7124_CFG_REG_BIPOLAR (1 << 11) #define AD7124_CFG_REG_BURNOUT(x) (((x) & 0x3) << 9) #define AD7124_CFG_REG_REF_BUFP (1 << 8) #define AD7124_CFG_REG_REF_BUFM (1 << 7) #define AD7124_CFG_REG_AIN_BUFP (1 << 6) #define AD7124_CFG_REG_AINN_BUFM (1 << 5) #define AD7124_CFG_REG_REF_SEL(x) ((x) & 0x3) << 3 #define AD7124_CFG_REG_PGA(x) (((x) & 0x7) << 0) /* Filter Register 0-7 bits */ #define AD7124_FILT_REG_FILTER(x) (((x) & 0x7) << 21) #define AD7124_FILT_REG_REJ60 (1 << 20) #define AD7124_FILT_REG_POST_FILTER(x) (((x) & 0x7) << 17) #define AD7124_FILT_REG_SINGLE_CYCLE (1 << 16) #define AD7124_FILT_REG_FS(x) (((x) & 0x7FF) << 0) /******************************************************************************/ /*************************** Types Declarations *******************************/ /******************************************************************************/ /*! AD7124 registers list*/ typedef enum { AD7124_STATUS = 0X00,//状态寄存器 AD7124_ADC_CONTROL,//ADC控制寄存器 AD7124_DATA,//数据寄存器 AD7124_IOCON1,//IO控制寄存器1 AD7124_IOCON2,//IO控制寄存器2 AD7124_ID,//ID寄存器 AD7124_ERROR,//错误寄存器 AD7124_ERROR_EN,//错误使能寄存器 AD7124_MCLK_COUNT,//MCLK计数寄存器 AD7124_CHANNEL_0,//通道0 AD7124_CHANNEL_1,//通道1 AD7124_CHANNEL_2,//通道2 AD7124_CHANNEL_3,//通道3 AD7124_CHANNEL_4,//通道4 AD7124_CHANNEL_5,//通道5 AD7124_CHANNEL_6,//通道6 AD7124_CHANNEL_7,//通道7 AD7124_CHANNEL_8,//通道8 AD7124_CHANNEL_9,//通道9 AD7124_CHANNEL_10,//通道10 AD7124_CHANNEL_11,//通道11 AD7124_CHANNEL_12,//通道12 AD7124_CHANNEL_13,//通道13 AD7124_CHANNEL_14,//通道14 AD7124_CHANNEL_15,//通道15 AD7124_CONFIG_0,//配置寄存器0 AD7124_CONFIG_1,//配置寄存器1 AD7124_CONFIG_2,//配置寄存器2 AD7124_CONFIG_3,//配置寄存器3 AD7124_CONFIG_4,//配置寄存器4 AD7124_CONFIG_5,//配置寄存器5 AD7124_CONFIG_6,//配置寄存器6 AD7124_CONFIG_7,//配置寄存器7 AD7124_FILTER_0,//滤波寄存器0 AD7124_FILTER_1,//滤波寄存器1 AD7124_FILTER_2,//滤波寄存器2 AD7124_FILTER_3,//滤波寄存器3 AD7124_FILTER_4,//滤波寄存器4 AD7124_FILTER_5,//滤波寄存器5 AD7124_FILTER_6,//滤波寄存器6 AD7124_FILTER_7,//滤波寄存器7 AD7124_OFFSET_0,//偏移寄存器0 AD7124_OFFSET_1,//偏移寄存器1 AD7124_OFFSET_2,//偏移寄存器2 AD7124_OFFSET_3,//偏移寄存器3 AD7124_OFFSET_4,//偏移寄存器4 AD7124_OFFSET_5,//偏移寄存器5 AD7124_OFFSET_6,//偏移寄存器6 AD7124_OFFSET_7,//偏移寄存器7 AD7124_GAIN_0,//增益寄存器0 AD7124_GAIN_1,//增益寄存器1 AD7124_GAIN_2,//增益寄存器2 AD7124_GAIN_3,//增益寄存器3 AD7124_GAIN_4,//增益寄存器4 AD7124_GAIN_5,//增益寄存器5 AD7124_GAIN_6,//增益寄存器6 AD7124_GAIN_7,//增益寄存器7 AD7124_REG_NO//寄存器数量 } ad7124_registers_addr_e; typedef enum { AD7124_SIZE_1 = 1, AD7124_SIZE_2 = 2, AD7124_SIZE_3 = 3, } ad7124_registers_size_e; typedef enum { AD7124_RW = 1,//读写 AD7124_R = 2,//读 AD7124_W = 3,//写 } ad7124_registers_rw_e; typedef struct { int addr; int32_t value; int size; int rw; } ad7124_st_reg_t; typedef enum { STOP_NC_ADC = 0, STOP_NO_ADC, AI_IN1_ADC, AI_IN2_ADC, P1_DI2_ADC, P1_DI1_ADC, P1_AI_ADC, P2_DI2_ADC, P2_DI1_ADC, P2_AI_ADC, AD7124_CHANNEL_EN_MAX, } ad7124_channel_e; typedef struct { uint8_t channel; int32_t data; float voltage; float current; } ad7124_analog_t; // 声明外部变量 extern ad7124_st_reg_t ad7124_regs[AD7124_REG_NO]; extern ad7124_st_reg_t ad7124_channel_regs[AD7124_CHANNEL_EN_MAX]; extern int32_t g_ad7124_id; // 函数声明 int32_t ad7124_read_register(ad7124_st_reg_t *p_reg); int32_t ad7124_write_register(ad7124_st_reg_t *reg); int32_t ad7124_no_check_read_register(ad7124_st_reg_t *p_reg); int32_t ad7124_no_check_write_register(ad7124_st_reg_t *reg); int32_t ad7124_reset(void); int32_t ad7124_wait_for_spi_ready(uint32_t timeout); int32_t ad7124_wait_to_power_on(uint32_t timeout); int32_t ad7124_wait_for_conv_ready(uint32_t timeout); int32_t ad7124_read_data(void); void ad7124_get_analog(uint8_t channel_nr); int32_t ad7124_setup(void); int32_t ad7124_read_write_spi(uint8_t *buff, uint8_t length); #endif /* __AD7124_H */