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This commit is contained in:
许晟昊 2024-12-18 15:38:47 +08:00
commit fbe9e356f7
204 changed files with 94703 additions and 0 deletions
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.gitignore vendored Normal file
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# Binaries for programs and plugins
*.exe
*.exe~
*.dll
*.so
*.dylib
# Test binary, built with `go test -c`
*.test
*.log
# Output of the go coverage tool, specifically when used with LiteIDE
*.out
.VSCodeCounter
USER/Listings
USER/Objects
build
dist
/MDK-ARM/.vscode/uv4.log
/MDK-ARM/.cmsis/include
/MDK-ARM/.eide
/MDK-ARM/MDK-ARM.code-workspace
/MDK-ARM/.vscode/settings.json
/MDK-ARM/.vscode/tasks.json
/MDK-ARM/.clang-format
/MDK-ARM/.vscode/uv4.log.lock
/MDK-ARM/*.hex
/MDK-ARM/*.bin
/MDK-ARM/.pack
.vscode/settings.json

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[PreviousLibFiles]
LibFiles=Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_gpio.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_dma.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_pwr.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_exti.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_tim.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_rcc.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_utils.c;Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_usart.c;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_gpio.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_dma.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_pwr.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_system.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_exti.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_tim.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_bus.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_cortex.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_rcc.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_utils.h;Drivers\STM32F1xx_HAL_Driver\Inc\stm32f1xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f103xb.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Include\system_stm32f1xx.h;Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
[PreviousUsedKeilFiles]
SourceFiles=..\Core\Src\main.c;..\Core\Src\gpio.c;..\Core\Src\dma.c;..\Core\Src\tim.c;..\Core\Src\usart.c;..\Core\Src\stm32f1xx_it.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_gpio.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_dma.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_pwr.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_exti.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_tim.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_rcc.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_utils.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_usart.c;..\Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;..\Core\Src\system_stm32f1xx.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_gpio.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_dma.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_pwr.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_exti.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_tim.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_rcc.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_utils.c;..\Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_ll_usart.c;..\Drivers\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c;..\Core\Src\system_stm32f1xx.c;;;
HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc;
CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;HSI_VALUE:8000000;LSI_VALUE:40000;VDD_VALUE:3300;PREFETCH_ENABLE:1;STM32F103xB;USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;HSI_VALUE:8000000;LSI_VALUE:40000;VDD_VALUE:3300;PREFETCH_ENABLE:1;
[PreviousGenFiles]
AdvancedFolderStructure=true
HeaderFileListSize=7
HeaderFiles#0=..\Core\Inc\gpio.h
HeaderFiles#1=..\Core\Inc\dma.h
HeaderFiles#2=..\Core\Inc\tim.h
HeaderFiles#3=..\Core\Inc\usart.h
HeaderFiles#4=..\Core\Inc\stm32f1xx_it.h
HeaderFiles#5=..\Core\Inc\stm32_assert.h
HeaderFiles#6=..\Core\Inc\main.h
HeaderFolderListSize=1
HeaderPath#0=..\Core\Inc
HeaderFiles=;
SourceFileListSize=6
SourceFiles#0=..\Core\Src\gpio.c
SourceFiles#1=..\Core\Src\dma.c
SourceFiles#2=..\Core\Src\tim.c
SourceFiles#3=..\Core\Src\usart.c
SourceFiles#4=..\Core\Src\stm32f1xx_it.c
SourceFiles#5=..\Core\Src\main.c
SourceFolderListSize=1
SourcePath#0=..\Core\Src
SourceFiles=;

18
.vscode/c_cpp_properties.json vendored Normal file
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{
"configurations": [
{
"name": "windows-gcc-x64",
"includePath": [
"${workspaceFolder}/**"
],
"compilerPath": "C:/TDM-GCC-64/bin/gcc.exe",
"cStandard": "${default}",
"cppStandard": "${default}",
"intelliSenseMode": "windows-gcc-x64",
"compilerArgs": [
""
]
}
],
"version": 4
}

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{
"version": "0.2.0",
"configurations": [
{
"name": "C/C++ Runner: Debug Session",
"type": "cppdbg",
"request": "launch",
"args": [],
"stopAtEntry": false,
"externalConsole": true,
"cwd": "e:/work/stm32/电机学习工程/motor/Core/Src",
"program": "e:/work/stm32/电机学习工程/motor/Core/Src/build/Debug/outDebug",
"MIMode": "gdb",
"miDebuggerPath": "gdb",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
}
]
}

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Core/Inc/dma.h Normal file
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file dma.h
* @brief This file contains all the function prototypes for
* the dma.c file
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __DMA_H__
#define __DMA_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* DMA memory to memory transfer handles -------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_DMA_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __DMA_H__ */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file gpio.h
* @brief This file contains all the function prototypes for
* the gpio.c file
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_GPIO_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ GPIO_H__ */

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Core/Inc/main.h Normal file
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_dma.h"
#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_bus.h"
#include "stm32f1xx_ll_system.h"
#include "stm32f1xx_ll_exti.h"
#include "stm32f1xx_ll_cortex.h"
#include "stm32f1xx_ll_utils.h"
#include "stm32f1xx_ll_pwr.h"
#include "stm32f1xx_ll_tim.h"
#include "stm32f1xx_ll_usart.h"
#include "stm32f1xx_ll_gpio.h"
#if defined(USE_FULL_ASSERT)
#include "stm32_assert.h"
#endif /* USE_FULL_ASSERT */
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "sys.h"
#include "delay.h"
#include "lib.h"
#include "bsp.h"
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define LED_BLUE_Pin LL_GPIO_PIN_13
#define LED_BLUE_GPIO_Port GPIOC
#define OLED_SDA_Pin LL_GPIO_PIN_12
#define OLED_SDA_GPIO_Port GPIOB
#define OLDE_SCK_Pin LL_GPIO_PIN_13
#define OLDE_SCK_GPIO_Port GPIOB
#ifndef NVIC_PRIORITYGROUP_0
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
1 bit for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
0 bit for subpriority */
#endif
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32_assert.h
* @brief STM32 assert file.
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32_ASSERT_H
#define __STM32_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32_ASSERT_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f1xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_IT_H
#define __STM32F1xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void DMA1_Channel4_IRQHandler(void);
void DMA1_Channel5_IRQHandler(void);
void TIM1_UP_IRQHandler(void);
void TIM3_IRQHandler(void);
void USART1_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_IT_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file tim.h
* @brief This file contains all the function prototypes for
* the tim.c file
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TIM_H__
#define __TIM_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_TIM1_Init(void);
void MX_TIM2_Init(void);
void MX_TIM3_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_H__ */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file usart.h
* @brief This file contains all the function prototypes for
* the usart.c file
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USART_H__
#define __USART_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_USART1_UART_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /* __USART_H__ */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file dma.c
* @brief This file provides code for the configuration
* of all the requested memory to memory DMA transfers.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "dma.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/*----------------------------------------------------------------------------*/
/* Configure DMA */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/**
* Enable DMA controller clock
*/
void MX_DMA_Init(void)
{
/* Init with LL driver */
/* DMA controller clock enable */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
/* DMA interrupt init */
/* DMA1_Channel4_IRQn interrupt configuration */
NVIC_SetPriority(DMA1_Channel4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
NVIC_EnableIRQ(DMA1_Channel4_IRQn);
/* DMA1_Channel5_IRQn interrupt configuration */
NVIC_SetPriority(DMA1_Channel5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
NVIC_EnableIRQ(DMA1_Channel5_IRQn);
}
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file gpio.c
* @brief This file provides code for the configuration
* of all used GPIO pins.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "gpio.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/*----------------------------------------------------------------------------*/
/* Configure GPIO */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/** Configure pins as
* Analog
* Input
* Output
* EVENT_OUT
* EXTI
* Free pins are configured automatically as Analog (this feature is enabled through
* the Code Generation settings)
*/
void MX_GPIO_Init(void)
{
LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOC);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOD);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOB);
/**/
LL_GPIO_ResetOutputPin(LED_BLUE_GPIO_Port, LED_BLUE_Pin);
/**/
LL_GPIO_ResetOutputPin(GPIOB, OLED_SDA_Pin|OLDE_SCK_Pin);
/**/
GPIO_InitStruct.Pin = LED_BLUE_Pin;
GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
LL_GPIO_Init(LED_BLUE_GPIO_Port, &GPIO_InitStruct);
/**/
GPIO_InitStruct.Pin = LL_GPIO_PIN_14|LL_GPIO_PIN_15;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/**/
GPIO_InitStruct.Pin = LL_GPIO_PIN_0|LL_GPIO_PIN_2|LL_GPIO_PIN_3|LL_GPIO_PIN_4
|LL_GPIO_PIN_5|LL_GPIO_PIN_6|LL_GPIO_PIN_7|LL_GPIO_PIN_8
|LL_GPIO_PIN_11|LL_GPIO_PIN_12|LL_GPIO_PIN_15;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/**/
GPIO_InitStruct.Pin = LL_GPIO_PIN_0|LL_GPIO_PIN_1|LL_GPIO_PIN_2|LL_GPIO_PIN_10
|LL_GPIO_PIN_11|LL_GPIO_PIN_14|LL_GPIO_PIN_15|LL_GPIO_PIN_3
|LL_GPIO_PIN_4|LL_GPIO_PIN_5|LL_GPIO_PIN_6|LL_GPIO_PIN_7
|LL_GPIO_PIN_8|LL_GPIO_PIN_9;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/**/
GPIO_InitStruct.Pin = OLED_SDA_Pin|OLDE_SCK_Pin;
GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
}
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "dma.h"
#include "tim.h"
#include "usart.h"
#include "gpio.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "board.h"
#include "app.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
/* System interrupt init*/
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
LL_GPIO_AF_Remap_SWJ_NOJTAG();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
delay_init((SystemCoreClock / 1000000));
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_DMA_Init();
MX_TIM2_Init();
MX_USART1_UART_Init();
MX_TIM1_Init();
MX_TIM3_Init();
/* USER CODE BEGIN 2 */
my_mem_init(SRAMIN); // Initialize internal memory pool 1
board_init();
app_init();
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
app_run();
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_2)
{
}
LL_RCC_HSE_Enable();
/* Wait till HSE is ready */
while(LL_RCC_HSE_IsReady() != 1)
{
}
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE_DIV_1, LL_RCC_PLL_MUL_9);
LL_RCC_PLL_Enable();
/* Wait till PLL is ready */
while(LL_RCC_PLL_IsReady() != 1)
{
}
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
/* Wait till System clock is ready */
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
{
}
LL_Init1msTick(72000000);
LL_SetSystemCoreClock(72000000);
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f1xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32f1xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "sys.h"
#include "flow.h"
#include "board.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M3 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32F1xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32f1xx.s). */
/******************************************************************************/
/**
* @brief This function handles DMA1 channel4 global interrupt.
*/
void DMA1_Channel4_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
/* USER CODE END DMA1_Channel4_IRQn 0 */
/* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
uart_dma_reception_callback(uart);
/* USER CODE END DMA1_Channel4_IRQn 1 */
}
/**
* @brief This function handles DMA1 channel5 global interrupt.
*/
void DMA1_Channel5_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Channel5_IRQn 0 */
/* USER CODE END DMA1_Channel5_IRQn 0 */
/* USER CODE BEGIN DMA1_Channel5_IRQn 1 */
uart_dma_reception_callback(uart);
/* USER CODE END DMA1_Channel5_IRQn 1 */
}
/**
* @brief This function handles TIM1 update interrupt.
*/
void TIM1_UP_IRQHandler(void)
{
/* USER CODE BEGIN TIM1_UP_IRQn 0 */
/* USER CODE END TIM1_UP_IRQn 0 */
/* USER CODE BEGIN TIM1_UP_IRQn 1 */
if (IS_TIM_IT_FLAG(TASK_TIM))
{
TIM_IRQ_HANDLER(TASK_TIM);
LL_IncTick();
FLOW_TICK_UPDATE();
}
/* USER CODE END TIM1_UP_IRQn 1 */
}
/**
* @brief This function handles TIM3 global interrupt.
*/
void TIM3_IRQHandler(void)
{
/* USER CODE BEGIN TIM3_IRQn 0 */
/* USER CODE END TIM3_IRQn 0 */
/* USER CODE BEGIN TIM3_IRQn 1 */
if (IS_TIM_IT_FLAG(WORK_TIM))
{
TIM_IRQ_HANDLER(WORK_TIM);
}
/* USER CODE END TIM3_IRQn 1 */
}
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
/* USER CODE BEGIN USART1_IRQn 1 */
uart_reception_callback(uart);
/* USER CODE END USART1_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/**
******************************************************************************
* @file system_stm32f1xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* factors, AHB/APBx prescalers and Flash settings).
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f1xx_xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
* configure the system clock before to branch to main program.
*
* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
* the product used), refer to "HSE_VALUE".
* When HSE is used as system clock source, directly or through PLL, and you
* are using different crystal you have to adapt the HSE value to your own
* configuration.
*
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f1xx_system
* @{
*/
/** @addtogroup STM32F1xx_System_Private_Includes
* @{
*/
#include "stm32f1xx.h"
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/*!< Uncomment the following line if you need to use external SRAM */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
* @{
*/
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz or 25 MHz, depending on the product used), user has to ensure
* that HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
#if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
#endif /* STM32F105xC */
#if defined(STM32F100xB) || defined(STM32F100xE)
uint32_t prediv1factor = 0U;
#endif /* STM32F100xB or STM32F100xE */
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x04U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x08U: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#if !defined(STM32F105xC) && !defined(STM32F107xC)
pllmull = ( pllmull >> 18U) + 2U;
if (pllsource == 0x00U)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
}
else
{
#if defined(STM32F100xB) || defined(STM32F100xE)
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */
SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
}
else
{
SystemCoreClock = HSE_VALUE * pllmull;
}
#endif
}
#else
pllmull = pllmull >> 18U;
if (pllmull != 0x0DU)
{
pllmull += 2U;
}
else
{ /* PLL multiplication factor = PLL input clock * 6.5 */
pllmull = 13U / 2U;
}
if (pllsource == 0x00U)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
}
else
{/* PREDIV1 selected as PLL clock entry */
/* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
if (prediv1source == 0U)
{
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
}
else
{/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
#endif /* STM32F105xC */
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/**
* @brief Setup the external memory controller. Called in startup_stm32f1xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f1xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on STM3210E-EVAL
* board (STM32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmpreg;
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */
/* Enable FSMC clock */
RCC->AHBENR = 0x00000114U;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0U;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
(void)(tmpreg);
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
GPIOD->CRL = 0x44BB44BBU;
GPIOD->CRH = 0xBBBBBBBBU;
GPIOE->CRL = 0xB44444BBU;
GPIOE->CRH = 0xBBBBBBBBU;
GPIOF->CRL = 0x44BBBBBBU;
GPIOF->CRH = 0xBBBB4444U;
GPIOG->CRL = 0x44BBBBBBU;
GPIOG->CRH = 0x444B4B44U;
/*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
FSMC_Bank1->BTCR[4U] = 0x00001091U;
FSMC_Bank1->BTCR[5U] = 0x00110212U;
}
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file tim.c
* @brief This file provides code for the configuration
* of the TIM instances.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "tim.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* TIM1 init function */
void MX_TIM1_Init(void)
{
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
LL_TIM_InitTypeDef TIM_InitStruct = {0};
/* Peripheral clock enable */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
/* TIM1 interrupt Init */
NVIC_SetPriority(TIM1_UP_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),3, 0));
NVIC_EnableIRQ(TIM1_UP_IRQn);
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
TIM_InitStruct.Prescaler = 7199;
TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct.Autoreload = 99;
TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
TIM_InitStruct.RepetitionCounter = 0;
LL_TIM_Init(TIM1, &TIM_InitStruct);
LL_TIM_DisableARRPreload(TIM1);
LL_TIM_SetClockSource(TIM1, LL_TIM_CLOCKSOURCE_INTERNAL);
LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_RESET);
LL_TIM_DisableMasterSlaveMode(TIM1);
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
/* TIM2 init function */
void MX_TIM2_Init(void)
{
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
LL_TIM_InitTypeDef TIM_InitStruct = {0};
LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
/* Peripheral clock enable */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
TIM_InitStruct.Prescaler = 0;
TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct.Autoreload = 7199;
TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
LL_TIM_Init(TIM2, &TIM_InitStruct);
LL_TIM_EnableARRPreload(TIM2);
LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
LL_TIM_OC_EnablePreload(TIM2, LL_TIM_CHANNEL_CH2);
TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_PWM2;
TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
TIM_OC_InitStruct.CompareValue = 0;
TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_LOW;
LL_TIM_OC_Init(TIM2, LL_TIM_CHANNEL_CH2, &TIM_OC_InitStruct);
LL_TIM_OC_EnableFast(TIM2, LL_TIM_CHANNEL_CH2);
LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET);
LL_TIM_DisableMasterSlaveMode(TIM2);
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
/**TIM2 GPIO Configuration
PA1 ------> TIM2_CH2
*/
GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
}
/* TIM3 init function */
void MX_TIM3_Init(void)
{
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
LL_TIM_InitTypeDef TIM_InitStruct = {0};
/* Peripheral clock enable */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3);
/* TIM3 interrupt Init */
NVIC_SetPriority(TIM3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),3, 0));
NVIC_EnableIRQ(TIM3_IRQn);
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
TIM_InitStruct.Prescaler = 7199;
TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct.Autoreload = 99;
TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
LL_TIM_Init(TIM3, &TIM_InitStruct);
LL_TIM_DisableARRPreload(TIM3);
LL_TIM_SetClockSource(TIM3, LL_TIM_CLOCKSOURCE_INTERNAL);
LL_TIM_SetTriggerOutput(TIM3, LL_TIM_TRGO_RESET);
LL_TIM_DisableMasterSlaveMode(TIM3);
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file usart.c
* @brief This file provides code for the configuration
* of the USART instances.
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "usart.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* USART1 init function */
void MX_USART1_UART_Init(void)
{
/* USER CODE BEGIN USART1_Init 0 */
/* USER CODE END USART1_Init 0 */
LL_USART_InitTypeDef USART_InitStruct = {0};
LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
/* Peripheral clock enable */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = LL_GPIO_PIN_9;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = LL_GPIO_PIN_10;
GPIO_InitStruct.Mode = LL_GPIO_MODE_FLOATING;
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART1 DMA Init */
/* USART1_RX Init */
LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_5, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_5, LL_DMA_PRIORITY_LOW);
LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_5, LL_DMA_MODE_NORMAL);
LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_5, LL_DMA_PERIPH_NOINCREMENT);
LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_5, LL_DMA_MEMORY_INCREMENT);
LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_5, LL_DMA_PDATAALIGN_BYTE);
LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_5, LL_DMA_MDATAALIGN_BYTE);
/* USART1_TX Init */
LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_4, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_4, LL_DMA_PRIORITY_LOW);
LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_4, LL_DMA_MODE_NORMAL);
LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_4, LL_DMA_PERIPH_NOINCREMENT);
LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_4, LL_DMA_MEMORY_INCREMENT);
LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_4, LL_DMA_PDATAALIGN_BYTE);
LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_4, LL_DMA_MDATAALIGN_BYTE);
/* USART1 interrupt Init */
NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
NVIC_EnableIRQ(USART1_IRQn);
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
USART_InitStruct.BaudRate = 115200;
USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
USART_InitStruct.Parity = LL_USART_PARITY_NONE;
USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
LL_USART_Init(USART1, &USART_InitStruct);
LL_USART_ConfigAsyncMode(USART1);
LL_USART_Enable(USART1);
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/**
******************************************************************************
* @file stm32f1xx.h
* @author MCD Application Team
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F1xx device used in the target application
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f1xx
* @{
*/
#ifndef __STM32F1XX_H
#define __STM32F1XX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F1)
#define STM32F1
#endif /* STM32F1 */
/* Uncomment the line below according to the target STM32L device used in your
application
*/
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F100xB)
#include "stm32f100xb.h"
#elif defined(STM32F100xE)
#include "stm32f100xe.h"
#elif defined(STM32F101x6)
#include "stm32f101x6.h"
#elif defined(STM32F101xB)
#include "stm32f101xb.h"
#elif defined(STM32F101xE)
#include "stm32f101xe.h"
#elif defined(STM32F101xG)
#include "stm32f101xg.h"
#elif defined(STM32F102x6)
#include "stm32f102x6.h"
#elif defined(STM32F102xB)
#include "stm32f102xb.h"
#elif defined(STM32F103x6)
#include "stm32f103x6.h"
#elif defined(STM32F103xB)
#include "stm32f103xb.h"
#elif defined(STM32F103xE)
#include "stm32f103xe.h"
#elif defined(STM32F103xG)
#include "stm32f103xg.h"
#elif defined(STM32F105xC)
#include "stm32f105xc.h"
#elif defined(STM32F107xC)
#include "stm32f107xc.h"
#else
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F1xx_H */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file system_stm32f1xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f10x_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F10X_H
#define __SYSTEM_STM32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F10x_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F10X_H */
/**
* @}
*/
/**
* @}
*/

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This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the Apache-2.0 license shall apply.
You may obtain a copy of the Apache-2.0 at:
https://opensource.org/licenses/Apache-2.0

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.5
* @date 28. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.0
* @date 23. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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/**
******************************************************************************
* @file stm32f1xx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) MPU API to configure and enable regions
(MPU services provided only on some devices)
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_CORTEX_H
#define __STM32F1xx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
* @{
*/
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
* @{
*/
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
* @{
*/
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
* @{
*/
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
* @{
*/
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
* @{
*/
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
* @{
*/
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
{
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
else
{
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Constant number
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
* @retval Value should be equal to 0xF for Cortex-M3 devices
*/
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xC23 for Cortex-M3
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EF_MPU MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param Options This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
{
/* Enable the MPU*/
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU*/
WRITE_REG(MPU->CTRL, 0U);
}
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
}
/**
* @brief Enable a MPU region
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Configure and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RASR XN LL_MPU_ConfigRegion\n
* MPU_RASR AP LL_MPU_ConfigRegion\n
* MPU_RASR S LL_MPU_ConfigRegion\n
* MPU_RASR C LL_MPU_ConfigRegion\n
* MPU_RASR B LL_MPU_ConfigRegion\n
* MPU_RASR SIZE LL_MPU_ConfigRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Address Value of region base address
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
}
/**
* @brief Disable a region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RASR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_CORTEX_H */

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/**
******************************************************************************
* @file stm32f1xx_ll_exti.h
* @author MCD Application Team
* @brief Header file of EXTI LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_EXTI_H
#define STM32F1xx_LL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private Macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
* @{
*/
typedef struct
{
uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_MODE. */
uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
} LL_EXTI_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_LL_EC_LINE LINE
* @{
*/
#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
#if defined(EXTI_IMR_IM16)
#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
#endif
#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
#if defined(EXTI_IMR_IM18)
#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
#endif
#if defined(EXTI_IMR_IM19)
#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
#endif
#if defined(EXTI_IMR_IM20)
#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
#endif
#if defined(EXTI_IMR_IM21)
#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
#endif
#if defined(EXTI_IMR_IM22)
#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
#endif
#if defined(EXTI_IMR_IM23)
#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
#endif
#if defined(EXTI_IMR_IM24)
#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
#endif
#if defined(EXTI_IMR_IM25)
#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
#endif
#if defined(EXTI_IMR_IM26)
#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
#endif
#if defined(EXTI_IMR_IM27)
#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
#endif
#if defined(EXTI_IMR_IM28)
#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
#endif
#if defined(EXTI_IMR_IM29)
#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
#endif
#if defined(EXTI_IMR_IM30)
#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
#endif
#if defined(EXTI_IMR_IM31)
#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
#endif
#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
#if defined(USE_FULL_LL_DRIVER)
#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EC_MODE Mode
* @{
*/
#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */
#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */
/**
* @}
*/
/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
* @{
*/
#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */
#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */
#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */
#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
* @{
*/
/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in EXTI register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
/**
* @brief Read a value in EXTI register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->IMR, ExtiLine);
}
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->IMR, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
* @{
*/
/**
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->EMR, ExtiLine);
}
/**
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->EMR, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
* @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->RTSR, ExtiLine);
}
/**
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->RTSR, ExtiLine);
}
/**
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
* @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->FTSR, ExtiLine);
}
/**
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a Falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for the same interrupt line.
* In this case, both generate a trigger condition.
* @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->FTSR, ExtiLine);
}
/**
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
* @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
* @{
*/
/**
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
* resulting in an interrupt request generation.
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
* register (by writing a 1 into the bit)
* @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->SWIER, ExtiLine);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
* @{
*/
/**
* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
}
/**
* @brief Read ExtLine Combination Flag for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
}
/**
* @brief Clear ExtLine Flags for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
{
WRITE_REG(EXTI->PR, ExtiLine);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
* @{
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
uint32_t LL_EXTI_DeInit(void);
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* EXTI */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_EXTI_H */

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/**
******************************************************************************
* @file stm32f1xx_ll_pwr.h
* @author MCD Application Team
* @brief Header file of PWR LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_PWR_H
#define __STM32F1xx_LL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(PWR)
/** @defgroup PWR_LL PWR
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_PWR_WriteReg function
* @{
*/
#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
/**
* @}
*/
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_PWR_ReadReg function
* @{
*/
#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
/**
* @}
*/
/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
* @{
*/
#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
/**
* @}
*/
/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
* @{
*/
#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
/**
* @}
*/
/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
* @{
*/
#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
/**
* @}
*/
/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
* @{
*/
#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
* @{
*/
/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in PWR register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
/**
* @brief Read a value in PWR register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable access to the backup domain
* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->CR, PWR_CR_DBP);
}
/**
* @brief Disable access to the backup domain
* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
}
/**
* @brief Check if the backup domain is enabled
* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
{
return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
}
/**
* @brief Set voltage Regulator mode during deep sleep mode
* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
* @param RegulMode This parameter can be one of the following values:
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
{
MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
}
/**
* @brief Get voltage Regulator mode during deep sleep mode
* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
*/
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
{
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
}
/**
* @brief Set Power Down mode when CPU enters deepsleep
* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
* @rmtoll CR LPDS LL_PWR_SetPowerMode
* @param PDMode This parameter can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
* @arg @ref LL_PWR_MODE_STOP_LPREGU
* @arg @ref LL_PWR_MODE_STANDBY
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
{
MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
}
/**
* @brief Get Power Down mode when CPU enters deepsleep
* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
* @rmtoll CR LPDS LL_PWR_GetPowerMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
* @arg @ref LL_PWR_MODE_STOP_LPREGU
* @arg @ref LL_PWR_MODE_STANDBY
*/
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
{
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
}
/**
* @brief Configure the voltage threshold detected by the Power Voltage Detector
* @rmtoll CR PLS LL_PWR_SetPVDLevel
* @param PVDLevel This parameter can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
{
MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
}
/**
* @brief Get the voltage threshold detection
* @rmtoll CR PLS LL_PWR_GetPVDLevel
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
*/
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
{
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
}
/**
* @brief Enable Power Voltage Detector
* @rmtoll CR PVDE LL_PWR_EnablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePVD(void)
{
SET_BIT(PWR->CR, PWR_CR_PVDE);
}
/**
* @brief Disable Power Voltage Detector
* @rmtoll CR PVDE LL_PWR_DisablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
}
/**
* @brief Check if Power Voltage Detector is enabled
* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
{
return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
}
/**
* @brief Enable the WakeUp PINx functionality
* @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
{
SET_BIT(PWR->CSR, WakeUpPin);
}
/**
* @brief Disable the WakeUp PINx functionality
* @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
{
CLEAR_BIT(PWR->CSR, WakeUpPin);
}
/**
* @brief Check if the WakeUp PINx functionality is enabled
* @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
{
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
}
/**
* @}
*/
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get Wake-up Flag
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
}
/**
* @brief Get Standby Flag
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
}
/**
* @brief Indicate whether VDD voltage is below the selected PVD threshold
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
}
/**
* @brief Clear Standby Flag
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
{
SET_BIT(PWR->CR, PWR_CR_CSBF);
}
/**
* @brief Clear Wake-up Flags
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
{
SET_BIT(PWR->CR, PWR_CR_CWUF);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup PWR_LL_EF_Init De-initialization function
* @{
*/
ErrorStatus LL_PWR_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PWR) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_PWR_H */

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/**
******************************************************************************
* @file stm32f1xx_ll_system.h
* @author MCD Application Team
* @brief Header file of SYSTEM LL module.
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL SYSTEM driver contains a set of generic APIs that can be
used by user:
(+) Some of the FLASH features need to be handled in the SYSTEM file.
(+) Access to DBGCMU registers
(+) Access to SYSCFG registers
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_SYSTEM_H
#define __STM32F1xx_LL_SYSTEM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (FLASH) || defined (DBGMCU)
/** @defgroup SYSTEM_LL SYSTEM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
* @{
*/
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
* @{
*/
#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
#if defined(DBGMCU_CR_DBG_TIM5_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM5_STOP */
#if defined(DBGMCU_CR_DBG_TIM6_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM6_STOP */
#if defined(DBGMCU_CR_DBG_TIM7_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM7_STOP */
#if defined(DBGMCU_CR_DBG_TIM12_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM12_STOP */
#if defined(DBGMCU_CR_DBG_TIM13_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM13_STOP */
#if defined(DBGMCU_CR_DBG_TIM14_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM14_STOP */
#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
#if defined(DBGMCU_CR_DBG_CAN1_STOP)
#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
#if defined(DBGMCU_CR_DBG_CAN2_STOP)
#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_CAN2_STOP */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
#if defined(DBGMCU_CR_DBG_TIM8_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
#if defined(DBGMCU_CR_DBG_TIM9_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM9_STOP */
#if defined(DBGMCU_CR_DBG_TIM10_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM10_STOP */
#if defined(DBGMCU_CR_DBG_TIM11_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM11_STOP */
#if defined(DBGMCU_CR_DBG_TIM15_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM15_STOP */
#if defined(DBGMCU_CR_DBG_TIM16_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM16_STOP */
#if defined(DBGMCU_CR_DBG_TIM17_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM17_STOP */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
* @{
*/
#if defined(FLASH_ACR_LATENCY)
#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
#else
#endif /* FLASH_ACR_LATENCY */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
* @{
*/
/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
* @{
*/
/**
* @brief Return the device identifier
* @note For Low Density devices, the device ID is 0x412
* @note For Medium Density devices, the device ID is 0x410
* @note For High Density devices, the device ID is 0x414
* @note For XL Density devices, the device ID is 0x430
* @note For Connectivity Line devices, the device ID is 0x418
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
}
/**
* @brief Return the device revision identifier
* @note This field indicates the revision of the device.
For example, it is read as revA -> 0x1000,for Low Density devices
For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
For example, it is read as revA or 1 -> 0x1003,for XL Density devices
For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/**
* @brief Enable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Set Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
* @param PinAssignment This parameter can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
{
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
}
/**
* @brief Get Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
* @retval Returned value can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
{
return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
}
/**
* @brief Freeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Unfreeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Freeze APB2 peripherals
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Unfreeze APB2 peripherals
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->CR, Periphs);
}
/**
* @}
*/
#if defined(FLASH_ACR_LATENCY)
/** @defgroup SYSTEM_LL_EF_FLASH FLASH
* @{
*/
/**
* @brief Set FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
* @param Latency This parameter can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
}
/**
* @brief Get FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
}
/**
* @brief Enable Prefetch
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
}
/**
* @brief Disable Prefetch
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
}
/**
* @brief Check if Prefetch buffer is enabled
* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
{
return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
}
#endif /* FLASH_ACR_LATENCY */
/**
* @brief Enable Flash Half Cycle Access
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
}
/**
* @brief Disable Flash Half Cycle Access
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
}
/**
* @brief Check if Flash Half Cycle Access is enabled or not
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
{
return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (FLASH) || defined (DBGMCU) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_SYSTEM_H */

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/**
******************************************************************************
* @file stm32f1xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_UTILS_H
#define __STM32F1xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
#if defined(FLASH_ACR_LATENCY)
ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
#endif /* FLASH_ACR_LATENCY */
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
#if defined(RCC_PLL2_SUPPORT)
ErrorStatus LL_PLL_ConfigSystemClock_PLL2(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_PLLInitTypeDef *UTILS_PLL2InitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
#endif /* RCC_PLL2_SUPPORT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_UTILS_H */

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This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the BSD-3-Clause license shall apply.
You may obtain a copy of the BSD-3-Clause at:
https://opensource.org/licenses/BSD-3-Clause

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/**
******************************************************************************
* @file stm32f1xx_ll_dma.c
* @author MCD Application Team
* @brief DMA LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_dma.h"
#include "stm32f1xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (DMA1) || defined (DMA2)
/** @defgroup DMA_LL DMA
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup DMA_LL_Private_Macros
* @{
*/
#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
((__VALUE__) == LL_DMA_MODE_CIRCULAR))
#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
#if defined (DMA2)
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
((CHANNEL) == LL_DMA_CHANNEL_2) || \
((CHANNEL) == LL_DMA_CHANNEL_3) || \
((CHANNEL) == LL_DMA_CHANNEL_4) || \
((CHANNEL) == LL_DMA_CHANNEL_5) || \
((CHANNEL) == LL_DMA_CHANNEL_6) || \
((CHANNEL) == LL_DMA_CHANNEL_7))) || \
(((INSTANCE) == DMA2) && \
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
((CHANNEL) == LL_DMA_CHANNEL_2) || \
((CHANNEL) == LL_DMA_CHANNEL_3) || \
((CHANNEL) == LL_DMA_CHANNEL_4) || \
((CHANNEL) == LL_DMA_CHANNEL_5))))
#else
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
((CHANNEL) == LL_DMA_CHANNEL_2) || \
((CHANNEL) == LL_DMA_CHANNEL_3) || \
((CHANNEL) == LL_DMA_CHANNEL_4) || \
((CHANNEL) == LL_DMA_CHANNEL_5) || \
((CHANNEL) == LL_DMA_CHANNEL_6) || \
((CHANNEL) == LL_DMA_CHANNEL_7))))
#endif
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_LL_Exported_Functions
* @{
*/
/** @addtogroup DMA_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the DMA registers to their default reset values.
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are de-initialized
* - ERROR: DMA registers are not de-initialized
*/
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
{
DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
ErrorStatus status = SUCCESS;
/* Check the DMA Instance DMAx and Channel parameters*/
assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
/* Disable the selected DMAx_Channely */
CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
/* Reset DMAx_Channely control register */
LL_DMA_WriteReg(tmp, CCR, 0U);
/* Reset DMAx_Channely remaining bytes register */
LL_DMA_WriteReg(tmp, CNDTR, 0U);
/* Reset DMAx_Channely peripheral address register */
LL_DMA_WriteReg(tmp, CPAR, 0U);
/* Reset DMAx_Channely memory address register */
LL_DMA_WriteReg(tmp, CMAR, 0U);
if (Channel == LL_DMA_CHANNEL_1)
{
/* Reset interrupt pending bits for DMAx Channel1 */
LL_DMA_ClearFlag_GI1(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_2)
{
/* Reset interrupt pending bits for DMAx Channel2 */
LL_DMA_ClearFlag_GI2(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_3)
{
/* Reset interrupt pending bits for DMAx Channel3 */
LL_DMA_ClearFlag_GI3(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_4)
{
/* Reset interrupt pending bits for DMAx Channel4 */
LL_DMA_ClearFlag_GI4(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_5)
{
/* Reset interrupt pending bits for DMAx Channel5 */
LL_DMA_ClearFlag_GI5(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_6)
{
/* Reset interrupt pending bits for DMAx Channel6 */
LL_DMA_ClearFlag_GI6(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_7)
{
/* Reset interrupt pending bits for DMAx Channel7 */
LL_DMA_ClearFlag_GI7(DMAx);
}
else
{
status = ERROR;
}
return status;
}
/**
* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
* @arg @ref __LL_DMA_GET_INSTANCE
* @arg @ref __LL_DMA_GET_CHANNEL
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are initialized
* - ERROR: Not applicable
*/
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Check the DMA Instance DMAx and Channel parameters*/
assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
/* Check the DMA parameters from DMA_InitStruct */
assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
/*---------------------------- DMAx CCR Configuration ------------------------
* Configure DMAx_Channely: data transfer direction, data transfer mode,
* peripheral and memory increment mode,
* data size alignment and priority level with parameters :
* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
* - Mode: DMA_CCR_CIRC bit
* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
* - Priority: DMA_CCR_PL[1:0] bits
*/
LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
DMA_InitStruct->Mode | \
DMA_InitStruct->PeriphOrM2MSrcIncMode | \
DMA_InitStruct->MemoryOrM2MDstIncMode | \
DMA_InitStruct->PeriphOrM2MSrcDataSize | \
DMA_InitStruct->MemoryOrM2MDstDataSize | \
DMA_InitStruct->Priority);
/*-------------------------- DMAx CMAR Configuration -------------------------
* Configure the memory or destination base address with parameter :
* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
*/
LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
/*-------------------------- DMAx CPAR Configuration -------------------------
* Configure the peripheral or source base address with parameter :
* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
*/
LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
/*--------------------------- DMAx CNDTR Configuration -----------------------
* Configure the peripheral base address with parameter :
* - NbData: DMA_CNDTR_NDT[15:0] bits
*/
LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
return SUCCESS;
}
/**
* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval None
*/
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Set DMA_InitStruct fields to default values */
DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
DMA_InitStruct->NbData = 0x00000000U;
DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DMA1 || DMA2 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

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/**
******************************************************************************
* @file stm32f1xx_ll_exti.c
* @author MCD Application Team
* @brief EXTI LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_exti.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup EXTI_LL_Private_Macros
* @{
*/
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_LL_Exported_Functions
* @{
*/
/** @addtogroup EXTI_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the EXTI registers to their default reset values.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are de-initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_DeInit(void)
{
/* Interrupt mask register set to default reset values */
LL_EXTI_WriteReg(IMR, 0x00000000U);
/* Event mask register set to default reset values */
LL_EXTI_WriteReg(EMR, 0x00000000U);
/* Rising Trigger selection register set to default reset values */
LL_EXTI_WriteReg(RTSR, 0x00000000U);
/* Falling Trigger selection register set to default reset values */
LL_EXTI_WriteReg(FTSR, 0x00000000U);
/* Software interrupt event register set to default reset values */
LL_EXTI_WriteReg(SWIER, 0x00000000U);
/* Pending register clear */
LL_EXTI_WriteReg(PR, 0x000FFFFFU);
return SUCCESS;
}
/**
* @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
/* ENABLE LineCommand */
if (EXTI_InitStruct->LineCommand != DISABLE)
{
assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
/* Configure EXTI Lines in range from 0 to 31 */
if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
{
switch (EXTI_InitStruct->Mode)
{
case LL_EXTI_MODE_IT:
/* First Disable Event on provided Lines */
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable IT on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_EVENT:
/* First Disable IT on provided Lines */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Event on provided Lines */
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_IT_EVENT:
/* Directly Enable IT & Event on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
switch (EXTI_InitStruct->Trigger)
{
case LL_EXTI_TRIGGER_RISING:
/* First Disable Falling Trigger on provided Lines */
LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Rising Trigger on provided Lines */
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_FALLING:
/* First Disable Rising Trigger on provided Lines */
LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Falling Trigger on provided Lines */
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_RISING_FALLING:
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
}
}
}
/* DISABLE LineCommand */
else
{
/* De-configure EXTI Lines in range from 0 to 31 */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
}
return status;
}
/**
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval None
*/
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
EXTI_InitStruct->LineCommand = DISABLE;
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (EXTI) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

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/**
******************************************************************************
* @file stm32f1xx_ll_gpio.c
* @author MCD Application Team
* @brief GPIO LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_gpio.h"
#include "stm32f1xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
/** @addtogroup GPIO_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup GPIO_LL_Private_Macros
* @{
*/
#define IS_LL_GPIO_PIN(__VALUE__) ((((__VALUE__) & LL_GPIO_PIN_ALL)!= 0u) &&\
(((__VALUE__) & (~LL_GPIO_PIN_ALL))== 0u))
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_ANALOG) ||\
((__VALUE__) == LL_GPIO_MODE_FLOATING) ||\
((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
((__VALUE__) == LL_GPIO_MODE_ALTERNATE))
#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_DOWN) ||\
((__VALUE__) == LL_GPIO_PULL_UP))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_LL_Exported_Functions
* @{
*/
/** @addtogroup GPIO_LL_EF_Init
* @{
*/
/**
* @brief De-initialize GPIO registers (Registers restored to their default values).
* @param GPIOx GPIO Port
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are de-initialized
* - ERROR: Wrong GPIO Port
*/
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Force and Release reset on clock of GPIOx Port */
if (GPIOx == GPIOA)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA);
}
else if (GPIOx == GPIOB)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB);
}
else if (GPIOx == GPIOC)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC);
}
else if (GPIOx == GPIOD)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD);
}
#if defined(GPIOE)
else if (GPIOx == GPIOE)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE);
}
#endif
#if defined(GPIOF)
else if (GPIOx == GPIOF)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF);
}
#endif
#if defined(GPIOG)
else if (GPIOx == GPIOG)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG);
}
#endif
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
* @param GPIOx GPIO Port
* @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
* that contains the configuration information for the specified GPIO peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
* - ERROR: Not applicable
*/
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
uint32_t pinmask;
uint32_t pinpos;
uint32_t currentpin;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
/* ------------------------- Configure the port pins ---------------- */
/* Initialize pinpos on first pin set */
pinmask = ((GPIO_InitStruct->Pin) << GPIO_PIN_MASK_POS) >> GPIO_PIN_NB;
pinpos = POSITION_VAL(pinmask);
/* Configure the port pins */
while ((pinmask >> pinpos) != 0u)
{
/* skip if bit is not set */
if ((pinmask & (1u << pinpos)) != 0u)
{
/* Get current io position */
if (pinpos < GPIO_PIN_MASK_POS)
{
currentpin = (0x00000101uL << pinpos);
}
else
{
currentpin = ((0x00010001u << (pinpos - GPIO_PIN_MASK_POS)) | 0x04000000u);
}
if (GPIO_InitStruct->Mode == LL_GPIO_MODE_INPUT)
{
/* Check The Pull parameter */
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
/* Pull-up Pull-down resistor configuration*/
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
}
/* Check Pin Mode parameters */
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check speed and Output mode parameters */
assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
}
}
pinpos++;
}
return (SUCCESS);
}
/**
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
* @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
GPIO_InitStruct->Mode = LL_GPIO_MODE_FLOATING;
GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
GPIO_InitStruct->Pull = LL_GPIO_PULL_DOWN;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

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/**
******************************************************************************
* @file stm32f1xx_ll_pwr.c
* @author MCD Application Team
* @brief PWR LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_pwr.h"
#include "stm32f1xx_ll_bus.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(PWR)
/** @defgroup PWR_LL PWR
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_LL_Exported_Functions
* @{
*/
/** @addtogroup PWR_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the PWR registers to their default reset values.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PWR registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_PWR_DeInit(void)
{
/* Force reset of PWR clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
/* Release reset of PWR clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
return SUCCESS;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PWR) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

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/**
******************************************************************************
* @file stm32f1xx_ll_rcc.c
* @author MCD Application Team
* @brief RCC LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_rcc.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(RCC)
/** @defgroup RCC_LL RCC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RCC_LL_Private_Macros
* @{
*/
#if defined(RCC_PLLI2S_SUPPORT)
#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
#endif /* RCC_PLLI2S_SUPPORT */
#if defined(USB) || defined(USB_OTG_FS)
#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#endif /* USB */
#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup RCC_LL_Private_Functions RCC Private functions
* @{
*/
uint32_t RCC_GetSystemClockFreq(void);
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
uint32_t RCC_PLL_GetFreqDomain_SYS(void);
#if defined(RCC_PLLI2S_SUPPORT)
uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
#endif /* RCC_PLLI2S_SUPPORT */
#if defined(RCC_PLL2_SUPPORT)
uint32_t RCC_PLL2_GetFreqClockFreq(void);
#endif /* RCC_PLL2_SUPPORT */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCC_LL_Exported_Functions
* @{
*/
/** @addtogroup RCC_LL_EF_Init
* @{
*/
/**
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
* - HSE PLL, PLL2 & PLL3 are OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RCC_DeInit(void)
{
/* Set HSION bit */
LL_RCC_HSI_Enable();
/* Wait for HSI READY bit */
while (LL_RCC_HSI_IsReady() != 1U)
{}
/* Configure HSI as system clock source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
/* Wait till clock switch is ready */
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
{}
/* Reset PLLON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
/* Wait for PLL READY bit to be reset */
while (LL_RCC_PLL_IsReady() != 0U)
{}
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
/* Reset HSEON, HSEBYP & CSSON bits */
CLEAR_BIT(RCC->CR, (RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
#if defined(RCC_CR_PLL2ON)
/* Reset PLL2ON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
#endif /* RCC_CR_PLL2ON */
#if defined(RCC_CR_PLL3ON)
/* Reset PLL3ON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
#endif /* RCC_CR_PLL3ON */
/* Set HSITRIM bits to the reset value */
LL_RCC_HSI_SetCalibTrimming(0x10U);
#if defined(RCC_CFGR2_PREDIV1)
/* Reset CFGR2 register */
LL_RCC_WriteReg(CFGR2, 0x00000000U);
#endif /* RCC_CFGR2_PREDIV1 */
/* Disable all interrupts */
LL_RCC_WriteReg(CIR, 0x00000000U);
/* Clear reset flags */
LL_RCC_ClearResetFlags();
return SUCCESS;
}
/**
* @}
*/
/** @addtogroup RCC_LL_EF_Get_Freq
* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
* and different peripheral clocks available on the device.
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
* @note If SYSCLK source is PLL, function returns values based on
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
* @note (**) HSI_VALUE is a defined constant but the real value may vary
* depending on the variations in voltage and temperature.
* @note (***) HSE_VALUE is a defined constant, user has to ensure that
* HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result.
* @note The result of this function could be incorrect when using fractional
* value for HSE crystal.
* @note This function can be used by the user application to compute the
* baud-rate for the communication peripherals or configure other parameters.
* @{
*/
/**
* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
* must be called to update structure fields. Otherwise, any
* configuration based on this function will be incorrect.
* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
* @retval None
*/
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
{
/* Get SYSCLK frequency */
RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
/* HCLK clock frequency */
RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
/* PCLK1 clock frequency */
RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
/* PCLK2 clock frequency */
RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
}
#if defined(RCC_CFGR2_I2S2SRC)
/**
* @brief Return I2Sx clock frequency
* @param I2SxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2S2_CLKSOURCE
* @arg @ref LL_RCC_I2S3_CLKSOURCE
* @retval I2S clock frequency (in Hz)
*/
uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
{
uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
/* I2S1CLK clock frequency */
switch (LL_RCC_GetI2SClockSource(I2SxSource))
{
case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
i2s_frequency = RCC_GetSystemClockFreq();
break;
case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
default:
i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
break;
}
return i2s_frequency;
}
#endif /* RCC_CFGR2_I2S2SRC */
#if defined(USB) || defined(USB_OTG_FS)
/**
* @brief Return USBx clock frequency
* @param USBxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_USB_CLKSOURCE
* @retval USB clock frequency (in Hz)
* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
*/
uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
{
uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
/* USBCLK clock frequency */
switch (LL_RCC_GetUSBClockSource(USBxSource))
{
#if defined(RCC_CFGR_USBPRE)
case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
if (LL_RCC_PLL_IsReady())
{
usb_frequency = RCC_PLL_GetFreqDomain_SYS();
}
break;
case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
default:
if (LL_RCC_PLL_IsReady())
{
usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
}
break;
#endif /* RCC_CFGR_USBPRE */
#if defined(RCC_CFGR_OTGFSPRE)
/* USBCLK = PLLVCO/2
= (2 x PLLCLK) / 2
= PLLCLK */
case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
if (LL_RCC_PLL_IsReady())
{
usb_frequency = RCC_PLL_GetFreqDomain_SYS();
}
break;
/* USBCLK = PLLVCO/3
= (2 x PLLCLK) / 3 */
case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
default:
if (LL_RCC_PLL_IsReady())
{
usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
}
break;
#endif /* RCC_CFGR_OTGFSPRE */
}
return usb_frequency;
}
#endif /* USB */
/**
* @brief Return ADCx clock frequency
* @param ADCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_ADC_CLKSOURCE
* @retval ADC clock frequency (in Hz)
*/
uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
{
uint32_t adc_prescaler = 0U;
uint32_t adc_frequency = 0U;
/* Check parameter */
assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
/* Get ADC prescaler */
adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
/* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
/ (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
return adc_frequency;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup RCC_LL_Private_Functions
* @{
*/
/**
* @brief Return SYSTEM clock frequency
* @retval SYSTEM clock frequency (in Hz)
*/
uint32_t RCC_GetSystemClockFreq(void)
{
uint32_t frequency = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
switch (LL_RCC_GetSysClkSource())
{
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
frequency = HSI_VALUE;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
frequency = HSE_VALUE;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
frequency = RCC_PLL_GetFreqDomain_SYS();
break;
default:
frequency = HSI_VALUE;
break;
}
return frequency;
}
/**
* @brief Return HCLK clock frequency
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK clock frequency (in Hz)
*/
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
}
/**
* @brief Return PCLK1 clock frequency
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK1 clock frequency (in Hz)
*/
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK1 clock frequency */
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
}
/**
* @brief Return PCLK2 clock frequency
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK2 clock frequency (in Hz)
*/
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK2 clock frequency */
return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
}
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
/* Get PLL source */
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE / 2U;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
break;
#if defined(RCC_PLL2_SUPPORT)
case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
break;
#endif /* RCC_PLL2_SUPPORT */
default:
pllinputfreq = HSI_VALUE / 2U;
break;
}
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
}
#if defined(RCC_PLL2_SUPPORT)
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL2_GetFreqClockFreq(void)
{
return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
}
#endif /* RCC_PLL2_SUPPORT */
#if defined(RCC_PLLI2S_SUPPORT)
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
{
return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
}
#endif /* RCC_PLLI2S_SUPPORT */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RCC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

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/**
******************************************************************************
* @file stm32f1xx_ll_usart.c
* @author MCD Application Team
* @brief USART LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_usart.h"
#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
/** @addtogroup USART_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
*/
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
* divided by the smallest oversampling used on the USART (i.e. 8) */
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4500000U)
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|| ((__VALUE__) == LL_USART_PARITY_ODD))
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_2))
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USART_LL_Exported_Functions
* @{
*/
/** @addtogroup USART_LL_EF_Init
* @{
*/
/**
* @brief De-initialize USART registers (Registers restored to their default values).
* @param USARTx USART Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers are de-initialized
* - ERROR: USART registers are not de-initialized
*/
ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_UART_INSTANCE(USARTx));
if (USARTx == USART1)
{
/* Force reset of USART clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
/* Release reset of USART clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
}
else if (USARTx == USART2)
{
/* Force reset of USART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
/* Release reset of USART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
}
#if defined(USART3)
else if (USARTx == USART3)
{
/* Force reset of USART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
/* Release reset of USART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
}
#endif /* USART3 */
#if defined(UART4)
else if (USARTx == UART4)
{
/* Force reset of UART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
}
#endif /* UART4 */
#if defined(UART5)
else if (USARTx == UART5)
{
/* Force reset of UART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
}
#endif /* UART5 */
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
* that contains the configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
{
ErrorStatus status = ERROR;
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
LL_RCC_ClocksTypeDef rcc_clocks;
/* Check the parameters */
assert_param(IS_UART_INSTANCE(USARTx));
assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
#if defined(USART_CR1_OVER8)
assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
#endif /* USART_OverSampling_Feature */
/* USART needs to be in disabled state, in order to be able to configure some bits in
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
/*---------------------------- USART CR1 Configuration -----------------------
* Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
* - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
* - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
* - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
* - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
*/
#if defined(USART_CR1_OVER8)
MODIFY_REG(USARTx->CR1,
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
#else
MODIFY_REG(USARTx->CR1,
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
USART_CR1_TE | USART_CR1_RE),
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
USART_InitStruct->TransferDirection));
#endif /* USART_OverSampling_Feature */
/*---------------------------- USART CR2 Configuration -----------------------
* Configure USARTx CR2 (Stop bits) with parameters:
* - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
* - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
*/
LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
/*---------------------------- USART CR3 Configuration -----------------------
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
*/
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
/*---------------------------- USART BRR Configuration -----------------------
* Retrieve Clock frequency used for USART Peripheral
*/
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
if (USARTx == USART1)
{
periphclk = rcc_clocks.PCLK2_Frequency;
}
else if (USARTx == USART2)
{
periphclk = rcc_clocks.PCLK1_Frequency;
}
#if defined(USART3)
else if (USARTx == USART3)
{
periphclk = rcc_clocks.PCLK1_Frequency;
}
#endif /* USART3 */
#if defined(UART4)
else if (USARTx == UART4)
{
periphclk = rcc_clocks.PCLK1_Frequency;
}
#endif /* UART4 */
#if defined(UART5)
else if (USARTx == UART5)
{
periphclk = rcc_clocks.PCLK1_Frequency;
}
#endif /* UART5 */
else
{
/* Nothing to do, as error code is already assigned to ERROR value */
}
/* Configure the USART Baud Rate :
- valid baud rate value (different from 0) is required
- Peripheral clock as returned by RCC service, should be valid (different from 0).
*/
if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
&& (USART_InitStruct->BaudRate != 0U))
{
status = SUCCESS;
#if defined(USART_CR1_OVER8)
LL_USART_SetBaudRate(USARTx,
periphclk,
USART_InitStruct->OverSampling,
USART_InitStruct->BaudRate);
#else
LL_USART_SetBaudRate(USARTx,
periphclk,
USART_InitStruct->BaudRate);
#endif /* USART_OverSampling_Feature */
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
}
}
/* Endif (=> USART not in Disabled state => return ERROR) */
return (status);
}
/**
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
* @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
{
/* Set USART_InitStruct fields to default values */
USART_InitStruct->BaudRate = 9600U;
USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
#if defined(USART_CR1_OVER8)
USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
#endif /* USART_OverSampling_Feature */
}
/**
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
ErrorStatus status = SUCCESS;
/* Check USART Instance and Clock signal output parameters */
assert_param(IS_UART_INSTANCE(USARTx));
assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
/* USART needs to be in disabled state, in order to be able to configure some bits in
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
/*---------------------------- USART CR2 Configuration -----------------------*/
/* If Clock signal has to be output */
if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
{
/* Deactivate Clock signal delivery :
* - Disable Clock Output: USART_CR2_CLKEN cleared
*/
LL_USART_DisableSCLKOutput(USARTx);
}
else
{
/* Ensure USART instance is USART capable */
assert_param(IS_USART_INSTANCE(USARTx));
/* Check clock related parameters */
assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
/*---------------------------- USART CR2 Configuration -----------------------
* Configure USARTx CR2 (Clock signal related bits) with parameters:
* - Enable Clock Output: USART_CR2_CLKEN set
* - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
* - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
* - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
*/
MODIFY_REG(USARTx->CR2,
USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
}
}
/* Else (USART not in Disabled state => return ERROR */
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
* @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
/* Set LL_USART_ClockInitStruct fields with default values */
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */

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Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c Normal file
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@ -0,0 +1,767 @@
/**
******************************************************************************
* @file stm32f1xx_ll_utils.c
* @author MCD Application Team
* @brief UTILS LL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_utils.h"
#include "stm32f1xx_ll_system.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @addtogroup UTILS_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup UTILS_LL_Private_Constants
* @{
*/
/* Defines used for PLL range */
#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */
#define UTILS_PLL2_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL2 output, in Hz */
/* Defines used for HSE range */
#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */
#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */
/* Defines used for FLASH latency according to HCLK Frequency */
#if defined(FLASH_ACR_LATENCY)
#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
#else
/*!< No Latency Configuration in this device */
#endif
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup UTILS_LL_Private_Macros
* @{
*/
#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_16))
#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_2) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_4) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_8) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_16))
#if defined(RCC_CFGR_PLLMULL6_5)
#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
#else
#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_3) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_4) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_10) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_11) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_12) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_13) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_14) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_15) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_16))
#endif /* RCC_CFGR_PLLMULL6_5 */
#if defined(RCC_CFGR2_PREDIV1)
#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
#else
#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
#if defined(RCC_PLL2_SUPPORT)
#define IS_LL_UTILS_PLL2MUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL2_MUL_8) \
|| ((__VALUE__) == LL_RCC_PLL2_MUL_9) \
|| ((__VALUE__) == LL_RCC_PLL2_MUL_10) \
|| ((__VALUE__) == LL_RCC_PLL2_MUL_11) \
|| ((__VALUE__) == LL_RCC_PLL2_MUL_12) \
|| ((__VALUE__) == LL_RCC_PLL2_MUL_13) \
|| ((__VALUE__) == LL_RCC_PLL2_MUL_14) \
|| ((__VALUE__) == LL_RCC_PLL2_MUL_16) \
|| ((__VALUE__) == LL_RCC_PLL2_MUL_20))
#define IS_LL_UTILS_PREDIV2_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_1) || ((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_2) || \
((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_3) || ((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_4) || \
((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_5) || ((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_6) || \
((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_7) || ((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_8) || \
((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_9) || ((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_10) || \
((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_11) || ((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_12) || \
((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_13) || ((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_14) || \
((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_15) || ((__VALUE__) == LL_RCC_HSE_PREDIV2_DIV_16))
#define IS_LL_UTILS_PLL2_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL2_OUTPUT_MAX)
#endif /* RCC_PLL2_SUPPORT */
#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
* @{
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
static ErrorStatus UTILS_PLL_HSE_ConfigSystemClock(uint32_t PLL_InputFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
#if defined(RCC_PLL2_SUPPORT)
static uint32_t UTILS_GetPLL2OutputFrequency(uint32_t PLL2_InputFrequency,
LL_UTILS_PLLInitTypeDef *UTILS_PLL2InitStruct);
#endif /* RCC_PLL2_SUPPORT */
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_PLL_IsBusy(void);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UTILS_LL_Exported_Functions
* @{
*/
/** @addtogroup UTILS_LL_EF_DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
* @note When a RTOS is used, it is recommended to avoid changing the Systick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param HCLKFrequency HCLK frequency in Hz
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
* @retval None
*/
void LL_Init1msTick(uint32_t HCLKFrequency)
{
/* Use frequency provided in argument */
LL_InitTick(HCLKFrequency, 1000U);
}
/**
* @brief This function provides accurate delay (in milliseconds) based
* on SysTick counter flag
* @note When a RTOS is used, it is recommended to avoid using blocking delay
* and use rather osDelay service.
* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
* will configure Systick to 1ms
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
void LL_mDelay(uint32_t Delay)
{
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
/* Add this code to indicate that local variable is not used */
((void)tmp);
/* Add a period to guaranty minimum wait */
if (Delay < LL_MAX_DELAY)
{
Delay++;
}
while (Delay)
{
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
{
Delay--;
}
}
}
/**
* @}
*/
/** @addtogroup UTILS_EF_SYSTEM
* @brief System Configuration functions
*
@verbatim
===============================================================================
##### System Configuration functions #####
===============================================================================
[..]
System, AHB and APB buses clocks configuration
(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
@endverbatim
@internal
Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
(++) +-----------------------------------------------+
(++) | Latency | SYSCLK clock frequency (MHz) |
(++) |---------------|-------------------------------|
(++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
(++) |---------------|-------------------------------|
(++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
(++) |---------------|-------------------------------|
(++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
(++) +-----------------------------------------------+
@endinternal
* @{
*/
/**
* @brief This function sets directly SystemCoreClock CMSIS variable.
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
}
/**
* @brief Update number of Flash wait states in line with new frequency and current
voltage range.
* @param Frequency SYSCLK frequency
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
#if defined(FLASH_ACR_LATENCY)
ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
{
uint32_t timeout;
uint32_t getlatency;
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
ErrorStatus status = SUCCESS;
/* Frequency cannot be equal to 0 */
if (Frequency == 0U)
{
status = ERROR;
}
else
{
if (Frequency > UTILS_LATENCY2_FREQ)
{
/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
}
else
{
if (Frequency > UTILS_LATENCY1_FREQ)
{
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
}
else
{
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
latency = LL_FLASH_LATENCY_0;
}
}
if (status != ERROR)
{
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
timeout = 2;
do
{
/* Wait for Flash latency to be updated */
getlatency = LL_FLASH_GetLatency();
timeout--;
}
while ((getlatency != latency) && (timeout > 0));
if (getlatency != latency)
{
status = ERROR;
}
else
{
status = SUCCESS;
}
}
}
return status;
}
#endif /* FLASH_ACR_LATENCY */
/**
* @brief This function configures system clock with HSI as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
* @note Function is based on the following formula:
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
* - PREDIV: Set to 2 for few devices
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
* not exceed 72MHz
* @note FLASH latency can be modified through this function.
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t pllfreq = 0U;
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
{
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
/* Check PREDIV value */
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
#else
/* Force PREDIV value to 2 */
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
/* Enable HSI if not enabled */
if (LL_RCC_HSI_IsReady() != 1U)
{
LL_RCC_HSI_Enable();
while (LL_RCC_HSI_IsReady() != 1U)
{
/* Wait for HSI ready */
}
}
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
}
return status;
}
/**
* @brief This function configures system clock with HSE as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
* @note Function is based on the following formula:
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
* - PREDIV: Set to 2 for few devices
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
* not exceed @ref UTILS_PLL_OUTPUT_MAX
* @note FLASH latency can be modified through this function.
* @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
* @param HSEBypass This parameter can be one of the following values:
* @arg @ref LL_UTILS_HSEBYPASS_ON
* @arg @ref LL_UTILS_HSEBYPASS_OFF
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t pllfrequency = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
/* Calculate the new PLL output frequency */
pllfrequency = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
/* Enable HSE if not enabled */
status = UTILS_PLL_HSE_ConfigSystemClock(HSEFrequency, HSEBypass, UTILS_PLLInitStruct, UTILS_ClkInitStruct);
/* Check if HSE is not enabled*/
if (status == SUCCESS)
{
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_SYS((LL_RCC_PLLSOURCE_HSE | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfrequency, UTILS_ClkInitStruct);
}
return status;
}
#if defined(RCC_PLL2_SUPPORT)
/**
* @brief This function configures system clock with HSE as clock source of the PLL, via PLL2
* @note The application need to ensure that PLL and PLL2 are disabled.
* @note Function is based on the following formula:
* - PLL output frequency = ((((HSE frequency / PREDIV2) * PLL2MUL) / PREDIV) * PLLMUL)
* - PREDIV, PLLMUL, PREDIV2, PLL2MUL: The application software must set correctly the
* PLL multiplication factor to not exceed @ref UTILS_PLL_OUTPUT_MAX
* @note FLASH latency can be modified through this function.
* @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
* @param HSEBypass This parameter can be one of the following values:
* @arg @ref LL_UTILS_HSEBYPASS_ON
* @arg @ref LL_UTILS_HSEBYPASS_OFF
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_PLL2InitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL2.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_PLL2(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_PLLInitTypeDef *UTILS_PLL2InitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t pllfrequency = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
assert_param(IS_LL_UTILS_PREDIV2_VALUE(UTILS_PLL2InitStruct->Prediv));
/* Calculate the new PLL output frequency */
pllfrequency = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
/* Enable HSE if not enabled */
status = UTILS_PLL_HSE_ConfigSystemClock(HSEFrequency, HSEBypass, UTILS_PLLInitStruct, UTILS_ClkInitStruct);
/* Check if HSE is not enabled*/
if (status == SUCCESS)
{
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_PLL2(UTILS_PLL2InitStruct->Prediv, UTILS_PLL2InitStruct->PLLMul);
LL_RCC_PLL_ConfigDomain_SYS((LL_RCC_PLLSOURCE_PLL2 | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
/* Calculate the new PLL output frequency */
pllfrequency = UTILS_GetPLL2OutputFrequency(pllfrequency, UTILS_PLL2InitStruct);
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfrequency, UTILS_ClkInitStruct);
}
return status;
}
#endif /* RCC_PLL2_SUPPORT */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup UTILS_LL_Private_Functions
* @{
*/
/**
* @brief Function to check that PLL can be modified
* @param PLL_InputFrequency PLL input frequency (in Hz)
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @retval PLL output frequency (in Hz)
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
{
uint32_t pllfreq = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
/* Check different PLL parameters according to RM */
#if defined (RCC_CFGR2_PREDIV1)
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
#else
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
#endif /*RCC_CFGR2_PREDIV1SRC*/
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
return pllfreq;
}
/**
* @brief This function enable the HSE when it is used by PLL or PLL2
* @note The application need to ensure that PLL is disabled.
* @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
* @param HSEBypass This parameter can be one of the following values:
* @arg @ref LL_UTILS_HSEBYPASS_ON
* @arg @ref LL_UTILS_HSEBYPASS_OFF
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: HSE configuration done
* - ERROR: HSE configuration not done
*/
static ErrorStatus UTILS_PLL_HSE_ConfigSystemClock(uint32_t PLL_InputFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
{
/* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1U)
{
/* Check if need to enable HSE bypass feature or not */
if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
{
LL_RCC_HSE_EnableBypass();
}
else
{
LL_RCC_HSE_DisableBypass();
}
/* Enable HSE */
LL_RCC_HSE_Enable();
while (LL_RCC_HSE_IsReady() != 1U)
{
/* Wait for HSE ready */
}
}
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
}
return status;
}
#if defined(RCC_PLL2_SUPPORT)
/**
* @brief Function to check that PLL2 can be modified
* @param PLL2_InputFrequency PLL2 input frequency (in Hz)
* @param UTILS_PLL2InitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @retval PLL2 output frequency (in Hz)
*/
static uint32_t UTILS_GetPLL2OutputFrequency(uint32_t PLL2_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLL2InitStruct)
{
uint32_t pll2freq = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_PLL2MUL_VALUE(UTILS_PLL2InitStruct->PLLMul));
assert_param(IS_LL_UTILS_PREDIV2_VALUE(UTILS_PLL2InitStruct->Prediv));
/* Check different PLL2 parameters according to RM */
pll2freq = __LL_RCC_CALC_PLL2CLK_FREQ(PLL2_InputFrequency, UTILS_PLL2InitStruct->PLLMul, UTILS_PLL2InitStruct->Prediv);
assert_param(IS_LL_UTILS_PLL2_FREQUENCY(pll2freq));
return pll2freq;
}
#endif /* RCC_PLL2_SUPPORT */
/**
* @brief Function to check that PLL can be modified
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PLL modification can be done
* - ERROR: PLL is busy
*/
static ErrorStatus UTILS_PLL_IsBusy(void)
{
ErrorStatus status = SUCCESS;
/* Check if PLL is busy*/
if (LL_RCC_PLL_IsReady() != 0U)
{
/* PLL configuration cannot be modified */
status = ERROR;
}
#if defined(RCC_PLL2_SUPPORT)
/* Check if PLL2 is busy*/
if (LL_RCC_PLL2_IsReady() != 0U)
{
/* PLL2 configuration cannot be modified */
status = ERROR;
}
#endif /* RCC_PLL2_SUPPORT */
#if defined(RCC_PLLI2S_SUPPORT)
/* Check if PLLI2S is busy*/
if (LL_RCC_PLLI2S_IsReady() != 0U)
{
/* PLLI2S configuration cannot be modified */
status = ERROR;
}
#endif /* RCC_PLLI2S_SUPPORT */
return status;
}
/**
* @brief Function to enable PLL and switch system clock to PLL
* @param SYSCLK_Frequency SYSCLK frequency
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: No problem to switch system to PLL
* - ERROR: Problem to switch system to PLL
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
#if defined(FLASH_ACR_LATENCY)
uint32_t sysclk_frequency_current = 0U;
#endif /* FLASH_ACR_LATENCY */
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
#if defined(FLASH_ACR_LATENCY)
/* Calculate current SYSCLK frequency */
sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
#endif /* FLASH_ACR_LATENCY */
/* Increasing the number of wait states because of higher CPU frequency */
#if defined (FLASH_ACR_LATENCY)
if (sysclk_frequency_current < SYSCLK_Frequency)
{
/* Set FLASH latency to highest latency */
status = LL_SetFlashLatency(SYSCLK_Frequency);
}
#endif /* FLASH_ACR_LATENCY */
/* Update system clock configuration */
if (status == SUCCESS)
{
#if defined(RCC_PLL2_SUPPORT)
if (LL_RCC_PLL_GetMainSource() != LL_RCC_PLLSOURCE_HSI_DIV_2)
{
/* Enable PLL2 */
LL_RCC_PLL2_Enable();
while (LL_RCC_PLL2_IsReady() != 1U)
{
/* Wait for PLL2 ready */
}
}
#endif /* RCC_PLL2_SUPPORT */
/* Enable PLL */
LL_RCC_PLL_Enable();
while (LL_RCC_PLL_IsReady() != 1U)
{
/* Wait for PLL ready */
}
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
{
/* Wait for system clock switch to PLL */
}
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
}
/* Decreasing the number of wait states because of lower CPU frequency */
#if defined (FLASH_ACR_LATENCY)
if (sysclk_frequency_current > SYSCLK_Frequency)
{
/* Set FLASH latency to lowest latency */
status = LL_SetFlashLatency(SYSCLK_Frequency);
}
#endif /* FLASH_ACR_LATENCY */
/* Update SystemCoreClock variable */
if (status == SUCCESS)
{
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

15
MDK-ARM/.gitignore vendored Normal file
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@ -0,0 +1,15 @@
# dot files
/.vscode/launch.json
/.settings
/.eide/log
/.eide.usr.ctx.json
# project out
/build
/bin
/obj
/out
# eide template
*.ept
*.eide-template

9
MDK-ARM/EventRecorderStub.scvd Normal file
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@ -0,0 +1,9 @@
<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

21
MDK-ARM/RTE/_motor/RTE_Components.h Normal file
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@ -0,0 +1,21 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'motor'
* Target: 'motor'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "cs32f10x.h"
#endif /* RTE_COMPONENTS_H */

8
MDK-ARM/RTE_Components.h Normal file
View File

@ -0,0 +1,8 @@
/*-----------------------------------------------------------------------------------*/
/* Auto generate by EIDE, don't modify this file, any changes will be overwritten ! */
/*-----------------------------------------------------------------------------------*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#endif

851
MDK-ARM/motor.uvoptx Normal file
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@ -0,0 +1,851 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>motor</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath></ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>1</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0CS32F10x_128 -FS08000000 -FL020000 -FP0($$Device:CS32F103C8$Flash\CS32F10x_128.FLM))</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0CS32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:CS32F103C8$Flash\CS32F10x_128.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name></Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>buffer</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>app,0x0A</ItemText>
</Ww>
<Ww>
<count>2</count>
<WinNumber>1</WinNumber>
<ItemText>work,0x0A</ItemText>
</Ww>
<Ww>
<count>3</count>
<WinNumber>1</WinNumber>
<ItemText>ch</ItemText>
</Ww>
</WatchWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>1</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Application/MDK-ARM</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>startup_stm32f103xb.s</PathWithFileName>
<FilenameWithoutPath>startup_stm32f103xb.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Application/User/Core</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/gpio.c</PathWithFileName>
<FilenameWithoutPath>gpio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/dma.c</PathWithFileName>
<FilenameWithoutPath>dma.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/tim.c</PathWithFileName>
<FilenameWithoutPath>tim.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/usart.c</PathWithFileName>
<FilenameWithoutPath>usart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/stm32f1xx_it.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_it.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Drivers/CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Core/Src/system_stm32f1xx.c</PathWithFileName>
<FilenameWithoutPath>system_stm32f1xx.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>User/application</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\application\app.c</PathWithFileName>
<FilenameWithoutPath>app.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>User/system</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\system\src\btn.c</PathWithFileName>
<FilenameWithoutPath>btn.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\system\src\delay.c</PathWithFileName>
<FilenameWithoutPath>delay.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\system\src\sys.c</PathWithFileName>
<FilenameWithoutPath>sys.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\system\bsp\bsp.c</PathWithFileName>
<FilenameWithoutPath>bsp.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\system\bsp\gpios.c</PathWithFileName>
<FilenameWithoutPath>gpios.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\system\bsp\tims.c</PathWithFileName>
<FilenameWithoutPath>tims.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\system\bsp\uarts.c</PathWithFileName>
<FilenameWithoutPath>uarts.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\system\bsp\i2cs.c</PathWithFileName>
<FilenameWithoutPath>i2cs.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>User/lib</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\aes.c</PathWithFileName>
<FilenameWithoutPath>aes.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\clist.c</PathWithFileName>
<FilenameWithoutPath>clist.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\cmac.c</PathWithFileName>
<FilenameWithoutPath>cmac.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\cmd.c</PathWithFileName>
<FilenameWithoutPath>cmd.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\data_analysis.c</PathWithFileName>
<FilenameWithoutPath>data_analysis.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\debug.c</PathWithFileName>
<FilenameWithoutPath>debug.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>24</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\filter.c</PathWithFileName>
<FilenameWithoutPath>filter.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\lib.c</PathWithFileName>
<FilenameWithoutPath>lib.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\malloc.c</PathWithFileName>
<FilenameWithoutPath>malloc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\mlist.c</PathWithFileName>
<FilenameWithoutPath>mlist.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\pbuf.c</PathWithFileName>
<FilenameWithoutPath>pbuf.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\sqqueue.c</PathWithFileName>
<FilenameWithoutPath>sqqueue.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>30</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\storage.c</PathWithFileName>
<FilenameWithoutPath>storage.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>31</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\src\wl_flash.c</PathWithFileName>
<FilenameWithoutPath>wl_flash.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>6</GroupNumber>
<FileNumber>32</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\flow\flow_core.c</PathWithFileName>
<FilenameWithoutPath>flow_core.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Drivers/STM32F1xx_HAL_Driver</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>33</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_ll_gpio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>34</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_ll_dma.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_ll_pwr.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>36</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_ll_exti.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>37</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_ll_tim.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_ll_rcc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>39</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_ll_utils.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>40</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usart.c</PathWithFileName>
<FilenameWithoutPath>stm32f1xx_ll_usart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>User/board</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>8</GroupNumber>
<FileNumber>41</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\board\board.c</PathWithFileName>
<FilenameWithoutPath>board.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>User/lib/control</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>42</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\control\src\pid.c</PathWithFileName>
<FilenameWithoutPath>pid.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>43</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\control\src\pid_auto_tune.c</PathWithFileName>
<FilenameWithoutPath>pid_auto_tune.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>44</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\control\src\pid_common.c</PathWithFileName>
<FilenameWithoutPath>pid_common.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>45</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\control\src\pid_fuzzy.c</PathWithFileName>
<FilenameWithoutPath>pid_fuzzy.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>9</GroupNumber>
<FileNumber>46</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\lib\control\src\pid_neural.c</PathWithFileName>
<FilenameWithoutPath>pid_neural.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

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MDK-ARM/motor.uvprojx Normal file
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@ -0,0 +1,510 @@
:020000040800F2
:10000000802C002005010008950D0008AB010008B8
:10001000910D00087101000879130008000000002C
:10002000000000000000000000000000E5100008D3
:10003000A901000800000000E50F0008E710000813
:100040001F0100081F0100081F0100081F01000810
:100050001F0100081F0100081F0100081F01000800
:100060001F0100081F0100081F0100081F010008F0
:100070001F0100081F0100088901000899010008FC
:100080001F0100081F0100081F0100081F010008D0
:100090001F0100081F0100081F0100081F010008C0
:1000A0001F010008DD1100081F0100081F010008E2
:1000B0001F010008AD1200081F0100081F01000801
:1000C0001F0100081F0100081F0100081F01000890
:1000D0001F010008691300081F0100081F01000824
:1000E0001F0100081F0100081F010008DFF810D0E1
:1000F00000F02CF800480047C5150008AFF3008059
:10010000802C00200648804706480047FEE7FEE7AF
:10011000FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE7B7
:10012000D9110008ED000008D2B201E000F8012B5F
:10013000491EFBD270470022F6E710B513460A4667
:1001400004461946FFF7F0FF204610BD064C074D48
:1001500006E0E06840F0010394E807009847103497
:10016000AC42F6D3FFF7C6FF141F0008341F000887
:1001700000BFFEE7024600BF1AB901E000BF00BFA2
:10018000FCE700BF0120704710B50248006801F08D
:1001900098FB10BD5C00002010B50248006801F01B
:1001A00090FB10BD5C000020704700BFFEE7000020
:1001B00008B50549C9690143034AD1611146C969B6
:1001C0000140009100BF08BD0010024008B505497C
:1001D00089690143034A916111468969014000918F
:1001E00000BF08BD0010024008B5054989690143F8
:1001F000034A9161114689690140009100BF08BD21
:100200000010024008B5054989690143034A91611C
:10021000114689690140009100BF08BD00100240ED
:1002200010B54A1E044B9A5C825822F001034A1E04
:10023000014CA25C835010BDB81E000810B54A1EC8
:10024000044B9A5C825842F001034A1E014CA25CA6
:10025000835010BDB81E000810B54A1E044B9A5CAE
:10026000825842F002034A1E014CA25C835010BD2A
:10027000B81E000830B54B1E054CE35CC35823F490
:10028000405313434C1E024D2C5D035130BD000002
:10029000761E000830B54B1E064CE35C03445B68D9
:1002A0006FF30F0313434C1E024D2C5D0444636037
:1002B00030BD0000B81E000830B54B1E054CE35C95
:1002C000C35844F21004A34313434C1E014D2C5D4C
:1002D000035130BD761E000810B54B1E024CE35C86
:1002E0000344DA6010BD0000B81E000830B54B1E94
:1002F000054CE35CC35823F0800313434C1E024DAE
:100300002C5D035130BD0000761E000830B54B1E39
:10031000054CE35CC35823F4406313434C1E024D69
:100320002C5D035130BD0000761E000830B54B1E19
:10033000054CE35CC35823F0200313434C1E024DCD
:100340002C5D035130BD0000761E000810B54B1E19
:10035000024CE35C03449A6010BD0000B81E000824
:1003600030B54B1E054CE35CC35823F040031343E8
:100370004C1E024D2C5D035130BD0000761E00085E
:1003800030B54B1E054CE35CC35823F44073134354
:100390004C1E024D2C5D035130BD0000761E00083E
:1003A0002DE9F04102460B461868C0F30F2595FA77
:1003B000A5F0B0FA80F480E00120A0402840002899
:1003C0007AD0082C04D240F2011000FA04F106E0C1
:1003D000A4F108004FF00116864046F0806158688D
:1003E00008280ED11869D66826EA11260F0A97FA4E
:1003F000A7F7B7FA87F700FA07F73E43D66000BFC2
:1004000000BF586802EB116691FAA1FCBCFA8CFCA3
:100410004FEA8C084FF00F0C0CFA08FC376827EAFB
:100420000C0791FAA1FCBCFA8CFC4FEA8C0C00FA88
:100430000CFC47EA0C07376000BF5868012802D05F
:100440005868092838D1986802EB116691FAA1FC26
:10045000BCFA8CFC4FEA8C084FF0030C0CFA08FC39
:10046000376827EA0C0791FAA1FCBCFA8CFC4FEA2A
:100470008C0C00FA0CFC47EA0C07376000BFD86808
:1004800002EB116691FAA1FCBCFA8CFC4FEA8C08D5
:100490004FF0040C0CFA08FC376827EA0C0791FAB5
:1004A000A1FCBCFA8CFC4FEA8C0C00FA0CFC47EA6D
:1004B0000C07376000BF00BF641C25FA04F0002859
:1004C0007FF47AAFBDE8F081C1F30F22426170473B
:1004D00002480068401C0149086070472000002065
:1004E0004FF47A71B0FBF1F2521E4FF0E0235A61E3
:1004F00000229A6105221A6100BF704710B50446B8
:1005000000F0A6FD2060206800F06EFD606060686D
:1005100000F07AFDA060606800F088FDE06010BD2A
:10052000014908607047000000000020016821F0C8
:10053000800101607047816821F08001816070470F
:10054000016841F0010101607047C16841F001019B
:10055000C160704710B5024613681C48824208D03B
:10056000B2F1804F05D01A48824202D01948824227
:1005700004D123F070004C6840EA0403134882421F
:1005800008D0B2F1804F05D01148824202D0114804
:10059000824204D123F44070CC6840EA0403136023
:1005A0008868D06200BF0888906200BF0748824216
:1005B00003D10869106300BF00BF00BF506940F05D
:1005C0000100506100BF002010BD0000002C014060
:1005D000000400400008004001460869C0F34000E4
:1005E000704701460869C0F38000704701460869FA
:1005F000C0F3C000704701460869C0F3001070479F
:100600000146086900F0010070470146C868C0F360
:10061000400070470146C868C0F38000704701463B
:10062000C868C0F3C00070470146C868C0F3001036
:1006300070470146C86800F00100704770B5024677
:10064000012901D1002416E0042901D1012412E07E
:10065000102901D102240EE0402901D103240AE02F
:10066000B1F5807F01D1042405E0B1F5806F01D19F
:10067000052400E006242346064CE55C02F118043C
:1006800028190468044DEE5C0425B5402C43046031
:1006900070BD0000531E00085A1E000870B50246C7
:1006A000012901D1002416E0042901D1012412E01E
:1006B000102901D102240EE0402901D103240AE0CF
:1006C000B1F5807F01D1042405E0B1F5806F01D13F
:1006D000052400E006242346064CE55C02F11804DC
:1006E00028190468044DEE5C0825B5402C430460CD
:1006F00070BD0000531E00085A1E00082DE9F0418D
:1007000006460C4615460127012C08D0102C0CD0AB
:10071000B4F5807F0FD0B4F5805F18D111E0294681
:10072000304600F079FB074612E02946304600F0DB
:10073000AFFB07460CE02946304600F0EBFB0746CE
:1007400006E02946304600F021FC074600E000BFE5
:1007500000BF3846BDE8F08181637047826844F28B
:1007600007039A430A4382607047426822F070028E
:100770000A434260704708B50168009100BF4168B4
:10078000009100BF08BD6FF040010160704700009C
:100790002DE9FF4104460D4601270026204600F0C2
:1007A00055F8002833D1E968686808432969084387
:1007B000E16841F20C6291430843E060A868216956
:1007C00021F440510143216100BF6869616921F44E
:1007D00040710143616100BF6846FFF78FFE0E481C
:1007E000844201D1039E08E00C48844201D1029E5C
:1007F00003E00B48844200D1029E46B1286830B124
:100800000027314620462A6800F025F800BF384608
:1008100004B0BDE8F0810000003801400044004011
:100820000048004001460868C0F340007047014698
:100830000868C0F38000704701460868C0F3C00034
:10084000704701460868C0F3801070470146C868C9
:10085000C0F34030704770B501EBC10303EB0113E7
:100860009400B3FBF4F301EBC10404EB0114950015
:10087000B4FBF5F46425B4FBF5F404EBC40505EB17
:100880000414A3EB8403322404EB03136424B3FBAA
:10089000F4F303F0F00301EBC10404EB0114950041
:1008A000B4FBF5F46425B4FBF5F403EB041401EB9D
:1008B000C10303EB01139500B3FBF5F301EBC10595
:1008C00005EB01159600B5FBF6F56426B5FBF6F5CC
:1008D00005EBC50606EB0515A3EB8503322505EBF5
:1008E00003136425B3FBF5F303F00F0323449BB21A
:1008F000836070BD38B50120144949690143134A2A
:100900005161114649690140009100BF00BF00F0EC
:100910004FFD05460022114600F03EFA04462146EE
:100920000E2000F055FD0E2000F028FD00F040FDE7
:1009300005460022114600F02FFA044621460F20FA
:1009400000F046FD0F2000F019FD38BD00100240F8
:1009500000B585B014216846FFF7EDFB1020FFF7C6
:1009600035FC2020FFF732FC0420FFF72FFC082085
:10097000FFF72CFC1C491D48FFF7A6FD1C491D482C
:10098000FFF7A2FD1848009001200190022002907C
:100990000020039069461548FFF702FD16480090B5
:1009A0000020019069461148FFF7FAFC13480090B7
:1009B0000020019069461248FFF7F2FC11480090B0
:1009C0000020019069460B48FFF7EAFC08480090B8
:1009D0000120019003200290002003906946054801
:1009E000FFF7DEFC05B000BD200020040010014030
:1009F00030003004000C0140C000C004FDFD99042B
:100A000000080140FFFFCF0430B585B014216846CF
:100A1000FFF791FB4FF40060FFF7E6FB00F0D0FC1E
:100A200005460022032100F0D7F90446214619208B
:100A300000F0E2FC192000F0AEFC41F61F40ADF8DA
:100A40000000002001906320029000200390049099
:100A500069460948FFF77EFD0748FFF767FD00215B
:100A60000548FFF77BFE00210348FFF77EFE0248A2
:100A7000FFF761FD05B030BD002C014000B593B01B
:100A800014210EA8FFF757FB202106A8FFF753FB00
:100A9000142101A8FFF74FFB0120FFF789FB00207D
:100AA000ADF838000F9041F61F40109000201190D3
:100AB0000EA94FF08040FFF74DFD00BF4FF0804082
:100AC000006840F080004FF08041086000BF0021C6
:100AD0004FF08040FFF742FE10218806FFF7DEFD51
:100AE00070200690002007900890099002200A903C
:100AF00006AA10214007FFF701FE10218806FFF724
:100B00009DFD00214FF08040FFF72FFE4FF0804009
:100B1000FFF711FD0420FFF767FB40F20220019070
:100B200009200290022003900020049001A90248AD
:100B3000FFF736FC13B000BD0008014030B585B0AA
:100B400014216846FFF7F7FA0220FFF731FB00F0A7
:100B500037FC05460022032100F03EF904462146F9
:100B60001D2000F049FC1D2000F015FC41F61F403F
:100B7000ADF8000000200190632002900020039057
:100B800069460948FFF7E6FC0748FFF7CFFC00215C
:100B90000548FFF7E3FD00210348FFF7E6FD0248A3
:100BA000FFF7C9FC05B030BD000400402DE9F0415D
:100BB0008CB01C2105A8FFF7BEFA14216846FFF788
:100BC000BAFA4FF48040FFF71DFB0420FFF71AFB31
:100BD00068480090092001900320029000200390B3
:100BE00069466548FFF7DCFB6448009004200190EB
:100BF00069466148FFF7D4FB002205216048FFF7F2
:100C00005BFB002205215E48FFF734FB0022052133
:100C10005B48FFF78BFB002205215948FFF7A0FB3B
:100C2000802205215648FFF761FB00220521544828
:100C3000FFF7A6FB002205215148FFF767FB1022B2
:100C400004214F48FFF738FB002204214C48FFF7EE
:100C500011FB002204214A48FFF768FB002204210F
:100C60004748FFF77DFB802204214548FFF73EFB04
:100C7000002204214248FFF783FB00220421404860
:100C8000FFF744FB25213F4B1B68C3F302200524DB
:100C900000250346C3F1070CBCF1040F02D94FF045
:100CA000040C01E0C3F1070C674603F1040CBCF12E
:100CB000070F02D24FF0000C01E0A3F1030C6646CF
:100CC0004FF0010C0CFA07FCACF1010C0CEA040C1F
:100CD0000CFA06FC4FF0010808FA06F8A8F1010822
:100CE00008EA05084CEA080200BF002904DB1007E7
:100CF000030E2548435407E01007040E21480C302A
:100D000001F00F031B1FC45400BF2520002809DB7E
:100D100000F01F02012191404209920002F1E022FD
:100D2000C2F8001100BF4FF4E1300590002006909A
:100D3000079008900C20099000200A900B9005A9BC
:100D40001248FFF725FD00BF1048006920F49040CD
:100D50000E4908610846406920F02A00486100BF3A
:100D600000BF0846C06840F40050C86000BF0CB027
:100D7000BDE8F08102000204000801400400040400
:100D8000000002400CED00E000E400E0003801400B
:100D900000BFFEE700BFFEE7F0B503460C4603F0D8
:100DA0000701C1F10700042801D9042001E0C1F1C5
:100DB00007000646081D072801D2002000E0C81ED3
:100DC00005460120B040401E2040A8400127AF400A
:100DD0007F1E17403843F0BDF0B503460C4603F0C4
:100DE0000701C1F10700042801D9042001E0C1F185
:100DF00007000646081D072801D2002000E0C81E93
:100E000005460120B040401E2040A8400127AF40C9
:100E10007F1E17403843F0BD70B50246106A20F0BF
:100E200001001062136A5568946924F0030424F0E9
:100E300070000E6840EA060423F002000E6940EAE2
:100E4000060323F001004E6840EA06030F48824281
:100E500013D123F008004E6940EA860323F0040012
:100E60008E6840EA860325F480708E6940EA0605A4
:100E700025F40070CE6940EA460555609461C86863
:100E8000506300BF1362002070BD0000002C0140C1
:100E90002DE9F04104460D46206A20F01000206242
:100EA000266AD4F80480A76927F4407727F4E04045
:100EB000296840EA012726F02000296940EA011646
:100EC00026F01000696840EA01161148844213D1E7
:100ED00026F08000696940EA811626F04000A96882
:100EE00040EA811628F48060A96940EA810828F464
:100EF0000060E96940EAC108C4F80480A76120469F
:100F0000E968FFF729FC26620020BDE8F0810000B7
:100F1000002C014070B50246106A20F48070106207
:100F2000136A5568D46924F0030424F070000E6835
:100F300040EA060423F400700E6940EA062323F415
:100F400080704E6840EA06230F48824213D123F492
:100F500000604E6940EA862323F480608E6840EA90
:100F6000862325F480508E6940EA061525F400504A
:100F7000CE6940EA46155560D461C868D06300BFA9
:100F80001362002070BD0000002C014070B50246C5
:100F9000106A20F480501062146A5568D36923F4F3
:100FA000407323F4E0400E6840EA062324F4005026
:100FB0000E6940EA063424F480504E6840EA063454
:100FC0000748824204D125F480408E6940EA8615A4
:100FD0005560D361C868106400BF1462002070BD02
:100FE000002C014070470000014600BF04484068E3
:100FF00000F0F0000009034A125C21FA02F0704789
:1010000000100240A01E0008014600BF05484068CD
:1010100000F4E060044A02EB1020027821FA02F0AA
:101020007047000000100240B01E0008014600BFDB
:101030000548406800F46050044A02EBD020027872
:1010400021FA02F07047000000100240B01E0008B4
:1010500010B5002400BF0B48406800F00C0020B120
:10106000042804D0082808D103E0074C07E0064C08
:1010700005E000F00BF8044601E0034C00BF00BFA0
:10108000204610BD0010024000127A00002100220C
:1010900000BF1148406800F4803002461AB1B2F532
:1010A000803F0CD101E00D490BE000BF0A484068C9
:1010B000C0F34040401C0A4BB3FBF0F101E007498C
:1010C00000BF00BF00BF0448406800F47010022356
:1010D00003EB9040484370470010024000093D0078
:1010E00000127A007047704710B50220374909682E
:1010F00021F007010143354A116000BF00BF00BF66
:101100003248006800F007000228F8D100BF3048DC
:10111000006840F480302E49086000BF00BF00BF67
:101120002B480068C0F340400028F8D04FF48030CE
:101130004FF4E011264A526822F47C1200F4403346
:101140000B431A43224B5A6000BF00BF1846006889
:1011500040F080701946086000BF00BF00BF1C4807
:101160000068C0F340600028F8D0002018494968A2
:1011700021F0F0010143164A516000BF10151146DD
:10118000496821F4E0610143516000BF002011462D
:10119000496821F460510143516000BF02201146AB
:1011A000496821F003010143516000BF00BF00BF47
:1011B0000748406800F00C000828F8D10548FFF700
:1011C0008FF90448FFF7ACF910BD00000020024081
:1011D0000010024000A24A047047000010B53148D8
:1011E000FFF70EFA01285CD100BF2E48FFF7F4F993
:1011F00001280AD12B48FFF708FA012805D100BFC2
:10120000001F2849086100BF00BF2648FFF7E9F921
:1012100001280AD12348FFF7FDF9012805D100BFB5
:10122000801F2049086100BF00BF1E48FFF7DEF99C
:1012300001280BD11B48FFF7F2F9012806D100BFA6
:101240006FF008001749086100BF00BF1548FFF79D
:10125000D2F901280BD11348FFF7E6F9012806D18E
:1012600000BF6FF010000F49086100BF00BF0D48BC
:10127000FFF7C6F901280AD10A48FFF7DAF9012871
:1012800005D100BFC01E0749086100BF00BF00BFF5
:10129000FFF71EF900BF04480068401C02490860BF
:1012A00000BF10BD002C01405800002010B52D4893
:1012B000FFF7A6F9012853D100BF2A48FFF78CF9A0
:1012C00001280AD12748FFF7A0F9012805D100BF5E
:1012D000001F2449086100BF00BF2248FFF781F9C1
:1012E00001280AD11F48FFF795F9012805D100BF51
:1012F000801F1C49086100BF00BF1A48FFF776F93C
:1013000001280BD11748FFF78AF9012806D100BF41
:101310006FF008001349086100BF00BF1148FFF7D4
:101320006AF901280BD10F48FFF77EF9012806D191
:1013300000BF6FF010000B49086100BF00BF0948F3
:10134000FFF75EF901280AD10648FFF772F9012874
:1013500005D100BFC01E0349086100BF00BF00BF28
:1013600010BD00000004004010B50248006800F005
:10137000D3FB10BD5C00002000BFFEE7002809DBA6
:1013800000F01F02012191404209920002F1E02287
:10139000C2F800117047002809DB00F01F0201218C
:1013A00091404209920002F1E022C2F80011704718
:1013B00002480068C0F30220704700000CED00E016
:1013C00002480068C0F30220704700000CED00E006
:1013D00010B5002804DB0A07130E054A135406E073
:1013E0000A07140E034A00F00F031B1FD45410BD4C
:1013F00000E400E018ED00E010B5002804DB0A0767
:10140000130E054A135406E00A07140E034A00F0AF
:101410000F031B1FD45410BD00E400E018ED00E0E2
:1014200002E008C8121F08C1002AFAD170477047AD
:10143000002001E001C1121F002AFBD1704700000B
:10144000014601F1100000E0001D02681AB9024ACD
:1014500012689042F8D370473400002010B5064857
:10146000046803E02046FFF7EBFF044603480068EA
:101470008442F7D310BD000030000020340000206B
:1014800010B504462146002000F090F910BD10B5BB
:1014900001E000F8011B131EA2F10104A2B2F8D171
:1014A00010BD000010B500200A4908600A49086014
:1014B00000BF0A48FFF744F80848FFF746F800BFA6
:1014C00000BF0748FFF73CF80548FFF73EF800BFAC
:1014D00010BD0000040000200C000020002C014082
:1014E0000004004010B5034800F00CF8024800F07A
:1014F00033F810BD040000200C00002010B500F0EF
:10150000DBFA10BD08B5014600200090086810B154
:10151000122813D108E000BF00BF0B4800684860E4
:1015200000BF1220086000BF074A48681268101AFE
:101530000A2801D2002008BD00BFEDE700200860A6
:1015400000900320F7E700005800002001490860E0
:10155000704700001C00002038B5014600200090B4
:10156000086810B1252821D116E000BF124B134C9A
:10157000E068C3F30F2222EA000400EA020544EA0D
:1015800005440E4D2C6100BF00BF0D480068486047
:1015900000BF2520086000BF094A48681268101A79
:1015A000642801D2002038BD00BFDFE700200860BA
:1015B00000900320F7E70000200020040010014005
:1015C0005800002008B50120274989690143264AAF
:1015D0009161114689690140009100BF00BF000779
:1015E0001146C9690143D1611146C96901400091A1
:1015F00000BF00BF032002461C4B19684FF6FF03D3
:1016000019401B4B0B4343EA0221184B196000BFE2
:1016100000BF1848406820F0E06040F000701549B5
:10162000486000BFFFF760FD134800681349B0FB36
:10163000F1F084B22046FFF789FFFFF789F9FFF741
:1016400059F9FFF71BFAFFF7B1FAFFF7DDF9FFF7DA
:1016500075FA002000F014F8FFF750FFFFF722FFA3
:1016600001E0FFF73FFFFCE7001002400CED00E057
:101670000000FA05000001400000002040420F0079
:1016800010B504460C4951F824104A000B4951F892
:101690002400002100F09EF8094951F82420074950
:1016A000083951F82400002100F094F80121034882
:1016B0000830015510BD0000FC1E00084C00002041
:1016C0000C1F00082DE9F04704460F460025A946E7
:1016D0002348005D20B92248183801682046884711
:1016E0001FB94FF0FF30BDE8F0871E4850F82400C6
:1016F000B7FBF0F61B4850F82400B7FBF0F100FBF5
:10170000117000B1761C184850F82400451E22E0E4
:101710001348083850F8240030F8150010B909F1C2
:10172000010901E04FF00009B14513D14FF0000865
:1017300009E00B48083850F8240005EB080220F8AF
:10174000126008F10108B045F3D3064850F82400B0
:101750006843C8E76D1E002DDADA4FF0FF30C2E7AC
:1017600054000020041F0008FC1E000810B50146AC
:101770000023002207E00B4850F8210030F8120047
:1017800000B15B1C521C084850F821009042F2D86E
:1017900064205843044C54F82140B0FBF4F0C0B22C
:1017A00010BD00004C000020FC1E000870B504466F
:1017B0000E4631462046FFF785FF0546681C08B9EE
:1017C000002070BD024850F824002844F9E70000CA
:1017D0004400002030B5034601E003F8011B141E4D
:1017E000A2F10102F9D130BD10B5044604B910BD13
:1017F00000202085A07D012808D1606A30B1218CAD
:1018000089040A0C0021606AFFF741FE00BFEEE781
:101810002DE9F05F0646884615469946DDE90B7BC3
:10182000DDF828A00EB1012100E0002108462921A1
:10183000FEF7A0FC4420FFF723FE04460CB1012173
:1018400000E0002108462C21FEF794FC0120E07501
:1018500000202076C4F83C902584C4F840B0A786C8
:10186000002D0CDD2846FFF70BFEE061E16909B1B0
:10187000012100E0002108463E21FEF77BFC002FFD
:101880000CDD3846FFF7FCFD2063216B09B1012117
:1018900000E0002108464521FEF76CFC84F8158025
:1018A00084F82CA066602046BDE8F09F10B5044681
:1018B00004B910BD002060852046FFF795FF00BFEA
:1018C000F7E710B504460CB1012100E000210846FD
:1018D00040F2D711FEF74EFC012084F83800216950
:1018E000A068FEF79DFC2069082865D2DFE800F0BB
:1018F0006404111E2C3A485600BFA0680168C1F369
:10190000400121B1A0680221416000BF00BF00BFBB
:1019100053E000BFA0680168C1F3401121B1A06885
:101920002021416000BF00BF00BF46E000BFA068AB
:101930000168C1F3402129B1A0684FF400714160F2
:1019400000BF00BF00BF38E000BFA0680168C1F35E
:10195000403129B1A0684FF40051416000BF00BF81
:1019600000BF2AE000BFA0680168C1F3404129B16F
:10197000A0684FF40031416000BF00BF00BF1CE011
:1019800000BFA0680168C1F3405129B1A0684FF4BD
:101990000011416000BF00BF00BF0EE000BFA068A3
:1019A0000168C1F3406129B1A0684FF00071416046
:1019B00000BF00BF00BF00E000BF00BF606800BF05
:1019C00000BF00BF00F10C0252E8002F42F04001BE
:1019D00000F10C0242E80013002BF3D100BF00BF5E
:1019E0002069082865D2DFE800F06404111E2C3A53
:1019F000485600BFA0680168C1F3C00121B1A068CA
:101A00000821416000BF00BF00BF53E000BFA068D5
:101A10000168C1F3C01121B1A0688021416000BFFD
:101A200000BF00BF46E000BFA0680168C1F3C0214D
:101A300029B1A0684FF40061416000BF00BF00BF42
:101A400038E000BFA0680168C1F3C03129B1A068C7
:101A50004FF40041416000BF00BF00BF2AE000BF5B
:101A6000A0680168C1F3C04129B1A0684FF400210A
:101A7000416000BF00BF00BF1CE000BFA06801685C
:101A8000C1F3C05129B1A0684FF40001416000BF0B
:101A900000BF00BF0EE000BFA0680168C1F3C061D5
:101AA00029B1A0684FF00061416000BF00BF00BFD6
:101AB00000E000BF00BF10BD0EB51348006808BBB2
:101AC0000020F0210122114BCDE9002102900A46AD
:101AD00001210F48FFF79CFE0B49086000200968B0
:101AE00008700C480849096888600520064909689B
:101AF000C8600420044909680861002102480068A0
:101B000000F0E2F80EBD00005C0000204B1E000853
:101B1000003801400000024038B5044604B938BD21
:101B20006068C168C1F34011B9B160680168C1F370
:101B3000401191B1608D218C884202DB2046FFF775
:101B4000B5FE61684A68D2B2608D411C6185E16969
:101B50000A5400202076E0753FE06068C168C1F358
:101B60000011002939D060680168C1F30011002913
:101B700033D0607D01282BD1D4E902014A1E514B9C
:101B80009A5C02445268208C801A6085207DF8B9E6
:101B9000D4E90201FEF744FBE06B80B1608D0028C0
:101BA0000DDD608D218C884209DC628D2078E36B2D
:101BB000E1699847228C0021E069FFF768FC228CDC
:101BC000D4E90201FEF766FBD4E90201FEF736FB19
:101BD000002060856068FEF7CEFD6068C168C1F3D3
:101BE000801151B16068FEF72CFE30B1206C08B155
:101BF000206C80476068FEF7C6FDA07D01285ED19D
:101C000001256068C168C1F3002171B16068016895
:101C100001F0010149B1022560680168009100BF2F
:101C20004168009100BF00BF00BF6068FEF7FAFD89
:101C300068B16068FEF7F6FD48B104256068016888
:101C4000009100BF4168009100BF00BF00BF606805
:101C5000FEF7EDFD60B16068FEF7E9FD40B1606838
:101C60000168009100BF4168009100BF00BF00BF44
:101C70006068FEF7E1FD68B16068FEF7DDFD48B120
:101C8000102560680168009100BF4168009100BFA5
:101C900000BF00BF012D11D0606A78B1618D491E6F
:101CA00088B2228D616A01EB82014880228D616ACF
:101CB00001F82250218D491C218500BF00BF00BFC3
:101CC0002DE70000B81E000870B504460D46607D83
:101CD00090B9A575606800BF00BF00BF00F10C029D
:101CE00052E8002F42F0200100F10C0242E80013FC
:101CF000002BF3D100BF70E00020A0756068FEF7F4
:101D00003AFD2169A068FEF78BFAD4E90201FEF7DB
:101D100087FA6068011D0E463246D4E90201FEF7DB
:101D200015FBE269D4E90201FEF7D6FA228CD4E968
:101D30000201FEF7AFFAD4E90201FEF78DFAD4E909
:101D40000201FEF77BFA606800BF00BF00BF00F130
:101D5000140252E8002F42F0400100F1140242E860
:101D60000013002BF3D100BF00BF606800BF00BFAD
:101D700000BF00F10C0252E8002F42F0100100F108
:101D80000C0242E80013002BF3D100BF00BF6068D3
:101D9000011D0E4632462169A068FEF7D7FA226B74
:101DA0002169A068FEF798FA2169A068FEF754FA45
:101DB000606800BF00BF00BF00F1140252E8002FAE
:101DC00042F0800100F1140242E80013002BF3D12D
:101DD00000BF00BF012084F83800A07D012833D166
:101DE000606A68B9218C8800FFF74AFB6062616A0B
:101DF00009B1012100E0002108468221FEF7BAF96D
:101E0000606800BF00BF00BF00F10C0252E8002F65
:101E100042F4807100F10C0242E80013002BF3D170
:101E200000BF00BF606800BF00BF00BF00F1140228
:101E300052E8002F42F0010100F1140242E80013C1
:101E4000002BF3D100BF00BF70BD7047081C3044A9
:101E5000586C80000000000404040000080000002A
:101E6000080000080000000800020406080A0C0030
:101E7000010203040506081C3044586C8000000071
:101E8000000404040000080000000800000800002E
:101E9000000800020406080A0C00010203040506FB
:101EA000000000000000000001020304060708090A
:101EB0000000000001020304081C3044586C80003C
:101EC00000000004040400000800000008000008EE
:101ED0000000000800020406080A0C0001020304C6
:101EE00005065F6C697374006C69737420616C6CB7
:101EF00020636F6D6D616E640000000000040000DF
:101F000000000000080000000800000000200000A1
:101F100000000000341F00080000002070000000D6
:101F200020140008A41F000870000020102C0000DE
:101F3000301400080024F40000000000000000003D
:101F40000000000000000000000000000000000091
:101F50000000000000000000000000000000000081
:101F60000000000000000000000000000000000071
:101F7000811600086D1700088000002000C00120B5
:101F80008020002038000020000000000000000039
:101F900000000000E21E0008E81E0008C6E533B499
:041FA0005D140008C4
:04000005080000ED02
:00000001FF

305
MDK-ARM/startup_stm32f103xb.s Normal file
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;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017-2021 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

18
Makefile Normal file
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current_time=$(shell date +%Y%m%d%H%M)
# 获得当前git的用户邮箱
current_user=$(shell git config user.email)
.PHONY:clean cc
all: clean
cc:
git rm -r --cached .
git add .
git commit -m "$(current_user) batch push $(current_time)"
git push origin develop
clean:
cmd /c keilkill.bat

BIN
Public/STM32_PID_电机.pdf Normal file
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User/application/app.c Normal file
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#include "app.h"
#include "board.h"
#include "flow.h"
static struct flow business_fw; // 业务流程
static struct flow idle_fw; // 空闲任务
app_t app;
static uint8_t business_inspection(struct flow *fl)
{
FL_HEAD(fl);
for (;;)
{
FL_LOCK_DELAY(fl, FL_CLOCK_100MSEC);
}
FL_TAIL(fl);
}
/**
* @brief 对流量进行空闲检查
*
* 该函数会对传入的流量结构体进行空闲检查。
*
* @param fl 指向流量结构体的指针
*
* @return 返回值始终为0，该函数不返回实际值
*/
static uint8_t idle_inspection(struct flow *fl)
{
FL_HEAD(fl);
for (;;)
{
GPIO_TOGGLE(LED_BLUE_GPIO_Port, LED_BLUE_Pin);
FL_LOCK_DELAY(fl, FL_CLOCK_SEC);
}
FL_TAIL(fl);
}
/**
* @brief 运行应用程序
*
* 该函数用于启动应用程序的运行。
*
* @details 此函数会调用 idle_inspection 函数，传入 idle_fw 作为参数。
* idle_inspection 函数的具体作用需参考其实现细节。
*/
void app_run(void)
{
business_inspection(&business_fw); // 业务流程检测
idle_inspection(&idle_fw);
}
/**
* @brief 初始化应用程序
*
* 初始化应用程序，包括启动空闲任务。
*/
void app_init(void)
{
FL_INIT(&business_fw); // 业务流程
FL_INIT(&idle_fw); // 空闲任务
ENABLE_TIM(TASK_TIM);
ENABLE_TIM(WORK_TIM);
}

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/**
* @file app.h
* @author xushenghao
* @date 2024-08-09 09:03:08
* @brief
* @copyright Copyright (c) 2024 by xxx, All Rights Reserved.
*/
#ifndef APP_H
#define APP_H
#include "main.h"
typedef struct
{
float32 pwm_percent;
uint32_t pwm_feq;
} app_t;
extern app_t app;
void app_init(void);
void app_run(void);
#endif // APP_H

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#include "board.h"
uart_t *uart = NULL;
static void uart_rx_cb(uint8_t uart_index, uint8_t *data, uint16_t len)
{
}
static void uart_init(void)
{
if (uart == NULL)
{
uart = uart_create(USART1, TRUE, UART_RXSIZE, uart_rx_cb, TRUE, UART_TXSIZE, NULL);
uart->uart_index = 0;
uart->dma = DMA1;
uart->dma_rx_channel = LL_DMA_CHANNEL_5;
uart->dma_tx_channel = LL_DMA_CHANNEL_4;
uart_recv_en(uart, FALSE);
}
}
/**
* @brief 通过UART发送数据
*
* 该函数通过UART接口发送指定长度的数据。
*
* @param data 指向要发送数据的指针
* @param len 要发送的数据长度
*/
void uart_send(uint8_t *data, uint16_t len)
{
uart_send_data(uart, data, len);
}
/**
* @brief 初始化显示板
*
*/
void board_init(void)
{
uart_init();
}

18
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#ifndef __BOARD_H__
#define __BOARD_H__
#include "lib.h"
#define UART_RXSIZE (240u) // 接收240个字节
#define UART_TXSIZE (240u) // 发送240个字节
#define TASK_TIM TIM1
#define PWM_TIM TIM2
#define PWM_CHANNEL LL_TIM_CHANNEL_CH2
#define WORK_TIM TIM3
extern uart_t *uart;
void board_init(void);
void uart_send(uint8_t *data, uint16_t len);
#endif

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User/board/ssd1306_oled.c Normal file
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/**
* @file ssd1306_oled.c
* @author xushenghao
* @brief SSD1306 OLED display driver
* @version 0.1
* @note PB13-SCK PB12-SDA
*/
#include "ssd1306_oled.h"
#include "ssd1306_oled.h"
/************************************6*8的点阵************************************/
const uint8_t F6x8[][6] =
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // sp
0x00, 0x00, 0x00, 0x2f, 0x00, 0x00, // !
0x00, 0x00, 0x07, 0x00, 0x07, 0x00, // "
0x00, 0x14, 0x7f, 0x14, 0x7f, 0x14, // #
0x00, 0x24, 0x2a, 0x7f, 0x2a, 0x12, // $
0x00, 0x62, 0x64, 0x08, 0x13, 0x23, // %
0x00, 0x36, 0x49, 0x55, 0x22, 0x50, // &
0x00, 0x00, 0x05, 0x03, 0x00, 0x00, // '
0x00, 0x00, 0x1c, 0x22, 0x41, 0x00, // (
0x00, 0x00, 0x41, 0x22, 0x1c, 0x00, // )
0x00, 0x14, 0x08, 0x3E, 0x08, 0x14, // *
0x00, 0x08, 0x08, 0x3E, 0x08, 0x08, // +
0x00, 0x00, 0x00, 0xA0, 0x60, 0x00, // ,
0x00, 0x08, 0x08, 0x08, 0x08, 0x08, // -
0x00, 0x00, 0x60, 0x60, 0x00, 0x00, // .
0x00, 0x20, 0x10, 0x08, 0x04, 0x02, // /
0x00, 0x3E, 0x51, 0x49, 0x45, 0x3E, // 0
0x00, 0x00, 0x42, 0x7F, 0x40, 0x00, // 1
0x00, 0x42, 0x61, 0x51, 0x49, 0x46, // 2
0x00, 0x21, 0x41, 0x45, 0x4B, 0x31, // 3
0x00, 0x18, 0x14, 0x12, 0x7F, 0x10, // 4
0x00, 0x27, 0x45, 0x45, 0x45, 0x39, // 5
0x00, 0x3C, 0x4A, 0x49, 0x49, 0x30, // 6
0x00, 0x01, 0x71, 0x09, 0x05, 0x03, // 7
0x00, 0x36, 0x49, 0x49, 0x49, 0x36, // 8
0x00, 0x06, 0x49, 0x49, 0x29, 0x1E, // 9
0x00, 0x00, 0x36, 0x36, 0x00, 0x00, // :
0x00, 0x00, 0x56, 0x36, 0x00, 0x00, // ;
0x00, 0x08, 0x14, 0x22, 0x41, 0x00, // <
0x00, 0x14, 0x14, 0x14, 0x14, 0x14, // =
0x00, 0x00, 0x41, 0x22, 0x14, 0x08, // >
0x00, 0x02, 0x01, 0x51, 0x09, 0x06, // ?
0x00, 0x32, 0x49, 0x59, 0x51, 0x3E, // @
0x00, 0x7C, 0x12, 0x11, 0x12, 0x7C, // A
0x00, 0x7F, 0x49, 0x49, 0x49, 0x36, // B
0x00, 0x3E, 0x41, 0x41, 0x41, 0x22, // C
0x00, 0x7F, 0x41, 0x41, 0x22, 0x1C, // D
0x00, 0x7F, 0x49, 0x49, 0x49, 0x41, // E
0x00, 0x7F, 0x09, 0x09, 0x09, 0x01, // F
0x00, 0x3E, 0x41, 0x49, 0x49, 0x7A, // G
0x00, 0x7F, 0x08, 0x08, 0x08, 0x7F, // H
0x00, 0x00, 0x41, 0x7F, 0x41, 0x00, // I
0x00, 0x20, 0x40, 0x41, 0x3F, 0x01, // J
0x00, 0x7F, 0x08, 0x14, 0x22, 0x41, // K
0x00, 0x7F, 0x40, 0x40, 0x40, 0x40, // L
0x00, 0x7F, 0x02, 0x0C, 0x02, 0x7F, // M
0x00, 0x7F, 0x04, 0x08, 0x10, 0x7F, // N
0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E, // O
0x00, 0x7F, 0x09, 0x09, 0x09, 0x06, // P
0x00, 0x3E, 0x41, 0x51, 0x21, 0x5E, // Q
0x00, 0x7F, 0x09, 0x19, 0x29, 0x46, // R
0x00, 0x46, 0x49, 0x49, 0x49, 0x31, // S
0x00, 0x01, 0x01, 0x7F, 0x01, 0x01, // T
0x00, 0x3F, 0x40, 0x40, 0x40, 0x3F, // U
0x00, 0x1F, 0x20, 0x40, 0x20, 0x1F, // V
0x00, 0x3F, 0x40, 0x38, 0x40, 0x3F, // W
0x00, 0x63, 0x14, 0x08, 0x14, 0x63, // X
0x00, 0x07, 0x08, 0x70, 0x08, 0x07, // Y
0x00, 0x61, 0x51, 0x49, 0x45, 0x43, // Z
0x00, 0x00, 0x7F, 0x41, 0x41, 0x00, // [
0x00, 0x55, 0x2A, 0x55, 0x2A, 0x55, // 55
0x00, 0x00, 0x41, 0x41, 0x7F, 0x00, // ]
0x00, 0x04, 0x02, 0x01, 0x02, 0x04, // ^
0x00, 0x40, 0x40, 0x40, 0x40, 0x40, // _
0x00, 0x00, 0x01, 0x02, 0x04, 0x00, // '
0x00, 0x20, 0x54, 0x54, 0x54, 0x78, // a
0x00, 0x7F, 0x48, 0x44, 0x44, 0x38, // b
0x00, 0x38, 0x44, 0x44, 0x44, 0x20, // c
0x00, 0x38, 0x44, 0x44, 0x48, 0x7F, // d
0x00, 0x38, 0x54, 0x54, 0x54, 0x18, // e
0x00, 0x08, 0x7E, 0x09, 0x01, 0x02, // f
0x00, 0x18, 0xA4, 0xA4, 0xA4, 0x7C, // g
0x00, 0x7F, 0x08, 0x04, 0x04, 0x78, // h
0x00, 0x00, 0x44, 0x7D, 0x40, 0x00, // i
0x00, 0x40, 0x80, 0x84, 0x7D, 0x00, // j
0x00, 0x7F, 0x10, 0x28, 0x44, 0x00, // k
0x00, 0x00, 0x41, 0x7F, 0x40, 0x00, // l
0x00, 0x7C, 0x04, 0x18, 0x04, 0x78, // m
0x00, 0x7C, 0x08, 0x04, 0x04, 0x78, // n
0x00, 0x38, 0x44, 0x44, 0x44, 0x38, // o
0x00, 0xFC, 0x24, 0x24, 0x24, 0x18, // p
0x00, 0x18, 0x24, 0x24, 0x18, 0xFC, // q
0x00, 0x7C, 0x08, 0x04, 0x04, 0x08, // r
0x00, 0x48, 0x54, 0x54, 0x54, 0x20, // s
0x00, 0x04, 0x3F, 0x44, 0x40, 0x20, // t
0x00, 0x3C, 0x40, 0x40, 0x20, 0x7C, // u
0x00, 0x1C, 0x20, 0x40, 0x20, 0x1C, // v
0x00, 0x3C, 0x40, 0x30, 0x40, 0x3C, // w
0x00, 0x44, 0x28, 0x10, 0x28, 0x44, // x
0x00, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C, // y
0x00, 0x44, 0x64, 0x54, 0x4C, 0x44, // z
0x14, 0x14, 0x14, 0x14, 0x14, 0x14, // horiz lines
};
/****************************************8*16的点阵************************************/
const uint8_t F8X16[] =
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 0
0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x30, 0x00, 0x00, 0x00, //! 1
0x00, 0x10, 0x0C, 0x06, 0x10, 0x0C, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //" 2
0x40, 0xC0, 0x78, 0x40, 0xC0, 0x78, 0x40, 0x00, 0x04, 0x3F, 0x04, 0x04, 0x3F, 0x04, 0x04, 0x00, // # 3
0x00, 0x70, 0x88, 0xFC, 0x08, 0x30, 0x00, 0x00, 0x00, 0x18, 0x20, 0xFF, 0x21, 0x1E, 0x00, 0x00, //$ 4
0xF0, 0x08, 0xF0, 0x00, 0xE0, 0x18, 0x00, 0x00, 0x00, 0x21, 0x1C, 0x03, 0x1E, 0x21, 0x1E, 0x00, //% 5
0x00, 0xF0, 0x08, 0x88, 0x70, 0x00, 0x00, 0x00, 0x1E, 0x21, 0x23, 0x24, 0x19, 0x27, 0x21, 0x10, //& 6
0x10, 0x16, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //' 7
0x00, 0x00, 0x00, 0xE0, 0x18, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x07, 0x18, 0x20, 0x40, 0x00, //( 8
0x00, 0x02, 0x04, 0x18, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x20, 0x18, 0x07, 0x00, 0x00, 0x00, //) 9
0x40, 0x40, 0x80, 0xF0, 0x80, 0x40, 0x40, 0x00, 0x02, 0x02, 0x01, 0x0F, 0x01, 0x02, 0x02, 0x00, //* 10
0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x1F, 0x01, 0x01, 0x01, 0x00, //+ 11
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xB0, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, //, 12
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, //- 13
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, //. 14
0x00, 0x00, 0x00, 0x00, 0x80, 0x60, 0x18, 0x04, 0x00, 0x60, 0x18, 0x06, 0x01, 0x00, 0x00, 0x00, /// 15
0x00, 0xE0, 0x10, 0x08, 0x08, 0x10, 0xE0, 0x00, 0x00, 0x0F, 0x10, 0x20, 0x20, 0x10, 0x0F, 0x00, // 0 16
0x00, 0x10, 0x10, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x3F, 0x20, 0x20, 0x00, 0x00, // 1 17
0x00, 0x70, 0x08, 0x08, 0x08, 0x88, 0x70, 0x00, 0x00, 0x30, 0x28, 0x24, 0x22, 0x21, 0x30, 0x00, // 2 18
0x00, 0x30, 0x08, 0x88, 0x88, 0x48, 0x30, 0x00, 0x00, 0x18, 0x20, 0x20, 0x20, 0x11, 0x0E, 0x00, // 3 19
0x00, 0x00, 0xC0, 0x20, 0x10, 0xF8, 0x00, 0x00, 0x00, 0x07, 0x04, 0x24, 0x24, 0x3F, 0x24, 0x00, // 4 20
0x00, 0xF8, 0x08, 0x88, 0x88, 0x08, 0x08, 0x00, 0x00, 0x19, 0x21, 0x20, 0x20, 0x11, 0x0E, 0x00, // 5 21
0x00, 0xE0, 0x10, 0x88, 0x88, 0x18, 0x00, 0x00, 0x00, 0x0F, 0x11, 0x20, 0x20, 0x11, 0x0E, 0x00, // 6 22
0x00, 0x38, 0x08, 0x08, 0xC8, 0x38, 0x08, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, // 7 23
0x00, 0x70, 0x88, 0x08, 0x08, 0x88, 0x70, 0x00, 0x00, 0x1C, 0x22, 0x21, 0x21, 0x22, 0x1C, 0x00, // 8 24
0x00, 0xE0, 0x10, 0x08, 0x08, 0x10, 0xE0, 0x00, 0x00, 0x00, 0x31, 0x22, 0x22, 0x11, 0x0F, 0x00, // 9 25
0x00, 0x00, 0x00, 0xC0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, //: 26
0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, //; 27
0x00, 0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x00, 0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x00, //< 28
0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, //= 29
0x00, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00, //> 30
0x00, 0x70, 0x48, 0x08, 0x08, 0x08, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x30, 0x36, 0x01, 0x00, 0x00, //? 31
0xC0, 0x30, 0xC8, 0x28, 0xE8, 0x10, 0xE0, 0x00, 0x07, 0x18, 0x27, 0x24, 0x23, 0x14, 0x0B, 0x00, //@ 32
0x00, 0x00, 0xC0, 0x38, 0xE0, 0x00, 0x00, 0x00, 0x20, 0x3C, 0x23, 0x02, 0x02, 0x27, 0x38, 0x20, // A 33
0x08, 0xF8, 0x88, 0x88, 0x88, 0x70, 0x00, 0x00, 0x20, 0x3F, 0x20, 0x20, 0x20, 0x11, 0x0E, 0x00, // B 34
0xC0, 0x30, 0x08, 0x08, 0x08, 0x08, 0x38, 0x00, 0x07, 0x18, 0x20, 0x20, 0x20, 0x10, 0x08, 0x00, // C 35
0x08, 0xF8, 0x08, 0x08, 0x08, 0x10, 0xE0, 0x00, 0x20, 0x3F, 0x20, 0x20, 0x20, 0x10, 0x0F, 0x00, // D 36
0x08, 0xF8, 0x88, 0x88, 0xE8, 0x08, 0x10, 0x00, 0x20, 0x3F, 0x20, 0x20, 0x23, 0x20, 0x18, 0x00, // E 37
0x08, 0xF8, 0x88, 0x88, 0xE8, 0x08, 0x10, 0x00, 0x20, 0x3F, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, // F 38
0xC0, 0x30, 0x08, 0x08, 0x08, 0x38, 0x00, 0x00, 0x07, 0x18, 0x20, 0x20, 0x22, 0x1E, 0x02, 0x00, // G 39
0x08, 0xF8, 0x08, 0x00, 0x00, 0x08, 0xF8, 0x08, 0x20, 0x3F, 0x21, 0x01, 0x01, 0x21, 0x3F, 0x20, // H 40
0x00, 0x08, 0x08, 0xF8, 0x08, 0x08, 0x00, 0x00, 0x00, 0x20, 0x20, 0x3F, 0x20, 0x20, 0x00, 0x00, // I 41
0x00, 0x00, 0x08, 0x08, 0xF8, 0x08, 0x08, 0x00, 0xC0, 0x80, 0x80, 0x80, 0x7F, 0x00, 0x00, 0x00, // J 42
0x08, 0xF8, 0x88, 0xC0, 0x28, 0x18, 0x08, 0x00, 0x20, 0x3F, 0x20, 0x01, 0x26, 0x38, 0x20, 0x00, // K 43
0x08, 0xF8, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x3F, 0x20, 0x20, 0x20, 0x20, 0x30, 0x00, // L 44
0x08, 0xF8, 0xF8, 0x00, 0xF8, 0xF8, 0x08, 0x00, 0x20, 0x3F, 0x00, 0x3F, 0x00, 0x3F, 0x20, 0x00, // M 45
0x08, 0xF8, 0x30, 0xC0, 0x00, 0x08, 0xF8, 0x08, 0x20, 0x3F, 0x20, 0x00, 0x07, 0x18, 0x3F, 0x00, // N 46
0xE0, 0x10, 0x08, 0x08, 0x08, 0x10, 0xE0, 0x00, 0x0F, 0x10, 0x20, 0x20, 0x20, 0x10, 0x0F, 0x00, // O 47
0x08, 0xF8, 0x08, 0x08, 0x08, 0x08, 0xF0, 0x00, 0x20, 0x3F, 0x21, 0x01, 0x01, 0x01, 0x00, 0x00, // P 48
0xE0, 0x10, 0x08, 0x08, 0x08, 0x10, 0xE0, 0x00, 0x0F, 0x18, 0x24, 0x24, 0x38, 0x50, 0x4F, 0x00, // Q 49
0x08, 0xF8, 0x88, 0x88, 0x88, 0x88, 0x70, 0x00, 0x20, 0x3F, 0x20, 0x00, 0x03, 0x0C, 0x30, 0x20, // R 50
0x00, 0x70, 0x88, 0x08, 0x08, 0x08, 0x38, 0x00, 0x00, 0x38, 0x20, 0x21, 0x21, 0x22, 0x1C, 0x00, // S 51
0x18, 0x08, 0x08, 0xF8, 0x08, 0x08, 0x18, 0x00, 0x00, 0x00, 0x20, 0x3F, 0x20, 0x00, 0x00, 0x00, // T 52
0x08, 0xF8, 0x08, 0x00, 0x00, 0x08, 0xF8, 0x08, 0x00, 0x1F, 0x20, 0x20, 0x20, 0x20, 0x1F, 0x00, // U 53
0x08, 0x78, 0x88, 0x00, 0x00, 0xC8, 0x38, 0x08, 0x00, 0x00, 0x07, 0x38, 0x0E, 0x01, 0x00, 0x00, // V 54
0xF8, 0x08, 0x00, 0xF8, 0x00, 0x08, 0xF8, 0x00, 0x03, 0x3C, 0x07, 0x00, 0x07, 0x3C, 0x03, 0x00, // W 55
0x08, 0x18, 0x68, 0x80, 0x80, 0x68, 0x18, 0x08, 0x20, 0x30, 0x2C, 0x03, 0x03, 0x2C, 0x30, 0x20, // X 56
0x08, 0x38, 0xC8, 0x00, 0xC8, 0x38, 0x08, 0x00, 0x00, 0x00, 0x20, 0x3F, 0x20, 0x00, 0x00, 0x00, // Y 57
0x10, 0x08, 0x08, 0x08, 0xC8, 0x38, 0x08, 0x00, 0x20, 0x38, 0x26, 0x21, 0x20, 0x20, 0x18, 0x00, // Z 58
0x00, 0x00, 0x00, 0xFE, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x40, 0x40, 0x40, 0x00, //[ 59
0x00, 0x0C, 0x30, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x38, 0xC0, 0x00, //\ 60
0x00, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0x7F, 0x00, 0x00, 0x00, //] 61
0x00, 0x00, 0x04, 0x02, 0x02, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //^ 62
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, //_ 63
0x00, 0x02, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //` 64
0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x19, 0x24, 0x22, 0x22, 0x22, 0x3F, 0x20, // a 65
0x08, 0xF8, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x11, 0x20, 0x20, 0x11, 0x0E, 0x00, // b 66
0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x0E, 0x11, 0x20, 0x20, 0x20, 0x11, 0x00, // c 67
0x00, 0x00, 0x00, 0x80, 0x80, 0x88, 0xF8, 0x00, 0x00, 0x0E, 0x11, 0x20, 0x20, 0x10, 0x3F, 0x20, // d 68
0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x1F, 0x22, 0x22, 0x22, 0x22, 0x13, 0x00, // e 69
0x00, 0x80, 0x80, 0xF0, 0x88, 0x88, 0x88, 0x18, 0x00, 0x20, 0x20, 0x3F, 0x20, 0x20, 0x00, 0x00, // f 70
0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x6B, 0x94, 0x94, 0x94, 0x93, 0x60, 0x00, // g 71
0x08, 0xF8, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x20, 0x3F, 0x21, 0x00, 0x00, 0x20, 0x3F, 0x20, // h 72
0x00, 0x80, 0x98, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x3F, 0x20, 0x20, 0x00, 0x00, // i 73
0x00, 0x00, 0x00, 0x80, 0x98, 0x98, 0x00, 0x00, 0x00, 0xC0, 0x80, 0x80, 0x80, 0x7F, 0x00, 0x00, // j 74
0x08, 0xF8, 0x00, 0x00, 0x80, 0x80, 0x80, 0x00, 0x20, 0x3F, 0x24, 0x02, 0x2D, 0x30, 0x20, 0x00, // k 75
0x00, 0x08, 0x08, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x3F, 0x20, 0x20, 0x00, 0x00, // l 76
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x20, 0x3F, 0x20, 0x00, 0x3F, 0x20, 0x00, 0x3F, // m 77
0x80, 0x80, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x20, 0x3F, 0x21, 0x00, 0x00, 0x20, 0x3F, 0x20, // n 78
0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x1F, 0x20, 0x20, 0x20, 0x20, 0x1F, 0x00, // o 79
0x80, 0x80, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xA1, 0x20, 0x20, 0x11, 0x0E, 0x00, // p 80
0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x0E, 0x11, 0x20, 0x20, 0xA0, 0xFF, 0x80, // q 81
0x80, 0x80, 0x80, 0x00, 0x80, 0x80, 0x80, 0x00, 0x20, 0x20, 0x3F, 0x21, 0x20, 0x00, 0x01, 0x00, // r 82
0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x33, 0x24, 0x24, 0x24, 0x24, 0x19, 0x00, // s 83
0x00, 0x80, 0x80, 0xE0, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x20, 0x20, 0x00, 0x00, // t 84
0x80, 0x80, 0x00, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x1F, 0x20, 0x20, 0x20, 0x10, 0x3F, 0x20, // u 85
0x80, 0x80, 0x80, 0x00, 0x00, 0x80, 0x80, 0x80, 0x00, 0x01, 0x0E, 0x30, 0x08, 0x06, 0x01, 0x00, // v 86
0x80, 0x80, 0x00, 0x80, 0x00, 0x80, 0x80, 0x80, 0x0F, 0x30, 0x0C, 0x03, 0x0C, 0x30, 0x0F, 0x00, // w 87
0x00, 0x80, 0x80, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x20, 0x31, 0x2E, 0x0E, 0x31, 0x20, 0x00, // x 88
0x80, 0x80, 0x80, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x81, 0x8E, 0x70, 0x18, 0x06, 0x01, 0x00, // y 89
0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x21, 0x30, 0x2C, 0x22, 0x21, 0x30, 0x00, // z 90
0x00, 0x00, 0x00, 0x00, 0x80, 0x7C, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x40, 0x40, //{ 91
0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, //| 92
0x00, 0x02, 0x02, 0x7C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40, 0x3F, 0x00, 0x00, 0x00, 0x00, //} 93
0x00, 0x06, 0x01, 0x01, 0x02, 0x02, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //~ 94
};
static uint8_t _buffer[SSD1306_WIDTH * SSD1306_HEIGHT / 8]; // 定义屏幕缓冲区
static void i2c_start(void)
{
SDA_OUT();
GPIO_SET(SSD1306_SDA_PORT, SSD1306_SDA_PIN);
GPIO_SET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
delay_us(4);
GPIO_RESET(SSD1306_SDA_PORT, SSD1306_SDA_PIN);
delay_us(4);
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
}
static void i2c_stop(void)
{
SDA_OUT();
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
GPIO_RESET(SSD1306_SDA_PORT, SSD1306_SDA_PIN);
delay_us(4);
GPIO_SET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
GPIO_SET(SSD1306_SDA_PORT, SSD1306_SDA_PIN);
delay_us(4);
}
static BOOL i2c_wait_ack(void)
{
uint8_t count = 0;
SDA_IN();
GPIO_SET(SSD1306_SDA_PORT, SSD1306_SDA_PIN);
delay_us(4);
GPIO_SET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
delay_us(4);
while (GPIO_READ(SSD1306_SDA_PORT, SSD1306_SDA_PIN))
{
count++;
if (count > 250)
{
i2c_stop();
return FALSE;
}
}
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
return TRUE;
}
static void i2c_ack(void)
{
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
SDA_OUT();
GPIO_RESET(SSD1306_SDA_PORT, SSD1306_SDA_PIN);
delay_us(2);
GPIO_SET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
delay_us(2);
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
}
static void i2c_nack(void)
{
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
SDA_OUT();
GPIO_SET(SSD1306_SDA_PORT, SSD1306_SDA_PIN);
delay_us(2);
GPIO_SET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
delay_us(2);
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
}
uint8_t i2c_read_byte(BOOL ack)
{
uint8_t i = 0, receive = 0;
SDA_IN();
for (i = 0; i < 8; i++)
{
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
delay_us(2);
GPIO_SET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
receive <<= 1;
if (GPIO_READ(SSD1306_SDA_PORT, SSD1306_SDA_PIN))
{
receive++;
}
delay_us(1);
}
if (!ack)
{
i2c_nack();
}
else
{
i2c_ack();
}
return receive;
}
void i2c_write_byte(uint8_t data)
{
uint8_t i = 0;
SDA_OUT();
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
for (i = 0; i < 8; i++)
{
// IIC_SDA=(txd&0x80)>>7;
if ((data & 0x80) >> 7)
GPIO_SET(SSD1306_SDA_PORT, SSD1306_SDA_PIN);
else
GPIO_RESET(SSD1306_SDA_PORT, SSD1306_SDA_PIN);
data <<= 1;
delay_us(2);
GPIO_SET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
delay_us(2);
GPIO_RESET(SSD1306_SCK_PORT, SSD1306_SCK_PIN);
delay_us(2);
}
}
static void i2c_write_command(uint8_t command)
{
uint8_t dd[2];
dd[0] = SSD1306_CMD_SET_LOW_COLUMN; // Co = 0, D/C# = 0
dd[1] = command;
i2c_start();
i2c_write_byte(SSD1306_I2C_ADDRESS);
i2c_wait_ack();
i2c_write_byte(dd[0]);
i2c_wait_ack();
i2c_write_byte(dd[1]);
i2c_wait_ack();
i2c_stop();
}
static void i2c_write_data(uint8_t data)
{
uint8_t dd[2];
dd[0] = SSD1306_CMD_SET_START_LINE; // Co = 0, D/C# = 1
dd[1] = data;
i2c_start();
i2c_write_byte(SSD1306_I2C_ADDRESS);
i2c_wait_ack();
i2c_write_byte(dd[0]);
i2c_wait_ack();
i2c_write_byte(dd[1]);
i2c_wait_ack();
}
/**
* @brief 设置SSD1306 OLED显示屏上的显示位置
*
* 该函数用于设置SSD1306 OLED显示屏上的显示位置，通过x和y坐标确定显示位置。
*
* @param x 要设置的横坐标（0-127）
* @param y 要设置的纵坐标（0-7，对应SSD1306 OLED的8个页面）
*/
void set_position(uint8_t x, uint8_t y)
{
i2c_write_command(0xb0 + y);
i2c_write_command(((x & 0xf0) >> 4) | 0x10);
i2c_write_command((x & 0x0f) | 0x01);
}
void ssd1306_test(void)
{
ssd1306_f8x16_string(0, 0, " TEST");
ssd1306_f8x16_number(40, 0, -15.26, 2);
ssd1306_f6x8_string_number(0, 3, " @ADC1:", 'V', 24);
ssd1306_update_screen();
}
void ssd1306_init(void)
{
i2c_write_command(SSD1306_CMD_DISPLAY_OFF); // display off
i2c_write_command(SSD1306_CMD_MEMORY_MODE); // Set Memory Addressing Mode
i2c_write_command(SSD1306_CMD_SET_HIGH_COLUMN); // 00,Horizontal Addressing Mode;01,Vertical Addressing Mode;10,Page Addressing Mode (RESET);11,Invalid
i2c_write_command(SSD1306_CMD_COM_SCAN_DEC); // Set COM Output Scan Direction
i2c_write_command(SSD1306_CMD_SET_LOW_COLUMN); //---set low column address
i2c_write_command(SSD1306_CMD_SET_HIGH_COLUMN); //---set high column address
i2c_write_command(SSD1306_CMD_SET_START_LINE); //--set start line address
i2c_write_command(SSD1306_CMD_SET_CONTRAST); //--set contrast control register
i2c_write_command(0xff); // 亮度调节 0x00~0xff
i2c_write_command(0xa1); //--set segment re-map 0 to 127
i2c_write_command(SSD1306_CMD_NORMAL_DISPLAY); //--set normal display
i2c_write_command(SSD1306_CMD_SET_MULTIPLEX); //--set multiplex ratio(1 to 64)
i2c_write_command(0x3f); //
i2c_write_command(SSD1306_CMD_DISPLAY_ALL_ON_RESUME); // 0xa4,Output follows RAM content;0xa5,Output ignores RAM content
i2c_write_command(SSD1306_CMD_SET_DISPLAY_OFFSET); //-set display offset
i2c_write_command(SSD1306_CMD_SET_LOW_COLUMN); //-not offset
i2c_write_command(SSD1306_CMD_SET_DISPLAY_CLOCK_DIV); //--set display clock divide ratio/oscillator frequency
i2c_write_command(0xf0); //--set divide ratio
i2c_write_command(SSD1306_CMD_SET_PRECHARGE); //--set pre-charge period
i2c_write_command(SSD1306_CMD_PAGE_ADDR); //
i2c_write_command(SSD1306_CMD_SET_COM_PINS); //--set com pins hardware configuration
i2c_write_command(0x12);
i2c_write_command(SSD1306_CMD_SET_VCOM_DETECT); //--set vcomh
i2c_write_command(SSD1306_CMD_MEMORY_MODE); // 0x20,0.77xVcc
i2c_write_command(SSD1306_CMD_CHARGE_PUMP); //--set DC-DC enable
i2c_write_command(SSD1306_CMD_SET_DC_DC_ENABLE); //
i2c_write_command(SSD1306_CMD_DISPLAY_ON); //--turn on oled panel
ssd1306_fill(0);
// ssd1306_test();
}
void ssd1306_display_on(void)
{
i2c_write_command(SSD1306_CMD_CHARGE_PUMP); // 设置电荷泵
i2c_write_command(SSD1306_CMD_SET_DC_DC_ENABLE); // 开启电荷泵
i2c_write_command(SSD1306_CMD_DISPLAY_ON); // OLED唤醒
}
void ssd1306_display_off(void)
{
i2c_write_command(SSD1306_CMD_CHARGE_PUMP); // 设置电荷泵
i2c_write_command(SSD1306_CMD_SET_HIGH_COLUMN); // 关闭电荷泵
i2c_write_command(SSD1306_CMD_DISPLAY_OFF); // OLED休眠
}
/**
* @brief 更新SSD1306 OLED显示屏的内容
*
* 此函数将缓冲区中的数据写入SSD1306 OLED显示屏，从而更新显示内容。
*
* 首先，通过发送命令设置列地址和页地址，然后将缓冲区中的数据逐行写入显示屏。
*
* @note 在调用此函数之前，需要将需要显示的数据写入缓冲区。
*/
void ssd1306_update_screen(void)
{
for (uint8_t i = 0; i < SSD1306_HEIGHT / 8; i++)
{
i2c_write_command(0xb0 + i);
i2c_write_command(0x01);
i2c_write_command(0x10);
for (uint8_t j = 0; j < SSD1306_WIDTH; j++)
{
i2c_write_data(_buffer[j + i * SSD1306_WIDTH]);
}
}
}
/**
* @brief 填充整个屏幕为指定颜色
*
* 该函数将 SSD1306 OLED 显示屏的每一个像素点都设置为指定的颜色。
*
* @param color 颜色值，0x00 表示关闭像素点（黑色），0xFF 表示打开像素点（白色）
*/
void ssd1306_fill(uint8_t color)
{
osel_memset(_buffer, color, ARRAY_LEN(_buffer));
ssd1306_update_screen();
}
/**
* @brief 清空SSD1306显示屏
*
* 该函数通过向SSD1306显示屏发送一系列命令来清空显示内容。
*
* 首先，通过循环遍历每个页面（SSD1306显示屏有8个页面），
* 对每个页面执行以下操作：
* 1. 发送页面地址命令（0xb0 + y），其中y为当前页面索引。
* 2. 发送列地址低位命令（0x01）。
* 3. 发送列地址高位命令（0x10），表示从第一列开始。
* 4. 循环遍历每一列（SSD1306显示屏的宽度），
* 发送数据0x00以清空该列的内容。
*/
void ssd1306_clear(void)
{
osel_memset(_buffer, 0, ARRAY_LEN(_buffer));
ssd1306_update_screen();
}
void ssd1306_clear_buffer(void)
{
osel_memset(_buffer, 0, ARRAY_LEN(_buffer));
}
/**
* @brief 在指定区域内绘制BMP
*
* 在指定坐标区域内绘制一个BMP，使用SSD1306 OLED显示屏
* ssd1306_draw_bmp(0, 0, SSD1306_WIDTH, 2);
* @param x0 BMP绘制的起始X坐标
* @param y0 BMP绘制的起始Y坐标
* @param x1 BMP绘制的结束X坐标
* @param y1 BMP绘制的结束Y坐标
*/
void ssd1306_draw_bmp(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1, uint8_t *bmp)
{
uint8_t j = 0;
uint8_t x, y;
osel_memset(_buffer, 0, ARRAY_LEN(_buffer));
if (y1 % 8 == 0)
y = y1 / 8;
else
y = y1 / 8 + 1;
for (y = y0; y < y1; y++)
{
set_position(x0, y);
for (x = x0; x < x1; x++)
{
i2c_write_data(bmp[j++]);
}
}
}
/**
* @brief 在SSD1306 OLED显示屏上显示字符串
*
* 在SSD1306 OLED显示屏上以6x8像素的字体显示给定的字符串。
*
* @param x 显示字符串的起始x坐标
* @param y 显示字符串的起始y坐标
* @param str 要显示的字符串
*/
void ssd1306_f6x8_string(uint8_t x, uint8_t y, const uint8_t *ch)
{
uint8_t c = 0, i = 0, j = 0;
while (ch[j] != '\0')
{
c = ch[j] - 32;
if (x > 126)
{
x = 0;
y++;
}
for (i = 0; i < 6; i++)
_buffer[(y * SSD1306_WIDTH) + x + i] = F6x8[c][i];
x += 6;
j++;
}
}
/**
* @brief 在SSD1306 OLED屏幕上显示字符串和数字
*
* 该函数用于在SSD1306 OLED屏幕上显示字符串和数字。首先显示一个字符串，
* 然后显示一个浮点数。字符串和数字按照指定的位置和单位显示。
*
* @param x 起始位置的x坐标
* @param y 起始位置的y坐标
* @param ch 要显示的字符串
* @param unit 数字的单位，例如'm'表示米
* @param num 要显示的浮点数
*/
void ssd1306_f6x8_string_number(uint8_t x, uint8_t y, const uint8_t *ch, uint8_t unit, float32 num)
{
uint8_t c = 0, i = 0, j = 0;
int8_t a, number[7] = {0, 0, 0, -2, 0, 0, 0};
uint32_t d;
while (ch[j] != '\0')
{
c = ch[j] - 32;
if (x > 126)
{
x = 0;
y++;
}
for (i = 0; i < 6; i++)
_buffer[(y * SSD1306_WIDTH) + x + i] = F6x8[c][i];
x += 6;
j++;
}
d = 1000 * num;
for (a = 0; a < 3; a++)
{
number[6 - a] = d % 10;
d = d / 10;
}
for (a = 4; a < 7; a++)
{
number[6 - a] = d % 10;
d = d / 10;
}
if (num >= 100)
{
a = 0;
}
else if (num >= 10)
{
a = 1;
}
else if (num >= 0)
{
a = 2;
}
for (; a < 7; a++)
{
c = number[a] + 16;
if (x > 126)
{
x = 0;
y++;
}
for (i = 0; i < 6; i++)
_buffer[(y * SSD1306_WIDTH) + x + i] = F6x8[c][i];
x += 6;
j++;
}
for (int h = 0; h < 7; h++)
{
c = unit - 32;
for (i = 0; i < 6; i++)
_buffer[(y * SSD1306_WIDTH) + x + i] = F6x8[c][i];
}
}
/**
* @brief 在SSD1306 OLED显示屏上显示8x16大小的字符串
*
* 该函数使用8x16字体在SSD1306 OLED显示屏上显示指定的字符串。字符串的字符位置由x和y参数指定。
*
* @param x 显示字符串的起始x坐标
* @param y 显示字符串的起始y坐标
* @param str 要显示的字符串
*/
void ssd1306_f8x16_string(uint8_t x, uint8_t y, const uint8_t *ch)
{
uint8_t c = 0, i = 0, j = 0;
while (ch[j] != '\0')
{
c = ch[j] - 32;
if (x > 120)
{
x = 0;
y++;
}
for (i = 0; i < 8; i++)
_buffer[(y * SSD1306_WIDTH) + x + i] = F8X16[c * 16 + i];
for (i = 0; i < 8; i++)
_buffer[((y + 1) * SSD1306_WIDTH) + x + i] = F8X16[c * 16 + i + 8];
x += 8;
j++;
}
}
/**
* @brief 在SSD1306 OLED显示屏上以8x16像素字体显示浮点数
*
* 在指定的坐标位置 (x, y) 上，使用8x16像素大小的字体显示浮点数 num，并显示指定数量的小数点 dot_num。
*
* @param x 显示位置的x坐标
* @param y 显示位置的y坐标
* @param num 要显示的浮点数
* @param dot_num 要显示的小数点数量
*/
void ssd1306_f8x16_number(uint8_t x, uint8_t y, float32 num, uint8_t dot_num)
{
uint8_t ch[9] = {'\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0'};
uint8_t c = 0, i = 0, j = 0;
if (num < 0)
{
ch[i++] = '-';
num = -num;
}
if (num > 32000)
return;
c = 8 - i;
if (num >= 10000)
{
ch[i++] = num / 10000 + 48;
ch[i++] = (int32_t)(num) % 10000 / 1000 + 48;
ch[i++] = (int32_t)(num) % 1000 / 100 + 48;
ch[i++] = (int32_t)(num) % 100 / 10 + 48;
ch[i++] = (int32_t)(num) % 10 + 48;
}
else if (num >= 1000)
{
ch[i++] = (int32_t)(num) % 10000 / 1000 + 48;
ch[i++] = (int32_t)(num) % 1000 / 100 + 48;
ch[i++] = (int32_t)(num) % 100 / 10 + 48;
ch[i++] = (int32_t)(num) % 10 + 48;
}
else if (num >= 100)
{
ch[i++] = (int32_t)(num) % 1000 / 100 + 48;
ch[i++] = (int32_t)(num) % 100 / 10 + 48;
ch[i++] = (int32_t)(num) % 10 + 48;
}
else if (num >= 10)
{
ch[i++] = (int32_t)(num) % 100 / 10 + 48;
ch[i++] = (int32_t)(num) % 10 + 48;
}
else if (num >= 0)
{
ch[i++] = (int32_t)(num) % 10 + 48;
}
if (dot_num > 0 && i < 7)
{
ch[i++] = '.';
num = num - (int32_t)num;
if (dot_num == 1 && i < 8)
{
num = num * 10;
ch[i++] = (int32_t)(num + 0.5) % 10 + 48;
}
if (dot_num >= 2 && i < 8)
{
num = num * 100;
ch[i++] = (int32_t)num % 100 / 10 + 48;
if (i < 8)
ch[i++] = (int32_t)(num + 0.5) % 10 + 48;
}
}
while (ch[j] != '\0')
{
c = ch[j] - 32;
if (x > 120)
{
x = 0;
y++;
}
for (i = 0; i < 8; i++)
_buffer[(y * SSD1306_WIDTH) + x + i] = F8X16[c * 16 + i];
for (i = 0; i < 8; i++)
_buffer[((y + 1) * SSD1306_WIDTH) + x + i] = F8X16[c * 16 + i + 8];
x += 8;
j++;
}
}

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#ifndef __SSD1306_OLED_H
#define __SSD1306_OLED_H
#include "main.h"
// OLED引脚定义
#define SSD1306_SDA_PORT OLED_SDA_GPIO_Port
#define SSD1306_SDA_PIN OLED_SDA_Pin
#define SSD1306_SCK_PORT OLDE_SCK_GPIO_Port
#define SSD1306_SCK_PIN OLDE_SCK_Pin
// I2C地址
#define SSD1306_I2C_ADDRESS 0x78
// OLED显示参数
#define SSD1306_WIDTH 128
#define SSD1306_HEIGHT 64
// OLED命令定义
#define SSD1306_CMD_DISPLAY_OFF 0xAE
#define SSD1306_CMD_DISPLAY_ON 0xAF
#define SSD1306_CMD_SET_CONTRAST 0x81
#define SSD1306_CMD_DISPLAY_ALL_ON_RESUME 0xA4
#define SSD1306_CMD_DISPLAY_ALL_ON 0xA5
#define SSD1306_CMD_NORMAL_DISPLAY 0xA6
#define SSD1306_CMD_INVERT_DISPLAY 0xA7
#define SSD1306_CMD_SET_DISPLAY_OFFSET 0xD3
#define SSD1306_CMD_SET_COM_PINS 0xDA
#define SSD1306_CMD_SET_VCOM_DETECT 0xDB
#define SSD1306_CMD_SET_DISPLAY_CLOCK_DIV 0xD5
#define SSD1306_CMD_SET_PRECHARGE 0xD9
#define SSD1306_CMD_SET_MULTIPLEX 0xA8
#define SSD1306_CMD_SET_LOW_COLUMN 0x00
#define SSD1306_CMD_SET_HIGH_COLUMN 0x10
#define SSD1306_CMD_SET_START_LINE 0x40
#define SSD1306_CMD_MEMORY_MODE 0x20
#define SSD1306_CMD_COLUMN_ADDR 0x21
#define SSD1306_CMD_PAGE_ADDR 0x22
#define SSD1306_CMD_COM_SCAN_INC 0xC0
#define SSD1306_CMD_COM_SCAN_DEC 0xC8
#define SSD1306_CMD_SEG_REMAP 0xA0
#define SSD1306_CMD_CHARGE_PUMP 0x8D
#define SSD1306_CMD_SET_DC_DC_ENABLE 0x14
#define SDA_OUT() \
{ \
GPIO_SET_OUTPUT(SSD1306_SDA_PORT, SSD1306_SDA_PIN); \
}
#define SDA_IN() \
{ \
GPIO_SET_INPUT(SSD1306_SDA_PORT, SSD1306_SDA_PIN); \
}
// 函数声明
void ssd1306_init(void);
void ssd1306_display_on(void);
void ssd1306_display_off(void);
void ssd1306_update_screen(void);
void ssd1306_fill(uint8_t color);
void ssd1306_clear(void);
void ssd1306_clear_buffer(void);
void ssd1306_draw_bmp(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1, uint8_t *bmp);
void ssd1306_f6x8_string(uint8_t x, uint8_t y, const uint8_t *ch);
void ssd1306_f6x8_string_number(uint8_t x, uint8_t y, const uint8_t *ch, uint8_t unit, float32 num);
void ssd1306_f8x16_string(uint8_t x, uint8_t y, const uint8_t *ch);
void ssd1306_f8x16_number(uint8_t x, uint8_t y, float32 num, uint8_t dot_num);
#endif // __SSD1306_OLED_H

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#include "bootload.h"
#include "ymodem.h"
#include "sys.h"
#include "delay.h"
#include "cmac.h"
#define AES_CMAC_DIGEST_LENGTH 16
typedef void (*fnc_ptr)(void); // 用于跳转到应用程序的函数指针
static bootload_transmit_callback transmit_callback = NULL;
static bootload_end_callback end_callback = NULL;
uint8_t upgrade_key[] =
{
0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6,
0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C}; // 密钥
static AES_CMAC_CTX upgrade_ctx; /**< AES CMAC context for upgrade process */
static uint8_t pre_upgrade_mic[AES_CMAC_DIGEST_LENGTH]; /**< MIC (Message Integrity Code) before upgrade */
static uint8_t upgrade_mic[AES_CMAC_DIGEST_LENGTH]; /**< MIC (Message Integrity Code) after upgrade */
static uint32_t flashdestination = BOOTLOAD_APP_BACKUP_ADDR_START; /**< Flash destination address for bootloading */
static uint32_t upgrade_size = 0; /**< Size of the upgrade */
static uint8_t read_cache[LL_FLASH_PAGE_SIZE]; /**< Read cache for flash pages */
static uint8_t data_src_from; /**< Data source for bootloading */
/**
* @brief Perform bootload inspection.
*
* This function calls the `rym_process()` function to perform bootload inspection.
*/
void bootload_inspection(void)
{
rym_process();
}
/**
* @brief Checks if the bootload timeout has occurred.
*
* This function calls the `rym_timeout()` function to determine if the bootload timeout has occurred.
*
* @return TRUE if the bootload timeout has occurred, FALSE otherwise.
*/
BOOL bootload_timeout(void)
{
return rym_timeout();
}
/**
* @brief Handles the beginning of the bootloading process.
*
* This function is responsible for handling the initial steps of the bootloading process.
* It checks if the length of the data to be bootloaded is greater than the end address of the application area.
* If the length is greater, it returns an error code indicating that the bootloading cannot proceed.
* Otherwise, it sets the flash destination address to the start address of the backup area,
* erases the bank of the flash memory where the application is stored,
* and initializes the AES-CMAC context for the upgrade process.
*
* @param p Pointer to the data to be bootloaded.
* @param len Length of the data to be bootloaded.
* @return Error code indicating the result of the operation.
* - RYM_CODE_CAN: If the length of the data is greater than the end address of the application area.
* - RYM_CODE_NONE: If the operation is successful.
*/
static rym_code_e on_begin(uint8_t *p, uint32_t len)
{
if (len > BOOTLOAD_APP_END_ADDRESS)
{
return RYM_CODE_CAN;
}
flashdestination = BOOTLOAD_APP_BACKUP_ADDR_START;
LL_FLASH_Unlock(FLASH);
LL_FLASH_EraseBank(LL_FLASH_BANK2);
LL_FLASH_Lock(FLASH);
AES_CMAC_Init(&upgrade_ctx);
AES_CMAC_SetKey(&upgrade_ctx, upgrade_key);
return RYM_CODE_NONE;
}
/**
* @brief Handles the received data and programs it into the flash memory.
*
* This function unlocks the flash memory, programs the received data into the specified flash destination,
* locks the flash memory again, updates the AES-CMAC context with the received data, and increments the flash destination.
*
* @param p Pointer to the data buffer.
* @param len Length of the data buffer.
* @return The result code indicating the success or failure of the operation.
*/
static rym_code_e on_data(uint8_t *p, uint32_t len)
{
LL_FLASH_Unlock(FLASH);
LL_FLASH_Program(flashdestination, p, len);
LL_FLASH_Lock(FLASH);
AES_CMAC_Update(&upgrade_ctx, p, len);
flashdestination += len;
return RYM_CODE_NONE;
}
/**
* @brief Calculate the MIC (Message Integrity Code) for the firmware upgrade.
*
* This function calculates the MIC using AES-CMAC algorithm for the firmware upgrade data.
* It reads the firmware data from flash memory in pages and updates the MIC calculation.
* Finally, it compares the calculated MIC with the pre-upgrade MIC to determine the success of the upgrade.
*
* @param p Pointer to the firmware data.
* @param len Length of the firmware data.
* @return The result code indicating the success or failure of the upgrade process.
*/
static rym_code_e on_end(uint8_t *p, uint32_t len)
{
AES_CMAC_Final(pre_upgrade_mic, &upgrade_ctx);
upgrade_size = flashdestination - BOOTLOAD_APP_BACKUP_ADDR_START;
AES_CMAC_Init(&upgrade_ctx);
AES_CMAC_SetKey(&upgrade_ctx, upgrade_key);
uint32_t start = BOOTLOAD_APP_BACKUP_ADDR_START;
uint16_t num = (upgrade_size / LL_FLASH_PAGE_SIZE);
uint16_t remain = (upgrade_size % LL_FLASH_PAGE_SIZE);
// STM32L476RG的flash页大小为2K,先读取整数页，再读取余数
for (uint16_t i = 0; i < num; i++)
{
LL_FLASH_Read((start + i * (LL_FLASH_PAGE_SIZE)), read_cache, LL_FLASH_PAGE_SIZE);
AES_CMAC_Update(&upgrade_ctx, read_cache, LL_FLASH_PAGE_SIZE);
}
if (remain)
{
osel_memset(read_cache, 0, LL_FLASH_PAGE_SIZE);
LL_FLASH_Read((start + num * (LL_FLASH_PAGE_SIZE)), read_cache, remain);
AES_CMAC_Update(&upgrade_ctx, read_cache, remain);
}
AES_CMAC_Final(upgrade_mic, &upgrade_ctx);
// 比较mic，相同可以写入标志位告知应用程序升级成功
if (osel_memcmp(upgrade_mic, pre_upgrade_mic, AES_CMAC_DIGEST_LENGTH) == 0)
{
end_callback(TRUE);
}
else
{
end_callback(FALSE);
}
return RYM_CODE_NONE;
}
/**
* @brief Handles the transmission of data.
*
* This function calls the transmit_callback function to transmit the data from the specified source.
*
* @param p Pointer to the data buffer.
* @param len Length of the data buffer.
* @return The return code indicating the status of the transmission.
*/
static rym_code_e on_transmit(uint8_t *p, uint32_t len)
{
transmit_callback(data_src_from, p, (uint16_t)len);
return RYM_CODE_NONE;
}
/**
* @brief Initializes the bootload module.
*
* This function initializes the bootload module by setting the transmit callback
* and configuring the RYM module. It asserts if the initialization fails.
*
* @param transmit The transmit callback function.
*/
void bootload_init(bootload_transmit_callback transmit, bootload_end_callback end)
{
BOOL res = FALSE;
transmit_callback = transmit;
end_callback = end;
res = rym_init();
DBG_ASSERT(res == TRUE __DBG_LINE);
res = rym_config(on_begin, on_data, on_end, on_transmit, BOOTLOAD_TIMEOUT);
DBG_ASSERT(res == TRUE __DBG_LINE);
}
/**
* @brief Sets the data source index for bootload transmission.
*
* This function sets the data source index for bootload transmission. The data source index
* determines the starting point from which the data will be transmitted.
*
* @param to_index The index of the data source.
*/
void bootload_transmit_from(const uint8_t to_index)
{
data_src_from = to_index;
}
/**
* @brief Jump to the specified address and execute the bootloader.
*
* @param address The entry address of the bootloader.
*/
void bootload_jump(uint32_t address)
{
// Get the entry address of the application program
fnc_ptr jump_to_bootload;
jump_to_bootload = (fnc_ptr)(*(__IO uint32_t *)(address + 4));
// Disable RCC
RCC->APB1ENR1 = 0;
RCC->APB1ENR2 = 0;
RCC->APB2ENR = 0;
RCC->AHB1ENR = 0;
RCC->AHB2ENR = 0;
RCC->AHB3ENR = 0;
// Disable SysTick
SysTick->CTRL = 0;
// 清空SysTick
SysTick->LOAD = 0;
// 清空SysTick
SysTick->VAL = 0;
// 设置向量表偏移地址
SCB->VTOR = address;
// 设置堆栈指针
sys_msr_msp(*(__IO uint32_t *)address);
// 跳转
jump_to_bootload();
}

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#ifndef __BOOTLOAD_H
#define __BOOTLOAD_H
#include "lib.h"
#include "flash.h"
#include "flow.h"
#define BOOTLOAD_SET_FLAG 0xbb01
#define BOOTLOAD_UNSET_FLAG 0xbb02
/**
* @brief Defines the start address of the application in flash memory.
*/
#define BOOTLOAD_APP_START_ADDRESS ((uint32_t)0x08000000u)
/**
* @brief Defines the end address of the application in flash memory.
*/
#define BOOTLOAD_APP_END_ADDRESS (BOOTLOAD_APP_START_ADDRESS + 220 * LL_FLASH_PAGE_SIZE) // 220*2048 = 450560
/**
* @brief Defines the start address of the bootloader in flash memory.
*/
#define BOOTLOAD_START_ADDRESS BOOTLOAD_APP_END_ADDRESS
/**
* @brief Defines the start address of the backup area for the application in flash memory.
*/
#define BOOTLOAD_APP_BACKUP_ADDR_START (BOOTLOAD_APP_START_ADDRESS + 256 * LL_FLASH_PAGE_SIZE)
/**
* @brief Defines the timeout for the bootloading process.
*
* This macro defines the timeout for the bootloading process, in seconds. The default value is 10 seconds.
*/
#define BOOTLOAD_TIMEOUT 10
/**
* @brief A function pointer type for a bootload transmit callback function.
*
* This function pointer type is used for a bootload transmit callback function, which is
* called when data needs to be transmitted to the bootloader. The function is passed the
* source of the data (the index of the data packet), a pointer to the data buffer, and the
* length of the data buffer.
*
* @param data_src The index of the data packet that is being transmitted.
* @param buf A pointer to the data buffer.
* @param len The length of the data buffer.
*/
typedef void (*bootload_transmit_callback)(const uint8_t data_src, const uint8_t *buf, const uint16_t len);
/**
* @brief A function pointer type for a bootload end callback function.
*
* This function pointer type is used for a bootload end callback function, which is called
* when the bootloading process is complete. The function takes no parameters and returns no
* value.
*/
typedef void (*bootload_end_callback)(BOOL);
/**
* @brief initializes the bootloader
*
* This function initializes the bootloader, including setting up the communication
* with the host and configuring the flash memory for bootloading.
*
* @param transmit a pointer to the function that will be called to transmit data to the host
*/
void bootload_init(bootload_transmit_callback transmit, bootload_end_callback end);
/**
* @brief Transmits data from the specified index.
*
* This function transmits data from the specified index to the bootloader.
*
* @param to_index The index from which the data should be transmitted.
*/
void bootload_transmit_from(const uint8_t to_index);
/**
* @brief Jumps to the specified address.
*
* This function jumps to the specified address, which is typically the start address of the bootloader.
*
* @param address The address to jump to.
*/
void bootload_jump(uint32_t address);
/**
* @brief Performs inspection of the bootloader.
*
* This function performs inspection of the bootloader, such as checking the version or integrity of the bootloader.
*/
void bootload_inspection(void);
/**
* @brief Checks if a timeout has occurred.
*
* This function checks if a timeout has occurred during the bootloading process.
*
* @return TRUE if a timeout has occurred, FALSE otherwise.
*/
BOOL bootload_timeout(void);
#endif // __BOOTLOAD_H

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# BOOTLOADER介绍
STM32的BOOTLOADER是在芯片复位或从停机模式唤醒时执行的一段小程序，它负责将用户代码加载到内存中并启动它。STM32F1、F4、H7等不同系列的MCU可能会有不同的BOOTLOADER程序。
BOOTLOADER通常用于以下几种情况：
1. 在应用程序无法正常启动时，提供一个后备启动方式。
2. 在系统需要进行固件更新时，可以先通过BOOTLOADER加载新的用户代码。
3. 用于在线调试或调试无法通过JTAG/SWD接口访问时，可以通过BOOTLOADER加载调试工具。
BOOTLOADER的设计和实现通常依赖于芯片的内部结构和特性，以及用户代码存储的介质（如内部FLASH，外部SPI FLASH等）。
一个简单的BOOTLOADER示例可能包括以下步骤：
1. 复位后，芯片开始执行内部的BOOTLOADER程序。
2. 通过某种通信接口（如USART，I2C，SPI）接收新的用户程序代码。
3. 将接收到的代码写入用户代码存储区（如内部FLASH）。
4. 设置启动引脚或者配置BOOT引导模式寄存器，选择启动用户代码。
5. 重启芯片，这次不再执行BOOTLOADER，而是加载并运行新的用户程序代码。
注意：实际的BOOTLOADER实现可能会更加复杂，包括错误检查和处理、加密解密、固件完整性校验等安全措施。
# bootload.c 文件说明
`bootload.c`是一个实现引导加载程序（bootloader）功能的源代码文件。引导加载程序是一段在系统启动时运行的代码，负责初始化硬件设备、建立内存空间映射图，然后加载操作系统内核并将控制权转交给它。
以下是 `bootload.c`文件中可能包含的主要函数和其功能：
1. **系统启动函数** ：这个函数是引导加载程序的入口点，它负责启动整个引导加载过程。
2. **硬件初始化函数** ：这些函数负责初始化系统的硬件设备，包括CPU、内存、IO设备等。
3. **内存映射设置函数** ：这些函数负责建立内存空间的映射图，包括物理内存、虚拟内存的映射关系。
4. **操作系统内核加载函数** ：这些函数负责加载操作系统内核，包括从存储设备读取内核镜像，加载到内存中，然后跳转到内核的入口点。
5. **错误处理函数** ：这些函数负责处理在引导加载过程中可能出现的各种错误，包括硬件错误、内核加载错误等。
# ymodem.c 文件说明
`ymodem.c`是一个实现YMODEM协议的源代码文件。YMODEM是一种用于文件传输的协议，它在XMODEM协议的基础上增加了一些新的特性，例如支持更大的文件和文件名传输。
以下是 `ymodem.c`文件中可能包含的主要函数和其功能：
1. **初始化和结束传输的函数** ：这些函数负责设置传输的开始和结束，包括打开和关闭必要的硬件接口，设置传输参数等。
2. **发送和接收数据包的函数** ：这些函数负责实际的数据传输，包括将数据打包成YMODEM格式的数据包，通过硬件接口发送和接收数据包，处理数据包的确认和重传等。
3. **CRC校验的函数** ：这些函数负责计算和检查数据包的CRC（循环冗余校验）值，以确保数据的完整性。
4. **处理错误和重试的函数** ：这些函数负责处理在传输过程中可能出现的各种错误，包括数据包丢失、CRC校验失败等，并在必要时进行重试。
此外，`ymodem.c`文件还可能包含一些辅助函数，用于处理如超时、缓冲区管理等问题。

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#include "unity.h"
#include "ymodem.c"
void setUp(void)
{
// 这里可以进行每个测试用例开始前的设置
}
void tearDown(void)
{
// 这里可以进行每个测试用例结束后的清理
}
void test_CRC16(void)
{
unsigned char data[] = {0x01, 0x02, 0x03, 0x04, 0x05};
TEST_ASSERT_EQUAL_HEX16(EXPECTED_CRC_VALUE, CRC16(data, sizeof(data)));
}
void test_IS_CAP_LETTER(void)
{
TEST_ASSERT_TRUE(IS_CAP_LETTER('A'));
TEST_ASSERT_FALSE(IS_CAP_LETTER('a'));
}
void test_IS_LC_LETTER(void)
{
TEST_ASSERT_TRUE(IS_LC_LETTER('a'));
TEST_ASSERT_FALSE(IS_LC_LETTER('A'));
}
void test_IS_09(void)
{
TEST_ASSERT_TRUE(IS_09('0'));
TEST_ASSERT_FALSE(IS_09('A'));
}
void test_ISVALIDHEX(void)
{
TEST_ASSERT_TRUE(ISVALIDHEX('A'));
TEST_ASSERT_TRUE(ISVALIDHEX('a'));
TEST_ASSERT_TRUE(ISVALIDHEX('0'));
TEST_ASSERT_FALSE(ISVALIDHEX('G'));
}
void test_ISVALIDDEC(void)
{
TEST_ASSERT_TRUE(ISVALIDDEC('0'));
TEST_ASSERT_FALSE(ISVALIDDEC('A'));
}
void test_CONVERTDEC(void)
{
TEST_ASSERT_EQUAL_HEX8(0, CONVERTDEC('0'));
TEST_ASSERT_EQUAL_HEX8(9, CONVERTDEC('9'));
}
void test_CONVERTHEX(void)
{
TEST_ASSERT_EQUAL_HEX8(10, CONVERTHEX('A'));
TEST_ASSERT_EQUAL_HEX8(10, CONVERTHEX('a'));
TEST_ASSERT_EQUAL_HEX8(0, CONVERTHEX('0'));
}
int main(void)
{
UNITY_BEGIN();
RUN_TEST(test_CRC16);
RUN_TEST(test_IS_CAP_LETTER);
RUN_TEST(test_IS_LC_LETTER);
RUN_TEST(test_IS_09);
RUN_TEST(test_ISVALIDHEX);
RUN_TEST(test_ISVALIDDEC);
RUN_TEST(test_CONVERTDEC);
RUN_TEST(test_CONVERTHEX);
return UNITY_END();
}

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/**
* @file ymodem.c
* @author xxx
* @date 2024-02-18 19:32:40
* @brief
* 该模块实现了YMODEM协议的核心功能，包括初始化、配置、数据接收、握手、数据传输和结束处理。
* 它使用了回调函数来处理不同阶段的事件，并使用信号量来同步不同的流程。CRC校验是用来确保数据传输的完整性和准确性
* @copyright Copyright (c) 2024 by xxx, All Rights Reserved.
*/
#include "ymodem.h"
#include "sys.h"
#include "delay.h"
#include "flow.h"
sqqueue_ctrl_t rym_sqqueue; // 一个接收队列控制结构体，用于管理接收到的数据。
static uint32_t tm_sec = 0; // 握手超时时间，用于握手阶段的超时计时
static enum rym_stage stage = RYM_STAGE_NONE; // 当前的阶段
static int32_t rym_tm_sec = 0; // YMODEM超时计时器
static uint8_t aPacketData[_RYM_PKG_SZ]; // 数据包缓冲区
// 回调函数，用于处理不同阶段的事件
static rym_callback rym_on_begin = NULL;
static rym_callback rym_on_data = NULL;
static rym_callback rym_on_end = NULL;
static rym_callback rym_transmit = NULL;
static struct flow handshake_fw; // 握手流程
static struct flow trans_fw; // 传输流程
static struct flow finsh_fw; // 结束流程
static struct flow_sem msg_sem; // 消息信号量，用于同步
static const uint16_t ccitt_table[256] =
{
0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0};
uint16_t CRC16(unsigned char *q, int len)
{
uint16_t crc = 0;
while (len-- > 0)
crc = (crc << 8) ^ ccitt_table[((crc >> 8) ^ *q++) & 0xff];
return crc;
}
/* Exported macro ------------------------------------------------------------*/
#define IS_CAP_LETTER(c) (((c) >= 'A') && ((c) <= 'F'))
#define IS_LC_LETTER(c) (((c) >= 'a') && ((c) <= 'f'))
#define IS_09(c) (((c) >= '0') && ((c) <= '9'))
#define ISVALIDHEX(c) (IS_CAP_LETTER(c) || IS_LC_LETTER(c) || IS_09(c))
#define ISVALIDDEC(c) IS_09(c)
#define CONVERTDEC(c) (c - '0')
#define CONVERTHEX_ALPHA(c) (IS_CAP_LETTER(c) ? ((c) - 'A' + 10) : ((c) - 'a' + 10))
#define CONVERTHEX(c) (IS_09(c) ? ((c) - '0') : CONVERTHEX_ALPHA(c))
/**
* @brief Convert a string to an integer
* @param p_inputstr: The string to be converted
* @param p_intnum: The integer value
* @retval 1: Correct
* 0: Error
*/
uint32_t Str2Int(uint8_t *p_inputstr, uint32_t *p_intnum)
{
uint32_t i = 0, res = 0;
uint32_t val = 0;
if ((p_inputstr[0] == '0') && ((p_inputstr[1] == 'x') || (p_inputstr[1] == 'X')))
{
i = 2;
while ((i < 11) && (p_inputstr[i] != '\0'))
{
if (ISVALIDHEX(p_inputstr[i]))
{
val = (val << 4) + CONVERTHEX(p_inputstr[i]);
}
else
{
/* Return 0, Invalid input */
res = 0;
break;
}
i++;
}
/* valid result */
if (p_inputstr[i] == '\0')
{
*p_intnum = val;
res = 1;
}
}
else /* max 10-digit decimal input */
{
while ((i < 11) && (res != 1))
{
if (p_inputstr[i] == '\0')
{
*p_intnum = val;
/* return 1 */
res = 1;
}
else if (((p_inputstr[i] == 'k') || (p_inputstr[i] == 'K')) && (i > 0))
{
val = val << 10;
*p_intnum = val;
res = 1;
}
else if (((p_inputstr[i] == 'm') || (p_inputstr[i] == 'M')) && (i > 0))
{
val = val << 20;
*p_intnum = val;
res = 1;
}
else if (ISVALIDDEC(p_inputstr[i]))
{
val = val * 10 + CONVERTDEC(p_inputstr[i]);
}
else
{
/* return 0, Invalid input */
res = 0;
break;
}
i++;
}
}
return res;
}
/**
* @brief Read data from the circular queue.
*
* This function reads the specified length of data from the circular queue and stores it in the given buffer.
* If the length of data in the queue is greater than or equal to the specified length, it directly reads the specified length of data.
* If the length of data in the queue is less than the specified length, it reads all the data in the queue.
*
* @param buffer The buffer to store the data.
* @param len The length of data to read.
*
* @return The actual length of data read.
*/
static uint16_t rym_sqqueue_read(void *buffer, uint16_t len)
{
uint16_t i = 0;
uint8_t *buf = buffer;
if (rym_sqqueue.get_len(&rym_sqqueue) >= len)
{
for (i = 0; i < len; i++)
{
buf[i] = *((uint8_t *)rym_sqqueue.del(&rym_sqqueue));
}
}
else
{
while ((rym_sqqueue.get_len(&rym_sqqueue) != 0) && (i < len))
{
buf[i] = *((uint8_t *)rym_sqqueue.del(&rym_sqqueue));
}
}
return i;
}
/**
* @brief Initializes the parameters for the YMODEM process.
*
* This function sets the stage variable to the specified stage and initializes the rym_tm_sec variable with the value of tm_sec.
* If the stage is RYM_STAGE_ESTABLISHING, it also clears the rym_sqqueue.
*
* @param st The stage of the YMODEM process.
*/
static void rym_process_params_init(enum rym_stage st)
{
stage = st;
rym_tm_sec = tm_sec;
if (st == RYM_STAGE_ESTABLISHING)
{
rym_sqqueue.clear_sqq(&rym_sqqueue);
}
}
/**
* @brief Performs the handshake process for the YMODEM protocol.
*
* This function reads packets from the input queue and performs the necessary checks and actions
* to establish a connection and initiate file transfer using the YMODEM protocol.
*
* @param fl The flow structure containing the necessary variables and synchronization mechanisms.
* @return The result of the handshake process.
* - 0: Handshake process completed successfully.
* - Non-zero: Handshake process failed.
*/
static uint8_t rym_do_handshake_process(struct flow *fl)
{
uint8_t index = 0;
FL_HEAD(fl);
static uint16_t rym_recv_len = 0;
static uint16_t recv_crc, cal_crc;
static uint8_t *file_ptr = NULL;
static uint8_t file_name[FILE_NAME_LENGTH];
static uint8_t file_size[FILE_SIZE_LENGTH];
static uint32_t filesize;
for (;;)
{
FL_LOCK_WAIT_SEM_OR_TIMEOUT(fl, &msg_sem, FL_CLOCK_SEC);
if (FL_SEM_IS_RELEASE(fl, &msg_sem))
{
rym_recv_len = rym_sqqueue_read(&aPacketData[PACKET_START_INDEX], 1);
if (rym_recv_len == 1)
{
if (aPacketData[PACKET_START_INDEX] != RYM_CODE_SOH && aPacketData[PACKET_START_INDEX] != RYM_CODE_STX)
continue;
/* SOH/STX + seq + payload + crc */
rym_recv_len = rym_sqqueue_read(&aPacketData[PACKET_NUMBER_INDEX],
_RYM_PKG_SZ - 1);
if (rym_recv_len != (_RYM_PKG_SZ - 1))
continue;
/* sanity check */
if ((aPacketData[PACKET_NUMBER_INDEX] != 0) || (aPacketData[PACKET_CNUMBER_INDEX] != 0xFF))
continue;
recv_crc = (uint16_t)(*(&aPacketData[PACKET_START_INDEX] + _RYM_PKG_SZ - 2) << 8) |
*(&aPacketData[PACKET_START_INDEX] + _RYM_PKG_SZ - 1);
cal_crc = CRC16(aPacketData + PACKET_DATA_INDEX, _RYM_PKG_SZ - 5);
if (recv_crc != cal_crc)
continue;
if (rym_on_begin != NULL)
{
file_ptr = aPacketData + PACKET_DATA_INDEX;
while ((*file_ptr != 0) && (index < FILE_NAME_LENGTH))
{
file_name[index++] = *file_ptr++;
}
file_name[index++] = '\0';
index = 0;
file_ptr++;
while ((*file_ptr != ' ') && (index < FILE_SIZE_LENGTH))
{
file_size[index++] = *file_ptr++;
}
file_size[index++] = '\0';
Str2Int(file_size, &filesize);
if (RYM_CODE_NONE != rym_on_begin(file_name, filesize))
{
for (uint8_t i = 0; i < RYM_END_SESSION_SEND_CAN_NUM; i++)
{
aPacketData[0] = RYM_CODE_CAN;
rym_transmit(aPacketData, 1);
}
}
else
{
aPacketData[0] = RYM_CODE_ACK;
rym_transmit(aPacketData, 1);
FL_LOCK_DELAY(fl, FL_CLOCK_100MSEC * 5);
aPacketData[0] = RYM_CODE_C;
rym_transmit(aPacketData, 1);
rym_process_params_init(RYM_STAGE_TRANSMITTING);
FL_LOCK_DELAY(fl, FL_CLOCK_SEC);
}
}
}
}
else
{
aPacketData[0] = RYM_CODE_C;
rym_transmit(aPacketData, 1);
rym_tm_sec--;
}
}
FL_TAIL(fl);
}
/**
* @brief Transfers data using the YMODEM protocol.
*
* This function is responsible for transferring data using the YMODEM protocol.
* It receives the size of the data to be transferred and a pointer to the code
* that will be returned. It performs various checks on the received data and
* calculates the CRC to ensure data integrity. If all checks pass, it sets the
* code to RYM_CODE_ACK and returns 0. Otherwise, it returns an error code.
*
* @param data_size The size of the data to be transferred.
* @param code Pointer to the code that will be returned.
* @return 0 if successful, otherwise an error code.
*/
static int8_t rym_tran_data(uint16_t data_size, uint8_t *code)
{
DBG_ASSERT(NULL != code __DBG_LINE);
uint16_t recv_len = 0;
uint16_t recv_crc, cal_crc;
const uint16_t tran_size = PACKET_HEADER_SIZE - 1 + data_size + PACKET_TRAILER_SIZE;
/* seq + data + crc */
recv_len = rym_sqqueue_read(&aPacketData[PACKET_NUMBER_INDEX],
tran_size);
if (recv_len != tran_size)
return -RYM_ERR_DSZ;
/* sanity check */
if ((aPacketData[PACKET_NUMBER_INDEX] + aPacketData[PACKET_CNUMBER_INDEX]) != 0xFF)
return -RYM_ERR_SEQ;
/* As we are sending C continuously, there is a chance that the
* sender(remote) receive an C after sending the first handshake package.
* So the sender will interpret it as NAK and re-send the package. So we
* just ignore it and proceed. */
if (stage == RYM_STAGE_ESTABLISHED && aPacketData[PACKET_NUMBER_INDEX] == RYM_CODE_NONE)
{
*code = RYM_CODE_NONE;
return 0;
}
stage = RYM_STAGE_TRANSMITTING;
recv_crc = (uint16_t)(*(&aPacketData[PACKET_START_INDEX] + tran_size - 1) << 8) |
*(&aPacketData[PACKET_START_INDEX] + tran_size);
cal_crc = CRC16(aPacketData + PACKET_DATA_INDEX, data_size);
if (recv_crc != cal_crc)
return -RYM_ERR_CRC;
*code = RYM_CODE_ACK;
return 0;
}
/**
* @brief Performs the YMODEM transmission process.
*
* This function is responsible for handling the YMODEM transmission process.
* It receives packets of data and performs the necessary operations based on the received data.
* It handles timeouts and retransmissions if necessary.
*
* @param fl The flow structure pointer.
* @return The status of the transmission process.
*/
static uint8_t rym_do_trans_process(struct flow *fl)
{
FL_HEAD(fl);
static uint16_t data_size, rym_recv_len;
static uint8_t rym_code;
static uint16_t tran_timeout = 0;
for (;;)
{
FL_LOCK_WAIT_SEM_OR_TIMEOUT(fl, &msg_sem, FL_CLOCK_SEC);
if (FALSE == FL_SEM_IS_RELEASE(fl, &msg_sem))
{
if (tran_timeout++ >= 5)
{
tran_timeout = 0;
rym_process_params_init(RYM_STAGE_ESTABLISHING);
FL_LOCK_DELAY(fl, FL_CLOCK_SEC);
}
}
else
{
tran_timeout = 0;
rym_recv_len = rym_sqqueue_read(&aPacketData[PACKET_START_INDEX], 1);
if (rym_recv_len == 1)
{
if (aPacketData[PACKET_START_INDEX] == RYM_CODE_SOH)
data_size = PACKET_SIZE;
else if (aPacketData[PACKET_START_INDEX] == RYM_CODE_STX)
data_size = PACKET_1K_SIZE;
else if (aPacketData[PACKET_START_INDEX] == RYM_CODE_EOT)
{
aPacketData[0] = RYM_CODE_NAK;
rym_transmit(aPacketData, 1);
rym_process_params_init(RYM_STAGE_FINISHING);
FL_LOCK_DELAY(fl, FL_CLOCK_SEC);
continue;
}
else
{
rym_process_params_init(RYM_STAGE_ESTABLISHING);
FL_LOCK_DELAY(fl, FL_CLOCK_SEC);
continue;
}
if (rym_tran_data(data_size, &rym_code) == 0)
{
if (rym_on_data != NULL)
rym_on_data(aPacketData + PACKET_DATA_INDEX, data_size);
if (rym_code == RYM_CODE_CAN)
{
for (uint8_t i = 0; i < RYM_END_SESSION_SEND_CAN_NUM; i++)
{
aPacketData[0] = RYM_CODE_CAN;
rym_transmit(aPacketData, 1);
}
}
else if (rym_code == RYM_CODE_ACK)
{
aPacketData[0] = RYM_CODE_ACK;
rym_transmit(aPacketData, 1);
}
}
}
}
}
FL_TAIL(fl);
}
/**
* @brief Performs the finishing process for the YMODEM protocol.
*
* This function is responsible for handling the final stage of the YMODEM protocol,
* where the receiver receives the end of transmission (EOT) signal from the sender.
* It verifies the received EOT signal, sends an acknowledgement (ACK) signal back to
* the sender, and waits for the start of header (SOH) signal to receive the final
* packet containing the payload and checksum. If the received packet is valid, it
* calculates the checksum and compares it with the received checksum. If they match,
* it sets the stage to RYM_STAGE_FINISHED and invokes the callback function if
* available. This function also handles timeout conditions and reinitializes the
* protocol parameters if necessary.
*
* @param fl The flow structure pointer.
* @return The result of the finishing process.
*/
static uint8_t rym_do_finish_process(struct flow *fl)
{
FL_HEAD(fl);
static uint16_t rym_recv_len;
static uint16_t recv_crc, cal_crc;
static uint16_t tran_timeout = 0;
for (;;)
{
FL_LOCK_WAIT_SEM_OR_TIMEOUT(fl, &msg_sem, FL_CLOCK_SEC);
if (FALSE == FL_SEM_IS_RELEASE(fl, &msg_sem))
{
if (tran_timeout++ >= 5)
{
tran_timeout = 0;
rym_process_params_init(RYM_STAGE_ESTABLISHING);
FL_LOCK_DELAY(fl, FL_CLOCK_SEC);
}
}
else
{
tran_timeout = 0;
/* read the length of the packet */
rym_recv_len = rym_sqqueue_read(&aPacketData[PACKET_START_INDEX], 1);
if (rym_recv_len == 1)
{
if (aPacketData[PACKET_START_INDEX] != RYM_CODE_EOT)
continue;
/* send an ACK */
aPacketData[0] = RYM_CODE_ACK;
rym_transmit(aPacketData, 1);
FL_LOCK_DELAY(fl, FL_CLOCK_100MSEC * 5);
/* send a C */
aPacketData[0] = RYM_CODE_C;
rym_transmit(aPacketData, 1);
FL_LOCK_WAIT_SEM_OR_TIMEOUT(fl, &msg_sem, FL_CLOCK_SEC);
if (FALSE == FL_SEM_IS_RELEASE(fl, &msg_sem))
continue;
/* read the length of the packet */
rym_recv_len = rym_sqqueue_read(&aPacketData[PACKET_START_INDEX], 1);
if (rym_recv_len == 1)
{
if (aPacketData[PACKET_START_INDEX] != RYM_CODE_SOH)
continue;
/* SOH/STX + seq + payload + crc */
rym_recv_len = rym_sqqueue_read(&aPacketData[PACKET_NUMBER_INDEX],
_RYM_SOH_PKG_SZ - 1);
if (rym_recv_len != (_RYM_SOH_PKG_SZ - 1))
continue;
/* sanity check */
if ((aPacketData[PACKET_NUMBER_INDEX] != 0) || (aPacketData[PACKET_CNUMBER_INDEX] != 0xFF))
continue;
recv_crc = (uint16_t)(*(&aPacketData[PACKET_START_INDEX] + _RYM_SOH_PKG_SZ - 2) << 8) |
*(&aPacketData[PACKET_START_INDEX] + _RYM_SOH_PKG_SZ - 1);
cal_crc = CRC16(aPacketData + PACKET_DATA_INDEX, _RYM_SOH_PKG_SZ - 5);
if (recv_crc != cal_crc)
continue;
/* we got a valid packet. invoke the callback if there is one. */
stage = RYM_STAGE_FINISHED;
aPacketData[0] = RYM_CODE_ACK;
rym_transmit(aPacketData, 1);
/* we already got one EOT in the caller. invoke the callback if there is
* one. */
if (rym_on_end)
rym_on_end(&aPacketData[PACKET_DATA_INDEX], PACKET_SIZE);
}
}
}
}
FL_TAIL(fl);
}
/**
* @brief Process the Ymodem protocol stages.
*
* This function is responsible for handling the different stages of the Ymodem protocol.
* It performs the necessary actions based on the current stage.
*
* @note The stages include establishing connection, transmitting data, finishing, and others.
*
* @param None
* @return None
*/
void rym_process(void)
{
switch (stage)
{
case RYM_STAGE_ESTABLISHING: // 建立连接 (Establishing connection)
rym_do_handshake_process(&handshake_fw);
break;
case RYM_STAGE_TRANSMITTING: // 传输中 (Transmitting)
rym_do_trans_process(&trans_fw);
break;
case RYM_STAGE_FINISHING: // 结束 (Finishing)
rym_do_finish_process(&finsh_fw);
break;
case RYM_STAGE_NONE:
rym_process_params_init(RYM_STAGE_ESTABLISHING);
break;
case RYM_STAGE_FINISHED:
rym_tm_sec = 0;
break;
default:
// rym_process_params_init(RYM_STAGE_ESTABLISHING);
break;
}
}
/**
* @brief Checks if the YMODEM receive timeout has occurred.
* @return TRUE if the timeout has occurred, FALSE otherwise.
*/
BOOL rym_timeout(void)
{
return rym_tm_sec == 0;
}
/**
* @brief Initializes the YMODEM protocol for receiving files.
*
* This function initializes the necessary data structures and variables
* for receiving files using the YMODEM protocol.
*
* @return TRUE if initialization is successful, FALSE otherwise.
*/
BOOL rym_init(void)
{
sqqueue_ctrl_init(&rym_sqqueue, sizeof(uint8_t), _RYM_PKG_SZ);
FL_INIT(&handshake_fw);
FL_INIT(&trans_fw);
FL_INIT(&finsh_fw);
return TRUE;
}
/**
* @brief Receive data using the Ymodem protocol.
*
* This function is used to receive data transmitted using the Ymodem protocol and store it in the specified buffer.
*
* @param p Pointer to the data storage buffer.
*/
uint16_t rym_receive(void *p, uint16_t size)
{
rym_sqqueue.string_enter(&rym_sqqueue, p, size);
FLOW_SEM_RELEASE(&msg_sem);
return 0;
}
/**
* @brief Configures the YMODEM protocol with the specified callbacks and handshake timeout.
*
* This function sets the callback functions for the YMODEM protocol, which will be called during different stages of the protocol.
* The `on_begin` callback is called when the YMODEM transfer begins.
* The `on_data` callback is called when a data packet is received during the transfer.
* The `on_end` callback is called when the YMODEM transfer ends.
* The `on_transmit` callback is called when a data packet needs to be transmitted during the transfer.
* The `handshake_timeout` parameter specifies the timeout duration for the handshake phase of the YMODEM protocol.
*
* @param on_begin The callback function to be called when the YMODEM transfer begins.
* @param on_data The callback function to be called when a data packet is received during the transfer.
* @param on_end The callback function to be called when the YMODEM transfer ends.
* @param on_transmit The callback function to be called when a data packet needs to be transmitted during the transfer.
* @param handshake_timeout The timeout duration for the handshake phase of the YMODEM protocol.
*
* @return TRUE if the configuration was successful, FALSE otherwise.
*/
BOOL rym_config(rym_callback on_begin, rym_callback on_data,
rym_callback on_end, rym_callback on_transmit,
int handshake_timeout)
{
rym_on_begin = on_begin;
rym_on_data = on_data;
rym_on_end = on_end;
rym_transmit = on_transmit;
tm_sec = handshake_timeout;
return TRUE;
}

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/**
* @file ymodem.h
* @author xsh
* @date 2024-02-18 19:32:46
* @brief
* @copyright Copyright (c) 2024 by xxx, All Rights Reserved.
*/
#ifndef __YMODEM_H__
#define __YMODEM_H__
#include "lib.h"
enum rym_code
{
RYM_CODE_NONE = 0x00,
RYM_CODE_SOH = 0x01, /* start of 128-byte data packet */
RYM_CODE_STX = 0x02, /* start of 1024-byte data packet */
RYM_CODE_EOT = 0x04, /* end of transmission */
RYM_CODE_ACK = 0x06, /* acknowledge */
RYM_CODE_NAK = 0x15, /* negative acknowledge */
RYM_CODE_CAN = 0x18, /* two of these in succession aborts transfer */
RYM_CODE_C = 0x43, /* 'C' == 0x43, request 16-bit CRC */
};
typedef enum rym_code rym_code_e;
/* RYM error code
*
* We use the rt_err_t to return error values. We take use of current error
* codes available in RTT and append ourselves.
*/
/* timeout on handshake */
#define RYM_ERR_TMO 0x70
/* wrong code, wrong SOH, STX etc. */
#define RYM_ERR_CODE 0x71
/* wrong sequence number */
#define RYM_ERR_SEQ 0x72
/* wrong CRC checksum */
#define RYM_ERR_CRC 0x73
/* not enough data received */
#define RYM_ERR_DSZ 0x74
/* the transmission is aborted by user */
#define RYM_ERR_CAN 0x75
/* how many ticks wait for chars between packet. */
#ifndef RYM_WAIT_CHR_TICK
#define RYM_WAIT_CHR_TICK (OSEL_TICK_RATE_HZ * 3)
#endif
/* how many ticks wait for between packet. */
#ifndef RYM_WAIT_PKG_TICK
#define RYM_WAIT_PKG_TICK (OSEL_TICK_RATE_HZ * 3)
#endif
/* how many ticks between two handshake code. */
#ifndef RYM_CHD_INTV_TICK
#define RYM_CHD_INTV_TICK (OSEL_TICK_RATE_HZ * 3)
#endif
/* how many CAN be sent when user active end the session. */
#ifndef RYM_END_SESSION_SEND_CAN_NUM
#define RYM_END_SESSION_SEND_CAN_NUM 0x03
#endif
/* Exported constants --------------------------------------------------------*/
/* Packet structure defines */
#define PACKET_HEADER_SIZE ((uint32_t)3)
#define PACKET_DATA_INDEX ((uint32_t)4)
#define PACKET_START_INDEX ((uint32_t)1)
#define PACKET_NUMBER_INDEX ((uint32_t)2)
#define PACKET_CNUMBER_INDEX ((uint32_t)3)
#define PACKET_TRAILER_SIZE ((uint32_t)2)
#define PACKET_OVERHEAD_SIZE (PACKET_HEADER_SIZE + PACKET_TRAILER_SIZE - 1)
#define PACKET_SIZE ((uint32_t)128)
#define PACKET_1K_SIZE ((uint32_t)1024)
#define _RYM_SOH_PKG_SZ (PACKET_SIZE + PACKET_HEADER_SIZE + PACKET_TRAILER_SIZE)
#define _RYM_STX_PKG_SZ (PACKET_1K_SIZE + PACKET_HEADER_SIZE + PACKET_TRAILER_SIZE)
#define _RYM_PKG_SZ _RYM_STX_PKG_SZ // 这里定义的是数据包的大小
/* 因为data是需要写入到flash里面，如果不对齐，会出现UNALIGNED异常
* /-------- Packet in IAP memory ------------------------------------------\
* | 0 | 1 | 2 | 3 | 4 | ... | n+4 | n+5 | n+6 |
* |------------------------------------------------------------------------|
* | unused | start | number | !num | data[0] | ... | data[n] | crc0 | crc1 |
* \------------------------------------------------------------------------/
* the first byte is left unused for memory alignment reasons */
#define FILE_NAME_LENGTH ((uint32_t)64)
#define FILE_SIZE_LENGTH ((uint32_t)16)
#define NEGATIVE_BYTE ((uint8_t)0xFF)
#define ABORT1 ((uint8_t)0x41) /* 'A' == 0x41, abort by user */
#define ABORT2 ((uint8_t)0x61) /* 'a' == 0x61, abort by user */
#define MAX_ERRORS ((uint32_t)5)
enum rym_stage
{
RYM_STAGE_NONE,
/* set when C is send */
RYM_STAGE_ESTABLISHING,
/* set when we've got the packet 0 and sent ACK and second C */
RYM_STAGE_ESTABLISHED,
/* set when the sender respond to our second C and recviever got a real
* data packet. */
RYM_STAGE_TRANSMITTING,
/* set when the sender send a EOT */
RYM_STAGE_FINISHING,
/* set when transmission is really finished, i.e., after the NAK, C, final
* NULL packet stuff. */
RYM_STAGE_FINISHED,
};
/* when receiving files, the buf will be the data received from ymodem protocol
* and the len is the data size.
*
* TODO:
* When sending files, the len is the buf size in RYM. The callback need to
* fill the buf with data to send. Returning RYM_CODE_EOT will terminate the
* transfer and the buf will be discarded. Any other return values will cause
* the transfer continue.
*/
typedef enum rym_code (*rym_callback)(uint8_t *buf, uint32_t len);
/** recv a file on device dev with ymodem session ctx.
*
* If an error happens, you can get where it is failed from ctx->stage.
*
* @param on_begin The callback will be invoked when the first packet arrived.
* This packet often contain file names and the size of the file, if the sender
* support it. So if you want to save the data to a file, you may need to
* create the file on need. It is the on_begin's responsibility to parse the
* data content. The on_begin can be NULL, in which case the transmission will
* continue without any side-effects.
*
* @param on_data The callback will be invoked on the packets received. The
* callback should save the data to the destination. The return value will be
* sent to the sender and in turn, only RYM_{ACK,CAN} is valid. When on_data is
* NULL, RYM will barely send ACK on every packet and have no side-effects.
*
* @param on_end The callback will be invoked when one transmission is
* finished. The data should be 128 bytes of NULL. You can do some cleaning job
* in this callback such as closing the file. The return value of this callback
* is ignored. As above, this parameter can be NULL if you don't need such
* function.
*
* @param handshake_timeout the timeout when hand shaking. The unit is in
* second.
*/
BOOL rym_config(rym_callback on_begin, rym_callback on_data,
rym_callback on_end, rym_callback on_transmit,
int handshake_timeout);
/**
* @brief Initializes the YMODEM protocol for receiving data.
*
* @return BOOL Returns TRUE if initialization is successful, FALSE otherwise.
*/
BOOL rym_init(void);
/**
* @brief Receives data using the YMODEM protocol.
*
* @param p Pointer to the buffer where the received data will be stored.
* @param size The size of the buffer.
* @return uint16_t The number of bytes received.
*/
uint16_t rym_receive(void *p, uint16_t size);
/**
* @brief Processes the received data using the YMODEM protocol.
*/
void rym_process(void);
/**
* @brief Checks if a timeout has occurred during the YMODEM protocol.
*
* @return BOOL Returns TRUE if a timeout has occurred, FALSE otherwise.
*/
BOOL rym_timeout(void);
#endif

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#ifndef __PID_H__
#define __PID_H__
#include "lib.h"
#include "pid_auto_tune.h"
#define INCOMPLETE_DIFFEREN 0 // 不完全微分
typedef enum
{
PID_SUB_TYPE_POSITION = 1, // 位置式
PID_SUB_TYPE_INCREMENT = 2, // 增量式
} pid_sub_type_e;
typedef enum
{
DEAD_ZONE_BOTH = 0, // 正负都可以
DEAD_ZONE_POSITIVE = 1, // 正数
DEAD_ZONE_NEGATIVE = 2, // 负数
} deadzone_e;
typedef enum
{
// PID自整定
PID_TYPE_AUTO_TUNE,
// 通用PID
PID_TYPE_COMMON,
// 神经PID
PID_TYPE_NEURAL,
// 模糊PID
PID_TYPE_FUZZY,
// 以下是自定义PID
// cj PID
PID_TYPE_CUSTOM_CAO,
// gp jPID
PID_TYPE_CUSTOM_GAO,
// xsh PID
PID_TYPE_CUSTOM_XU,
// zxm PID
PID_TYPE_CUSTOM_ZHANG,
// hangdian PID
PID_TYPE_CUSTOM_HANGDIAN,
} pid_type_e;
typedef struct
{
float32 ref;
float32 feedback;
float32 pre_feedback;
float32 e_0; // 当前误差
float32 e_1; // 上一次误差
float32 kp;
float32 ki;
float32 kd;
float32 err_limit;
BOOL detach;
float32 err_dead;
float32 alpha;
float32 lastdev;
float32 out;
float32 out_max;
float32 out_min;
float32 sv_range;
float32 iout; // 积分输出
BOOL sm;
BOOL ki_enable;
BOOL kd_enable;
float32 deviation; // 纠正系统误差造成的影响，作用于死区，大于0需要补偿，小于0需要反向补偿
BOOL in_dead_zone; // 是否在死区内
} pid_common_position_t; // 位置式PID
typedef struct
{
float32 ref; // 目标设定值
float32 feedback; // 传感器采集值
float32 out; // PID计算结果
float32 kp;
float32 ki;
float32 kd;
float32 e_0; // 当前误差
float32 e_1; // 上一次误差
float32 e_2; // 上上次误差
float32 err_dead;
float32 deviation; // 纠正系统误差造成的影响，作用于死区
float32 out_max; // 输出限幅
float32 out_min; // 输出限幅
float32 sum_iterm;
float32 iout; // 积分输出
float32 alpha; // 不完全微分参数
float32 lastdev; // 不完全微分参数
BOOL sm;
BOOL ki_enable;
BOOL kd_enable;
float32 sv_range;
// 没有用的
float32 err_limit;
BOOL detach;
} pid_common_increment_t; // 增量式PID
typedef struct PID_COMMON
{
uint8_t type;
/* 设置PID三个参数 */
void (*set_ctrl_prm)(struct PID_COMMON *self, float32 kp, float32 ki, float32 kd);
/* 设置积分范围 */
void (*set_integral_prm)(struct PID_COMMON *self, float32 integral_up, float32 integral_low);
/* 控制接口 */
float32 (*PID)(struct PID_COMMON *self, float32 err);
/* in value */
float32 err;
/* out value */
float32 out;
union
{
pid_common_position_t position;
pid_common_increment_t increment;
} pri_u;
} pid_common_t; // 通用PID
typedef struct PID_NEURAL
{
uint8_t type;
/* 设置PID三个参数 */
void (*set_ctrl_prm)(struct PID_NEURAL *self, float32 minimum, float32 maximum);
/* 设置输出范围 */
void (*set_out_prm)(struct PID_NEURAL *self, float32 minimum, float32 maximum);
/* 控制接口 */
float32 (*PID)(struct PID_NEURAL *self, float32 target, float32 feedback);
struct
{
float32 setpoint; /*设定值*/
float32 kcoef; /*神经元输出比例*/
float32 kp; /*比例学习速度*/
float32 ki; /*积分学习速度*/
float32 kd; /*微分学习速度*/
float32 lasterror; /*前一拍偏差*/
float32 preerror; /*前两拍偏差*/
float32 deadband; /*死区*/
float32 result; /*输出值*/
float32 output; /*百分比输出值*/
float32 maximum; /*输出值的上限*/
float32 minimum; /*输出值的下限*/
float32 wp; /*比例加权系数*/
float32 wi; /*积分加权系数*/
float32 wd; /*微分加权系数*/
} pri;
} pid_neural_t; // 神经PID
typedef struct
{
float32 kp;
float32 ki;
float32 kd;
float32 kup;
float32 kui;
float32 kud;
float32 maxe; // 非线性区间最大值
float32 mine; // 非线性区间最小值
} FUZZY_PID_t;
// 模糊PID
typedef struct PID_FUZZY
{
/* 设置PID三个参数 */
void (*set_ctrl_prm)(struct PID_FUZZY *self, float32 kp, float32 ki, float32 kd, float32 err_dead, float32 deviation,
float32 out_min, float32 out_max); // 设置PID参数
void (*set_error_max_min)(struct PID_FUZZY *self, float32 mine, float32 maxe); // 设置非线性区间值
void (*update_ctrl_prm)(struct PID_FUZZY *self, float32 kp, float32 ki, float32 kd, float32 err_dead,
float32 out_min, float32 out_max); // 更新PID参数
void (*set_range)(struct PID_FUZZY *self, float32 out_min, float32 out_max); // 更新最大最小值
void (*set_cfg)(struct PID_FUZZY *self, float32 max_err, BOOL mode); // 配置PID模式,默认不使用积分分离
void (*set_smooth_enable)(struct PID_FUZZY *self, BOOL enable, float32 sv_range); // 设置平滑范围
void (*set_iout)(struct PID_FUZZY *self, float32 iout); // 设置积分输出
void (*set_err_dead)(struct PID_FUZZY *self, float32 err_dead); // 设置死区
void (*set_kp)(struct PID_FUZZY *self, float32 kp);
void (*set_ki_enable)(struct PID_FUZZY *self, BOOL enable);
void (*set_ki)(struct PID_FUZZY *self, float32 ki);
// 微分开启使能
void (*set_kd_enable)(struct PID_FUZZY *self, BOOL enable);
void (*set_kd)(struct PID_FUZZY *self, float32 kd);
void (*set_kd_dev)(struct PID_FUZZY *self, float32 alpha);
void (*restctrl)(struct PID_FUZZY *self, float32 out); // 复位PID积分及微分控制数据
/* 控制接口 */
float32 (*execute)(struct PID_FUZZY *self, float32 target, float32 feedback);
BOOL(*in_dead_zone)
(struct PID_FUZZY *self);
union
{
pid_common_position_t position;
pid_common_increment_t increment;
} pri_u;
pid_sub_type_e sub_type; // 位置式PID，增量式PID
BOOL open; // 是否使用模糊PID控制
BOOL speed_integral_enable; // 变速积分，暂时没有验证成功
deadzone_e deadzone_dir;
FUZZY_PID_t pid_params;
} pid_fuzzy_t; // 模糊PID
// PID
typedef struct
{
BOOL is_init; // 是否初始化
pid_type_e type; // 不同的算法类型，模糊PID，神经PID，通用PID
pid_sub_type_e sub_type; // 位置式PID，增量式PID
union
{
pid_common_t common;
pid_neural_t neural;
pid_fuzzy_t fuzzy;
} pid_u;
pid_auto_tune_t auto_tune;
} pid_t;
// PID控制
extern void pid_constructor(pid_t *self);
// private
// 神经元PID
extern void pid_neural_constructor(struct PID_NEURAL *self);
// 模糊PID
extern void pid_fuzzy_constructor(struct PID_FUZZY *self);
#endif

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/***
* @Author:
* @Date: 2023-07-24 11:17:55
* @LastEditors: xxx
* @LastEditTime: 2023-07-24 11:19:06
* @Description:pid自动调参，构建闭环回路 确定稳定极限 确定两个参数 极限值KP和震荡周期
* @email:
* @Copyright (c) 2023 by xxx, All Rights Reserved.
*/
#ifndef __PID_AUTO_TUNE_H__
#define __PID_AUTO_TUNE_H__
#include "lib.h"
typedef struct PID_AUTO_TUNE
{
// public:
void (*set_ctrl_prm)(struct PID_AUTO_TUNE *self, float32 *input, float32 *output);
int32_t (*runtime)(struct PID_AUTO_TUNE *self);
void (*set_output_step)(struct PID_AUTO_TUNE *self, int32_t step);
void (*set_control_type)(struct PID_AUTO_TUNE *self, int32_t type);
void (*set_noise_band)(struct PID_AUTO_TUNE *self, int32_t band);
void (*set_look_back)(struct PID_AUTO_TUNE *self, int32_t n);
float32 (*get_kp)(struct PID_AUTO_TUNE *self);
float32 (*get_ki)(struct PID_AUTO_TUNE *self);
float32 (*get_kd)(struct PID_AUTO_TUNE *self);
// private:
struct
{
BOOL isMax, isMin; // 运算中出现最大、最小值标志
float32 *input, *output;
float32 setpoint; // 反向控制判断值，这个值需要根据对象的实际工作值确定！是通过第一次启动时对应的输入值带入的。
int32_t noiseBand; // 判断回差，类似于施密特触发器，实际控制反向的比较值是 setpoint + noiseBand 或 setpoint - noiseBand
int32_t controlType; // 计算 PID 参数时，选择 PI 或 PID 模式，输出 Kp Ki，或 Kp、Ki、Kd
BOOL running;
uint32_t peak1, peak2, lastTime; // 峰值对应的时间
int32_t sampleTime;
int32_t nLookBack;
int32_t peakType;
int32_t lastInputs[51]; // 保存的历史输入值, 改为 50 次。 by shenghao.xu
int32_t peaks[13]; // 保存的历史峰值，最多存前 12 次，对应 6个最大、6个最小。20221124 by Embedream
int32_t peakCount; // 峰值计数
int32_t peakPeriod[7]; // 保存前 6 次的最大值间隔时间 by shenghao.xu
int32_t peakMaxCount; // 最大峰值计数 by shenghao.xu
BOOL justchanged;
int32_t oStep; // 这个值是用于计算控制高低值的，以 outputStart 为中值，输出高值用 outputStart + oStep， 输出低值用 outputStart - oStep
float32 outputStart; // 输出控制的基础值，这个需要结合对象特征确定，此值也是通过第一次启动时对应的输出值带入的。
float32 Ku, Pu;
} pri;
} pid_auto_tune_t;
extern void pid_auto_tune_constructor(struct PID_AUTO_TUNE *self);
#endif // __PID_AUTO_TUNE_H__

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#ifndef __S_CURVE_H
#define __S_CURVE_H
#include "lib.h"
typedef struct
{
// 起始频率
float32 f0;
// 加加速段斜率
float32 faa;
// 减减速段斜率
float32 frr;
// 加加速段时间
float32 taa;
// 匀加速段时间
float32 tua;
// 减加速段时间
float32 tra;
// 匀速段时间
float32 tuu;
// 加减速段时间
float32 tar;
// 匀减速段时间
float32 tur;
// 减减速段时间
float32 trr;
} s_curve_t;
void s_curve_table_gen(uint16_t tmin, uint16_t tmax);
#endif // __S_CURVE_H

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#include "pid.h"
#include <math.h>
// 构造函数将接口绑定
void pid_constructor(pid_t *self)
{
switch (self->type)
{
case PID_TYPE_COMMON:
/* code */
break;
case PID_TYPE_NEURAL:
pid_neural_constructor(&self->pid_u.neural);
break;
case PID_TYPE_FUZZY:
DBG_ASSERT(self->sub_type != 0 __DBG_LINE);
self->pid_u.fuzzy.sub_type = self->sub_type;
pid_fuzzy_constructor(&self->pid_u.fuzzy);
break;
case PID_TYPE_AUTO_TUNE:
pid_auto_tune_constructor(&self->auto_tune);
break;
default:
break;
}
self->is_init = TRUE;
}

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#include "pid_auto_tune.h"
#include "sys.h"
/*
设置峰值回溯时间,单位 0.1 秒，最小 0.2秒， 最大 4 秒
*/
static void set_look_backsec(pid_auto_tune_t *self, int32_t value)
{
if (value < 2)
value = 2;
if (value > 40)
value = 40;
if (value < 40)
{
self->pri.nLookBack = 12; // 按目前实际周期约300ms、采样周期 10ms 考虑，一个周期只有 30 点，回溯 12 点即可。
self->pri.sampleTime = value * 10; // 改为 Value*10 ms， 20、30、40 ~ 200ms
}
else
{
self->pri.nLookBack = 50 + value;
self->pri.sampleTime = 4000;
}
}
static void _set_ctrl_prm(struct PID_AUTO_TUNE *self, float32 *input, float32 *output)
{
self->pri.input = input;
self->pri.output = output;
self->pri.controlType = 0; // 默认为 PI 模式
self->pri.noiseBand = 1;
self->pri.running = FALSE;
self->pri.oStep = 1;
set_look_backsec(self, 8);
self->pri.lastTime = sys_millis();
}
static void _set_noise_band(struct PID_AUTO_TUNE *self, int32_t value)
{
self->pri.noiseBand = value;
}
static void _set_output_step(struct PID_AUTO_TUNE *self, int32_t value)
{
self->pri.oStep = value;
}
// * Determies if the tuning parameters returned will be PI (D=0)
// or PID. (0=PI, 1=PID)
static void _set_control_type(struct PID_AUTO_TUNE *self, int32_t value)
{
self->pri.controlType = value;
}
static void _set_look_back(struct PID_AUTO_TUNE *self, int32_t value)
{
set_look_backsec(self, value);
}
static float32 _get_kp(struct PID_AUTO_TUNE *self)
{
float32 kp = self->pri.controlType == 1 ? 0.6f * self->pri.Ku : 0.4f * self->pri.Ku;
return kp;
}
static float32 _get_ki(struct PID_AUTO_TUNE *self)
{
float32 ki = self->pri.controlType == 1 ? 1.2f * self->pri.Ku / self->pri.Pu : 0.48f * self->pri.Ku / self->pri.Pu;
return ki;
}
static float32 _get_kd(struct PID_AUTO_TUNE *self)
{
return self->pri.controlType == 1 ? 0.075f * self->pri.Ku * self->pri.Pu : 0;
}
/**
* @brief 修改返回值，0 - 执行计算，未完成整定， 1 - 执行计算，完成整定过程， 2 - 采样时间未到
* @return {*}
*/
static int32_t _runtime(struct PID_AUTO_TUNE *self)
{
int32_t i, iSum;
uint32_t now = sys_millis();
if ((now - self->pri.lastTime) < ((uint32_t)self->pri.sampleTime))
{
return 2; // 原来返回值为 FALSE 不符合函数定义，也无法区分，改为 2，by shenghao.xu
}
// 开始整定计算
self->pri.lastTime = now;
float32 refVal = *(self->pri.input);
if (FALSE == self->pri.running) // 首次进入，初始化参数
{
self->pri.peakType = 0;
self->pri.peakCount = 0;
self->pri.peakMaxCount = 0;
self->pri.peak1 = 0;
self->pri.peak2 = 0;
self->pri.justchanged = FALSE;
self->pri.setpoint = refVal; // 不变
self->pri.running = TRUE;
self->pri.outputStart = *self->pri.output;
*self->pri.output = self->pri.outputStart + self->pri.oStep;
}
// 根据输入与设定点的关系振荡输出
if (refVal > (self->pri.setpoint + self->pri.noiseBand))
*self->pri.output = self->pri.outputStart - self->pri.oStep;
else if (refVal < (self->pri.setpoint - self->pri.noiseBand))
*self->pri.output = self->pri.outputStart + self->pri.oStep;
// bool isMax=TRUE, isMin=TRUE;
self->pri.isMax = TRUE;
self->pri.isMin = TRUE;
// id peaks
/*
以下循环完成，对回溯次数的输入缓存进行判断，如果输入值均大于或小于缓存值，则确定此次为峰值。
峰值特征根据 isMax、isMin 哪个为真确定。
同时完成输入缓存向后平移，腾出第一个单元存放新的输入值。
这一段代码完成的噪声所产生的虚假峰值判断，应该没有问题！
*/
for (i = self->pri.nLookBack - 1; i >= 0; i--)
{
int32_t val = self->pri.lastInputs[i];
if (self->pri.isMax)
self->pri.isMax = (refVal > val); // 第一次是新输入和缓存最后一个值比较，如果大于，则前面的值均判是否大于
if (self->pri.isMin)
self->pri.isMin = (refVal < val); // 第一次是新输入和缓存最后一个值比较，如果小于，则前面的值均判是否小于
self->pri.lastInputs[i + 1] = self->pri.lastInputs[i]; // 每采样一次，将输入缓存的数据向后挪一次
}
self->pri.lastInputs[0] = refVal; // 新采样的数据放置缓存第一个单元。
/*
以下代码完成峰值的确定，以及对应峰值的时间纪录。
因为上述代码只是去掉噪产生的波动峰值，但如果是连续超过 nLookBack 次数的的上升或下降，
则上述算法所确定的最大或最小值，并非是峰值，只能是前 nLookBack 次中的最大或最小值。
但逐句消化程序后，发现这段处理有几点疑惑：
1、peaks[] 的纪录好像不对，在执行最小到最大值转换时，peakCount 也应该+1，否则应该把
纪录的最小值覆盖了！所以后面的峰值判断总是满足条件。
2、峰值对应时间似乎也应该多次存放，取平均值，因对象没有那么理想化，目前应该是取的最后一组峰值的周期。
3、后续计算 Ku 用的是整个整定过程的最大、最小值，这对于非理想的对象而言也不是很合适。
考虑做如下改进：
1）修改峰值纪录，设计12个峰值保存单元，存满12个峰值（6大、6小）后再计算。
2）纪录 6 组最大值的间隔时间，作为最终计算 Pu 的数据。
*/
if (self->pri.isMax)
{
if (self->pri.peakType == 0)
self->pri.peakType = 1; // 首次最大值，初始化
if (self->pri.peakType == -1) // 如果前一次为最小值，则标识目前进入最大值判断
{
self->pri.peakType = 1; // 开始最大值判断
self->pri.peakCount++; // 峰值计数 by shenghao.xu
self->pri.justchanged = TRUE; // 标识峰值转换
if (self->pri.peak2 != 0) // 已经纪录一次最大峰值对应时间后，开始记录峰值周期 by shenghao.xu
{
self->pri.peakPeriod[self->pri.peakMaxCount] = (int32_t)(self->pri.peak1 - self->pri.peak2); // 最大峰值间隔时间（即峰值周期）
self->pri.peakMaxCount++; // 最大峰值计数
}
self->pri.peak2 = self->pri.peak1; // 刷新上次最大值对应时间
}
self->pri.peak1 = now; // 保存最大值对应时间 peak1
self->pri.peaks[self->pri.peakCount] = refVal; // 保存最大值
} // 此段代码可以保证得到的是真正的最大值，因为peakType不变，则会不断刷新最大值
else if (self->pri.isMin)
{
if (self->pri.peakType == 0)
self->pri.peakType = -1; // 首次最小值，初始化
if (self->pri.peakType == 1) // 如果前一次是最大值判断，则转入最小值判断
{
self->pri.peakType = -1; // 开始最小值判断
self->pri.peakCount++; // 峰值计数
self->pri.justchanged = TRUE;
}
if (self->pri.peakCount < 10)
self->pri.peaks[self->pri.peakCount] = refVal; // 只要类型不变，就不断刷新最小值
}
/* by shenghao.xu
以下计算是作为判断采集数据是否合适的部分，如果 2 次峰值判断条件满足，就结束整定过程，感觉不甚合理。
拟修改为：
1）计满 12 次峰值后再计算(到第 13 次)。
2）不再判断是否合理，因为对象如果特性好，自然已经稳定，如果不好，再长时间也无效果。
3）将后面5次的数据作为素材，去掉第一组数据，因为考虑第一组时对象可能处于过渡过程。
4）用后 10 点得到的 9 个峰值差平均值作为 Ku 计算值中的 A，取代原来的整个过程的最大、最小值差。
5）用后 5 点峰值周期平均值作为 Pu 的计算值，取代原来用最后一组的值。
*/
if (self->pri.justchanged && self->pri.peakCount == 12)
{
// we've transitioned. check if we can autotune based on the last peaks
iSum = 0;
for (i = 2; i <= 10; i++)
iSum += ABS(self->pri.peaks[i] - self->pri.peaks[i + 1]);
iSum /= 9; // 取 9 次峰峰值平均值
self->pri.Ku = (float32)(4 * (2 * self->pri.oStep)) / (iSum * 3.14159); // 用峰峰平均值计算 Ku
iSum = 0;
for (i = 1; i <= 5; i++)
iSum += self->pri.peakPeriod[i];
iSum /= 5; // 计算峰值的所有周期平均值
self->pri.Pu = (float32)(iSum) / 1000; // 用周期平均值作为 Pu，单位：秒
*self->pri.output = 0;
self->pri.running = FALSE;
return 1;
}
self->pri.justchanged = FALSE;
return 0;
}
void pid_auto_tune_constructor(struct PID_AUTO_TUNE *self)
{
self->set_ctrl_prm = _set_ctrl_prm;
self->runtime = _runtime;
self->set_output_step = _set_output_step;
self->set_control_type = _set_control_type;
self->set_noise_band = _set_noise_band;
self->set_look_back = _set_look_back;
self->get_kp = _get_kp;
self->get_ki = _get_ki;
self->get_kd = _get_kd;
}

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#include "pid.h"
#include <math.h>
// 定义死区枚举
#define DEADZONE DEAD_ZONE_POSITIVE
// 模糊集合
#define NL -3
#define NM -2
#define NS -1
#define ZE 0
#define PS 1
#define PM 2
#define PL 3
// 定义偏差E的范围，因为设置了非线性区间，误差在10时才开始进行PID调节，这里E的范围为10
#define MAXE (100)
#define MINE (-MAXE)
// 定义EC的范围，因为变化非常缓慢！，每次的EC都非常小，这里可以根据实际需求来调整，
#define MAXEC (100)
#define MINEC (-MAXEC)
// 定义e,ec的量化因子
#define KE 3 / MAXE
#define KEC 3 / MAXEC
// 定义输出量比例因子
#define KUP 1.0f // 这里只使用了模糊PID的比例增益
#define KUI 0.0f
#define KUD 0.0f
static const float32 fuzzyRuleKp[7][7] = {
PL, PL, PM, PL, PS, PM, PL,
PL, PM, PM, PM, PS, PM, PL,
PM, PS, PS, PS, PS, PS, PM,
PM, PS, ZE, ZE, ZE, PS, PM,
PS, PS, PS, PS, PS, PM, PM,
PM, PM, PM, PM, PL, PL, PL,
PM, PL, PL, PL, PL, PL, PL};
static const float32 fuzzyRuleKi[7][7] = {
NL, NL, NL, NL, NM, NL, NL,
NL, NL, NM, NM, NM, NL, NL,
NM, NM, NS, NS, NS, NM, NM,
NM, NS, ZE, ZE, ZE, NS, NM,
NM, NS, NS, NS, NS, NM, NM,
NM, NM, NS, NM, NM, NL, NL,
NM, NL, NM, NL, NL, NL, NL};
static const float32 fuzzyRuleKd[7][7] = {
PS, PS, ZE, ZE, ZE, PL, PL,
NS, NS, NS, NS, ZE, NS, PM,
NL, NL, NM, NS, ZE, PS, PM,
NL, NM, NM, NS, ZE, PS, PM,
NL, NM, NS, NS, ZE, PS, PS,
NM, NS, NS, NS, ZE, PS, PS,
PS, ZE, ZE, ZE, ZE, PL, PL};
static void fuzzy(float32 e, float32 ec, FUZZY_PID_t *fuzzy_pid)
{
float32 etemp, ectemp;
float32 eLefttemp, ecLefttemp; // ec,e，左隶属度
float32 eRighttemp, ecRighttemp;
int eLeftIndex, ecLeftIndex; // 模糊位置标号
int eRightIndex, ecRightIndex;
e = RANGE(e, fuzzy_pid->mine, fuzzy_pid->maxe);
ec = RANGE(ec, MINEC, MAXEC);
e = e * KE;
ec = ec * KEC;
etemp = e > 3.0f ? 0.0f : (e < -3.0f ? 0.0f : (e >= 0.0f ? (e >= 2.0f ? 2.5f : (e >= 1.0f ? 1.5f : 0.5f)) : (e >= -1.0f ? -0.5f : (e >= -2.0f ? -1.5f : (e >= -3.0f ? -2.5f : 0.0f)))));
eLeftIndex = (int)((etemp - 0.5f) + 3); //[-3,3] -> [0,6]
eRightIndex = (int)((etemp + 0.5f) + 3);
eLefttemp = etemp == 0.0f ? 0.0f : ((etemp + 0.5f) - e); //
eRighttemp = etemp == 0.0f ? 0.0f : (e - (etemp - 0.5f));
ectemp = ec > 3.0f ? 0.0f : (ec < -3.0f ? 0.0f : (ec >= 0.0f ? (ec >= 2.0f ? 2.5f : (ec >= 1.0f ? 1.5f : 0.5f)) : (ec >= -1.0f ? -0.5f : (ec >= -2.0f ? -1.5f : (ec >= -3.0f ? -2.5f : 0.0f)))));
ecLeftIndex = (int)((ectemp - 0.5f) + 3); //[-3,3] -> [0,6]
ecRightIndex = (int)((ectemp + 0.5f) + 3);
ecLefttemp = ectemp == 0.0f ? 0.0f : ((ectemp + 0.5f) - ec);
ecRighttemp = ectemp == 0.0f ? 0.0f : (ec - (ectemp - 0.5f));
/*************************************反模糊*************************************/
fuzzy_pid->kp = (eLefttemp * ecLefttemp * fuzzyRuleKp[eLeftIndex][ecLeftIndex] + eLefttemp * ecRighttemp * fuzzyRuleKp[eLeftIndex][ecRightIndex] + eRighttemp * ecLefttemp * fuzzyRuleKp[eRightIndex][ecLeftIndex] + eRighttemp * ecRighttemp * fuzzyRuleKp[eRightIndex][ecRightIndex]);
fuzzy_pid->ki = (eLefttemp * ecLefttemp * fuzzyRuleKi[eLeftIndex][ecLeftIndex] + eLefttemp * ecRighttemp * fuzzyRuleKi[eLeftIndex][ecRightIndex] + eRighttemp * ecLefttemp * fuzzyRuleKi[eRightIndex][ecLeftIndex] + eRighttemp * ecRighttemp * fuzzyRuleKi[eRightIndex][ecRightIndex]);
fuzzy_pid->kd = (eLefttemp * ecLefttemp * fuzzyRuleKd[eLeftIndex][ecLeftIndex] + eLefttemp * ecRighttemp * fuzzyRuleKd[eLeftIndex][ecRightIndex] + eRighttemp * ecLefttemp * fuzzyRuleKd[eRightIndex][ecLeftIndex] + eRighttemp * ecRighttemp * fuzzyRuleKd[eRightIndex][ecRightIndex]);
// 对解算出的KP,KI,KD进行量化映射
fuzzy_pid->kp = fuzzy_pid->kp * fuzzy_pid->kup;
fuzzy_pid->ki = fuzzy_pid->ki * fuzzy_pid->kui;
fuzzy_pid->kd = fuzzy_pid->kd * fuzzy_pid->kud;
}
/**
* @brief SV平滑给定,步长默认为0.1，范围0-1之间，越大平滑性越差
* @param {PID_FUZZY} *self
* @param {float32} target_sv
* @return {*}
* @note
*/
static void smooth_setpoint(struct PID_FUZZY *self, float32 target_sv)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
float32 stepIn = (pri->sv_range) * 0.1f;
float32 kFactor = 0.0f;
if (fabs(pri->ref - target_sv) <= stepIn)
{
pri->ref = target_sv;
}
else
{
if (pri->ref - target_sv > 0)
{
kFactor = -1.0f;
}
else if (pri->ref - target_sv < 0)
{
kFactor = 1.0f;
}
else
{
kFactor = 0.0f;
}
pri->ref = pri->ref + kFactor * stepIn;
}
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
float32 stepIn = (pri->sv_range) * 0.1f;
float32 kFactor = 0.0f;
if (fabs(pri->ref - target_sv) <= stepIn)
{
pri->ref = target_sv;
}
else
{
if (pri->ref - target_sv > 0)
{
kFactor = -1.0f;
}
else if (pri->ref - target_sv < 0)
{
kFactor = 1.0f;
}
else
{
kFactor = 0.0f;
}
pri->ref = pri->ref + kFactor * stepIn;
}
}
}
// 变速积分
static float32 changing_integral_rate(struct PID_FUZZY *self)
{
float32 err = 0, iout = 0;
float32 err_1 = 1, // 误差下限
err_2 = 10; // 误差上限
float32 index = 0;
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
err = pri->e_0;
iout = pri->iout;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
err = pri->e_0;
iout = pri->iout;
}
if (err * iout > 0) // 判断积分是否为积累趋势
{
if (ABS(err) <= err_1)
{
index = 1; // 完整积分
}
else if (ABS(err) <= (err_1 + err_2))
{
// 使用线性函数过渡
index = (float)(err_2 - ABS(err) + err_1) / err_2;
}
else
{
index = 0;
}
}
return index;
}
/*封装模糊接口*/
static void compensate(float32 e, float32 ec, FUZZY_PID_t *fuzzy_d)
{
fuzzy(e, ec, fuzzy_d);
}
/**
* @brief 更新最大最小值
* @param {PID_FUZZY} *self
* @param {float32} out_min
* @param {float32} out_max
* @return {*}
* @note
*/
static void _set_range(struct PID_FUZZY *self, float32 out_min, float32 out_max)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->out_max = out_max;
pri->out_min = out_min;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->out_max = out_max;
pri->out_min = out_min;
}
}
/**
* @brief 设置死区
* @param {PID_FUZZY} *self
* @param {float32} err_dead
* @return {*}
* @note
*/
static void _set_err_dead(struct PID_FUZZY *self, float32 err_dead)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->err_dead = err_dead;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->err_dead = err_dead;
}
}
static void _set_iout(struct PID_FUZZY *self, float32 iout)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->iout = iout;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->iout = iout;
}
}
static void _set_kp(struct PID_FUZZY *self, float32 kp)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->kp = kp;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->kp = kp;
}
}
/**
* @brief 使能积分控制
* @param {PID_FUZZY} *self
* @param {BOOL} enable
* @return {*}
* @note
*/
// static void _set_ki_enable(struct PID_FUZZY *self, BOOL enable)
// {
// pri->ki_enable = enable;
// }
/**
* @brief 使能微分控制
* @param {PID_FUZZY} *self
* @param {BOOL} enable
* @return {*}
* @note
*/
static void _set_kd_enable(struct PID_FUZZY *self, BOOL enable)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->kd_enable = enable;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->kd_enable = enable;
}
}
static void _set_kd(struct PID_FUZZY *self, float32 kd)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->kd = kd;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->kd = kd;
}
}
/**
* @brief 配置不完全微分系数
* @param {PID_FUZZY} *self
* @param {float32} alpha
* @return {*}
* @note alpha范围0-1，系数越大,不完全微分的作用越强
*/
static void _set_kd_dev(struct PID_FUZZY *self, float32 alpha)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->alpha = alpha;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->alpha = alpha;
}
}
static void _set_ki_enable(struct PID_FUZZY *self, BOOL enable)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->ki_enable = enable;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->ki_enable = enable;
}
}
static void _set_ki(struct PID_FUZZY *self, float32 ki)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->ki = ki;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->ki = ki;
}
}
/*
* Function:使能平滑控制
* parameter:*pid需要配，PID参数结构指针，sv_range控制范围sv的范围
* return:无
*/
static void _set_smooth_enable(struct PID_FUZZY *self, BOOL enable, float32 sv_range)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->sm = enable;
pri->sv_range = sv_range;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->sm = enable;
pri->sv_range = sv_range;
}
}
// 设置控制参数
static void _set_ctrl_prm(struct PID_FUZZY *self, float32 kp, float32 ki, float32 kd, float32 err_dead, float32 deviation,
float32 out_min, float32 out_max)
{
self->open = TRUE;
self->pid_params.kup = KUP;
self->pid_params.kui = KUI;
self->pid_params.kud = KUD;
self->pid_params.mine = MINE;
self->pid_params.maxe = MAXE;
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
osel_memset((uint8_t *)pri, 0, sizeof(pid_common_position_t));
pri->kp = kp;
pri->ki = ki;
pri->kd = kd;
pri->err_dead = err_dead;
pri->deviation = deviation;
pri->out_max = out_max;
pri->out_min = out_min;
pri->detach = FALSE;
pri->sm = FALSE;
pri->ki_enable = TRUE;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
osel_memset((uint8_t *)pri, 0, sizeof(pid_common_increment_t));
pri->kp = kp;
pri->ki = ki;
pri->kd = kd;
pri->err_dead = err_dead;
pri->deviation = deviation;
pri->out_max = out_max;
pri->out_min = out_min;
pri->ki_enable = TRUE;
}
}
static void _set_error_max_min(struct PID_FUZZY *self, float32 mine, float32 maxe)
{
self->pid_params.mine = mine;
self->pid_params.maxe = maxe;
}
static void _update_ctrl_prm(struct PID_FUZZY *self, float32 kp, float32 ki, float32 kd, float32 err_dead,
float32 out_min, float32 out_max)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->kp = kp;
pri->ki = ki;
pri->kd = kd;
pri->err_dead = err_dead;
pri->out_max = out_max;
pri->out_min = out_min;
pri->detach = FALSE;
pri->sm = FALSE;
if (kd > 0)
{
pri->kd_enable = TRUE;
}
else
{
pri->kd_enable = FALSE;
}
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->kp = kp;
pri->ki = ki;
pri->kd = kd;
pri->err_dead = err_dead;
pri->out_max = out_max;
pri->out_min = out_min;
if (kd > 0)
{
pri->kd_enable = TRUE;
}
else
{
pri->kd_enable = FALSE;
}
}
}
/**
* @brief 非0时配置为积分分离+抗积分饱和PID,否则为普通抗积分饱和PID
* @param {PID_FUZZY} *self
* @param {float32} max_err
* @param {BOOL} mode
* @return {*}
*/
static void _set_cfg(struct PID_FUZZY *self, float32 max_err, BOOL mode)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->err_limit = max_err;
pri->detach = mode == FALSE ? FALSE : TRUE;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->err_limit = max_err;
pri->detach = mode == FALSE ? FALSE : TRUE;
}
}
/**
* @brief 判断是否处于死区范围内
*
* 根据给定的 PID_FUZZY 结构体，判断当前值是否处于死区范围内。
*
* @param self PID_FUZZY 结构体指针
*
* @return 如果处于死区范围内，返回 TRUE；否则返回 FALSE
*/
static BOOL _in_dead_zone(struct PID_FUZZY *self)
{
float32 deviation = 0.0f;
float32 err_dead = 0.0f;
float32 err = 0.0f;
float32 offset = 0.0f;
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
deviation = pri->deviation;
err_dead = pri->err_dead;
err = pri->feedback - pri->ref;
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
deviation = pri->deviation;
err_dead = pri->err_dead;
err = pri->feedback - pri->ref;
}
offset = err + deviation;
if (self->deadzone_dir == DEAD_ZONE_POSITIVE)
{
if (offset >= 0 && offset <= ABS(err_dead))
{
return TRUE;
}
else
{
return FALSE;
}
}
else if (self->deadzone_dir == DEAD_ZONE_NEGATIVE)
{
if (offset <= 0 && offset >= err_dead)
{
return TRUE;
}
else
{
return FALSE;
}
}
else
{
if (ABS(offset) <= ABS(err_dead))
{
return TRUE;
}
else
{
return FALSE;
}
}
}
static float32 position_pid(struct PID_FUZZY *self, float32 target, float32 feedback)
{
float32 error = 0;
float32 ec = 0;
float32 kd = 0;
float32 thisdev = 0;
pid_common_position_t *pri = &self->pri_u.position;
kd = pri->kd;
/*获取期望值与实际值,进行偏差计算*/
if (pri->sm == 1)
{
smooth_setpoint(self, target);
}
else
{
pri->ref = target;
}
pri->feedback = feedback;
error = pri->ref - pri->feedback;
if (self->in_dead_zone(self) == TRUE)
{
error = 0;
pri->in_dead_zone = TRUE;
}
else
{
pri->in_dead_zone = FALSE;
}
pri->e_0 = error;
/* fuzzy control caculate */
ec = error - pri->e_1;
if (self->open == TRUE)
{
compensate(error, ec, &self->pid_params);
}
/*根据PID配置的模式,获取积分数据,进行积分累加*/
if (self->speed_integral_enable == TRUE)
{
pri->iout = (pri->ki + self->pid_params.ki) * error * changing_integral_rate(self);
}
else
{
float32 temp_iterm = 0.0f;
float32 insert = 0;
if (pri->out >= pri->out_max)
{
if (fabs(error) > pri->err_limit && pri->detach)
{
insert = 0;
}
else
{
insert = 1;
if (error < 0)
{
temp_iterm = (pri->ki + self->pid_params.ki) * error;
}
}
}
else if (pri->out <= pri->out_min)
{
if (fabs(error) > pri->err_limit && pri->detach)
{
insert = 0;
}
else
{
insert = 1;
if (error > 0)
{
temp_iterm = (pri->ki + self->pid_params.ki) * error;
}
}
}
else
{
if (fabs(error) > pri->err_limit && pri->detach)
{
insert = 0;
}
else
{
insert = 1;
temp_iterm = (pri->ki + self->pid_params.ki) * error;
}
}
pri->iout += temp_iterm;
/* limt integral */
if (pri->iout > pri->out_max)
{
pri->iout = pri->out_max;
}
else if (pri->iout < pri->out_min)
{
pri->iout = pri->out_min;
}
pri->iout = pri->iout * insert;
}
#if INCOMPLETE_DIFFEREN == 1
/*不完全微分*/
thisdev = kd * (1.0 - pri->alpha) * (error - pri->e_1) + pri->alpha * pri->lastdev;
/*record last dev result*/
pri->lastdev = thisdev;
#else
thisdev = (error - pri->e_1) * (kd);
#endif
if (pri->kd_enable == FALSE)
{
thisdev = 0;
}
if (pri->ki_enable == FALSE)
{
pri->iout = 0;
}
pri->out = (pri->kp + self->pid_params.kp) * error + pri->iout + thisdev;
pri->e_1 = error;
/*record last feedback sensor result*/
pri->pre_feedback = pri->feedback;
/*limt pid output*/
pri->out = RANGE(pri->out, pri->out_min, pri->out_max);
return pri->out;
}
static float32 increment_pid(struct PID_FUZZY *self, float32 target, float32 feedback)
{
float32 ep, ei, ed;
float32 inc_out;
float32 thisdev = 0;
pid_common_increment_t *pri = &self->pri_u.increment;
pri->feedback = feedback;
pri->e_0 = pri->ref - pri->feedback;
if (pri->e_0 >= MAXE)
{
return pri->out_max;
}
else if (pri->e_0 <= MINE)
{
return pri->out_min;
}
if (fabs(pri->e_0) <= pri->err_dead)
{
pri->e_0 = 0;
}
ep = pri->e_0 - pri->e_1;
ei = pri->e_0;
ed = pri->e_0 - 2 * pri->e_1 + pri->e_2;
if (self->open == TRUE)
{
compensate(pri->e_0, ep, &self->pid_params);
}
if (pri->sm == 1)
{
smooth_setpoint(self, target);
}
else
{
pri->ref = target;
}
#if INCOMPLETE_DIFFEREN == 1
/*不完全微分*/
thisdev = (1.0 - pri->alpha) * (pri->kd + self->pid_params.kd) * ed + pri->alpha * pri->lastdev;
#else
ed = ed;
#endif
if (self->speed_integral_enable == TRUE)
{
if (ABS(pri->e_0) > MAXE)
{
pri->iout = (pri->ki + self->pid_params.ki) * ei;
}
else
{
// 变速积分
pri->iout = (pri->ki + self->pid_params.ki) * ei * changing_integral_rate(self);
}
}
else
{
pri->iout = (pri->ki + self->pid_params.ki) * ei;
}
if (pri->kd_enable == FALSE)
{
thisdev = 0;
}
if (pri->ki_enable == FALSE)
{
pri->iout = 0;
}
inc_out = (pri->kp + self->pid_params.kp) * ep + pri->iout + thisdev;
pri->e_2 = pri->e_1;
pri->e_1 = pri->e_0;
pri->lastdev = thisdev;
pri->out = pri->out + inc_out;
pri->out = RANGE(pri->out, pri->out_min, pri->out_max);
return pri->out;
}
static float32 _pid(struct PID_FUZZY *self, float32 target, float32 feedback)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
return position_pid(self, target, feedback);
}
else
{
return increment_pid(self, target, feedback);
}
}
/**
* @brief 复位PID积分及微分控制数据
* @param {PID_FUZZY} *self
* @return {*}
*/
static void _restctrl(struct PID_FUZZY *self, float32 out)
{
if (self->sub_type == PID_SUB_TYPE_POSITION)
{
pid_common_position_t *pri = NULL;
pri = &self->pri_u.position;
pri->e_1 = 0;
pri->iout = 0;
pri->out = out;
pri->iout = out;
#if INCOMPLETE_DIFFEREN == 1
pri->lastdev = 0;
#endif
}
else
{
pid_common_increment_t *pri = NULL;
pri = &self->pri_u.increment;
pri->e_0 = 0;
pri->e_1 = 0;
pri->e_2 = 0;
pri->lastdev = 0;
pri->out = out;
pri->iout = out;
}
}
void pid_fuzzy_constructor(struct PID_FUZZY *self)
{
self->set_ctrl_prm = _set_ctrl_prm;
self->set_error_max_min = _set_error_max_min;
self->update_ctrl_prm = _update_ctrl_prm;
self->set_cfg = _set_cfg;
self->set_smooth_enable = _set_smooth_enable;
self->set_err_dead = _set_err_dead;
self->set_kp = _set_kp;
self->set_ki_enable = _set_ki_enable;
self->set_ki = _set_ki;
self->set_kd_enable = _set_kd_enable;
self->set_kd = _set_kd;
self->set_kd_dev = _set_kd_dev;
self->set_range = _set_range;
self->restctrl = _restctrl;
self->set_iout = _set_iout;
self->in_dead_zone = _in_dead_zone;
self->execute = _pid;
}

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#include "pid.h"
#include <math.h>
// 设置控制参数
static void _set_ctrl_prm(struct PID_NEURAL *self, float32 minimum, float32 maximum)
{
self->pri.setpoint = minimum; /*设定值*/
self->pri.kcoef = 0.12; /*神经元输出比例*/
self->pri.kp = 0.45; /*比例学习速度*/
self->pri.ki = 0.05; /*积分学习速度*/
self->pri.kd = 0; /*微分学习速度*/
self->pri.lasterror = 0.0; /*前一拍偏差*/
self->pri.preerror = 0.0; /*前两拍偏差*/
self->pri.result = minimum; /*PID控制器结果*/
self->pri.output = 0.0; /*输出值，百分比*/
self->pri.maximum = maximum; /*输出值上限*/
self->pri.minimum = minimum; /*输出值下限*/
self->pri.deadband = (maximum - minimum) * 0.0005f; /*死区*/
self->pri.wp = 0.10; /*比例加权系数*/
self->pri.wi = 0.10; /*积分加权系数*/
self->pri.wd = 0.10; /*微分加权系数*/
}
// 设置输出参数
static void _set_out_prm(struct PID_NEURAL *self, float32 minimum, float32 maximum)
{
self->pri.maximum = maximum;
self->pri.minimum = minimum;
}
/*单神经元学习规则函数*/
static void NeureLearningRules(struct PID_NEURAL *self, float32 zk, float32 uk, float32 *xi)
{
self->pri.wi = self->pri.wi + self->pri.ki * zk * uk * xi[0];
self->pri.wp = self->pri.wp + self->pri.kp * zk * uk * xi[1];
self->pri.wd = self->pri.wd + self->pri.kd * zk * uk * xi[2];
}
static float32 _PID(struct PID_NEURAL *self, float32 target, float32 feedback)
{
float32 x[3];
float32 w[3];
float32 sabs;
float32 error;
float32 result;
float32 deltaResult;
self->pri.setpoint = target;
error = self->pri.setpoint - feedback;
result = self->pri.result;
if (fabs(error) > self->pri.deadband)
{
x[0] = error;
x[1] = error - self->pri.lasterror;
x[2] = error - self->pri.lasterror * 2 + self->pri.preerror;
sabs = fabs(self->pri.wi) + fabs(self->pri.wp) + fabs(self->pri.wd);
w[0] = self->pri.wi / sabs;
w[1] = self->pri.wp / sabs;
w[2] = self->pri.wd / sabs;
deltaResult = (w[0] * x[0] + w[1] * x[1] + w[2] * x[2]) * self->pri.kcoef;
}
else
{
deltaResult = 0;
}
result = result + deltaResult;
if (result > self->pri.maximum)
{
result = self->pri.maximum;
}
if (result < self->pri.minimum)
{
result = self->pri.minimum;
}
self->pri.result = result;
self->pri.output = self->pri.result;
// 单神经元学习
NeureLearningRules(self, error, result, x);
self->pri.preerror = self->pri.lasterror;
self->pri.lasterror = error;
return self->pri.output;
}
void pid_neural_constructor(struct PID_NEURAL *self)
{
self->set_ctrl_prm = _set_ctrl_prm;
self->set_out_prm = _set_out_prm;
self->PID = _PID;
}

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#include "s_curve.h"
// s曲线加速度各段参数定义
// 起始速度
#define F0 0.0f
// 加加速度与减减速度
#define FAA 0.0f
#define FRR 0.0f
// 加速段三个时间
#define TAA 0.1f
#define TUA 0.2f
#define TRA 0.1f
// 匀速段
#define TUU 5.0f
// 减速段
#define TAR 0.1f
#define TUR 0.2f
#define TRR 0.1f
// 表格长度
#define S_CURVE_TABLE_LEN 400
int16_t s_curve_table[S_CURVE_TABLE_LEN] = {0};
static int16_t s_curve_func(s_curve_t *s, float32 t, float32 *freq, float32 *acc)
{
// 辅助常数项
float32 A, B, C, D, E, F;
// 表达式中间值
float32 f3, f4, f5;
// 加速段，匀速段，减速段时间
float32 Ta, Tu, Tr;
// 减加速与加减速段斜率
float32 fra, far;
// 起始频率与加加速频率，减减速频率
float32 f0, faa, frr;
float32 taa, tua, tra, tuu, tar, tur, trr;
// 获取参数
faa = s->faa;
frr = s->frr;
taa = s->taa;
tua = s->tua;
tra = s->tra;
tuu = s->tuu;
tar = s->tar;
tur = s->tur;
trr = s->trr;
f0 = s->f0;
fra = faa * taa / tra;
far = frr * trr / tar;
Ta = taa + tua + tra;
Tu = tuu;
Tr = tar + tur + trr;
A = f0;
B = f0 - 0.5 * faa * taa * taa;
C = f0 + 0.5 * faa * taa * taa + faa * taa * tua + 0.5 * fra * (taa + tua) * (taa + tua) - fra * Ta * (taa + tua);
// f1 = f0 + 0.5 * faa * taa * taa;
// f2 = f0 + 0.5 * faa * taa * taa + faa * taa * tua;
f3 = 0.5 * fra * Ta * Ta + C;
D = f3 - 0.5 * far * (Ta + Tu) * (Ta + Tu);
f4 = -far * 0.5 * (Ta + Tu + tar) * (Ta + Tu + tar) + far * (Ta + Tu) * (Ta + Tu + tar) + D;
E = f4 + far * tar * (Ta + Tu + tar);
f5 = -far * tar * (Ta + Tu + Tr - trr) + E;
F = f5 + frr * (Ta + Tu + Tr) * (Ta + Tu + Tr - trr) - 0.5 * frr * (Ta + Tu + Tr - trr) * (Ta + Tu + Tr - trr);
// 如果时间点在全行程规定的时间段内
if ((t >= 0) && (t <= Ta + Tu + Tr))
{
// 加加速段
if ((t >= 0) && (t <= taa))
{
*freq = 0.5 * faa * t * t + A;
*acc = faa * t;
}
// 匀加速段
else if ((t >= taa) && (t <= taa + tua))
{
*freq = faa * taa * t + B;
*acc = faa * taa;
}
// 加减速段
else if ((t >= taa + tua) && (t <= taa + tua + tra))
{
*freq = -0.5 * fra * t * t + fra * Ta * t + C;
*acc = -fra * t + fra * Ta;
}
// 匀速段
else if ((t >= Ta) && (t <= Ta + tuu))
{
*freq = f3;
*acc = 0;
}
// 加减速段
else if ((t >= Ta + Tu) && (t <= Ta + Tu + tar))
{
*freq = -0.5 * far * t * t + far * (Ta + Tu) * t + D;
*acc = -far * t + far * (Ta + Tu);
}
// 匀减速
else if ((t >= Ta + Tu + tar) && (t <= Ta + Tu + tar + tur))
{
*freq = -far * tar * t + E;
*acc = -far * tar;
}
// 减减速
else if ((t >= Ta + Tu + Tr - trr) && (t <= Ta + Tu + Tr))
{
*freq = 0.5 * frr * t * t - frr * (Ta + Tu + Tr) * t + F;
*acc = frr * t - frr * (Ta + Tu + Tr);
}
}
else
{
return -1;
}
return 0;
}
// S型曲线初始化
void s_curve_table_gen(uint16_t tmin, uint16_t tmax)
{
uint16_t i, tint;
float32 ti;
float32 freq;
float32 acc;
float32 fi;
s_curve_t s;
osel_memset((uint8_t *)&s, 0, sizeof(s_curve_t));
s.f0 = F0;
s.taa = TAA;
s.tua = TUA;
s.tra = TRA;
s.tuu = TUU;
s.tar = TAR;
s.tur = TUR;
s.trr = TRR;
// 根据约束条件求出加加速段与减减速段斜率
s.faa = 2.0 / (s.taa * (s.taa + s.tra + 2 * s.tua));
s.frr = 2.0 / (s.trr * (s.tar + s.trr + 2 * s.tur));
for (i = 0; i < S_CURVE_TABLE_LEN; i++)
{
// 求出每个时间点对应的频率以及加速度
fi = i * (TAA + TUA + TRA + TUU + TAR + TUR + TRR) / S_CURVE_TABLE_LEN;
s_curve_func(&s, fi, &freq, &acc);
// 根据最大与最小装载值确定定时器实际值
ti = tmax - (tmax - tmin) * freq;
// 转换为整数值
tint = (uint16_t)ti;
// 存入s曲线表
s_curve_table[i] = tint;
}
}

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# 模糊PID控制器设计文档
# 模糊PID控制器详细设计文档
## 1. 引言
### 1.1 目的
本文档旨在详细介绍模糊PID控制器的设计理念、实现方法和使用指南，为开发者提供一套完整的模糊PID控制解决方案。
### 1.2 背景
PID控制器因其结构简单、稳定性好、易于实现等优点，在工业控制系统中得到了广泛应用。然而，传统PID控制器在面对复杂或非线性系统时，性能表现不佳。模糊PID控制器通过引入模糊逻辑，动态调整PID参数，以适应系统在不同工作状态下的控制需求，从而提高控制性能。
## 2. 设计概述
### 2.1 设计目标
- **适应性**：能够适应不同类型和不同工作状态的控制系统。
- **稳定性**：保证控制系统在各种工作条件下的稳定运行。
- **易用性**：提供简单易懂的接口，便于开发者快速实现和调试。
### 2.2 功能模块
模糊PID控制器主要包括以下几个功能模块：
1. **模糊控制模块**：负责根据输入的误差和误差变化率，通过模糊逻辑计算出PID参数。
2. **SV平滑给定模块**：负责平滑控制目标值，减少控制过程中的突变。
3. **变速积分模块**：根据误差的大小调整积分速率，提高控制效率。
4. **参数设置模块**：提供接口函数，用于设置和调整PID参数。
## 3. 功能模块详细设计
### 3.1 模糊控制模块
#### 3.1.1 输入处理
- **误差处理**：将实时误差 `e`限制在预定的范围内，并进行模糊化处理。
- **误差变化率处理**：将误差变化率 `ec`进行相同的处理。
#### 3.1.2 模糊规则库
- **规则定义**：根据系统的具体需求，定义一套模糊规则，用于计算PID参数。
- **规则应用**：根据输入的误差和误差变化率的模糊化值，通过模糊规则库计算出 `kp`、`ki`、`kd`。
### 3.2 SV平滑给定模块
- **平滑策略**：根据当前目标值与新目标值之间的差值，动态调整目标值变化的步长，实现平滑过渡。
### 3.3 变速积分模块
- **积分策略**：根据误差的大小，调整积分速率。误差较小时，使用完整积分；误差较大时，减小或停止积分。
### 3.4 参数设置模块
- **接口设计**：提供一系列接口函数，用于设置PID控制器的参数，如输出限制、死区误差等。
## 4. 使用说明
### 4.1 初始化
- **控制器初始化**：根据控制对象的特性，初始化模糊PID控制器的相关参数和模糊规则库。
### 4.2 实时控制
- **参数调整**：在控制循环中，根据实时误差和误差变化率，动态调整PID参数。
- **控制执行**：根据调整后的PID参数，执行PID控制算法，输出控制信号。
### 4.3 参数调整
- **动态调整**：根据系统运行情况，通过参数设置模块调整PID参数，优化控制效果。
## 5. 结论
模糊PID控制器通过动态调整PID参数，提高了控制系统的适应性和稳定性，特别适用于复杂或非线性系统的控制。本文档提供了模糊PID控制器的详细设计方案，旨在帮助开发者更好地理解和应用模糊PID控制技术
## 概述
本文档旨在详细介绍模糊PID控制器的设计与实现。模糊PID控制器结合了传统PID控制和模糊逻辑控制的优点，通过模糊逻辑对PID参数进行动态调整，以适应控制系统在不同工作状态下的需求。
## 功能模块
### 1. 模糊控制模块
- **功能描述**：根据误差 `e`和误差变化率 `ec`的模糊化值，通过模糊规则库计算出模糊PID控制器的三个参数：比例系数 `kp`、积分系数 `ki`、微分系数 `kd`。
- **实现方法**：首先将输入的误差 `e`和误差变化率 `ec`限制在预定范围内，然后通过模糊化处理得到其隶属度和模糊位置标号，最后根据模糊规则库计算出 `kp`、`ki`、`kd`的值。
### 2. SV平滑给定模块
- **功能描述**：平滑控制目标值（Setpoint Value, SV），以减少控制过程中的突变，提高系统的稳定性。
- **实现方法**：根据当前目标值与新目标值之间的差值，动态调整目标值的变化步长，以实现平滑过渡。
### 3. 变速积分模块
- **功能描述**：根据误差的大小调整积分速率，以提高控制系统的快速性和稳定性。
- **实现方法**：当误差较小时，使用完整积分；当误差在一定范围内变化时，通过线性函数调整积分速率；当误差较大时，减小或停止积分，以避免积分饱和。
### 4. 参数设置模块
- **功能描述**：提供接口函数，用于设置PID控制器的各项参数，包括输出限制范围、死区误差、积分输出值、PID参数等。
- **实现方法**：根据控制器的子类型（位置型或增量型），分别设置相应参数的值。
## 使用说明
1. **初始化**：根据控制对象的具体情况，初始化模糊PID控制器的结构体，包括最大误差、最小误差、PID参数的模糊规则库等。
2. **实时控制**：在控制循环中，根据当前的误差 `e`和误差变化率 `ec`调用模糊控制模块，计算出动态调整的PID参数，然后根据这些参数进行PID控制。
3. **参数调整**：根据系统运行情况，通过参数设置模块调整PID控制器的参数，以优化控制效果。
## 结论
模糊PID控制器通过引入模糊逻辑，使得PID参数能够根据控制系统的实时状态动态调整，从而提高了控制系统的适应性和稳定性。通过本文档的设计与实现，开发者可以更好地理解和应用模糊PID控制器。

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https://www.cnblogs.com/foxclever/p/16299063.html

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#include "dac161p997.h"
#include "delay.h"
static dac161p997_t _handle;
static void dac161p997_output_0()
{
_handle.io->set(*_handle.io);
delay_us(DUTY_CYCLE_25);
_handle.io->reset(*_handle.io);
delay_us(DUTY_CYCLE_75);
}
static void dac161p997_output_1()
{
_handle.io->set(*_handle.io);
delay_us(DUTY_CYCLE_75);
_handle.io->reset(*_handle.io);
delay_us(DUTY_CYCLE_25);
}
static void dac161p997_output_d()
{
_handle.io->set(*_handle.io);
delay_us(DUTY_CYCLE_50);
_handle.io->reset(*_handle.io);
delay_us(DUTY_CYCLE_50);
}
/**
* @brief 输出DAC161符号
*
* 根据传入的符号类型，调用相应的DAC161输出函数。
*
* @param sym 符号类型，可以是ZERO_SYM、ONE_SYM或其他值。
*/
static void dac161p997_output_symbol(uint8_t sym)
{
switch (sym)
{
case ZERO_SYM:
dac161p997_output_0();
break;
case ONE_SYM:
dac161p997_output_1();
break;
default:
dac161p997_output_d();
break;
}
}
/**
* @brief 向DAC161写入寄存器
*
* 向DAC161写入一个16位的数据，并附加一个8位的标签。
* 芯片会回复一个应答信号，此处忽略应答信号。可以通过设置寄存器关闭应答信号。
* @param data 要写入的数据，16位。
* @param tag 附加的标签，8位。tag = 0时，写DAC寄存器；tag = 1时，写配置寄存器。
*/
void dac161p997_swif_write_reg(uint16_t data, uint8_t tag)
{
uint8_t plow, phigh;
uint16_t i, tmp;
/* compute parity low */
tmp = data & 0x00ff; // get least significant byte
for (plow = 0; tmp != 0; tmp >>= 1)
{
if (tmp & 0x1) // test if lsb is 1
plow++; // count number of bits equal to 1
}
if (plow & 0x1) // check if number of 1s is odd
plow = 0; // set even parity
else
plow = 1; // else set odd parity
/* compute parity high */
tmp = (data & 0xff00) >> 8; // get most significant byte
for (phigh = 0; tmp != 0; tmp >>= 1)
{
if (tmp & 0x1) // test if lsb is 1
phigh++; // count number of bits equal to 1
}
if (phigh & 0x1) // check if number of 1s is odd
phigh = 0; // set even parity
else
phigh = 1; // set odd parity
phigh = phigh ^ tag; // parity high is for high slice = tag + 1 byte
dac161p997_output_symbol(IDLE_SYM); // Frame start: send an idle symbol first
dac161p997_output_symbol(tag);
tmp = data;
for (i = 0; i < 16; i++) // send 16 data bits msb to lsb
{
if (tmp & 0x8000)
{
dac161p997_output_symbol(ONE_SYM); // send 1
}
else
{
dac161p997_output_symbol(ZERO_SYM); // send 0
}
tmp = tmp << 1; // move next data bit to msb
}
dac161p997_output_symbol(phigh); // send parity high bit
dac161p997_output_symbol(plow); // send parity low bit
dac161p997_output_symbol(IDLE_SYM); // send idle
}
/**
* @brief 设置DAC161输出电流
*
* 通过向DAC161写入指定的电流值来设置其输出电流,输出电流持续时间100ms。
*
* @param current 要设置的电流值
*/
void dac161p997_output_current(float32 current)
{
uint8_t adc = (uint16_t)(current * DAC161P997_CURRENT_SLOPE) >> 8;
static uint8_t last_adc;
if (adc == last_adc)
{
last_adc = adc;
return;
}
dac161p997_swif_write_reg(DAC161P997_LCK_REG_UNLOCK, CONFIG_WRITE);
dac161p997_swif_write_reg(DAC161P997_ERR_LOW_REG + adc, CONFIG_WRITE);
dac161p997_swif_write_reg(DAC161P997_LCK_REG_LOCK, CONFIG_WRITE);
}
/**
* @brief 初始化DAC161设备
*
* 此函数用于初始化DAC161设备，进行必要的配置，以便设备正常工作。
* 写寄存器之前要先解锁，具体配置寄存器根据需要配置的寄存器而定
* 具体步骤包括：
* 1. 解锁DAC161的配置寄存器
* 2. 配置DAC161的错误下限寄存器
* 3. 锁定DAC161的配置寄存器
*/
void dac161p997_init()
{
_handle.io = gpio_create(DAC161P997_IO_PORT, DAC161P997_IO_PIN);
dac161p997_swif_write_reg(DAC161P997_LCK_REG_UNLOCK, CONFIG_WRITE);
dac161p997_swif_write_reg(DAC161P997_CONFIG2_REG +
DAC161P997_CONFIG2_REG_LOOP +
DAC161P997_CONFIG2_REG_CHANNEL +
DAC161P997_CONFIG2_REG_PARITY +
DAC161P997_CONFIG2_REG_FRAME,
CONFIG_WRITE);
dac161p997_swif_write_reg(DAC161P997_LCK_REG_LOCK, CONFIG_WRITE);
}

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#ifndef __DAC161P997_H__
#define __DAC161P997_H__
#include "main.h"
#include "gpios.h"
#define DAC161P997_IO_PORT (DAC161P997_GPIO_Port)
#define DAC161P997_IO_PIN (DAC161P997_Pin)
#define DAC161P997_CURRENT_SLOPE 2730.625f // adc = (current / 24) * 0xffff
// Symbol Periods
#define DUTY_CYCLE_100 (1000U) // (CPU_CLK / BAUD_RATE)
#define DUTY_CYCLE_75 (DUTY_CYCLE_100 * 0.75f)
#define DUTY_CYCLE_50 (DUTY_CYCLE_100 * 0.50f)
#define DUTY_CYCLE_25 (DUTY_CYCLE_100 * 0.25f)
/************************************************************
* TI DAC161P997 REGISTER SET ADDRESSES
************************************************************/
#define DAC161P997_LCK_REG (0x0000)
#define DAC161P997_CONFIG1_REG (0x0100)
#define DAC161P997_CONFIG2_REG (0x0200)
#define DAC161P997_CONFIG3_REG (0x0300)
#define DAC161P997_ERR_LOW_REG (0x0400)
#define DAC161P997_ERR_HIGH_REG (0x0500)
// TI DAC161P997 Register Bits
#define DAC161P997_LCK_REG_LOCK (0x00AA) // any value other than 0x95
#define DAC161P997_LCK_REG_UNLOCK (0x0095)
#define DAC161P997_CONFIG1_REG_RST (0x0001)
#define DAC161P997_CONFIG1_REG_NOP (0 * 0x08u)
#define DAC161P997_CONFIG1_REG_SET_ERR (1 * 0x08u)
#define DAC161P997_CONFIG1_REG_CLEAR_ERR (2 * 0x08u)
#define DAC161P997_CONFIG1_REG_NOP3 (3 * 0x08u)
#define DAC161P997_CONFIG2_REG_LOOP (0x0001)
#define DAC161P997_CONFIG2_REG_CHANNEL (0x0002)
#define DAC161P997_CONFIG2_REG_PARITY (0x0004)
#define DAC161P997_CONFIG2_REG_FRAME (0x0008)
#define DAC161P997_CONFIG2_REG_ACK_EN (0x0010)
#define DAC161P997_CONFIG3_REG_RX_ERR_CNT_16 (0x000F)
#define DAC161P997_CONFIG3_REG_RX_ERR_CNT_8 (0x0007)
#define DAC161P997_CONFIG3_REG_RX_ERR_CNT_1 (0x0000)
// Tags
#define DACCODE_WRITE (0x00)
#define CONFIG_WRITE (0x01)
// Valid Symbols
#define ZERO_SYM (0x00)
#define ONE_SYM (0x01)
#define IDLE_SYM (0x02)
#define STATIC_LOW_SYM (0x03)
// DAC Codes for different currents
#define DACCODE_0mA (0x0000)
#define DACCODE_4mA (0x2AAA)
#define DACCODE_8mA (0x5555)
#define DACCODE_12mA (0x7FFF)
#define DACCODE_16mA (0xAAAA)
#define DACCODE_20mA (0xD555)
#define DACCODE_24mA (0xFFFF)
// cycles
// #define QUARTER_CYCLES (625)
// #define HALF_CYCLES (1250)
// #define THREE_CYCLES (1875)
// #define FULL_CYCLES (2500)
typedef struct
{
gpio_t *io;
} dac161p997_t;
void dac161p997_output_0(void);
void dac161p997_output_1(void);
void dac161p997_output_d(void);
void dac161p997_output_symbol(uint8_t sym);
void dac161p997_swif_write_reg(uint16_t data, uint8_t tag);
extern void dac161p997_output_current(float32 current);
extern void dac161p997_init(void);
#endif

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User/lib/driver/eeprom_fm24.c Normal file
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/**
* @file eeprom_fm24.c
* @author xxx
* @date 2023-08-29 07:58:27
* @brief 用于实现FM24 EEPROM相关的读写操作
* @copyright Copyright (c) 2023 by xxx, All Rights Reserved.
*/
#include "entity.h"
#include "board.h"
#include "eeprom_fm24.h"
#include "delay.h"
#define FM24_SPI SPI1
#define EEPROM_FM24_CS_PORT EE3_CS_GPIO_Port
#define EEPROM_FM24_CS_PIN EE3_CS_Pin
#define EEPROM_FM24_MOSI_PORT SPI_MOSI_GPIO_Port
#define EEPROM_FM24_MOSI_PIN SPI_MOSI_Pin
#define EEPROM_FM24_MISO_PORT SPI_MISO_GPIO_Port
#define EEPROM_FM24_MISO_PIN SPI_MISO_Pin
#define EEPROM_FM24_SCK_PORT SPI_CLK_GPIO_Port
#define EEPROM_FM24_SCK_PIN SPI_CLK_Pin
static fm24_t _eeprom_fm24;
void eeprom_fm24_init(void)
{
spi_gpio_group_t gpios;
spi_normal_config_t cfg;
osel_memset((uint8_t *)&cfg, 0, sizeof(spi_normal_config_t));
// 创建CS引脚
gpios.cs = gpio_create(EEPROM_FM24_CS_PORT, EEPROM_FM24_CS_PIN);
gpios.mosi = gpio_create(EEPROM_FM24_MOSI_PORT, EEPROM_FM24_MOSI_PIN);
gpios.sck = gpio_create(EEPROM_FM24_SCK_PORT, EEPROM_FM24_SCK_PIN);
gpios.miso = gpio_create(EEPROM_FM24_MISO_PORT, EEPROM_FM24_MISO_PIN);
gpios.rst = gpio_create(NULL, 0);
gpios.rdy = gpio_create(NULL, 0);
// 创建SPI对象
eeprom_fm24_get()->spi = spi_create(SPI_TYPE_NORMAL, gpios, 0);
DBG_ASSERT(eeprom_fm24_get() != NULL __DBG_LINE);
cfg.cmd_rdsr = FM24_CMD_RDSR;
cfg.cmd_wrsr = FM24_CMD_WRSR;
cfg.cmd_wren = FM24_CMD_WREN;
cfg.cmd_wrdi = FM24_CMD_WRDI;
cfg.cmd_write = FM24_CMD_WRITE;
cfg.cmd_read = FM24_CMD_READ;
cfg.dummy_byte = FM24_DUMMY_BYTE;
cfg.address_bytes = 2;
cfg.page_size = FM24_PAGE_SIZE;
cfg.total_size = FM24_SIZE;
cfg.continuous_write = FALSE;
osel_memcpy((uint8_t *)&eeprom_fm24_get()->spi->cfg, (uint8_t *)&cfg, sizeof(spi_normal_config_t));
// 使能SPI
eeprom_fm24_get()->spi->interface.hardware_enable(eeprom_fm24_get()->spi, FM24_SPI);
// 这里需要复位下SPI，否则读出的数据不对
eeprom_fm24_get()->spi->interface.u.normal.spi_reset(eeprom_fm24_get()->spi);
eeprom_fm24_write_protection_close();
// eeprom_fm24_test();
}
fm24_t *eeprom_fm24_get(void)
{
return &_eeprom_fm24;
}
void eeprom_fm24_dinit(void)
{
LL_SPI_Disable(FM24_SPI);
GPIO_SET_ANALOG(eeprom_fm24_get()->spi->gpios.mosi->port, eeprom_fm24_get()->spi->gpios.mosi->pin);
GPIO_SET_ANALOG(eeprom_fm24_get()->spi->gpios.miso->port, eeprom_fm24_get()->spi->gpios.miso->pin);
GPIO_SET_ANALOG(eeprom_fm24_get()->spi->gpios.sck->port, eeprom_fm24_get()->spi->gpios.sck->pin);
GPIO_SET_ANALOG(eeprom_fm24_get()->spi->gpios.cs->port, eeprom_fm24_get()->spi->gpios.cs->pin);
}
void eeprom_fm24_enable(void)
{
uint16_t count = 100;
LL_SPI_Enable(FM24_SPI);
// 判断SPI是否使能成功
while (LL_SPI_IsEnabled(FM24_SPI) != 1)
{
if (count-- == 0)
{
return;
}
else
{
__NOP();
}
}
}
void eeprom_fm24_disable(void)
{
uint16_t count = 100;
LL_SPI_Disable(FM24_SPI);
// 判断SPI是否关闭成功
while (LL_SPI_IsEnabled(FM24_SPI) != 0)
{
if (count-- == 0)
{
return;
}
else
{
__NOP();
}
}
}
/**
* @brief 关闭EEPROM FM24的写保护
*
* 此函数用于关闭EEPROM FM24的写保护功能，允许对其进行写操作。
*
* 调用此函数前，应确保EEPROM FM24的SPI接口已正确初始化。
*/
void eeprom_fm24_write_protection_close(void)
{
DBG_ASSERT(eeprom_fm24_get()->spi != NULL __DBG_LINE);
eeprom_fm24_enable();
eeprom_fm24_get()->spi->interface.u.normal.spi_write_reg(eeprom_fm24_get()->spi, eeprom_fm24_get()->spi->cfg.cmd_wrsr, 0);
eeprom_fm24_disable();
}
/**
* @brief 获取EEPROM FM24的写保护状态
*
* 获取EEPROM FM24的写保护状态。
*
* @return BOOL 返回TRUE表示没有写保护，返回FALSE表示有写保护
*/
BOOL eeprom_fm24_write_protection_state(void)
{
DBG_ASSERT(eeprom_fm24_get()->spi != NULL __DBG_LINE);
eeprom_fm24_enable();
eeprom_fm24_get()->write_protection.data = eeprom_fm24_get()->spi->interface.u.normal.spi_read_reg(eeprom_fm24_get()->spi, eeprom_fm24_get()->spi->cfg.cmd_rdsr);
eeprom_fm24_disable();
if (eeprom_fm24_get()->write_protection.bits.bp0 == 1 ||
eeprom_fm24_get()->write_protection.bits.bp1 == 1 ||
eeprom_fm24_get()->write_protection.bits.wpen == 1)
{
return FALSE;
}
else
{
return TRUE;
}
}
BOOL eeprom_fm24_write(uint32_t write_addr, uint8_t *data, uint16_t length)
{
BOOL ret = FALSE;
if (length == 0)
{
return ret;
}
// 开启和关闭SPI对读写实时性有影响
eeprom_fm24_enable();
ret = eeprom_fm24_get()->spi->interface.u.normal.spi_write(eeprom_fm24_get()->spi, write_addr, data, length);
eeprom_fm24_disable();
return ret;
}
BOOL eeprom_fm24_read(uint32_t read_addr, uint8_t *data, uint16_t length)
{
BOOL ret = FALSE;
if (length == 0)
{
return ret;
}
// 开启和关闭SPI对读写实时性有影响
eeprom_fm24_enable();
ret = eeprom_fm24_get()->spi->interface.u.normal.spi_read(eeprom_fm24_get()->spi, read_addr, data, length);
eeprom_fm24_disable();
return ret;
}
BOOL eeprom_fm24_test(void)
{
const uint8_t buf_size = 5;
uint16_t test_address = FM24_TEST_PAGE * FM24_PAGE_SIZE;
uint8_t buf[buf_size];
uint8_t rbuf[buf_size];
osel_memset(buf, 0, buf_size);
osel_memset(rbuf, 0, buf_size);
buf[0] = 0xD5;
buf[1] = 0xC8;
buf[2] = 0x00;
buf[3] = 0x01;
buf[4] = 0x02;
buf[buf_size - 1] = 0xfe;
eeprom_fm24_write(test_address, buf, buf_size);
__NOP();
eeprom_fm24_read(test_address, rbuf, buf_size);
if (osel_memcmp(buf, rbuf, buf_size) == 0)
{
return TRUE;
}
else
{
return FALSE;
}
}
/**
* @brief 获取FM24 EEPROM的状态
*
* 获取FM24 EEPROM的当前状态。该函数始终返回TRUE，表示EEPROM正常工作。
*
* @return BOOL 始终返回TRUE
*/
BOOL eeprom_fm24_status_get(void)
{
return TRUE;
}

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